EDE5108AGSE-6E-E

PRELIMINARY DATA SHEET 512MB Fully Buffered DIMM EBE51FD8AGFD EBE51FD8AGFN Specifications • Density: 512MB • Organization  64M words × 72 bits, 1 rank • Mounting 9 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package  240-pin fully buffered, socket type dual in line memory module (FB-DIMM) PCB height: 30.35mm Lead pitch: 1.00mm  Advanced Memory Buffer (AMB): 655-ball FCBGA  Lead-free (RoHS compliant) • Power supply  DDR2 SDRAM: VDD = 1.8V ± 0.1V  AMB: VCC = 1.5V + 0.075V/−0.045 • Data rate: 667Mbps/533Mbps (max.) • Four internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range  TC = 0°C to +95°C Features • JEDEC standard Raw Card A Design • Industry Standard Advanced Memory Buffer (AMB) • High-speed differential point-to-point link interface at 1.5V (JEDEC draft spec)  14 north-bound (NB) high speed serial lanes  10 south-bound (SB) high speed serial lanes • Various features/modes:  MemBIST and IBIST test functions  Transparent mode and direct access mode for DRAM testing  Interface for a thermal sensor and status indicator • Channel error detection and reporting • Automatic DDR2 SDRAM bus and channel calibration • SPD (serial presence detect) with 1piece of 256 byte serial EEPROM Note: Warranty void if removed DIMM heat spreader. Performance FB-DIMM System clock frequency 167MHz 133MHz Speed grade PC2-5300F PC2-4200F Peak channel throughput 8.0GByte/s 6.4GByte/s FB-DIMM link data rate 4.0Gbps 3.2Gbps DDR2 SDRAM Speed Grade DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR data rate 667Mbps 533Mbps Document No. E0869E30 (Ver. 3.0) Date Published August 2006 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2006 EBE51FD8AGFD, EBE51FD8AGFN Ordering Information Part number EBE51FD8AGFD-6E-E EBE51FD8AGFD-5C-E EBE51FD8AGFN-6E-E EBE51FD8AGFN-5C-E DIMM speed grade PC2-5300F PC2-4200F PC2-5300F PC2-4200F Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-667 (5-5-5) DDR2-533 (4-4-4) Package Mounted devices* EDE5108AGSE-6E-E EDE5108AGSE-5C-E 240-pin FB-DIMM EDE5108AGSE-6E-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E 240-pin FB-DIMM EDE5108AGSE-6E-E Note: Please refer to the EDE5104AGSE, EDE5108AGSE datasheet (E0715E) for detailed operation part and timing waveforms Part Number E B E 51 F D 8 A G F D - 6E - E Elpida Memory Type B: Module Environment code E: Lead Free (RoHS compliant) Product Family E: DDR2 DRAM Speed Grade 6E: DDR2-667 (5-5-5) 5C: DDR2-533 (4-4-4) AMB Device Information D: Integrated Device Technology, Inc. N: Intel Corporation Density / Rank 51: 512MB/1-rank Module Type F: Fully Buffered Mono Density D: 512Mbit Mono Organization 8: x8 Module Outline F: 240-pin DIMM Die Rev. (Mono) Power Supply, Interface A: 1.8V, SSTL_1.8 Preliminary Data Sheet E0869E30 (Ver. 3.0) 2 EBE51FD8AGFD, EBE51FD8AGFN Advanced Memory Buffer Overview The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FB-DIMM channel. The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density. The AMB is the buffer that isolates the DRAMs from the channel. Advanced Memory Buffer Functionality The AMB will perform the following FB-DIMM channel functions. • Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. • Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. • If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. • Detects errors on the channel and reports them to the host memory controller. • Support the FB-DIMM configuration register set as defined in the register chapters. • Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. • Provides a read buffer FIFO and a write buffer FIFO. • Supports an SMBus protocol interface for access to the AMB configuration registers. • Provides logic to support MemBIST and IBIST design for test functions. • Provides a register interface for the thermal sensor and status indicator. • Functions as a repeater to extend the maximum length of FB-DIMM links. Preliminary Data Sheet E0869E30 (Ver. 3.0) 3 EBE51FD8AGFD, EBE51FD8AGFN Advanced Memory Buffer Block Diagram Southbound 10×2 Data in 10×2 Southbound Data out Reference clock 1× 2 PLL Data merge RE-time Re-synch Demux PISO /RESET Reset control 10×12 Thermal sensor failover Command decoder & CRC check Link init SM and control and CSRs IBIST-RX 10×12 Init patterns Mux 4 IBIST-TX DRAM clock 4 DRAM clock Command out DRAM interface Data out 29 DRAM address and command copy1 DRAM address and command copy2 DRAM data and strobes LAI logic DRAM Command Mux DDR state controller and CSRs 29 Core controller and CSRs Write data FIFO External MemBIST DDR calibration Sync & idle pattern generator IBIST-TX IBIST-RX Mux 72+18×2 Data in Data CRC generator and Read FIFO LAI controller NB LAI Buffer Mux Link init SM and control and CSRs SMBus SMBus controller failover 14×6×2 PISO 14×12 Demux Re-synch RE-time Data merge Northbound 14×2 Data Out 14×2 Northbound Data In Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains. Preliminary Data Sheet E0869E30 (Ver. 3.0) 4 EBE51FD8AGFD, EBE51FD8AGFN Interfaces Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a FB-DIMM. Memory Interface NB FBD out Link SB FBD in Link AMB NB FBD in Link SB FBD out Link SMB Block Diagram AMB Interfaces Interface Topology The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached. Host Southbound Nourthbound AMB AMB AMB AMB n/c Block Diagram FB-DIMM Channel Southbound and Northbound Paths Preliminary Data Sheet E0869E30 (Ver. 3.0) 5 Secondary or to optional next FBD Primary or Host Direction n/c EBE51FD8AGFD, EBE51FD8AGFN High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound on 14 secondary differential pairs. DDR2 Channel The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 800MHz. Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides four copies of the command clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble. SMBus Slave interface The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID. Preliminary Data Sheet E0869E30 (Ver. 3.0) 6 EBE51FD8AGFD, EBE51FD8AGFN Block Diagram /CS0 /DQS0 DQS0 NU/ /CS /RDQS DQS /DQS /DQS4 DQS4 NU/ /CS /RDQS DQS /DQS DQS9 DQ0 to DQ7 /DQS1 DQS1 DQS10 DQ8 to DQ15 /DQS2 DQS2 8 8 DM/ RDQS DQ0 to DQ7 D0 DQS13 DQ32 to DQ39 /DQS5 DQS5 8 DM/ RDQS DQ0 to DQ7 D4 NU/ /CS /RDQS DM/ RDQS DQ0 to DQ7 DQS /DQS D1 DQS14 DQ40 to DQ47 /DQS6 DQS6 8 NU/ /CS /RDQS DM/ RDQS DQ0 to DQ7 DQS /DQS D5 NU/ /CS /RDQS DQS /DQS NU/ /CS /RDQS DQS /DQS DQS11 DQ16 to DQ23 /DQS3 DQS3 DQS12 DQ24 to DQ31 8 8 DM/ RDQS DQ0 to DQ7 D2 DQS15 DQ48 to DQ55 /DQS7 DQS7 8 DM/ RDQS DQ0 to DQ7 D6 NU/ /CS /RDQS DM/ RDQS DQ0 to DQ7 DQS /DQS D3 DQS16 DQ56 to DQ63 /DQS8 8 NU/ /CS DQS /DQS /RDQS DM/ RDQS D7 DQ0 to DQ7 PN0 to PN13 /PN0 to /PN13 PS0 to PS9 /PS0 to /PS9 DQ0 to DQ63 CB0 to CB7 DQS0 to DQS17 /DQS0 to /DQS8 SCL SDA SA0 to SA2 /RESET SCK/ /SCK SN0 to SN13 /SN0 to /SN13 SS0 to SS9 /SS0 to /SS9 DQS8 DQS17 CB0 to CB7 8 NU/ /CS /RDQS DM/ RDQS DQ0 to DQ7 DQS /DQS A M B /CS0 -> /CS (all SDRAMs) CKE0 -> CKE (all SDRAMs) D8 ODT -> ODT (all SDRAMs) BA0, BA1 (all SDRAMs) A0 to A13 (all SDRAMs) /RAS (all SDRAMs) /CAS (all SDRAMs) /WE (all SDRAMs) CK/ /CK SCL Serial PD SDA U0 SDA WP A0 A1 A2 VTT VCC VDDSPD VDD VREF VSS Teminators AMB SPD, AMB D0 to D8, AMB D0 to D8 D0 to D8, SPD, AMB All address/command/control/clock VTT SA0 SA1 SA2 * D0 to D8 : 512M bits DDR2 SDRAM Notes: U0 : 256 bytes EEPROM 1. DQ wiring may be changed within a byte. 2. There are two physical copies of each address/command/control/clock Preliminary Data Sheet E0869E30 (Ver. 3.0) 7 EBE51FD8AGFD, EBE51FD8AGFN Pin Configurations Front side 1 pin 68 pin 69 pin 120 pin 121 pin Back side 188 pin 189 pin 240 pin Front side No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID1 No. Name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 VSS PN5 /PN5 VSS PN13 /PN13 VSS VSS NC NC VSS VSS PN12 /PN12 VSS PN6 /PN6 VSS PN7 /PN7 VSS PN8 /PN8 VSS PN9 /PN9 VSS PN10 /PN10 VSS PN11 /PN11 VSS VSS PS0 No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Name /PS0 VSS PS1 /PS1 VSS PS2 /PS2 VSS PS3 /PS3 VSS PS4 /PS4 VSS VSS NC NC VSS VSS PS9 /PS9 VSS PS5 /PS5 VSS PS6 /PS6 VSS PS7 /PS7 VSS PS8 /PS8 VSS NC No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name NC VSS VDD VDD VSS VDD VDD VDD VSS VDD VDD VTT SA2 SDA SCL Back side No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID0 No. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Name VSS SN5 /SN5 VSS SN13 /SN13 VSS VSS NC NC VSS VSS SN12 /SN12 VSS SN6 /SN6 VSS SN7 /SN7 VSS SN8 /SN8 VSS SN9 /SN9 VSS SN10 /SN10 VSS SN11 /SN11 VSS VSS SS0 No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 Name No. /SS0 VSS SS1 /SS1 VSS SS2 /SS2 VSS SS3 /SS3 VSS SS4 /SS4 VSS VSS NC NC VSS VSS SS9 /SS9 VSS SS5 /SS5 VSS SS6 /SS6 VSS SS7 /SS7 VSS SS8 /SS8 VSS NC 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name NC VSS SCK /SCK VSS VDD VDD VDD VSS VDD VDD VTT VDDSPD SA0 SA1 /RESET 52 VSS NC NC VSS PN0 /PN0 VSS PN1 /PN1 VSS PN2 /PN2 VSS PN3 /PN3 VSS PN4 /PN4 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 M_TEST 172 VSS NC NC VSS SN0 /SN0 VSS SN1 /SN1 VSS SN2 /SN2 VSS SN3 /SN3 VSS SN4 /SN4 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Preliminary Data Sheet E0869E30 (Ver. 3.0) 8 EBE51FD8AGFD, EBE51FD8AGFN Pin Description Pin name SCK, /SCK PN0 to PN13, /PN0 to /PN13 PS0 to PS9, /PS0 to /PS9 SN0 to SN13, /SN0 to /SN13 SS0 to SS9, /SS0 to /SS9 SCL SDA SA0 to SA2* 1 2 Pin Type Input Output Input Input Output Input Input / Output Input Input Input 3 Function System clock input Primary northbound data Primary southbound data Secondary northbound data Secondary southbound data Serial presence detect (SPD) clock input SPD data and AMB SMBus address/data SPD address inputs Voltage ID AMB reset signal VREF margin test input No connection AMB core power and AMB channel interface power (1.5V) DRAM power and AMB DRAM I/O power (1.8V) DRAM address, Command and clock termination voltage (VDD/2) SPD power (3.3V) Ground VID0 to VID1* /RESET M_TEST* NC VCC VDD VTT VDDSPD VSS Input  Power supply Power supply Power supply Power supply  Notes: 1. They are also used to select the DIMM number in the AMB. 2. These pins must be unconnected. 3. Don’t connect in a system. Preliminary Data Sheet E0869E30 (Ver. 3.0) 9 EBE51FD8AGFD, EBE51FD8AGFN Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS AMB core power voltage relative to VSS DRAM interface power voltage relative to VSS Termination voltage relative to VSS Storage temperature Symbol VIN/VOUT VCC VDD VTT Tstg Value –0.3 to +1.75 –0.3 to +1.75 –0.5 to +2.30 –0.5 to +2.30 –55 to +100 Unit V V V V °C Note Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Conditions Parameter SDRAM component case temperature AMB component case temperature Symbol TC_DRAM TC_AMB Value 0 to +95 110 Unit °C °C Note 1 Note: 1. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. DC Operating Conditions Parameter AMB supply voltage DDR2 SDRAM supply voltage Input termination voltage EEPROM supply voltage SPD input high voltage SPD input low voltage RESET input high voltage RESET input low voltage Leakage current (RESET) Leakage current (link) Symbol VCC VDD VTT VDDSPD VIH (DC) VIL (DC) VIH (DC) VIL (DC) IL IL min. 1.455 1.7 0.48 × VDD 3.0 2.1 — 1.0 — –90 –5 typ. 1.50 1.8 0.50 × VDD 3.3 — — — — — — max. 1.575 1.9 0.52 × VDD 3.6 VDDSPD 0.8 — 0.5 90 5 Unit V V V V V V V V µA µA 1 1 2 2 2 3 Note Notes: 1. Applies for SMB and SPD bus signals. 2. Applies for AMB CMOS signal /RESET. 3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification. Preliminary Data Sheet E0869E30 (Ver. 3.0) 10 EBE51FD8AGFD, EBE51FD8AGFN AMB Component Timing For purposes of IDD testing, the following parameters are to be utilized. Parameter EI Assertion pass-thru timing EI deassertion pass-thru timing EI assertion duration Resample pass-thru time Resynch pass-thru Time Bit lock Interval Frame lock Interval tBitLock tFrameLock Symbol tEI propagate tEID tEI min. — — 100 — — — — typ. — — — TBD TBD — — max. 4 bit lock — — — 119 154 Units clks clks clks ns ns frames frames Note Note: 1. The EI stands for ″Electrical Idle″. Power Specification Parameter and Test Conditions -6E Frequency (Mbps) Parameter Symbol Power Supply @1.5V Idle Current, single or last DIMM Idd_Idle_0 @1.8V Total @1.5V Idle Current, first DIMM Idd_Idle_1 @1.8V Total @1.5V Active Power Idd_Active_1 @1.8V Total @1.5V Active Power, Idd_Active_2 data pass through @1.8V Total @1.5V Training Idd_Training (for AMB spec. @1.8V Not in SPD) Total 667 max. 2.60 1.02 5.37 3.40 1.02 6.63 3.90 2.65 10.52 3.70 1.02 7.11 4.00 0.99 7.53 -5C 533 max. 2.20 0.95 4.62 3.00 0.95 5.88 3.40 2.71 9.85 3.20 0.95 6.19 3.50 0.91 6.58 Unit A A W A A W A A W A A W A A W L0 state 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. Primary and secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. L0 state 50% DRAM BW, 67% read, 33% write. Primary and secondary channels enabled. DRAM clock active, CKE high. Conditions L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. DRAM clock active. L0 state, idle (0 BW) Primary and secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. Note Preliminary Data Sheet E0869E30 (Ver. 3.0) 11 EBE51FD8AGFD, EBE51FD8AGFN Reference Clock Input Specifications*1 Parameter Reference clock frequency@ 3.2Gb/s (nominal 133.33MHz) Reference clock frequency@ 4.0 Gb/s (nominal 166.67MHz) Single-ended maximum voltage Single-ended minimum voltage Differential voltage high Differential voltage low Absolute crossing point VCross variation AC common mode Rising and falling edge rates % Mismatch between rise and fall edge rates Duty cycle of reference clock Ringback voltage threshold Allowed time before ringback Clock leakage current Clock input capacitance Clock input capacitance delta Transport delay Symbol fRefclk-3.2 fRefclk-4.0 Vmax Vmin VRefclk-diff-ih VRefclk-diff-il VCross VCross-delta VSCK-cm-acp-p ERRefclk-diff-Rise, ERRefclk-diff-Fall ERRefclk-Match TRefclk-Dutycycle VRB-diff TStable II_CK CI_CK CI_CK (∆) TD NSAMPLE Reference clock jitter (rms), filtered min. 126.67 158.33  −0.3 150  250   0.6  40 −100 500 −10 0.5 −0.25  10 12 max. 133.40 166.75 1.15   −150 550 140 225 4.0 20 60 100  10 2.0 0.25 5  3.0 30 TBD Units MHz MHz V V mV mV mV mV mV V/ns % % mV ps µA pF pF ns periods ps ps ps Notes 2, 3, 4 2, 3, 4 5, 7 5, 8 6 6 5, 9, 10 5, 9, 11 12 6, 13 6, 14 6 6, 15 6, 15 16, 17 17 Difference between RefClk and RefClk# input capacitance 18, 19 20 21, 22 TREF-JITTER-RMS    Reference clock jitter (peak-to-peak) due TREF-SSCp-p to spectrum clocking effects Reference clock jitter difference between TREF-JITTERadjacent AMB DELTA Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”. 2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FBDIMM channel and so on. 3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency. 4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only required for those data rates that are supported by the device under test. 5. Measurement taken from single-ended waveform. 6. Measurement taken from differential waveform. 7. Defined as the maximum instantaneous voltage including overshoot. 8. Defined as the minimum instantaneous voltage including undershoot. 9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in for any particular system. 12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock frequency). Preliminary Data Sheet E0869E30 (Ver. 3.0) 12 EBE51FD8AGFD, EBE51FD8AGFN 13. Measured from −150mV to + 150mV on the differential waveform. The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential 0V crossing. 14. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ± 75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. The rising edge rate of REFCLK+ should be compared to the falling edge rate of REFCLK-. The maximum allowed difference should not exceed 20% of the slowest edge 15. Tstable is the time the differential clock must maintain a minimum ±150mV differential voltage after rising /falling edges before it is allowed to droop back into the ±100mV differential range. 16.Measured with a single-ended input voltage of 1V. 17. Applies to RefClk and RefClk#. 18. This parameter is not a direct clock output parameter but it indirectly determines the clock output parameter TREF-JITTER. 19. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The clock path is defined from the reference clock source to clock arrival at the same sampling point. The path delays are caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these delays are modeled by the PLL transfer functions. 20. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that the jitter will be measured over a smaller, yet statistically significant, sample size and the total jitter at NSAMPLE samples extrapolated from an estimate of the sigma of the random jitter components. 21. Measured with SSC enabled on reference clock generator. 22. As “measured” after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRX-Total-MIN parameters. Preliminary Data Sheet E0869E30 (Ver. 3.0) 13 EBE51FD8AGFD, EBE51FD8AGFN Differential Transmitter Output Specifications*1 Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to-peak output voltage for regular voltage swing Differential peak-to-peak output voltage for small voltage swing DC common code output voltage for large voltage swing DC common code output voltage for small voltage swing De-emphasized differential output voltage ratio for -3.5dB de-emphasis De-emphasized differential output voltage ratio for -6dB de-emphasis Symbol VTX-DIFFp-p_L min. 900 max. 1300 Unit mV Comments VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 VTX-DIFFp-p = 2 × | VTX-D+ − VTX-D- | Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 3 2, 4, 5 VTX-DIFFp-p_R 800  mV VTX-DIFFp-p_S 520  mV VTX-CM_L  375 mV VTX-CM_S 135 280 mV VTX-DE-3.5-Ratio −3.0 −5.0 −4.0 −7.0 dB VTX-DE-6.0-Ratio dB 2, 4, 5 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 – Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 7, 8 AC peak-to-peak common mode output voltage for large VTX-CM-ACp-p L swing AC peak-to-peak common mode output voltage for regular swing  90 mV VTX-CM-ACp-p R  80 mV AC peak-to-peak common mode output voltage for small VTX-CM-ACp-p S swing Maximum single-ended voltage in EI condition, DC + AC Maximum single-ended voltage in EI condition, DC only Maximum peak-to-peak differential voltage in EI condition Single-ended voltage (w.r.t.VSS) on D+/DMinimum TX eye width Maximum TX deterministic jitter Instantaneous pulse width  70 mV VTX-IDLE-SE  50 mV VTX-IDLE-SE-DC  20 mV 7, 8, 9 VTX-IDLE-DIFFp-p VTX-SE TTX-Eye-MIN TTX-DJ-DD TTX-PULSE  −75 0.7  0.85 30  8 6 40 750  0.2  90 20   mV mV UI UI UI ps ps dB dB 8 2, 10 2, 11, 12 2, 11, 12, 13 14 Given by 20%-80% voltage levels. Measured as note 2 Differential TX output rise/fall TTX-RISE, time TTX-FALL Mismatch between rise and TTX-RF-MISMATCH fall times Differential return loss Common mode return loss RLTX-DIFF RLTX-CM Measured over 0.1GHz to 2.4GHz. See also note 15 Measured over 0.1GHz to 2.4GHz. See also note 15 Preliminary Data Sheet E0869E30 (Ver. 3.0) 14 EBE51FD8AGFD, EBE51FD8AGFN Parameter Transmitter termination resistance Symbol RTX min. 41 max. 55 Unit Ω Comments 16 RTX-Match-DC = 2×|RTX-D+ − RTX-D-| / (RTX-D+ + RTX-D-) Bounds are applied separately to high and low output voltage states 17, 19 18, 19 20 20 21 D+/D- TX resistance difference RTX-Match-DC  4 % Lane-to-lane skew at TX Lane-to-lane skew at TX Maximum TX Drift (resync mode) Maximum TX Drift (resample mode only) Bit Error Ratio LTX-SKEW 1 LTX-SKEW 2   100 + 3UI ps 100 + 2UI ps 240 120 10 -12 TTX-DRIFT-RESYNC  TTX-DRIFTRESAMPLE BER   ps ps Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”. 2. Specified at the package pins into a timing and voltage compliance test load. Common-mode measurements to be performed using a 101010 pattern. 3. The transmitter designer should not artificially elevate the common mode in order to meet this specification. 4. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. 5. De-emphasis shall be disabled in the calibration state. 6. Includes all sources of AC common mode noise. 7. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle condition. 8. Specified at the package pins into a voltage compliance test load. Transmitters must meet both singleended and differential output EI specifications. 9. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered. 10. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2) 11. This number does not include the effects of SSC or reference clock jitter. 12. These timing specifications apply to resync mode only. 13. Defined as the dual-dirac deterministic jitter. 14. Pulse width measured at 0 V differential. 15. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin. 17. Lane to Lane skew at the Transmitter pins for an end component. 18. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT). 19. This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship after initialization. 20. Measured from the reference clock edge to the center of the output eye. This specification must be met across specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver. 21. BER per differential lane. Preliminary Data Sheet E0869E30 (Ver. 3.0) 15 EBE51FD8AGFD, EBE51FD8AGFN Differential Receiver Input Specifications*1 Parameter Differential peak-to-peak input voltage Maximum single-ended voltage for EI condition (AC + DC) Maximum single-ended voltage for EI condition (DC only) Maximum peak-to-peak differential voltage for EI condition Single-ended voltage (w.r.t. VSS) on D+/DSingle-pulse peak differential input voltage Amplitude ratio between adjacent symbols, 1100mV < VRX-DIFFp-p