PRELIMINARY DATA SHEET
1G bits DDR3 SDRAM
EDJ1104BDSE (256M words × 4 bits) EDJ1108BDSE (128M words × 8 bits)
Specifications
• Density: 1G bits • Organization 32M words × 4 bits × 8 banks (EDJ1104BDSE) 16M words × 8 bits × 8 banks (EDJ1108BDSE) • Package 78-ball FBGA Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V • Data rate 1600Mbps/1333Mbps/1066Mbps (max.) • 1KB page size Row address: A0 to A13 Column address: A0 to A9, A11 (EDJ1104BDSE) A0 to A9 (EDJ1108BDSE) • Eight internal banks for concurrent operation • Interface: SSTL_15 • Burst lengths (BL): 8 and 4 with Burst Chop (BC) • Burst type (BT): Sequential (8, 4 with BC) Interleave (8, 4 with BC) • /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11 • /CAS Write Latency (CWL): 5, 6, 7, 8 • Precharge: auto precharge option for each burst access • Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω) • Refresh: auto-refresh, self-refresh
Features
• Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT • Multi Purpose Register (MPR) for temperature read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • /RESET pin for Power-up sequence and reset function • SRT range: Normal/extended • Programmable Output driver impedance control
• Refresh cycles
Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C
Document No. E1494E50 (Ver. 5.0) Date Published July 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2009
EDJ1104BDSE, EDJ1108BDSE
Ordering Information
P art number EDJ1104BDSE-GL-F EDJ1104BDSE-GN-F EDJ1104BDSE-DJ-F EDJ1104BDSE-AE-F E DJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-DJ-F EDJ1108BDSE-AE-F Die revision D Organization (words × b its) 256M × 4 Internal banks 8 JEDEC speed bin (CL-tRCD-tRP) D DR3-1600J (10-10-10) DDR3-1600K (11-11-11) DDR3-1333H (9-9-9) DDR3-1066F (7-7-7) D DR3-1600J (10-10-10) DDR3-1600K (11-11-11) DDR3-1333H (9-9-9) DDR3-1066F (7-7-7) Package 78-ball FBGA
128M × 8
Part Number
E D J 11 04 B D SE - GL - F
Elpida Memory
Type D: Monolithic Device
Environment code F: Lead Free (RoHS compliant) and Halogen Free
Product Family J: DDR3
Density / Bank 11: 1Gb / 8-bank
Speed GL: DDR3-1600J (10-10-10) GN: DDR3-1600K (11-11-11) DJ: DDR3-1333H (9-9-9) AE: DDR3-1066F (7-7-7)
Organization 04: x4 08: x8
Package SE: FBGA
Power Supply, Interface B: 1.5V, SSTL_15
Die Rev.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Pin Configurations
/xxx indicates active low signal.
78-ball FBGA (×4 configuration) 1 A VSS B VSS VSSQ C VDDQ D VSSQ E VREFDQ VDDQ F NC G ODT H NC J VSS K VDD L VSS M N VSS /RESET A13 (Top view) NC A8 VSS VDD A5 A7 A2 A9 A1 A11 A4 A6 VSS VDD M N VSS /RESET A13 (Top view) NC A8 VSS A3 A0 A12(/BC) BA1 VDD L VSS VDD A5 A7 A2 A9 A1 A11 A4 A6 VSS VDD BA0 BA2 NC VREFCA VSS K VDD A3 A0 A12(/BC) BA1 VDD /CS /WE A10(AP) ZQ NC J VSS BA0 BA2 NC VREFCA VSS VDD /CAS /CK VDD CKE H NC /CS /WE A10(AP) ZQ NC VSS /RAS CK VSS NC G ODT VDD /CAS /CK VDD CKE NC NC NC VDDQ F NC VSS /RAS CK VSS NC NC /DQS VDD VSS VSSQ E VREFDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ D VSSQ DQ6 /DQS DQ4 VDD DQ7 VSS DQ5 VSSQ VDDQ DQ0 DM VSSQ VDDQ C VDDQ DQ2 DQS DQ1 DQ3 VSSQ VDD NC NC VSS VDD B VSS VSSQ DQ0
DM/TDQS VSSQ VDDQ
78-ball FBGA (×8 configuration) 9 A VSS VDD NC
NU/(/TDQS) VSS
2
3
7
8
1
2
3
7
8
9 VDD
P in name A0 to A13*
3
Function A ddress inputs A10 (AP): Auto precharge A12(/BC): Burst chop
3
Pin name /RESET* VDD VSS VDDQ VSSQ VREFDQ VREFCA ZQ NC* NU*
1 2 3
Function A ctive low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage Reference pin for ZQ calibration N o connection N ot usable
BA0 to BA2* D Q0 to DQ7 D QS, /DQS
B ank select Data input/output Differential data strobe Termination data strobe C hip select
3
T DQS, /TDQS / CS*
3
/ RAS, /CAS, /WE* C KE*
3
C ommand input C lock enable Differential clock input Write data mask
C K, /CK DM O DT*
3
O DT control
Notes: 1. Not internally connected with die. 2. Don’t connect. Internally connected. 3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Conditions ......................................................................................................................................6
Absolute Maximum Ratings .......................................................................................................................... 6 Operating Temperature Condition ................................................................................................................ 6 Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................... 7 AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)....................... 7 VREF Tolerances ......................................................................................................................................... 8 Input Slew Rate Derating .............................................................................................................................. 9 AC and DC Logic Input Levels for Differential Signals ................................................................................ 15 AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) .................. 20 AC Overshoot/Undershoot Specification..................................................................................................... 22 Output Driver Impedance............................................................................................................................ 23 On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 25 ODT Timing Definitions............................................................................................................................... 27 IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................... 31
Electrical Specifications...............................................................................................................................44
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 44 DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 45 Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V) ..................................................................... 46 Standard Speed Bins .................................................................................................................................. 47 AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)....................... 50
Block Diagram .............................................................................................................................................64 Pin Function.................................................................................................................................................65 Command Operation ...................................................................................................................................67
Command Truth Table ................................................................................................................................ 67 CKE Truth Table ......................................................................................................................................... 71
Simplified State Diagram .............................................................................................................................72 RESET and Initialization Procedure ............................................................................................................73
Power-Up and Initialization Sequence ........................................................................................................ 73 Reset and Initialization with Stable Power .................................................................................................. 74
Programming the Mode Register.................................................................................................................75
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 75 MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 75 DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 76 DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 77
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 77 DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 78 DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 79 Burst Length (MR0) .................................................................................................................................... 80 Burst Type (MR0) ....................................................................................................................................... 80 DLL Enable (MR1) ...................................................................................................................................... 81 DLL-off Mode .............................................................................................................................................. 81 DLL on/off switching procedure .................................................................................................................. 82 Additive Latency (MR1)............................................................................................................................... 84 Write Leveling (MR1) .................................................................................................................................. 85 TDQS, /TDQS function (MR1) .................................................................................................................... 88 Extended Temperature Usage (MR2) ......................................................................................................... 89 Multi Purpose Register (MR3)..................................................................................................................... 91
Operation of the DDR3 SDRAM ..................................................................................................................98
Read Timing Definition................................................................................................................................ 98 Read Operation ........................................................................................................................................ 102 Write Timing Definition.............................................................................................................................. 109 Write Operation......................................................................................................................................... 110 Write Timing Violations ............................................................................................................................. 116 Write Data Mask ....................................................................................................................................... 117 Precharge ................................................................................................................................................. 118 Auto Precharge Operation ........................................................................................................................ 119 Auto-Refresh............................................................................................................................................. 120 Self-Refresh.............................................................................................................................................. 121 Power-Down Mode ................................................................................................................................... 122 Input Clock Frequency Change during Precharge Power-Down............................................................... 129 On-Die Termination (ODT)........................................................................................................................ 130 ZQ Calibration........................................................................................................................................... 142
Package Drawing ......................................................................................................................................144
78-ball FBGA ............................................................................................................................................ 144
Recommended Soldering Conditions........................................................................................................145
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Electrical Conditions
• All voltages are referenced to VSS (GND) • Execute power-up and Initialization sequence before proper device operation is achieved. Absolute Maximum Ratings
P arameter Power supply voltage P ower supply voltage for output I nput voltage O utput voltage R eference voltage R eference voltage for DQ S torage temperature P ower dissipation S hort circuit output current Symbol VDD VDDQ VIN VOUT VREFCA VREFDQ Tstg PD IOUT Rating − 0.4 to +1.975 − 0.4 to +1.975 − 0.4 to +1.975 − 0.4 to +1.975 − 0.4 to 0.6 × V DD − 0.4 to 0.6 × V DDQ − 55 to +100 1.0 50 Unit V V V V V V °C W mA Notes 1, 3 1, 3 1 1 3 3 1, 2 1 1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 × VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Condition
P arameter Operating case temperature Symbol TC Rating 0 to +95 Unit °C Notes 1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
P arameter Supply voltage S upply voltage for DQ I nput reference voltage I nput reference voltage for DQ Symbol VDD VDDQ min. 1.425 1.425 typ. 1.5 1.5 0.50 × V DD 0.50 × V DDQ max. 1.575 1.575 0.51 × V DD 0.51 × V DDQ Unit V V V V Notes 1, 2 1, 2 3, 4 3, 4
VREFCA (DC) 0.49 × V DD VREFDQ (DC) 0.49 × V DDQ
Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx ±15 mV). 4. For reference: approx. VDD/2 ± 15 mV. AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) Single-Ended AC and DC Input Levels for Command and Address
P arameter DC input logic high D C input logic low A C input logic high A C input logic low A C input logic high A C input logic low Symbol VIHCA (DC) VILCA (DC) VIHCA (AC) VILCA (AC) VIHCA (AC150) VILCA (AC150) min. VREF + 0 .100 VSS VREF + 0 .175 *
2
typ.
max. V DD V REF − 0 .100 *
2
Unit V V V V V V
Notes 1 1 1 1 1 1
V REF − 0 .175 *
2
VREF + 0 .150 *
2
V REF − 0 .150
Notes: 1. For input only pins except /RESET; VREF = VREFCA. 2. See Overshoot and Undershoot Specifications section. Single-Ended AC and DC Input Levels for DQ and DM
P arameter DC input logic high D C input logic low A C input logic high DDR3-1066 D DR3-1333, 1600 A C input logic low DDR3-1066 D DR3-1333, 1600 Symbol VIHDQ (DC) VILDQ (DC) VIHDQ (AC) VIHDQ (AC) VILDQ (AC) VILDQ (AC) min. VREF + 0 .100 VSS VREF + 0 .175 VREF + 0 .150 * *
2 2
typ.
max. V DD V REF − 0 .100 * *
2 2
Unit V V V V V V
Notes 1 1 1 1 1 1
V REF − 0 .175 V REF − 0 .150
Notes: 1. For DQ and DM: VREF = VREFDQ. 2. See Overshoot and Undershoot Specifications section.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are shown in Figure VREF(DC) Tolerance and VREF AC-Noise Limits. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table of(Single-Ended AC and DC Input Levels for Command and Address). Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD.
voltage
VDD
VREF AC-noise VREF(DC)
VREF(t)
VREF(DC)max. VDD/2 VREF(DC)min.
VSS time
VREF(DC) Tolerance and VREF AC-Noise Limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. VREF shall be understood as VREF(DC), as defined in figure above, VREF(DC) Tolerance and VREF AC-Noise Limits. This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (±1% of VDD) are included in DRAM timings and their associated deratings.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Input Slew Rate Derating For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the ∆tIS, ∆tDS and ∆tIH, ∆tDH derating value respectively. Example: tDS (total setup time) = tDS (base) + ∆tDS. Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure of Slew Rate Definition Tangent). Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’, the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value (see the figure of Slew Rate Definition Tangent). For a valid transition the input signal has to remain above/below VIH/VIL(AC) for some time tVAC (see the table of Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL (AC). For slew rates in between the values listed in the tables below, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
[Address/Command Setup and Hold Base-Values for 1V/ns]
D DR3-1066 tIS(base) t IH(base) t IS(base) AC150 125 200 125 + 150 DDR3-1333 65 140 65 + 125 DDR3-1600 45 120 45 + 125 Unit ps ps ps Reference VIH/VIL(AC) VIH/VIL(DC) VIH/VIL(AC)
Notes: 1 AC/DC referenced for 1V/ns Address/Command slew rate and 2V/ns differential CK, /CK slew rate. 2. The tHS (base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv − 150mv)/1V/ns]
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Derating Values of tIS/tIH AC/DC based (DDR3-1066, 1333, 1600)]
∆ tIS, ∆ tIH derating in [ps] AC/DC based AC175 Threshold -> VIH(AC)=VREF(DC)+175mV, VIL(AC)=VREF(DC)-175mV CK, /CK differential slew rate 4 .0 V/ns ∆ tIS 2 .0 1 .5 1 .0 C MD, ADD 0 .9 slew 0 .8 rate 0 .7 (V/ns) 0 .6 0 .5 0.4 +88 +59 0 −2 −6 − 11 − 17 − 35 − 62 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 3.0 V/ns ∆ tIS +88 +59 0 −2 −6 − 11 − 17 − 35 − 62 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 2.0 V/ns ∆ tIS +88 +59 0 −2 −6 − 11 − 17 − 35 − 62 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 1.8 V/ns ∆ tIS +96 +67 +8 +6 +2 −3 −9 − 27 − 54 ∆ tIH +58 +42 +8 +4 −2 −8 − 18 − 32 − 52 1.6 V/ns ∆ tIS ∆ tIH 1.4 V/ns ∆ tIS ∆ tIH 1.2 V/ns ∆ tIS ∆ tIH 1.0 V/ns ∆ tIS ∆ tIH Unit
+104 +66 +75 +16 +14 +10 +5 −1 − 19 − 46 +50 +16 +12 +6 0 − 10 − 24 − 44
+112 +74 +83 +24 +22 +18 +13 +7 − 11 − 38 +58 +24 +20 +14 +8 −2 − 16 − 36
+120 +84 +91 +32 +30 +26 +21 +15 −2 − 30 +68 +34 +30 +24 +18 +8 −6 − 26
+128 +100 ps +99 +40 +38 +34 +29 +23 +5 − 22 +84 +50 +46 +40 +34 +24 +10 − 10 ps ps ps ps ps ps ps ps
[Derating Values of tIS/tIH AC/DC based-Alternate AC150 Threshold (DDR3-1066, 1333, 1600)]
∆ tIS, ∆ tIH derating in [ps] AC/DC based Alternate AC150 Threshold -> VIH(AC)=VREF(DC)+150mV, VIL(AC)=VREF(DC)-150mV CK, /CK differential slew rate 4 .0 V/ns ∆ tIS 2 .0 1 .5 1 .0 C MD, ADD 0 .9 slew 0 .8 rate 0 .7 (V/ns) 0 .6 0 .5 0.4 +75 +50 0 0 0 0 −1 − 10 − 25 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 3.0 V/ns ∆ tIS +75 +50 0 0 0 0 −1 − 10 − 25 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 2.0 V/ns ∆ tIS +75 +50 0 0 0 0 −1 − 10 − 25 ∆ tIH +50 +34 0 −4 − 10 − 16 − 26 − 40 − 60 1.8 V/ns ∆ tIS +83 +58 +8 +8 +8 +8 +7 −2 − 17 ∆ tIH +58 +42 +8 +4 −2 −8 − 18 − 32 − 52 1.6 V/ns ∆ tIS +91 +66 +16 +16 +16 +16 +15 +6 −9 ∆ tIH +66 +50 +16 +12 +6 0 − 10 − 24 − 44 1.4 V/ns ∆ tIS +99 +74 +24 +24 +24 +24 +23 +14 −1 ∆ tIH +74 +58 +24 +20 +14 +8 −2 − 16 − 36 1.2 V/ns ∆ tIS ∆ tIH 1.0 V/ns ∆ tIS ∆ tIH Unit
+107 +84 +82 +32 +32 +32 +32 +31 +22 7 +68 +34 +30 +24 +18 +8 −6 − 26
+115 +100 ps +90 +40 +40 +40 +40 +39 +30 15 +84 +50 +46 +40 +34 +24 +10 − 10 ps ps ps ps ps ps ps ps
[Required time tVAC above VIH(AC) {below VIL(AC)} for Valid Transition]
t VAC @ 175 mV[ps] Slew rate (V/ns) > 2.0 2 .0 1 .5 1 .0 0 .9 0 .8 0 .7 0 .6 0 .5 < 0.5 min. 75 57 50 38 34 29 22 13 0 0 max. tVAC @ 150 mV[ps] min. 1 75 1 70 1 67 1 63 1 62 1 61 1 59 1 55 1 50 1 50 max.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Data Setup and Hold Base-Values]
D DR3-1066 tDS(base) t DH(base) 25 100 DDR3-1333 30 65 DDR3-1600 10 45 Unit ps ps Reference VIH/VIL(AC) VIH/VIL(DC)
Note: 1
AC/DC referenced for 1V/ns DQ slew rate and 2V/ns DQS slew rate
[Derating Values of tDS/tDH AC/DC based (DDR3-1066)]
∆ tDS, ∆ tDH derating in [ps] AC/DC based DQS, /DQS differential slew rate 4 .0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH Unit 2 .0 1 .5 1 .0 DQ 0 .9 slew 0 .8 rate (V/ns) 0 .7 0 .6 0 .5 0.4 +88 +59 0 +50 +34 0 +88 +59 0 −2 +50 +34 0 −4 +88 +59 0 −2 −6 +50 +34 0 −4 − 10 +67 +8 +6 +2 −3 +42 +8 +4 −2 −8 +16 +14 +10 +5 −1 +16 +12 +6 0 − 10 +22 +18 +13 +7 − 11 +20 +14 +8 −2 − 16 +26 +21 +15 −2 − 30 +24 +18 +8 −6 − 26 +29 +23 +5 − 22 +34 +24 +10 − 10 ps ps ps ps ps ps ps ps ps
[Derating Values of tDS/tDH AC/DC based (DDR3-1333, 1600)]
∆ tDS, ∆ tDH derating in [ps] AC/DC based DQS, /DQS differential slew rate 4 .0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH ∆ tDS ∆ tDH Unit 2 .0 1 .5 1 .0 DQ 0 .9 slew 0 .8 rate (V/ns) 0 .7 0 .6 0 .5 0.4 +75 +59 0 +50 +34 0 +75 +59 0 0 +50 +34 0 −4 +75 +59 0 0 +50 +34 0 −4 − 10 +58 +8 +8 +8 +8 +42 +8 +4 −2 −8 +16 +16 +16 +16 + 15 +16 +12 +6 0 − 10 +24 +24 +24 +23 + 14 +20 +14 +8 −2 − 16 +32 +32 +31 +22 +7 +24 +18 +8 −6 − 26 +40 +39 +30 +15 +34 +24 +10 − 10 ps ps ps ps ps ps ps ps ps
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition]
D DR3-1066 tVAC [ps] S lew rate (V/ns) > 2.0 2 .0 1 .5 1 .0 0 .9 0 .8 0 .7 0 .6 0 .5 < 0.5 min. 75 57 50 38 34 29 22 13 0 0 max. DDR3-1333, 1600 tVAC [ps] min. 1 75 1 70 1 67 1 63 1 62 1 61 1 59 1 55 1 50 1 50 max.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
CK /CK
tIS
tIH
tIS
tIH
VDD
tVAC
VIH (AC) min. VREF to AC region VIH (DC) min. DC to VREF region nominal slew rate nominal slew rate DC to VREF region
VREF (DC)
VIL (DC) max.
VIL (AC) max.
tVAC
VREF to AC region
VSS ∆TFS ∆TRH ∆TRS ∆TFH
Slew Rate Definition Nominal (CK, /CK)
/DQS
DQS tDS VDD tVAC VIH (AC) min. VREF to AC region VIH (DC) min. DC to VREF region nominal slew rate nominal slew rate DC to VREF region tDH tDS tDH
VREF (DC)
VIL (DC) max.
VIL (AC) max. tVAC VSS ∆TFS ∆TRH ∆TRS
VREF to AC region
∆TFH
Slew Rate Definition Nominal (DQS, /DQS)
VREF (DC) - VIL (AC) max. Setup slew rate = Falling signal ∆TFS
VIH (AC) min. - VREF (DC) Setup slew rate = Rising signal ∆TRS Hold slew rate Falling signal = VIH (DC) min. - VREF (DC)
Hold slew rate Rising signal
=
VREF (DC) - VIL (DC) max.
∆TRH
∆TFH
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
CK /CK tIS VDD tVAC VIH (AC) min. VREF to AC region VIH (DC) min. DC to VREF region tangent line nominal line nominal line tIH tIS tIH
VREF (DC)
tangent line DC to VREF region
VIL (DC) max. nominal line VIL (AC) max. tVAC ∆TFS ∆TRH
nominal line
VREF to AC region
VSS
∆TRS
∆TFH
Slew Rate Definition Tangent (CK, /CK)
/DQS
DQS
tDS
tDH
tDS
tDH
VDD
tVAC
VIH (AC) min. VREF to AC region VIH (DC) min. DC to VREF region tangent line nominal line nominal line
VREF (DC)
tangent line DC to VREF region
VIL (DC) max. nominal line VIL (AC) max.
tVAC
nominal line
VREF to AC region
VSS
∆TFS
∆TRH
∆TRS
∆TFH
Slew Rate Definition Tangent (DQS, /DQS)
tangent line [VREF (DC) - VIL (AC) max.] Setup slew rate = Falling signal ∆TFS
tangent line [VIH (AC) min. - VREF (DC)] Setup slew rate = Rising signal ∆TRS Hold slew rate Falling signal = tangent line [VIH (DC) min. - VREF (DC)]
Hold slew rate Rising signal
=
tangent line [VREF (DC) - VIL (DC) max.]
∆TRH
∆TFH
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
AC and DC Logic Input Levels for Differential Signals Differential signal definition
tDVAC
Differential Input Voltage (i.e. DQS - /DQS, CK - /CK)
VIH.DIFF.AC.min.
VIH.DIFF.min.
0
half cycle
VIL.DIFF.max.
VIL.DIFF.AC.max. tDVAC
time
Definition of Differential AC-swing and “time above AC-level” tDVAC
[Differential AC and DC Input Levels]
P arameter Differential input logic high D ifferential input logic low D ifferential input logic AC D ifferential input logic AC Symbol VIHdiff VILdiff min. + 0.200 *
3
typ.
max. *
3
Unit V V V
Notes 1 1 2 2
– 0.200 *
3
2 × ( VIH (AC) − VIHdiff (AC) V REF) VILdiff (AC) *
3
2 × ( VREF − V IL(AC)) V
Notes: 1 Used to define a differential signal slew-rate. 2. For CK, /CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, /DQS) use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3 These values are not defined, however the single ended components of differential signal CK, /CK, DQS, /DQS to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and Undershoot specifications.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition]
@ [VIH/Ldiff (AC)] = 350 mV tDVAC [ps] S lew rate (V/ns) > 4.0 4 .0 3 .0 2 .0 1 .8 1 .6 1 .4 1 .2 1 .0 < 1.0 min. 75 57 50 38 34 29 22 13 0 0 max. @[VIH/Ldiff (AC)] = 300 mV tDVAC [ps] min. 1 75 1 70 1 67 1 63 1 62 1 61 1 59 1 55 1 50 1 50 max.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Single-Ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain requirements for single-ended signals. CK and /CK have to approximately reach VSEH min. / VSEL max. (approximately equal to the AC-levels (VIH(AC) / VIL(AC)) for Address/command signals) in every half-cycle. DQS, /DQS have to reach VSEH min./VSEL max. (approximately the AC-levels (VIH(AC) / VIL(AC)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for Address/command and DQ’s might be different per speed-bin etc. E.g. if VIH 150 (AC)/VIL 150 (AC) is used for Address/command signals, then these ac-levels apply also for the single ended components of differential CK and /CK.
VDD or VDDQ
VSEH min.
VSEH
VDD/2 or VDDQ/2 CK or DQS
VSEL max.
VSS or VSSQ
Single-Ended Requirement for Differential Signals.
VSEL
time
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Single-ended levels for CK, DQS, /CK, /DQS]
P arameter Single-ended high level for strobes S ingle-ended high level for CK, /CK S ingle-ended low level for strobes S ingle-ended low level for CK, /CK Symbol VSEH min. typ. max. * *
3 3
Unit V V
Notes 1, 2 1, 2 1, 2 1, 2
(VDD/2) + 0 .175 (VDD/2) + 0 .175 * *
3 3
VSEL
( VDD/2) − 0 .175 V ( VDD/2) − 0 .175 V
Notes: 1. For CK, /CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, /DQS) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3 These values are not defined, however the single ended components of differential signals CK, /CK, DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and Undershoot specifications. To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, /CK and DQS, /DQS) must meet the requirements in table above. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS.
VDD CK, DQS
VIX VDD/2 VIX /CK, /DQS VSS VIX
VIX Definition
[Cross point voltage for differential input signals (CK, DQS)]
P arameter Differential input cross point voltage relative to VDD/2 Symbol VIX pins CK, /CK min. − 150 − 175 V IX DQS, /DQS − 150 max. 150 1 75 1 50 Unit mV mV mV 1 Note
Note: 1. Extended range for VIX is only allowed for clock and if CK and /CK are monotonic, have a single-ended swing VSEL/VSEH of at least VDD/2 +/-250 mV, and the differential slew rate of CK - /CK is larger than 3 V/ ns. Refer to the table of Cross point voltage for differential input signals (CK, DQS) for VSEL and VSEH standard values.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Differential Input Slew Rate Definition]
M easured Description D ifferential input slew rate for rising edge (CK - /CK and DQS - /DQS) D ifferential input slew rate for falling edge (CK - /CK and DQS - /DQS) From VILdiff (max.) To VIHdiff (min.) Defined by VIHdiff (min.) – VILdiff (max.) ∆ TRdiff VIHdiff (min.) – VILdiff (max.) ∆ TFdiff Applicable for Note
VIHdiff (min.)
VILdiff (max.)
Note: The differential signal (i.e. CK, /CK and DQS, /DQS) must be linear between these thresholds.
VIHdiff(min.) 0 VILdiff (max.)
∆TFdiff
∆TRdiff
Falling slew =
VIHdiff (min.) − VILdiff (max.) ∆TFdiff
Rising slew =
VIHdiff (min.) − VILdiff (max.) ∆TRdiff
Differential Input Slew Rate Definition for DQS, /DQS and CK, /CK
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
P arameter DC output high measurement level (for IV curve linearity) D C output middle measurement level (for IV curve linearity) D C output low measurement level (for IV curve linearity) A C output high measurement level (for output slew rate) A C output low measurement level (for output slew rate) A C differential output high measurement level (for output slew rate) A C differential output low measurement level (for output slew rate) A C differential cross point voltage Symbol VOH (DC) VOM (DC) VOL (DC) VOH (AC) VOL (AC) VOHdiff VOLdiff VOX (AC) Specification 0.8 × V DDQ 0.5 × V DDQ 0.2 × V DDQ VTT + 0.1 × V DDQ VTT − 0 .1 × V DDQ 0.2 × V DDQ − 0.2 × V DDQ TBD Unit V V V V V V V V 1 1 2 2 Notes
Notes: 1. The swing of ±0.1 × VDDQ is based on approximately swing with a driver impedance of 34Ω and an effective differential outputs. 2. The swing of ±0.2 × VDDQ is based on approximately swing with a driver impedance of 34Ω and an effective differential outputs.
50% of the static single-ended output high or low test load of 25Ω to VTT = VDDQ/2 at each of the 50% of the static single-ended output high or low test load of 25Ω to VTT = VDDQ/2 at each of the
Output Slew Rate Definitions [Single-Ended Output Slew Rate Definition]
M easured Description O utput slew rate for rising edge O utput slew rate for falling edge From VOL (AC) VOH (AC) To VOH (AC) VOL (AC) Defined by VOH (AC) – VOL (AC) ∆ TRse VOH (AC) – VOL (AC) ∆ TFse
VOH (AC) VTT VOL (AC)
∆TFse
∆TRse
Falling slew =
VOH (AC) − VOL (AC) ∆TFse
Rising slew =
VOH (AC) − VOL (AC) ∆TRse
Input Slew Rate Definition for Single-Ended Signals
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[Differential Output Slew Rate Definition]
M easured Description D ifferential output slew rate for rising edge D ifferential output slew rate for falling edge From VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) Defined by VOHdiff(AC) – VOLdiff (AC) ∆ TRdiff VOHdiff (AC) – VOLdiff (AC) ∆ TFdiff
VOHdiff (AC) 0 VOLdiff (AC)
∆TFdiff
∆TRdiff
Falling slew =
VOHdiff (AC) − VOLdiff (AC) ∆TFdiff
Rising slew =
VOHdiff (AC) − VOLdiff (AC) ∆TRdiff
Differential Input Slew Rate Definition for DQS, /DQS and CK, /CK Output Slew Rate (RON = RZQ/7 setting)
P arameter Output slew rate (Single-ended) O utput slew rate (Differential) Symbol SRQse Speed DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1066 DDR3-1333 DDR3-1600 min. 2.5 max. 5 Unit V/ns Notes 1
SRQdiff
5
10
V/ns
1
Remark: SR = slew rate. se = single-ended signals. diff = differential signals. Q = Query output Note: 1.In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. (a) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). (b) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5V/ns applies. Reference Load for AC Timing and Output Slew Rate
VDDQ
DUT
CK, /CK
DQ DQS, /DQS
VTT = VDDQ/2
25Ω
Reference Output Load
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
AC Overshoot/Undershoot Specification
P arameter Maximum peak amplitude allowed for overshoot M aximum peak amplitude allowed for undershoot M aximum overshoot area above VDD DDR3-1600 D DR3-1333 D DR3-1066 M aximum undershoot area below VSS DDR3-1600 D DR3-1333 D DR3-1066 M aximum peak amplitude allowed for overshoot M aximum peak amplitude allowed for undershoot M aximum overshoot area above VDD DDR3-1600 D DR3-1333 D DR3-1066 M aximum undershoot area below VSS DDR3-1600 D DR3-1333 D DR3-1066 M aximum peak amplitude allowed for overshoot M aximum peak amplitude allowed for undershoot M aximum overshoot area above VDDQ DDR3-1600 D DR3-1333 D DR3-1066 M aximum undershoot area below VSSQ DDR3-1600 D DR3-1333 D DR3-1066 DQ, DQS, /DQS, DM CK, /CK Pins Command, Address, CKE, ODT Specification 0.4V 0.4V 0.33V-ns 0.4V-ns 0.5V-ns 0.33V-ns 0.4V-ns 0.5V-ns 0.4V 0.4V 0.13V-ns 0.15V-ns 0.19V-ns 0.13V-ns 0.15V-ns 0.19V-ns 0.4V 0.4V 0.13V-ns 0.15V-ns 0.19V-ns 0.13V-ns 0.15V-ns 0.19V-ns
Maximum amplitude Overshoot area
Volts (V)
VDD, VDDQ VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Output Driver Impedance RON will be achieved by the DDR3 SDRAM after proper I/O calibration. Tolerance and linearity requirements are referred to the Output Driver DC Electrical Characteristics table. A functional representation of the output buffer is shown in the figure Output Driver: Definition of Voltages and Currents. RON is defined by the value of the external reference resistor RZQ as follows: • RON40 = RZQ/6 • RON34 = RZQ/7 The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
P arameter Output driver pull-up impedance O utput driver pull-down impedance Symbol RONPu RONPd
Chip in Drive Mode Output Driver VDDQ IPu To other circuitry like RCV, ... RONPu
DQ
Definition VDDQ − V OUT IOUT VOUT IOUT
Conditions R ONPd is turned off R ONPu is turned off
IOut
RONPd
VOut
IPd
VSSQ
Output Driver: Definition of Voltages and Currents
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Output Driver DC Electrical Characteristics (RZQ = 240Ω, entire operating temperature range; after proper ZQ calibration)
R ONnom Resistor 40 Ω R ON40Pd VOUT VOL (DC) = 0.2 × VDDQ VOM (DC) = 0.5 × VDDQ VOH (DC) = 0.8 × VDDQ VOL (DC) = 0.2 × VDDQ VOM (DC) = 0.5 × VDDQ VOH (DC) = 0.8 × VDDQ VOL (DC) = 0.2 × VDDQ VOM (DC) = 0.5 × VDDQ VOH (DC) = 0.8 × VDDQ VOL (DC) = 0.2 × VDDQ VOM (DC) = 0.5 × VDDQ VOH (DC) = 0.8 × VDDQ min. 0.6 0.9 0.9 0.9 0.9 0.6 0.6 0.9 0.9 0.9 0.9 0.6 − 10 nom. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 max. 1.1 1.1 1.4 1.4 1.1 1.1 1.1 1.1 1.4 1.4 1.1 1.1 10 Unit Notes
RZQ/6 1, 2, 3
R ON40Pu
RZQ/6 1, 2, 3
34Ω
R ON34Pd
RZQ/7 1, 2, 3
R ON34Pu
RZQ/7 1, 2, 3 % 1, 2, 4
M ismatch between pull-up and pull down, MMPuPd VOM (DC) = 0.5 × VDDQ
Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 × VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, both at 0.5 × VDDQ:
MMPuPd = RONPu - RONPd × 100 RONnom
Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the table Output Driver Sensitivity Definition and Output Driver Voltage and Temperature Sensitivity. ∆T = T − T (@calibration); ∆V= VDDQ − VDDQ (@calibration); VDD = VDDQ Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. [Output Driver Sensitivity Definition]
m in RONPu@VOH (DC) 0.6 − d RONdTH × | ∆ T| − d RONdVH × | ∆ V| R ON@ VOM (DC) R ONPd@VOL (DC) 0.6 − d RONdTL × | ∆ T| − d RONdVL × | ∆ V| max 1.1 + dRONdTH × | ∆ T| + dRONdVH × | ∆ V| 1.1 + dRONdTL × | ∆ T| + dRONdVL × | ∆ V| unit RZQ/7
0.9 − d RONdTM × | ∆ T| − d RONdVM × | ∆ V| 1.1 + dRONdTM × | ∆ T| + dRONdVM × | ∆ V| RZQ/7 RZQ/7
[Output Driver Voltage and Temperature Sensitivity]
D DR3-1066, 1333 min. d RONdTM d RONdVM d RONdTL d RONdVL d RONdTH d RONdVH 0 0 0 0 0 0 max. 1.5 0.15 1.5 0.15 1.5 0.15 DDR3-1600 max. 1.5 0.13 1.5 0.13 1.5 0.13 Unit %/ ° C %/mV %/ ° C %/mV %/ ° C %/mV
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS, /DQS and TDQS, /TDQS (×8 devices only) pins. A functional representation of the on-die termination is shown in the figure On-Die Termination: Definition of Voltages and Currents. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows:
P arameter ODT pull-up resistance O DT pull-down resistance Symbol RTTPu RTTPd Definition VDDQ − V OUT IOUT VOUT IOUT Conditions R TTPd is turned off R TTPu is turned off
Chip in Termination Mode ODT VDDQ IPu To other circuitry like RCV, ...
IOut = IPd - IPu
RTTPu
DQ
IOut
RTTPd
VOut
IPd
VSSQ
On-Die Termination: Definition of Voltages and Currents The value of the termination resistor can be set via MRS command to RTT60 = RZQ/4 (nom) or RTT120 = RZQ/2 (nom). RTT60 or RTT120 will be achieved by the DDR3 SDRAM after proper I/O calibration has been performed. Tolerances requirements are referred to the ODT DC Electrical Characteristics table. Measurement Definition for RTT Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively.
RTT = VIH( AC) − VIL( AC) I( VIH( AC)) − I( VIL( AC))
Measurement Definition for ∆VM Measure voltage (VM) at test pin (midpoint) with no load.
2 × VM ∆VM = VDDQ - 1 × 100
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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ODT DC Electrical Characteristics (RZQ = 240Ω, entire operating temperature range; after proper ZQ calibration)
M R1 [A9, A6, A2] RTT Resistor VOUT VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) VIL (AC) to VIH (AC) VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) VIL (AC) to VIH (AC) VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) VIL (AC) to VIH (AC) VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) VIL (AC) to VIH (AC) VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) VIL (AC) to VIH (AC) min. 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 −5 nom. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 max. 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 Unit Notes
[0, 1, 0]
120 Ω R TT120Pd240
RZQ
1, 2, 3, 4
R TT120Pu240 R TT120 [ 0, 0, 1] 60 Ω R TT60Pd120
RZQ RZQ/2 RZQ/2
1, 2, 3, 4 1, 2, 5 1, 2, 3, 4
R TT60Pu120 R TT60 [ 0, 1.1] 40 Ω R TT40Pd80
RZQ/2 RZQ/4 RZQ/3
1, 2, 3, 4 1, 2, 5 1, 2, 3, 4
R TT40Pu80 R TT40 [ 1, 0, 1] 30 Ω R TT30Pd60
RZQ/3 RZQ/6 RZQ/4
1, 2, 3, 4 1, 2, 5 1, 2, 3, 4
R TT30Pu60 R TT30 [ 1, 0, 0] 20 Ω R TT20Pd40
RZQ/4 RZQ/8 RZQ/6
1, 2, 3, 4 1, 2, 5 1, 2, 3, 4
R TT20Pu40 R TT20 D eviation of VM w.r.t. VDDQ/2, ∆ VM
RZQ/6
1, 2, 3, 4
RZQ/12 1, 2, 5 % 1, 2, 5, 6
Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output resistors are recommended to be calibrated at 0.5 × VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ. 4. Not a specification requirement, but a design guide line. 5. Measurement Definition for RTT: Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively.
RTT = VIH( AC) − VIL( AC) I( VIH( AC)) − I( VIL( AC))
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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6. Measurement Definition for VM and ∆VM: Measure voltage (VM) at test pin (midpoint) with no load:
2 × VM ∆VM = VDDQ - 1 × 100
ODT Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the table ODT Sensitivity Definition and ODT Voltage and Temperature Sensitivity. ∆T = T − T (@calibration); ∆V= VDDQ − VDDQ (@calibration); VDD = VDDQ Note: dRTTdT and dRTTdV are not subject to production test but are verified by design and characterization. [ODT Sensitivity Definition]
m in. RTT max. Unit RZQ/2, 4, 6, 8, 12 0.9 − d RTTdT × | ∆ T| - dRTTdV × | ∆ V| 1.6 + dRTTdT × | ∆ T| + dRTTdV × | ∆ V|
[ODT Voltage and Temperature Sensitivity]
m in. dRTTdT d RTTdV 0 0 max. 1.5 0.15 Unit %/ ° C %/mV
ODT Timing Definitions Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings are defined in ODT Timing Reference Load.
VDDQ
DUT
CK, /CK
DQ DQS, /DQS
VTT = VSSQ
RTT = 25Ω
ODT Timing Reference Load
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EDJ1104BDSE, EDJ1108BDSE
ODT Measurement Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the following table and subsequent figures.
S ymbol tAON t AONPD t AOF t AOFPD t ADC Begin Point Definition Rising edge of CK - /CK defined by the end point of ODTLon Rising edge of CK - /CK with ODT being first registered high Rising edge of CK - /CK defined by the end point of ODTLoff Rising edge of CK - /CK with ODT being first registered low Rising edge of CK - /CK defined by the end point of ODTLcnw, ODTLcwn4 or ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_WR and VRTT_Nom respectively Figure Figure a) Figure b) Figure c) Figure d) Figure e)
Reference Settings for ODT Timing Measurements Measurement reference settings are provided in the following Table.
M easured Parameter RTT_Nom Setting tAON RZQ/4 R ZQ/12 t AONPD RZQ/4 R ZQ/12 t AOF RZQ/4 R ZQ/12 t AOFPD RZQ/4 R ZQ/12 t ADC RZQ/12 RTT_WR Setting N/A N/A N/A N/A N/A N/A N/A N/A RZQ/2
Begin point: Rising edge of CK - /CK defined by the end point of ODTLon CK
VTT
VSW1 [V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20
VSW2 [V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30
Note
/CK tAON
tSW2
DQ, DM DQS, /DQS TDQS, /TDQS
tSW1 VSW2
VSSQ
VSW1
VSSQ
End point: Extrapolated point at VSSQ
a) Definition of tAON
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Begin point: Rising edge of CK - /CK with ODT being first registered high CK
VTT
/CK tAONPD
tSW2
DQ, DM DQS, /DQS TDQS, /TDQS
tSW1 VSW2
VSSQ
VSW1
VSSQ
End point: Extrapolated point at VSSQ
b) Definition of tAONPD
Begin point: Rising edge of CK - /CK defined by the end point of ODTLoff CK
VTT
/CK tAOF VRTT_Nom
DQ, DM DQS, /DQS TDQS, /TDQS
End point: Extrapolated point at VRTT_Nom tSW2 tSW1
VSW2 VSW1
VSSQ
c) Definition of tAOF
Begin point: Rising edge of CK - /CK with ODT being first registered low
CK
VTT
/CK tAOFPD VRTT_Nom
DQ, DM DQS, /DQS TDQS, /TDQS
End point: Extrapolated point at VRTT_Nom tSW2 tSW1
VSW2 VSW1
VSSQ
d) Definition of tAOFPD
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Begin point: Rising edge of CK - /CK defined by the end point of ODTLcnw CK
VTT
Begin point: Rising edge of CK - /CK defined by the end point of ODTLcwn4 or ODTLcwn8
/CK
tADC
tADC
VRTT_Nom
End point: DQ, DM Extrapolated DQS, /DQS point at VRTT_Nom TDQS, /TDQS
TSW21 TSW11 VSW1
VRTT_Wr
VRTT_Nom
VSW2
TSW22 TSW12 End point: Extrapolated point at VRTT_Wr
VSSQ
e) Definition of tADC
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. • IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Note: IDDQ values cannot be directly used to calculate I/O power of the DDR3 SDRAM. They can be used to support correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O power to actual channel I/O power supported by IDDQ measurement. For IDD and IDDQ measurements, the following definitions apply: • L and 0: VIN ≤ VIL (AC)(max.) • H and 1: VIN ≥ VIH (AC)(min.) • FLOATING: is defined as inputs are VREF = VDDQ / 2 • Timings used for IDD and IDDQ measurement-loop patterns are provided in Timings used for IDD and IDDQ Measurement-Loop Patterns table. • Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions table. Note: The IDD and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. • Detailed IDD and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table through IDD7 Measurement-Loop Pattern table. • IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting. RON = RZQ/7 (34 Ω in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ω in MR1); RTT_WR = RZQ/2 (120 Ω in MR2); TDQS Feature disabled in MR1 • Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L} • Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H}
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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I DD
I DDQ
VDD
/RESET CK, /CK
VDDQ DDR3 SDRAM
CKE /CS /RAS, /CAS, /WE Address, BA ODT ZQ
DQS, /DQS, DQ, DM, TDQS, /TDQS
RTT = 25Ω
VDDQ/2
VSS
VSSQ
Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific memory channel environment
IDDQ Test load
Channel I/O power simulation
IDDQ simulation
IDDQ measurement
Correlation Correction
Channel I/O power number
Correlation from Simulated Channel I/O Power to Actual Channel I/O Power Supported by IDDQ Measurement.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Timings used for IDD and IDDQ Measurement-Loop Patterns
D DR3-1600 Parameter CL t CK min. n RCD min. n RC min. n RAS min. n RP min. n FAW n RRD n RFC 10-10-10 10 1.25 10 38 28 10 24 5 88 11-11-11 11 1.25 11 39 28 11 24 5 88 DDR3-1333 9-9-9 9 1.5 9 33 24 9 20 4 74 DDR3-1066 7-7-7 7 1.875 7 27 20 7 20 4 59 Unit tCK ns nCK nCK nCK nCK nCK nCK nCK
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Basic IDD and IDDQ Measurement Conditions
P arameter Symbol Description CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Timings used for IDD and 1 IDDQ Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to IDD0 Measurement-loop pattern table; Data I/O: FLOATING; DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see IDD0 2 Measurement-Loop Pattern table); output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD0 Measurement-Loop Pattern table CKE: H; external clock: On; tCK, nRC, nRAS, nRCD, CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table; BL: 8(1,7); AL: 0; /CS: H between ACT, READ and PRE; Command, Address, Bank Address Inputs, data I/O: partially toggling according to IDD1 Measurement-Loop Pattern table; DM: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see IDD1 Measurement-Loop Pattern table); Output buffer and RTT: enabled in 2 MR* ; ODT Signal: stable at 0; Pattern details: see IDD1 Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop patterns table BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, Bank address Inputs: partially toggling according to IDD2N and IDD3N Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0; 2 bank activity: all banks closed; output buffer and RTT: enabled in mode registers* ; ODT signal: stable at 0; pattern details: see IDD2N and IDD3N Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to IDD2NT and IDDQ2NT Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable 2 at 0; bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: toggling according to IDD2NT and IDDQ2NT Measurement-Loop pattern table; pattern details: see IDD2NT and IDDQ2NT Measurement-Loop Pattern table Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, bank Address inputs: stable at 0; data I/O: FLOATING; DM: 2 stable at 0; bank activity: all banks closed; output buffer and RTT: EMR * ; ODT 3 signal: stable at 0; pecharge power down mode: slow exit* CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; data I/O: FLOATING; DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in 2 3 MR* ; ODT signal: stable at 0; pecharge power down mode: fast exit* CKE: H; External clock: On; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; data I/O: FLOATING; DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in 2 MR* ; ODT signal: stable at 0
Operating one bank active precharge current
IDD0
O perating one bank active-read-precharge current
IDD1
P recharge standby current
IDD2N
P recharge standby ODT current
IDD2NT
P recharge standby ODT IDDQ current P recharge power-down current slow exit
IDDQ2NT
IDD2P0
P recharge power-down current fast exit
IDD2P1
P recharge quiet standby current
IDD2Q
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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P arameter
Symbol
Description CKE: H; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to IDD2N and IDD3N Measurement-Loop Pattern; data I/O: FLOATING; DM: stable at 0; 2 bank activity: all banks open; output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD2N and IDD3N Measurement-Loop Pattern table CKE: L; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, Address, bank address inputs: stable at 0; data I/O: FLOATING; DM:stable at 0; bank activity: all banks open; output buffer and RTT: 2 enabled in MR* ; ODT signal: stable at 0 CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1, 7 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between READ; Command, Address, Bank Address Inputs: partially toggling according to IDD4R and IDDQ4R Measurement-Loop Pattern table; data I/O: seamless read data burst with different data between one burst and the next one according to IDD4R and IDDQ4R Measurement-Loop Pattern table; DM: stable at 0; bank activity: all banks open, READ commands cycling through banks: 0,0,1,1,2,2,... (see IDD4R and IDDQ4R Measurement-Loop Pattern table); output buffer and 2 RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD4R and IDDQ4R Measurement-Loop Pattern table Same definitI/on like for IDD4R, however measuring IDDQ current instead of IDD current CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between WR; command, address, bank address inputs: partially toggling according to IDD4W Measurement-Loop Pattern table; data I/O: seamless write data burst with different data between one burst and the next one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see IDD4W Measurement2 Loop Pattern table); output buffer and RTT: enabled in MR* ; ODT signal: stable at H; pattern details: see IDD4W Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL, nRFC: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between REF; Command, Address, Bank Address Inputs: partially toggling according to IDD5B Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0; bank activity: REF command every nRFC (IDD5B Measurement-Loop Pattern); 2 output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD5B Measurement-Loop Pattern table 4 TC: 0 to 85°C; ASR: disabled* ; SRT: 5 Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Timings used for 1 IDD and IDDQ Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable at 0; bank activity: Self-Refresh operatI/On; output buffer and RTT: enabled in 2 MR* ; ODT signal: FLOATING
Active standby current
IDD3N
A ctive power-down current
IDD3P
O perating burstr current
IDD4R
O perating burst read IDDQ current
IDDQ4R
O perating burst write current
IDD4W
B urst refresh current
IDD5B
S elf refresh current: normal temperature range
IDD6
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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P arameter
Symbol
Description TC: 0 to 95°C; ASR: Disabled* ; SRT: Extended* ; CKE: L; External clock: off; CK and /CK: L; CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table; 1 BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable at 0; bank activity: 2 Extended temperature self-refresh operation; output buffer and RTT: enabled in MR* ; ODT signal: FLOATING 4 5 TC: 0 to 95°C; ASR: Enabled* ; SRT: Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Table Timings used for IDD and IDDQ Measurement-Loop 1 Patterns table; BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable at 0; bank activity: Auto self-refresh operation; output buffer 2 and RTT: enabled in MR* ; ODT signal: FLOATNG CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table; 1 BL: 8* ; AL: CL-1; /CS: H between ACT and READA; command, address, bank address Inputs: partially toggling according to IDD7 Measurement-Loop Pattern table; data I/O: read data bursts with different data between one burst and the next one according to IDD7 Measurement-Loop Pattern table; DM: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see IDD7 2 Measurement-Loop Pattern table; output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD7 Measurement-Loop Pattern table
4 5
Self refresh current: extended temperature range
IDD6ET
A uto Self-Refresh Current (optional)
IDD6TC
O perating Bank Interleave Read Current
IDD7
Notes: 1. Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0]. 2. MR: Mode Register Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1]; RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0]. 3. Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit. 4. Auto self refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature. 5. Self refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range. 6. Read burst type: nibble sequential, set MR0 bit A3 = 0.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
IDD0 Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 1, 2 3, 4 … n RAS … 0 1 × n RC +0 1 × n RC +1, 2, 1 × n RC + 3, 4 … 1 × n RC + nRAS . .. 1 2 3 4 5 6 7 2 × n RC 4 × n RC 6 × n RC 8 × n RC Command /CS A CT 0 D, D 1 / D, /D 1 /RAS /CAS /WE 0 0 1 1 0 1 1 0 1 ODT BA* 0 0 0 0 0 0
3
A11 -A13 A10 00 00 00 0 0 0
A7 -A9 0 0 0
A3 -A6 0 0 0
A0 -A2 0 0 0
Data*
2
R epeat pattern 1...4 until nRAS − 1 , truncate if necessary P RE 0 0 1 0 0 0 00 0 0 0 0 R epeat pattern 1...4 until nRC − 1 , truncate if necessary A CT 0 D, D 1 /D, /D 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 00 00 00 0 0 0 0 0 0 F F F 0 0 0
T oggling Static H
R epeat pattern nRC + 1,...,4 until 1 × n RC + nRAS − 1 , truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F 0
Repeat nRC + 1,...,4 until 2 × n RC − 1 , truncate if necessary Repeat Sub-Loop 0, use BA= 1 instead Repeat Sub-Loop 0, use BA= 2 instead Repeat Sub-Loop 0, use BA= 3 instead Repeat Sub-Loop 0, use BA= 4 instead
1 0 × n RC Repeat Sub-Loop 0, use BA= 5 instead 1 2 × n RC Repeat Sub-Loop 0, use BA= 6 instead 1 4 × n RC Repeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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IDD1 Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 1, 2 3, 4 … n RCD … n RAS … 0 1 + 1 + 1 + . .. 1 × n RC + nRCD . .. 1 × n RC + nRAS … 1 2 3 4 5 6 7 2 × n RC 4 × n RC 6 × n RC 8 × n RC × n RC 0 × n RC 1, 2 × n RC 3, 4 Command /CS /RAS /CAS /WE A CT D, D 0 1 0 0 1 1 0 1 1 0 1 ODT BA* 0 0 0 0 0 0
3
A11 -A13 A10 00 00 00 0 0 0
A7 -A9 0 0 0
A3 -A6 0 0 0
A0 -A2 0 0 0
Data*
2
/ D, /D 1
R epeat pattern 1...4 until nRCD − 1 , truncate if necessary R EAD 0 1 0 1 0 0 00 0 0 0 0 0 0000000 R epeat pattern 1...4 until nRAS − 1 , truncate if necessary P RE 0 0 1 0 0 0 00 0 0 0 0 R epeat pattern 1...4 until nRC − 1 , truncate if necessary ACT D, D 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 00 00 00 0 0 0 0 0 0 F F F 0 0 0
/D, /D 1
T oggling Static H
Repeat pattern nRC + 1,..., 4 until nRC + nRCD − 1 , truncate if necessary READ 0 1 0 1 0 0 00 0 0 F 0 0 0110011
Repeat pattern nRC + 1,..., 4 until nRC +nRAS − 1 , truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F 0
R epeat pattern nRC + 1,..., 4 until 2 * nRC − 1 , truncate if necessary Repeat Sub-Loop 0, use BA= 1 instead Repeat Sub-Loop 0, use BA= 2 instead Repeat Sub-Loop 0, use BA= 3 instead Repeat Sub-Loop 0, use BA= 4 instead
1 0 × n RC Repeat Sub-Loop 0, use BA= 5 instead 1 2 × n RC Repeat Sub-Loop 0, use BA= 6 instead 1 4 × n RC Repeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
IDD2N and IDD3N Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 0 1 2 3 1 T oggling Static H 2 3 4 5 6 7 4 to 7 8 t o 11 1 2 to 15 1 6 to 19 2 0 to 23 2 4 to 27 2 8 to 31 Command /CS D D /D /D 1 1 1 1 /RAS /CAS /WE ODT BA* 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0
3
A11 -A13 A10 0 0 0 0 0 0 0 0
A7 -A9 0 0 0 0
A3 -A6 0 0 F F
A0 -A2 0 0 0 0
Data*
2
R epeat Sub-Loop 0, use BA= 1 instead R epeat Sub-Loop 0, use BA= 2 instead R epeat Sub-Loop 0, use BA= 3 instead R epeat Sub-Loop 0, use BA= 4 instead R epeat Sub-Loop 0, use BA= 5 instead R epeat Sub-Loop 0, use BA= 6 instead R epeat Sub-Loop 0, use BA= 7 instead
Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2.
IDD2NT and IDDQ2NT Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 0 1 2 3 1 T oggling Static H 2 3 4 5 6 7 4 to 7 8 t o 11 1 2 to 15 1 6 to 19 2 0 to 23 2 4 to 27 2 8 to 31 Command /CS D D /D /D 1 1 1 1 /RAS /CAS /WE ODT BA* 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0
3
A11 -A13 A10 0 0 0 0 0 0 0 0
A7 -A9 0 0 0 0
A3 -A6 0 0 F F
A0 -A2 0 0 0 0
Data*
2
R epeat Sub-Loop 0, but ODT = 0 and BA= 1 R epeat Sub-Loop 0, but ODT = 1 and BA= 2 R epeat Sub-Loop 0, but ODT = 1 and BA= 3 R epeat Sub-Loop 0, but ODT = 0 and BA= 4 R epeat Sub-Loop 0, but ODT = 0 and BA= 5 R epeat Sub-Loop 0, but ODT = 1 and BA= 6 R epeat Sub-Loop 0, but ODT = 1 and BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
IDD4R and IDDQ4R Measurement-Loop Patter
C K, /CK CKE Sub Cycle Com-Loop number mand 0 1 0 2, 3 4 5 6, 7 T oggling Static H 1 2 3 4 5 6 7 8 t o 15 D /D, /D /CS 1 1 /RAS /CAS /WE ODT BA* 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
3
A11 -A13 A10 0 0 0 0 0 0 0 0 0 0 0 0
A7 A3 A0 -A9 -A6 -A2 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 0 0
Data*
2
R EAD 0
0 0000000 00110011
R EAD 0 D /D, /D 1 1
R epeat Sub-Loop 0, but BA= 1
1 6 to 23 R epeat Sub-Loop 0, but BA= 2 2 4 to 31 R epeat Sub-Loop 0, but BA= 3 3 2 to 39 R epeat Sub-Loop 0, but BA= 4 4 0 to 47 R epeat Sub-Loop 0, but BA= 5 4 8 to 55 R epeat Sub-Loop 0, but BA= 6 5 6 to 63 R epeat Sub-Loop 0, but BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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IDD4W Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 1 0 2, 3 4 5 6, 7 T oggling Static H 1 2 3 4 5 6 7 8 t o 15 1 6 to 23 2 4 to 31 3 2 to 39 4 0 to 47 4 8 to 55 5 6 to 63 Command W RIT D /D, /D W RIT D /D, /D /CS 0 1 1 0 1 1 /RAS /CAS /WE ODT BA* 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
3
A11 A7 -A13 A10 -A9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A3 -A6 0 0 0 F F F
A0 -A2 0 0 0 0 0 0
Data*
2
0 0000000 00110011
R epeat Sub-Loop 0, but BA= 1 R epeat Sub-Loop 0, but BA= 2 R epeat Sub-Loop 0, but BA= 3 R epeat Sub-Loop 0, but BA= 4 R epeat Sub-Loop 0, but BA= 5 R epeat Sub-Loop 0, but BA= 6 R epeat Sub-Loop 0, but BA= 7
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2.
IDD5B Measurement-Loop Pattern
C K, /CK CKE Sub Cycle -Loop number 0 0 1, 2 3, 4 5 to 8 9 t o 12 T oggling Static H 1 1 3 to 16 1 7 to 20 2 1 to 24 2 5 to 28 2 9 to 32 2 Command /CS /RAS /CAS /WE R EF D 0 1 0 0 1 0 0 1 1 0 1 ODT BA* 1 1 1 0 0 0
3
A11 -A13 A10 0 0 0 0 0 0
A7 -A9 0 0 0
A3 -A6 0 0 0
A0 -A2 0 0 0
Data*
2
/D, /D 1
R epeat cycles 1...4, but BA= 1 R epeat cycles 1...4, but BA= 2 R epeat cycles 1...4, but BA= 3 R epeat cycles 1...4, but BA= 4 R epeat cycles 1...4, but BA= 5 R epeat cycles 1...4, but BA= 6 R epeat cycles 1...4, but BA= 7
3 3 to R epeat Sub-Loop 1, until nRFC − 1 . Truncate, if necessary. nRFC − 1
Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
41
EDJ1104BDSE, EDJ1108BDSE
IDD7 Measurement-Loop Pattern
C K, /CK CKE Sub -Loop Cycle number 0 0 1 2 … n RRD 1 n RRD + 1 nRRD + 2 … 2 3 4 5 6 7 8 9 2 × n RRD 3 × n RRD 4 × n RRD n FAW Command A CT R EADA D /CS 0 0 1 /RAS /CAS /WE ODT BA* 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0
3
A11 A7 A3 A0 2 Data* -A13 A10 -A9 -A6 -A2 00 00 00 0 1 0 0 0 0 0 0 0 0 0 0 0 0000000 00110011
R epeat above D Command until nRRD − 1 ACT READA D 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 00 00 00 0 1 0 0 0 0 F F F 0 0 0
R epeat above D Command until 2 × n RRD - 1 Repeat Sub-Loop 0, but BA= 2 Repeat Sub-Loop 1, but BA= 3 D 1 0 0 0 0 3 00 0 0 F 0
Assert and repeat above D Command until nFAW - 1, if necessary Repeat Sub-Loop 0, but BA= 4
n FAW Repeat Sub-Loop 1, but BA= 5 + nRRD n FAW Repeat Sub-Loop 0, but BA= 6 + 2 × n RRD n FAW Repeat Sub-Loop 1, but BA= 7 + 3 × n RRD n FAW + 4nRRD 2 + 2 + × n FAW 0 × n FAW 1 D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2 × n FAW - 1, if necessary ACT READA D 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 00 00 00 0 1 0 0 0 0 F F F 0 0 0 00110011
T oggling
Static H 10
2 × n FAW +2 2 + 2 +
Repeat above D Command until 2 × n FAW + nRRD - 1 0 0 0 1 1 0 1 1 0 0 0 0 00 00 0 1 0 0 0 0 0 0 0 0 00000000
11
× n FAW ACT nRRD × n FAW READA nRRD + 1
D 1 0 0 0 0 0 00 0 0 2 × n FAW + nRRD + 2 Repeat above D Command until 2 × n FAW + 2 × n RRD − 1 12 13 14 15 16 17 18 19 2 × n FAW Repeat Sub-Loop 10, but BA= 2 +2 × n RRD 2 × n FAW Repeat Sub-Loop 11, but BA= 3 + 3 × n RRD
D 1 0 0 0 0 3 00 0 0 0 0 2 × n FAW + 4 × n RRD Assert and repeat above D Command until 3 × n FAW − 1 , if necessary 3 × n FAW Repeat Sub-Loop 10, but BA= 4 3 × nFAW Repeat Sub-Loop 11, but BA= 5 +nRRD 3 × n FAW Repeat Sub-Loop 10, but BA= 6 + 2 × n RRD 3 × n FAW Repeat Sub-Loop 11, but BA= 7 + 3 × n RRD D 1 0 0 0 0 7 00 0 0 0 0 3 × n FAW + 4 × n RRD Assert and repeat above D Command until 4 × n FAW − 1 , if necessary
Preliminary Data Sheet E1494E50 (Ver. 5.0)
42
EDJ1104BDSE, EDJ1108BDSE
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
43
EDJ1104BDSE, EDJ1108BDSE
Electrical Specifications
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
×4 P arameter O perating current (ACT-PRE) O perating current (ACT-READ-PRE) Symbol IDD0 Data rate (Mbps) 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 max. 105 95 85 120 110 100 45 40 35 15 14 13 65 60 55 65 60 55 60 55 50 45 40 35 75 65 60 230 200 160 240 210 170 280 270 260 350 310 270 ×8 max. 105 95 85 120 110 100 45 40 35 15 14 13 65 60 55 65 60 55 60 55 50 45 40 35 75 65 60 230 200 160 240 210 170 280 270 260 350 310 270 Unit mA Notes
IDD1
mA
I DD2P1 P recharge power-down standby current IDD2P0 P recharge standby current P recharge standby ODT current
mA
Fast PD Exit
mA
Slow PD Exit
IDD2N
mA
IDD2NT
mA
P recharge quiet standby IDD2Q current A ctive power-down current (Always fast exit) A ctive standby current O perating current (Burst read operating) O perating current (Burst write operating) B urst refresh current A ll bank interleave read current IDD3P
mA
mA
IDD3N
mA
IDD4R
mA
IDD4W
mA
IDD5B
mA
IDD7
mA
Preliminary Data Sheet E1494E50 (Ver. 5.0)
44
EDJ1104BDSE, EDJ1108BDSE
Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
×4 P arameter S elf-refresh current normal temperature range S elf-refresh current extended temperature range A uto self-refresh current (optional) Symbol IDD6 IDD6ET IDD6TC Grade max. 10 18 ×8 max. 10 18 Unit mA mA mA Notes
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)
P arameter Input leakage current O utput leakage current Symbol ILI ILO Value 2 5 Unit µA µA Notes VDD ≥ V IN ≥ V SS VDDQ ≥ V OUT ≥ V SS
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V)
P arameter Input pin capacitance, CK and /CK DDR3-1600, 1333 D DR3-1066 D elta input pin capacitance, CK and /CK DDR3-1600, 1333 D DR3-1066 I nput pin capacitance, control pins DDR3-1600, 1333 D DR3-1066 I nput pin capacitance, address and command pins DDR3-1600, 1333 D DR3-1066 D elta input pin capacitance, control pins DDR3-1600, 1333 D DR3-1066 D elta input pin capacitance, address and command pins CDIN_ADD_CMD DDR3-1600, 1333 D DR3-1066 I nput/output pin capacitance DDR3-1600 D DR3-1333 D DR3-1066 D elta input/output pin capacitance DDR3-1600, 1333 D DR3-1066 D elta input/output pin capacitance DDR3-1600, 1333 D DR3-1066 I nput/output pin capacitance of ZQ CZQ ZQ CDDQS DQS, /DQS CDIO CIO DQ, DQS, /DQS, TDQS, /TDQS DM /RAS, /CAS, /WE, Address CDIN_CTRL /CS, CKE, ODT /RAS, /CAS, /WE, Address CIN_CTRL /CS, CKE, ODT CDCK Symbol CCK CK, /CK Pins min. 0.8 0.8 0 0 0.75 0.75 0.75 0.75 − 0.4 − 0.5 − 0.4 − 0.5 1.5 1.5 1.5 − 0.5 − 0.5 0 0 max. 1.4 1.6 0.15 0.15 1.3 1.5 1.3 1.5 0.2 0 .3 0 .4 0.5 2.3 2.5 3.0 0.3 0.3 0.15 0 .2 3 Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF Notes 1, 3 1, 3 1, 2 1, 2 1 1 1 1 1, 4 1, 4 1, 5 1, 5 1, 6 1, 6 1, 6 1, 7, 8 1, 7, 8 1, 10 1, 10 1, 9
CIN_ADD_CMD
Notes: 1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating. VDD = VDDQ =1.5V, VBIAS=VDD/2. 2. Absolute value of CCK(CK-pin) − CCK(/CK-pin). 3. CCK (min.) will be equal to CIN (min.) 4. CDIN_CTRL = CIN_CTRL − 0.5 × (CCK(CK-pin) + CCK(/CK-pin)) 5. CDIN_ADD_CMD = CIN_ADD_CMD − 0.5 × (CCK(CK-pin) + CCK(/CK-pin)) 6. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS. 7. DQ should be in high impedance state. 8. CDIO = CIO (DQ, DM) −0.5 × (CIO(DQS-pin) + CIO(/DQS-pin)). 9. Maximum external load capacitance on ZQ pin: 5pF. 10 Absolute value of CIO(DQS) − CIO(/DQS).
Preliminary Data Sheet E1494E50 (Ver. 5.0)
46
EDJ1104BDSE, EDJ1108BDSE
Standard Speed Bins [DDR3-1600 Speed Bins]
S peed Bin CL-tRCD-tRP S ymbol t AA t RCD t RP t RC t RAS t CK (avg)@CL=5 CWL = 5 C WL = 6, 7, 8 t CK (avg)@CL=6 CWL = 5 C WL = 6 C WL = 7, 8 t CK (avg)@CL=7 CWL = 5 C WL = 6 C WL = 7 C WL = 8 t CK (avg)@CL=8 CWL = 5 C WL = 6 C WL = 7 C WL = 8 t CK (avg)@CL=9 CWL = 5, 6 C WL= 7 C WL= 8 t CK (avg)@CL=10 CWL = 5, 6 C WL= 7 C WL= 8 t CK (avg)@CL=11 CWL = 5, 6, 7 C WL= 8 C WL= 8 S upported CL settings S upported CWL settings /CAS write latency DDR3-1600J 10-10-10 min. 12.5 12.5 12.5 47.5 35 2.5 Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.5 Reserved Reserved 1.5 1.25 Reserved 1.25 Optional 5, 6, 7, 8, 9, 10 5, 6, 7, 8 max. 20 9 × t REFI 3.3 Reserved 3.3 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 1.875 Reserved Reserved < 1.875 85 < 1.5 Reserved < 1.5 Optional DDR3-1600K 11-11-11 min. 13.125 1 3.125 1 3.125 4 8.125 35 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.5 Reserved Reserved 1.5 Reserved Reserved 1.25 1.25 max. 20 9 × t REFI Reserved Reserved 3.3 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 1.875 Reserved Reserved < 1.875 Reserved Reserved < 1.5 < 1.5 nCK nCK Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 1, 2, 3, 4, 8 4 1, 2, 3, 8 1, 2, 3, 4, 8 4 4 1, 2, 3, 4, 8 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 8 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3 5 4 1, 2, 3 5 Notes
6, 7, 8, 9, 10, 11 5, 6, 7, 8
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[DDR3-1333 Speed Bins]
S peed Bin CL-tRCD-tRP S ymbol t AA t RCD t RP t RC t RAS t CK (avg)@CL=5 CWL = 5 C WL = 6, 7 t CK (avg)@CL=6 CWL = 5 C WL = 6 C WL = 7 t CK (avg)@CL=7 CWL = 5 C WL = 6 C WL = 7 t CK (avg)@CL=8 CWL = 5 C WL = 6 C WL = 7 t CK (avg)@CL=9 CWL = 5, 6 C WL= 7 t CK (avg)@CL=10 CWL = 5, 6 C WL= 7 C WL= 7 S upported CL settings S upported CWL settings /CAS write latency DDR3-1333H 9-9-9 min. 13.125 13.125 13.125 49.125 36 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved 1.875 Reserved Reserved < 1.5 Reserved 1.5 Optional 6, 7, 8, 9, 10 5, 6, 7 max. 20 9 × t REFI Reserved Reserved 3.3 Reserved Reserved Reserved < 2.5 Reserved Reserved < 2.5 Reserved Reserved < 1.875 Reserved < 1.875 Optional Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 9 1, 2, 3, 4, 7 4 1, 2, 3, 7 1, 2, 3, 4, 7 4 4 1, 2, 3, 4, 7 1, 2, 3, 4 4 1, 2, 3, 7 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 5 Notes
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
[DDR3-1066 Speed Bins]
S peed Bin CL-tRCD-tRP S ymbol t AA t RCD t RP t RC t RAS t CK (avg)@CL=5 CWL = 5 C WL = 6 t CK (avg)@CL=6 CWL = 5 C WL = 6 t CK (avg)@CL=7 CWL = 5 C WL = 6 t CK (avg)@CL=8 CWL = 5 C WL = 6 S upported CL settings S upported CWL settings /CAS write latency DDR3-1066F 7-7-7 min. 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 max. 20 9 × t REFI Reserved Reserved 3.3 Reserved Reserved < 2.5 Reserved < 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 9 1, 2, 3, 4, 6 4 1, 2, 3, 6 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Notes
Notes: 1
2.
3.
4. 5. 6. 7. 8 9.
The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg) (max.) corresponding to CL selected. Reserved’ settings are not allowed. User must program a different value. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1066 Speed Bins which are not subject to production tests but verified by design/characterization. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1333 Speed Bins which is not subject to production tests but verified by design/characterization. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1600 Speed Bins which is not subject to production tests but verified by design/characterization. tREFI depends on operating case temperature (TC).
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V) • New units tCK(avg) and nCK, are introduced in DDR3. tCK(avg): actual tCK(avg) of the input clock under operation. nCK: one clock cycle of the input clock, counting the actual clock edges. AC Characteristics [DDR3-1600, 1333]
- GL, -GN Data rate (Mbps) P arameter A verage clock cycle time M inimum clock cycle time (DLL-off mode) A verage CK high-level width A verage CK low-level width A ctive to read or write command delay P recharge command period A ctive to active/auto-refresh command time A ctive to precharge command A ctive bank A to active bank B command period F our active window A ddress and control input hold time (VIH/VIL (DC) levels) A ddress and control input setup time (VIH/VIL (AC) levels) A ddress and control input setup time (VIH/VIL (AC150) levels) D Q and DM input hold time (VIH/VIL (DC) levels) D Q and DM input setup time (VIH/VIL (AC) levels) C ontrol and Address input pulse width for each input D Q and DM input pulse width for each input D Q high-impedance time D Q low-impedance time Symbol tCK (avg) tCK (DLL-off) tCH (avg) tCL (avg) tRCD tRP tRC tRAS t RRD tRRD tFAW tIH (base) 1600 min. 1250 8 0.47 0.47 12.5 (GL) 13.125 (GN) 12.5 (GL) 13.125 (GN) 47.5 (GL) 48.125 (GN) 35 6 4 30 120 max. 3333 0.53 0.53 9× t REFI -DJ 1333 min. 1500 8 0.47 0.47 1 3.125 1 3.125 4 9.125 36 6 4 30 1 40 max. 3333 0.53 0.53 9× t REFI Unit ps ns tCK (avg) tCK (avg) ns ns ns ns ns n CK ns ps 26 26 26 26 26, 27 26, 27 26 16, 23 6 Notes
tIS (base) tIS (base) AC150 tDH (base) tDS (base) tIPW tDIPW tHZ (DQ) tLZ (DQ)
45
65
ps
16, 23 16, 23, 31 17, 25 17, 25 32 32 12, 14, 12, 14, 12, 14, 12, 14, 13, 37 13, 37 13, 37 13, 37
45 + 125 45 10 560 360 − 450 − 450 4 0.38 − 225
2 25 225 2 25 225 1 00 225
6 5 + 125 65 30 6 20 4 00 − 500 − 500 4 0 .38 − 255
2 50 250 2 50 250 1 25 255
ps ps ps ps ps ps ps ps ps ps n CK t CK (avg) ps
D QS, /DQS high-impedance time tHZ (DQS) (RL + BL/2 reference) D QS, /DQS low-impedance time tLZ (DQS) (RL − 1 r eference) D QS, /DQS to DQ skew, tDQSQ per group, per access / CAS to /CAS command delay tCCD D Q output hold time from tQH DQS, /DQS D QS, /DQS rising edge output tDQSCK access time from rising CK, /CK
12, 13
12, 13, 38 12, 13, 37
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
- GL, -GN Data rate (Mbps) P arameter Symbol 1600 min. − 0.27 0.18 0.18 0.45 0.45 0.40 0.40 4 15 12 0.9 0.3 0.9 0.3 15 max. 0 .27 0.55 0.55 -DJ 1333 min. − 0.25 0 .2 0 .2 0.45 0.45 0 .40 0 .40 4 15 12 0 .9 0 .3 0 .9 0 .3 15 max. 0.25 0.55 0.55 Unit Notes
D QS latching rising transitions tDQSS to associated clock edges D QS falling edge hold time from tDSH rising CK D QS falling edge setup time to tDSS rising CK D QS input high pulse width D QS input low pulse width D QS output high time D QS output low time M ode register set command cycle time M ode register set command update delay tDQSH tDQSL tQSH tQSL tMRD tMOD t MOD R ead preamble R ead postamble W rite preamble W rite postamble W rite recovery time A uto precharge write recovery + precharge time M ulti-Purpose register recovery time R ead to write command delay (BC4MRS, BC4OTF) ( BL8MRS, BL8OTF) I nternal write to read command delay tRPRE tRPST tWPRE tWPST tWR tDAL tMPRR tRTW tRTW tWTR t WTR I nternal read to precharge command delay A ctive to READ with auto precharge command delay tRTP t RTP tRAP
tCK (avg) 24 t CK (avg) 24, 36 t CK (avg) 24, 36 tCK (avg) 34, 35 tCK (avg) 33, 35 12, 13, 38 12, 13, t CK (avg) 38 t CK (avg) n CK ns n CK 27 27
1, 19, t CK (avg) 38 11, 12, t CK (avg) 13, 38 t CK (avg) 1 t CK (avg) 1 ns n CK n CK 29 26
WR + R U (tRP/tCK (avg)) 1 RL + tCCD/2 + 2nCK − W L RL + tCCD + 2nCK − W L 7.5 4 7.5 4 tRCD min
WR + RU (tRP/tCK (avg)) 1 R L + tCCD/2 + 2nCK − W L R L + tCCD + 2nCK − W L 7 .5 4 7 .5 4 t RCD min
ns n CK ns n CK
18, 26, 27 18, 26, 27 26, 27 26, 27 28
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
- GL, -GN Data rate (Mbps) P arameter Minimum CKE low width for selfrefresh entry to exit timing V alid clock requirement after selfrefresh entry or power-down entry Symbol tCKESR tCKSRE t CKSRE V alid clock requirement before tCKSRX self-refresh exit or power-down exit t CKSRX E xit self-refresh to commands not requiring a locked DLL tXS t XS E xit self-refresh to commands tXSDLL requiring a locked DLL A uto-refresh to active/auto-refresh tRFC command time A verage periodic refresh interval tREFI (0 ° C ≤ T C ≤ + 85 ° C) ( +85 ° C < T C ≤ + 95 ° C) C KE minimum pulse width (high and low pulse width) tREFI tCKE t CKE E xit reset from CKE high to a valid tXPR command t XPR D LL locking time P ower-down entry to exit time tDLLK tPD 1600 min. tCKE (min.) +1nCK 10 5 10 5 tRFC (min.) + 10 5 tDLLK (min.) 110 5 3 tRFC (min.)+10 5 512 tCKE (min.) 24 10 max. 7 .8 3 .9
-DJ 1333 min. t CKE (min.) +1nCK 10 5 10 5 t RFC (min.) + 10 5 t DLLK (min.) 1 10 5 .625 3 max. 7 .8 3 .9 ns n CK ns n CK ns n CK n CK ns µs µs ns n CK ns n CK n CK 15 ns n CK 2 2 27 27 27 27 27 27 27 27 27 27 Unit Notes
t RFC (min.)+10 5 5 12 9 × t REFI
9 × t REFI tCKE (min.) 24 10
E xit precharge power-down with DLL frozen to commands requiring tXPDLL a locked DLL t XPDLL E xit power-down with DLL on to any valid command; Exit precharge tXP power- down with DLL frozen to commands not requiring a locked DLL t XP C ommand pass disable/enable delay T iming of last ACT command to power-down entry T iming of last PRE command to power-down entry T iming of last READ/READA command to power-down entry T iming of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) ( BC4MRS) tCPDED tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN
6
6
ns
27
3 1 1 1 RL + 4 + 1 WL + 4 + tWR/tCK (avg) WL + 2 + tWR/tCK (avg)
3 1 1 1 RL + 4 + 1 WL + 4 + tWR/tCK (avg) WL + 2 + tWR/tCK (avg)
n CK n CK n CK n CK n CK n CK n CK
27
20 20
9 9
Preliminary Data Sheet E1494E50 (Ver. 5.0)
52
EDJ1104BDSE, EDJ1108BDSE
- GL, -GN Data rate (Mbps) P arameter T iming of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) ( BC4MRS) T iming of last REF command to power-down entry T iming of last MRS command to power-down entry Symbol tWRAPDEN tWRAPDEN tREFPDEN 1600 min. WL + 4 + WR + 1 WL + 2 + WR + 1 1 max.
-DJ 1333 min. WL + 4 + WR + 1 WL + 2 + WR + 1 1 t MOD (min.) max. Unit n CK n CK n CK Notes 10 10 20, 21
tMRSPDEN tMOD (min.)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
ODT AC Electrical Characteristics [DDR3-1600, 1333]
- GL, -GN Data rate (Mbps) P arameter R TT turn-on A synchronous RTT turn-on delay (power-down with DLL frozen) R TT_Nom and RTT_WR turn-off time from ODTLoff reference A synchronous RTT turn-off delay (power-down with DLL frozen) O DT to power-down entry/exit latency O DT turn-on Latency O DT turn-off Latency O DT Latency for changing from RTT_Nom to RTT_WR O DT Latency for change from RTT_WR to RTT_Nom (BC4) O DT Latency for change from RTT_WR to RTT_Nom (BL8) O DT high time without WRIT command or with WRIT command and BC4 O DT high time with WRIT command and BL8 R TT dynamic change skew P ower-up and reset calibration time N ormal operation full calibration time N ormal operation short calibration time Symbol tAON tAONPD tAOF tAOFPD tANPD ODTLon ODTLoff ODTLcnw 1600 min. − 225 2 0.3 2 WL – 1.0 WL – 2 WL – 2 WL – 2 max. 2 25 8.5 0.7 8.5 WL – 2 WL – 2 WL – 2 4 + O DTLoff -DJ 1333 min. − 250 2 0.3 2 W L – 1.0 WL – 2.0 WL – 2.0 WL – 2.0 max. 250 8.5 0.7 8.5 WL – 2.0 WL – 2.0 WL – 2.0 4 + O DTLoff Unit ps ns tCK (avg) ns n CK nCK nCK nCK nCK 8, 12, 37 Notes 7, 12, 37
ODTLcwn4
ODTLcwn8
6 + O DTLoff
6 + O DTLoff
nCK
ODTH4 ODTH8 tADC tZQinit tZQoper tZQCS
4 6 0.3 512 256 64
0.7
4 6 0.3 5 12 2 56 64
0.7
n CK n CK tCK (avg) n CK n CK n CK 30 12, 37
Write Leveling Characteristics [DDR3-1600, 1333]
- GL, -GN 1600 P arameter F irst DQS pulse rising edge after write leveling mode is programmed D QS, /DQS delay after write leveling mode is programmed W rite leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing W rite leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing W rite leveling output delay W rite leveling output error Symbol tWLMRD min. 40 max. -DJ 1333 min. 40 25 1 95 max. Unit n CK n CK ps Notes 3 3
tWLDQSEN 25 tWLS 165
tWLH tWLO tWLOE
165 0 0
7.5 2
1 95 0 0
9 2
ps ns ns
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
AC Characteristics [DDR3-1066]
- AE Data rate (Mbps) P arameter C lock cycle time Average CL = X M inimum clock cycle time (DLL-off mode) A verage duty cycle high-level A verage duty cycle low-level A ctive to read or write command delay P recharge command period A ctive to active/auto-refresh command time A ctive to precharge command A ctive bank A to active bank B command period F our active window A ddress and control input hold time (VIH/VIL (DC) levels) A ddress and control input setup time (VIH/VIL (AC) levels) A ddress and control input setup time (VIH/VIL (AC150) levels) D Q and DM input hold time (VIH/VIL (DC) levels) D Q and DM input setup time (VIH/VIL (AC) levels) C ontrol and Address input pulse width for each input D Q and DM input pulse width for each input D Q high-impedance time D Q low-impedance time D QS, /DQS high-impedance time (RL + BL/2 reference) D QS, /DQS low-impedance time (RL − 1 r eference) D QS, /DQS -DQ skew, per group, per access / CAS to /CAS command delay D Q output hold time from DQS, /DQS D QS, /DQS rising edge output access time from rising CK, /CK D QS latching rising transitions to associated clock edges D QS falling edge hold time from rising CK D QS falling edge setup time to rising CK Symbol tCK(avg) tCK (DLL-off) tCH (avg) tCL (avg) tRCD tRP tRC tRAS t RRD tRRD tFAW tIH (base) tIS (base) tIS (base) AC150 tDH (base) tDS (base) tIPW tDIPW tHZ (DQ) tLZ (DQ) tHZ (DQS) tLZ (DQS) tDQSQ tCCD tQH tDQSCK tDQSS tDSH tDSS 1066 min. 1875 8 0.47 0.47 13.1 13.1 50.6 37.5 7.5 4 37.5 200 125 max. 3333 0.53 0.53 9 × t REFI Unit ps ns tCK (avg) tCK (avg) ns ns ns ns ns n CK ns ps ps 26 26 26 26 26, 27 26, 27 26 16, 23 16, 23 16, 23, 31 17, 25 17, 25 32 32 12, 14, 12, 37 12, 37 12, 14, 13, 37 13, 14, 13, 14, 13, 37 6 Notes
125 + 150 100 25 780 490 − 600 − 600 4 0.38 − 300 − 0.25 0.2 0.2
3 00 300 3 00 300 1 50 + 300 0.25
ps ps ps ps ps ps ps ps ps ps n CK t CK (avg) ps tCK (avg) t CK (avg) t CK (avg)
12, 13
12, 13, 38 12, 13, 37 24 24, 36 24, 36
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- AE Data rate (Mbps) P arameter D QS input high pulse width D QS input low pulse width D QS output high time D QS output low time M ode register set command cycle time M ode register set command update delay Symbol tDQSH tDQSL tQSH tQSL tMRD tMOD t MOD R ead preamble R ead postamble W rite preamble W rite postamble W rite recovery time A uto precharge write recovery + precharge time M ulti-Purpose register recovery time R ead to write command delay (BC4MRS, BC4OTF) ( BL8MRS, BL8OTF) I nternal write to read command delay I nternal read to precharge command delay A ctive to READ with auto precharge command delay M inimum CKE low width for selfrefresh entry to exit timing V alid clock requirement after selfrefresh entry or power-down entry tRPRE tRPST tWPRE tWPST tWR tDAL tMPRR tRTW tRTW tWTR t WTR tRTP t RTP tRAP tCKESR tCKSRE t CKSRE V alid clock requirement before tCKSRX self-refresh exit or power-down exit t CKSRX 1066 min. 0.45 0.45 0.38 0.38 4 15 12 0.9 0.3 0.9 0.3 15 WR + RU (tRP/tCK (avg)) 1 RL + tCCD/2 + 2nCK − W L RL + tCCD + 2nCK − W L 7.5 4 7.5 4 tRCD min tCKE (min.) +1nCK 10 5 10 5 max. 0.55 0.55 ns n CK ns n CK 27 27 27 27 ns n CK ns n CK 18, 26, 27 18, 26, 27 26, 27 26, 27 28 Unit tCK (avg) tCK (avg) t CK (avg) t CK (avg) n CK ns n CK t CK (avg) t CK (avg) t CK (avg) t CK (avg) ns n CK n CK 29 27 27 1, 19, 38 11, 12, 13, 38 1 1 26 Notes 34, 35 33, 35 12, 13, 38 12, 13, 38
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- AE Data rate (Mbps) P arameter E xit self-refresh to commands not requiring a locked DLL E xit self-refresh to commands requiring a locked DLL A uto-refresh to active/auto-refresh command time A verage periodic refresh interval (0 ° C ≤ T C ≤ + 85 ° C) ( +85 ° C < T C ≤ + 95 ° C) C KE minimum pulse width (high and low pulse width) E xit reset from CKE high to a valid command D LL locking time P ower-down entry to exit time E xit precharge power-down with DLL frozen to commands requiring a locked DLL F ast exit/active precharge power down to any command C ommand pass disable/enable delay T iming of last ACT command to power-down entry T iming of last PRE command to power-down entry T iming of last READ/READA command to power-down entry T iming of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) ( BC4MRS) T iming of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) ( BC4MRS) T iming of last REF command to power-down entry T iming of last MRS command to power-down entry Symbol tXS t XS tXSDLL tRFC tREFI tREFI tCKE t CKE tXPR t XPR tDLLK tPD tXPDLL t XPDLL tXP t XP tCPDED tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN tWRAPDEN tWRAPDEN tREFPDEN tMRSPDEN 1066 min. tRFC (min.) + 10 5 tDLLK (min.) 110 5.625 3 tRFC (min.) +10 5 512 tCKE (min.) 24 10 7.5 3 1 1 1 RL + 4 + 1 WL + 4 + tWR/tCK (avg) WL + 2 + tWR/tCK (avg) WL + 4 + WR + 1 WL + 2 + WR + 1 1 tMOD (min.) max. 7 .8 3 .9 9 × t REFI ns n CK ns n CK n CK n CK n CK n CK n CK n CK n CK n CK n CK 9 9 10 10 20, 21 20 20 Unit ns n CK n CK ns µs µs ns n CK ns n CK n CK 15 2 2 27 27 27 27 27 27 Notes 27 27
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ODT AC Electrical Characteristics [DDR3-1066]
- AE Data rate (Mbps) P arameter R TT turn-on Symbol tAON 1066 min. –300 2 0.3 2 WL – 1.0 WL – 2.0 WL – 2.0 WL – 2.0 max. 300 8.5 0.7 8.5 WL – 2.0 WL – 2.0 WL – 2.0 4 + O DTLoff Unit ps ns tCK (avg) 8, 12, 37 ns n CK nCK nCK nCK nCK Notes 7, 12, 37
Asynchronous RTT turn-on delay tAONPD (power-down with DLL frozen) R TT_Nom and RTT_WR turn-off time tAOF from ODTLoff reference ODT turn-off (power-down mode) O DT to power-down entry/exit latency O DT turn-on Latency O DT turn-off Latency O DT Latency for changing from RTT_Nom to RTT_WR O DT Latency for change from RTT_WR to RTT_Nom (BC4) O DT Latency for change from RTT_WR to RTT_Nom (BL8) O DT high time without WRIT command or with WRIT command and BC4 O DT high time with WRIT command and BL8 R TT dynamic change skew P ower-up and reset calibration time N ormal operation full calibration time N ormal operation short calibration time tAOFPD tANPD ODTLon ODTLoff ODTLcnw ODTLcwn4
ODTLcwn8
6 + O DTLoff
nCK
ODTH4 ODTH8 tADC tZQinit tZQoper tZQCS
4 6 0.3 512 256 64
0.7
n CK n CK tCK (avg) 12, 37 n CK n CK n CK 30
Write Leveling Characteristics [DDR3-1066]
- AE 1066 P arameter F irst DQS pulse rising edge after write leveling mode is programmed D QS, /DQS delay after write leveling mode is programmed W rite leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing W rite leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing W rite leveling output delay W rite leveling output error Symbol tWLMRD tWLDQSEN tWLS min. 40 25 245 max. Unit n CK n CK ps Notes 3 3
tWLH tWLO tWLOE
245 0 0
9 2
ps ns ns
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Notes for AC Electrical Characteristics Notes: 1. Actual value dependent upon measurement level definitions that are TBD. 2. Commands requiring locked DLL are: READ (and READA) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rounded-up to next integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon. 8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is when the bus is in high impedance. Both are measured from ODTLoff. 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer. 10. WR in clock cycles as programmed in MR0. 11. The maximum read postamble is bound by tDQSCK(min.) plus tQSH(min.) on the left side and tHZ(DQS)(max.) on the right side. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. Refer to the section of tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes for definition and measurement method. 15. tREFI depends on operating case temperature (TC). 16. tIS(base) and tIH(base) values are for 1V/ns command/address single-ended slew rate and 2V/ns CK, /CK differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and Slew Rate Derating section. 18. Start of internal write transaction is definited as follows: For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL. 19. The maximum read preamble is bound by tLZ(DQS)(min.) on the left side and tDQSCK(max.) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, auto precharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered low after a refresh command once tREFPDEN(min.) is satisfied, there are cases where additional time such as tXPDLL(min.) is also required. See Figure Power-Down Entry/Exit Clarifications - Case 2. 22. tJIT(duty) = ± { 0.07 × tCK(avg) – [(0.5 - (min (tCH(avg), tCL(avg))) × tCK(avg)] }. For example, if tCH/tCL was 0.48/0.52, tJIT(duty) would calculate out to ±125ps for DDR3-800. The tCH(avg) and tCL(avg) values listed must not be exceeded. 23. These parameters are measured from a command/address signal (CKE, /CS, /RAS, /CAS, /WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24 These parameters are measured from a data strobe signal (TDQS, /DQS) crossing to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 25. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal (TDQS, /DQS) crossing.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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26. For these parameters, the DDR3 SDRAM device is characterized and verified to support tnPARAM [nCK] = RU{tPARAM [ns] / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP =RU{tRP / tCK(avg)} = 6, i.e. as long as the input clock jitter specifications are met, precharge command at Tm and active command at Tm+6 is valid even if (Tm+6 − Tm) is less than 15ns due to input clock jitter. 27. These parameters should be the larger of the two values, analog (ns) and number of clocks (nCK). 28 The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. 29 Defined between end of MPR read burst and MRS which reloads MPR or disables. 30 One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection (Tsens × Tdriftrate) + (Vsens × Vdriftrate)
where TSens = max.(dRTTdT, dRONdTM) and VSens = max.(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/°C, VSens = 0.15%/mV, Tdriftrate = 1°C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as:
0.5 = 0.133 = 128ms (1.5 × 1) + (0.15 × 15)
31 The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV − 150mV)/1V/ns]. 32 Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 33 tDQSL describes the instantaneous differential input low pulse width on DQS − /DQS, as measured from one falling edge to the next consecutive rising edge. 34 tDQSH describes the instantaneous differential input high pulse width on DQS −/DQS, as measured from one rising edge to the next consecutive falling edge. 35 tDQSH,act + tDQSL,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 36 tDSH,act + tDSS,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 37 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 ≤ m ≤ 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = −172ps and tERR(mper),act,max = +193ps, then tDQSCK,min(derated) = tDQSCK,min − tERR(mper),act,max = −400ps − 193ps = −593ps and tDQSCK,max(derated) =tDQSCK,max − tERR(mper),act,min = 400ps + 172ps = +572ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = −800ps − 193ps = −993ps and tLZ(DQ),max(derated) = 400ps + 172ps = +572ps. Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 ≤ n ≤ 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 ≤ n ≤ 12. 38 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500ps, tJIT(per),act,min = − 72ps and tJIT(per),act,max = +93ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 × tCK(avg),act + tJIT(per),act,min = 0.9 × 2500ps − 72ps = +2178ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 × tCK(avg),act + tJIT(per),act,min = 0.38 × 2500ps − 72ps = + 878ps.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Clock Jitter [DDR3-1600, 1333]
- GL, -GN Data rate (Mbps) P arameter A verage clock period A bsolute clock period C lock period jitter C lock period jitter during DLL locking period C ycle to cycle period Jitter C ycle to cycle clock period jitter during DLL locking period C umulative error across 2 cycles C umulative error across 3 cycles C umulative error across 4 cycles C umulative error across 5 cycles C umulative error across 6 cycles C umulative error across 7 cycles C umulative error across 8 cycles C umulative error across 9 cycles C umulative error across 10 cycles C umulative error across 11 cycles C umulative error across 12 cycles C umulative error across n = 13, 14…49, 50 cycles A verage high pulse width A verage low pulse width A bsolute clock high pulse width A bsolute clock low pulse width D uty cycle jitter Symbol tCK (avg) tCK (abs) tJIT (per) 1600 min. 1250 max. 3333 -DJ 1333 min. 1500 max. 3333 Unit ps Notes 1 2 6 6 7 7 8 8 8 8 8 8 8 8 8 8 8 9 3 4 10, 11 10, 12 5
tCK(avg)min tCK(avg)max tCK(avg)min + + + tJIT(per)min tJIT(per)max tJIT(per)min − 70 70 60 1 40 1 20 103 122 136 147 155 163 169 175 180 184 188 − 80 − 70 − 118 − 140 − 155 − 168 − 177 − 186 − 193 − 200 − 205 − 210 − 215
tCK(avg)max + ps tJIT(per)max 80 70 1 60 1 40 118 140 155 168 177 186 193 200 205 210 215 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) t CK (avg) t CK (avg) ps
tJIT (per, lck) − 60 tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6per) tERR (7per) tERR (8per) tERR (9per) − 103 − 122 − 136 − 147 − 155 − 163 − 169 − 175
tERR (10per) − 180 tERR (11per) − 184 tERR (12per) − 188 tERR (nper) tCH (avg) tCL (avg) tCH (abs) tCL (abs) tJIT (duty)
tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max 0.47 0.47 0.43 0.43 0.53 0.53 0.47 0.47 0 .43 0 .43 0.53 0.53
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Clock Jitter [DDR3-1066]
- AE Data rate (Mbps) P arameter A verage clock period A bsolute clock period C lock period jitter C lock period jitter during DLL locking period C ycle to cycle period jitter C ycle to cycle clock period jitter during DLL locking period C umulative error across 2 cycles C umulative error across 3 cycles C umulative error across 4 cycles C umulative error across 5 cycles C umulative error across 6 cycles C umulative error across 7 cycles C umulative error across 8 cycles C umulative error across 9 cycles C umulative error across 10 cycles C umulative error across 11 cycles C umulative error across 12 cycles C umulative error across n=13, 14…49,50 cycles A verage high pulse width A verage low pulse width A bsolute clock high pulse width A bsolute clock low pulse width D uty cycle jitter Symbol tCK (avg) tCK (abs) tJIT (per) 1066 min. 1875 tCK(avg)min + tJIT(per)min − 90 max. 3333 tCK(avg)max+ tJIT(per)max 90 80 1 80 1 60 132 157 175 188 200 209 217 224 231 237 242 Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) t CK (avg) t CK (avg) ps Notes 1 2 6 6 7 7 8 8 8 8 8 8 8 8 8 8 8 9 3 4 10, 11 10, 12 5
tJIT (per, lck) − 80 tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6per) tERR (7per) tERR (8per) tERR (9per) − 132 − 157 − 175 − 188 − 200 − 209 − 217 − 224
tERR (10per) − 231 tERR (11per) − 237 tERR (12per) − 242 tERR (nper) tCH (avg) tCL (avg) tCH (abs) tCL (abs) tJIT (duty)
tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max 0.47 0.47 0.43 0.43 0.53 0.53
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window, where each clock period is calculated from rising edge to rising edge.
Σ
N j=1
tCKj
N
N = 200
2. tCK (abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK (abs) is not subject to production test. 3. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.
Σ
N j=1
tCHj
(N × tCK(avg))
N = 200
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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4. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
Σ
N j=1
tCLj
(N × tCK(avg))
N = 200
5. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where: tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200} tJIT (CL) = {tCLj- tCL (avg) where j = 1 to 200} 6. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCKj − tCK (avg) where j = 1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production test. 7. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT (cc) = Max. of {tCKj+1 - tCKj} tJIT (cc) is defines the cycle when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle-to-cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production test. 8. tERR (nper) is defined as the cumulative error across n multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production test. 9 n = from 13 cycles to 50 cycles. This row defines 38 parameters. 10. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.)
P arameter Absolute clock period A bsolute clock high pulse width A bsolute clock low pulse width Symbol tCK (abs) tCH (abs) tCL (abs) min. tCK (avg), min. + tJIT (per),min. tCH (avg), min. × t CK (avg),min. + tJIT (duty),min. tCL (avg), min. × t CK (avg),min. + tJIT (duty),min. max. Unit tCK (avg), max. + tJIT ps (per),max. tCH (avg), max. × t CK ps (avg),max. + tJIT (duty),max. tCL (avg), max. × t CK ps (avg),max. + tJIT (duty),max.
11 tCH (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 12 tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Block Diagram
CK /CK CKE
Clock generator
Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1
Row decoder
Address, BA0, BA1, BA2
Mode register
Row address buffer and refresh counter
Memory cell array Bank 0
Sense amp.
Command decoder
/CS /RAS /CAS /WE
Column address buffer and burst counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS, /DQS
CK, /CK
DLL
Input & Output buffer
TDQS, /TDQS ODT
DM
DQ
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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Pin Function
CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A13 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table]
A ddress (A0 to A13) Part number E DJ1104BDSE E DJ1108BDSE Page size 1KB Row address (RA) AX0 to AX13 AX0 to AX13 Column address (CA) AY0 to AY9, AY11 AY0 to AY9 Note
A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto precharge should be performed to the accessed bank after the read/write operation. (high: auto precharge; low: no auto precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12(/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) See command truth table for details. BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine which Mode Register (MR0 to MR3) is to be accessed during a MRS cycle. [Bank Select Signal Table]
B A0 Bank 0 B ank 1 B ank 2 B ank 3 B ank 4 B ank 5 B ank 6 B ank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DM (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a write access. DM is sampled on both edges of DQS. For ×8 configuration, the function of DM or TDQS, /TDQS is enabled by mode register A11 setting in MR1. DQ (input/output pins) Bi-directional data bus. DQS, /DQS (input/output pins) Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. The data strobe DQS is paired with differential signal /DQS to provide differential pair signaling to the system during READs and WRITEs. TDQS, /TDQS (output pins) TDQS and /TDQS is applicable for ×8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM will enable the same termination resistance function on TDQS, /TDQS as is applied to DQS, /DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and /TDQS is not used. In ×4 configuration, the TDQS function must be disabled via mode register A11 = 0 in MR1. /RESET (input pin) /RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD (1.20V for DC high and 0.30V for DC low). It is negative active signal (active low) and is referred to GND. There is no termination required on this signal. It will be heavily loaded across multiple chips. /RESET is destructive to data contents. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM/TDQS, NU(/TDQS) (when TDQS is enabled via mode register A11 = 1 in MR1) signal for ×4/×8 configuration. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. ZQ (supply) Reference pin for ZQ calibration. VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VREFCA, VREFDQ (power supply) Reference voltage
Preliminary Data Sheet E1494E50 (Ver. 5.0)
66
EDJ1104BDSE, EDJ1108BDSE
Command Operation
Command Truth Table The DDR3 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
C KE Function Mode register set A uto-refresh S elf-refresh entry S elf-refresh exit Previous Current Symbol cycle cycle /CS MRS REF SELF SREX H H H L L S ingle bank precharge P recharge all banks B ank activate W rite (Fixed BL) W rite (BC4, on the fly) W rite (BL8, on the fly) W rite with auto precharge (Fixed BL) W rite with auto precharge (BC4, on the fly) W rite with auto precharge (BL8, on the fly) R ead (Fixed BL) R ead (BC4, on the fly) R ead (BL8, on the fly) R ead with auto precharge (Fixed BL) R ead with auto precharge (BC4, on the fly) R ead with auto precharge (BL8, on the fly) N o operation D evice deselect P ower-down mode entry PRE PALL ACT WRIT WRS4 WRS8 WRITA H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L L H H H H L L L H L L L L L L L L L L L L L L L L L H H L H L L L BA0 to A12 /RAS /CAS /WE BA2 (/BC) L L L × H L L L H H H H H H H H H H H H H × × H × H H H L L L × H H H H L L L L L L L L L L L L H × × H × H H H L H H × H L L H L L L L L L H H H H H H H × × H × H L L BA V V × V BA V BA BA BA BA BA BA BA BA BA BA BA BA BA V × × V × V × × op-code V V × V V V RA V L H V L H V L H V L H V × × V × V × × L L L H H H L L L H H H V × × V × V H L CA CA CA CA CA CA CA CA CA CA CA CA V × × V × V × × 5 , 11 9 10 5 , 11 V V × V L H V V × V V V 12 6, 8, 11 6 , 7, 8, 11 A10 Address (AP) Notes
WRAS4 H WRAS8 H READ RDS4 RDS8 H H H
READA H RDAS4 H RDAS8 H NOP DESL PDEN H H H H
P ower-down mode exit
PDEX
L L
Z Q calibration long Z Q calibration short
ZQCL ZQCS
H H
Remark: H = VIH. L = VIL. × = Don't care (defined or undefined (including floating around VREF)) logic level. V = VIH or VIL (defined logic level). BA = Bank addresses. RA = Row Address. CA = Column Address. /BC = Burst Chop.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
67
EDJ1104BDSE, EDJ1108BDSE
Notes: 1. All DDR3 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. The most significant bit (MSB) of BA, RA, and CA are device density and configuration dependent. 2. /RESET is an active low asynchronous signal that must be driven high during normal operation 3. Bank Addresses (BA) determine which bank is to be operated upon. For MRS, BA selects an mode register. 4. Burst READs or WRITEs cannot be terminated or interrupted and fixed/on the fly BL will be defined by MRS. 5. The power-down mode does not perform any refresh operations. 6. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 7. Self-refresh exit is asynchronous. 8. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation. 9. The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 10. The DESL command performs the same function as a NOP command. 11. Refer to the CKE Truth Table for more detail with CKE transition. 12. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9.
No Operation Command [NOP] The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The no operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP (/CS low, /RAS, /CAS, /WE high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Device Deselect Command [DESL] The deselect function (/CS high) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. Mode Register Set Command [MR0 to MR3] The mode registers are loaded via row address inputs. See mode register descriptions in the Programming the Mode Register section. The mode register set command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Bank Activate Command [ACT] This command is used to open (or activate) a row in a particular bank for a subsequent access. The values on the BA inputs select the bank, and the address provided on row address inputs selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. Note: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
68
EDJ1104BDSE, EDJ1108BDSE
Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8] The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8] The write command is used to initiate a burst write access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to memory; if the DM signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. Precharge Command [PRE, PALL] The precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA select the bank. Otherwise BA are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. A precharge command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto precharge Command [READA, WRITA] Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the read or write command is issued, then the auto precharge function is engaged. During auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is (AL* + tRTP) cycles later from the read with auto precharge command. Auto precharge can also be implemented during write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Note: AL (Additive Latency), refer to Posted /CAS description in the Register Definition section. Auto-Refresh Command [REF] Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to /CAS-before-/RAS (CBR) refresh in FPM/EDO DRAM. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an auto-refresh command. A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 × tREFI. This maximum absolute interval is to allow DDR3 output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
69
EDJ1104BDSE, EDJ1108BDSE
Self-Refresh Command [SELF] The self-refresh command can be used to retain data in the DDR3, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 retains data without external clocking. The self-refresh command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled upon entering self-refresh and is automatically enabled and reset upon exiting self-refresh. The active termination is also disabled upon entering self-refresh and enabled upon exiting self-refresh. (512 clock cycles must then occur before a read command can be issued). Input signals except CKE are "Don't Care" during self-refresh. The procedure for exiting self-refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back high. Once CKE is high, the DDR3 must have NOP commands issued for tXSDLL because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is to apply NOPs for 512 clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. ZQ calibration Command [ZQCL, ZQCS] ZQ calibration command (short or long) is used to calibrate DRAM RON and ODT values over PVT. ZQ Calibration Long (ZQCL) command is used to perform the initial calibration during power-up initialization sequence. ZQ Calibration Short (ZQCS) command is used to perform periodic calibrations to account for VT variations. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
70
EDJ1104BDSE, EDJ1108BDSE
CKE Truth Table
C KE Current state* P ower-down
2 *3
P revious C urrent 1 *1 cycle (n-1)* cycle (n) L L L H L H L L L L L L L H
C ommand (n) *3 / CS, /RAS, /CAS, /WE Operation (n) × D ESL or NOP × D ESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP R EFRESH M aintain power-down P ower-down exit M aintain self-refresh S elf-refresh exit A ctive power-down entry Power-down entry Power-down entry Power-down entry
N otes 14, 15 11, 14 15, 16 8, 12, 16 11, 13, 14 11, 13, 14, 17 11, 13, 14, 17 11, 13, 14, 17
S elf-refresh
L L
B ank Active R eading W riting P recharging R efreshing A ll banks idle
H H H H H H H
Precharge power-down entry 11 P recharge power-down entry 11, 13, 14, 18 Self-refresh entry 9, 13, 18 10
A ny state other than H listed above
Refer to the Command Truth Table
Remark: H = VIH. L = VIL. × = Don’t care Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) is the state of CKE at the previous clock edge. 2. Current state is the state of the DDR3 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n). ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 6. CKE must be registered with the same value on tCKE (min.) consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKE (min.) clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (min.) + tIH. 7. DESL and NOP are defined in the Command Truth Table. 8. On self-refresh exit, DESL or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT command may be issued only after tXSDLL is satisfied. 9. Self-refresh mode can only be entered from the all banks idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for power-down entry and exit are NOP and DESL only. 12. Valid commands for self-refresh exit are NOP and DESL only. 13. Self-refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. See section Power-Down and self-refresh Command for a detailed list of restrictions. 14. The power-down does not perform any refresh operations. 15. “×” means “don’t care” (including floating around VREF) in self-refresh and power-down. It also applies to address pins. 16. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation. 17. If all banks are closed at the conclusion of the read, write or precharge command, the precharge powerdown is entered, otherwise active power-down is entered. 18. Idle state means that all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress. CKE is high and all timings from previous operation are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
Preliminary Data Sheet E1494E50 (Ver. 5.0)
71
EDJ1104BDSE, EDJ1108BDSE
Simplified State Diagram
CKE_L
POWER APPLIED
POWER ON
RESET PROCEDURE
INITIALIZATION
MRS, MPR, WRITE LEVELING
SELF SELFX REF
SELF REFRESH
MRS
FROM ANY STATE
RESET
ZQ CALIBRATION
ZQCL ZQCS
IDLE
REFRESHING
ACT
PDEN PDEX
ACTIVE POWER DOWN
ACTIVATING
PRECHARGE POWER DOWN
CKE_L
PDEN
PDEX
CKE_L
BANK ACTIVE
WRIT WRIT
WRITA
WRITING
READ READ
READA READ
READING
WRIT
WRITA WRITA
WRITING
READA
READA
PRE, PALL
READING
PRE, PALL
PRE, PALL
PRECHARGING
Automatic sequence Command sequence
Preliminary Data Sheet E1494E50 (Ver. 5.0)
72
EDJ1104BDSE, EDJ1108BDSE
RESET and Initialization Procedure
Power-Up and Initialization Sequence 1. Apply power (/RESET is recommended to be maintained below 0.2 × VDD, (all other inputs may be undefined). ) /RESET needs to be maintained for minimum 200µs with stable power. CKE is pulled low anytime before /RESET being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD (min.) must be no greater than 200ms; and during the ramp, VDD > VDDQ and (VDD − VDDQ) < 0.3V. • VDD and VDDQ are driven from a single power converter output AND • The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND • VREF tracks VDDQ/2. OR • Apply VDD without any slope reversal before or at the same time as VDDQ. • Apply VDDQ without any slope reversal before or at the same time as VTT and VREF. • The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After /RESET is de-asserted, wait for another 500µs until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clocks (CK, /CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also a NOP or DESL command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “high” after Reset, CKE needs to be continuously registered high until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 SDRAM will keep its on-die termination in high-impedance state during /RESET being asserted at least until CKE being registered high. Therefore, the ODT signal may be in undefined state until tIS before CKE being registered high. After that, the ODT signal must be kept inactive (low) until the power-up and initialization sequence is finished, including expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of tXPR, before issuing the first MRS command to load mode register. (tXPR = max. (tXS ; 5 × tCK) 6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide low to BA0 and BA2, high to BA1.) 7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide low to BA2, high to BA0 and BA1.) 8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue DLL Enable command, provide low to A0, high to BA0 and low to BA1 and BA2). 9. Issue MRS command to load MR0 with all application settings and DLL reset. (To issue DLL reset command, provide high to A8 and low to BA0 to BA2). 10. Issue ZQCL command to start ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3 SDRAM is now ready for normal operation.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
73
EDJ1104BDSE, EDJ1108BDSE
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, /CK
tCKSRX max. (10 ns; 5tCK)
VDD, VDDQ
200ms
500ms
/RESET
10ns
tIS
CKE
* tXPR tIS
Command BA
2
tDLLK
tMRD
tMRD
tMRD
tMOD
tZQinit
*1
tIS
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQcal
ODT DRAM_RTT
Notes: 1. From time point "Td" until "Tk", NOP or DESL commands must be applied between MRS and ZQcal commands. 2. tXPR = max. (tXS; 5tCK)
: VIH or VIL
Reset and Initialization Sequence at Power-On Ramping Reset and Initialization with Stable Power The following sequence is required for /RESET at no power interruption initialization. 1. Assert /RESET below 0.2 × VDD anytime when reset is needed (all other inputs may be undefined). /RESET needs to be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time 10ns). 2. Follow Power-Up Initialization Sequence steps 2 to 12. 3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, /CK
tCKSRX max. (10 ns; 5tCK)
VDD, VDDQ
100ns
/RESET
500ms
10ns
CKE
tIS
* tXPR tIS
Command BA
2
tDLLK
tMRD
tMRD
tMRD
tMOD
ZQCL
tZQinit
*1
tIS
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ODT DRAM_RTT
Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be applied between MRS and ZQCL commands. 2. tXPR = max. (tXS; 5tCK)
: VIH or VIL
Reset Procedure at Power Stable Condition
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Programming the Mode Register
For application flexibility, various functions, features and modes are programmable in four mode registers, provided by the DDR3 SDRAM, as user defined variables, and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, content of mode registers must be fully initialized and/or re-initialized, i.e. written, after Power-up and/or reset for proper operation. Also the contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset does not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands. The MRS command to non-MRS command delay, tMOD, is required for the DRAM to update the features except DLL reset and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is already high prior to writing into the mode register. The mode registers are divided into various fields depending on the functionality and/or modes. Mode Register Set Command Cycle Time (tMRD) tMRD is the minimum time required from an MRS command to the next MRS command. As DLL enable and DLL reset are both MRS commands, tMRD is applicable between MRS to MR1 for DLL enable and MRS to MR0 for DLL reset, and not tMOD.
/CK CK
Command
MRS
NOP
tMRD
MRS
NOP
tMRD Timing MRS Command to Non-MRS Command Delay (tMOD) tMOD is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. Note that additional restrictions may apply, for example, MRS to MR0 for DLL reset followed by read.
/CK CK
Command
MRS
NOP
tMOD
non-MRS
NOP
Old setting
Updating
New Setting
tMOD Timing
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
DDR3 SDRAM Mode Register 0 [MR0] The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, /CAS latency, test mode, DLL reset, WR and DLL control for precharge power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the states of address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address field
0*1
0
0
0*1 PPD
WR
DLL TM
/CAS latency
RBT CL
BL
Mode register 0
A8 0 1
BA1 BA0 0 0 1 1
0 1 0 1
DLL reset No Yes
A7 0 1
Mode Normal Test
A3 0 1
Read burst type Nibble sequential Interleave
Burst length
A1 0 0 1 1
A0 0 1 0 1
BL 8 (Fixed) 4 or 8 (on the fly) 4 (Fixed) Reserved
MRS mode MR0 MR1 MR2 MR3
Write recovery for autoprecharge A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR Reserved 5*2 6*2 7*2 8*2 10*2 12*2 Reserved
/CAS latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1
A2 0 0 0 0 0 0 0 0
Latency Reserved 5 6 7 8 9 10 11
A12 DLL Control for Precharge PD 0 1 Slow exit (DLL off) Fast exit (DLL on)
Notes: 1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS. 2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR (min.) [cycles] = roundup tWR (ns) / tCK (ns)). (The WR value in the mode register must be programmed to be equal or larger than WR (min.) This is also used with tRP to determine tDAL.
MR0 Programming
Preliminary Data Sheet E1494E50 (Ver. 5.0)
76
EDJ1104BDSE, EDJ1108BDSE
DDR3 SDRAM Mode Register 1 [MR1] The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins according to the table below
BA2 BA1 BA0 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address field
0*1
0
1
0*1
Qoff TDQS 0*1
Rtt_Nom
0*1 Level Rtt_Nom D.I.C
AL
Rtt_Nom D.I.C
DLL
Mode register 1
A11 0 1
TDQS enable Disabled Enabled
A9 A6 A2 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
RTT_Nom*5 ODT Disabled RZQ/4 RZQ/2 RZQ/6 RZQ/12*4 RZQ/8*4 Reserved Reserved
Output driver
A0 0 1
DLL enable Enable Disable
A7 0 1
Write leveling enable Disabled Enabled
1 1 1
A12 0 1
Qoff Output buffers enabled Output buffers disabled*2
A4 0 0 1 1
A3 0 1 0 1
Additive Latency 0 (AL disabled) CL-1 CL-2 Reserved
A5 0 0 1 1
A1 0 1 0 1
impedance control RZQ/6 RZQ/7 RZQ/TBD RZQ/TBD
Notes: 1. 2. 3. 4. 5.
BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS. Outputs disabled - DQ, DQS, /DQS. RZQ = 240Ω If RTT_Nom is used during writes, only the values RZQ/2, RZQ/4 and RAQ/6 are allowed. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] =1) with MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed
MR1 Programming
Preliminary Data Sheet E1494E50 (Ver. 5.0)
77
EDJ1104BDSE, EDJ1108BDSE
DDR3 SDRAM Mode Register 2 [MR2] The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on BA0, while con-trolling the states of address pins according to the table below.
BA2 BA1 BA0 A13 0*1 1 A12 0*1 A11 A10 A9 A8 0*1 A7 A6 A5 A4 A3 A2 A1 A0
Address field Mode register 2
0
Rtt_WR*2
SRT ASR
CWL
PASR* 2
A7 0 1
Self-refresh range Normal self-refresh Extend temperature self-refresh
Partial array self-refresh
A2 0 0 0 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Full Half : Bank 0 to Bank 3 Refresh array
(BA [2:0] = 000, 001, 010, 011) (BA [2:0] = 000) (BA [2:0] = 010, 011, 100, 101,110 ,111) (BA [2:0] = 100, 101, 110, 111) (BA [2:0] = 111)
Quarter: Bank 0 and Bank 1 (BA [2:0] = 000, 001) 1/8 3/4 Half : Bank 0 : Bank 2 to Bank 7 : Bank 4 to Bank 7
A6 0 1
Auto self-refresh method Manual SR reference (SRT) ASR enable (Optional)
0 1 1 1 1
Quarter: Bank 6 and Bank 7 (BA [2:0] = 110, 111) 1/8 : Bank 7
A5 A10 0 0 1 1 A9 0 1 0 1 Rtt_WR Dynamic ODT off (write does not affect Rtt value) RZQ/4 RZQ/2 Reserved 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1
A3 0 1 0 1 0 1 0 1
CAS write Latency (CWL) 5 (tCK ≥ 2.5ns) 6 (2.5ns > tCK ≥ 1.875ns) 7 (1.875ns > tCK ≥ 1.5ns) 8 (1.5ns > tCK ≥ 1.25ns) Reserved Reserved Reserved Reserved
Notes: 1. BA2, A8, and A11 to A13 are RFU and must be programmed to 0 during MRS. 2. The Rtt_WR value can be applied during writes even when Rtt_Nom is desabled. Dring write leveling, Dynamic ODT is not avaiable. 3. Optiona in DDR3 SDRAM: If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self-refresh is entered. Data integrity will be maintained if tREF conditions are met and no self-refresh command is issued.
MR2 Programming
Preliminary Data Sheet E1494E50 (Ver. 5.0)
78
EDJ1104BDSE, EDJ1108BDSE
DDR3 SDRAM Mode Register 3 [MR3] The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and BA0, while controlling the states of address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address field Mode register 3
0*1
1
1
0*1
MPR
MPR Loc
MPR Address MPR location A1 A0 MPR Operation
0
0 1 0 1
Predefined pattern*2 RFU RFU RFU
A2 0 1
MPR Normal operation*3 Data flow from MPR
0 1 1
Notes : 1. BA2, A3 to A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
2. The predefined pattern will be used for read synchronization. 3 . When MPR control is set for normal operation, MR3 A[2]=0, MR3 A[1:0] will be ignored.
MR3 Programming
Preliminary Data Sheet E1494E50 (Ver. 5.0)
79
EDJ1104BDSE, EDJ1108BDSE
Burst Length (MR0) Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as shown in the figure MR0 Programming. The burst length determines the maximum number of column locations that can be accessed for a given read or write command. Burst length options include fixed BC4, fixed BL8, and on the fly which allows BC4 or BL8 to be selected coincident with the registration of a read on write command Via A12 (/BC). Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Burst Chop In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on the fly via A12(/BC), the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
Burst Type (MR0) [Burst Length and Sequence]
B urst length 4 (burst chop) Operation READ Starting address (A2, A1, A0) 000 0 01 0 10 0 11 1 00 1 01 1 10 1 11 W RITE 0VV 1 VV 8 R EAD 000 0 01 0 10 0 11 1 00 1 01 1 10 1 11 W RITE VVV Sequential addressing (decimal) 0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Interleave addressing (decimal) 0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7
Remark: T: Output driver for data and strobes are in high impedance. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. X: Don’t Care. Notes: 1. Page length is a function of I/O organization and column addressing 2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
80
EDJ1104BDSE, EDJ1108BDSE
DLL Enable (MR1) The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering selfrefresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any write operation. DDR3 does not require DLL to be locked prior to any write operation. DDR3 requires DLL to be locked only for read operation and to achieve synchronous ODT timing. DLL-off Mode DDR3 DLL-off mode is entered by setting MR1 bit A0 to 1; this will disable the DLL for subsequent operations until A0 bit set back to 0. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLLoff mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of /CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL = 6 and CWL = 6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the Data Strobe to Data relationship (tDQSQ, tQH, tQHS). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL + CL − 1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCK (min.). and tDQSCK (max.) is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation are shown at following Timing Diagram (CL = 6, BL8):
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CK, /CK Command BA DQSdiff_DLL-on
RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6
READ
A
DQ_DLL-on
RL (DLL-off) = AL + (CL - 1) = 5
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
tDQSCK(DLL-off)_min
DQSdiff_DLL-off DQ_DLL-off
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
tDQSCK(DLL-off)_max
DQSdiff_DLL-off DQ_DLL-off
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
DLL-Off Mode Read Timing Operation
Preliminary Data Sheet E1494E50 (Ver. 5.0)
81
EDJ1104BDSE, EDJ1108BDSE
DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set back to “0”. DLL “on” to DLL “off” Procedure To switch from DLL “on” to DLL “off” requires the frequency to be changed during self-refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL.) 2. Set MR1 Bit A0 to “1” to disable the DLL. 3. Wait tMOD. 4. Enter self-refresh mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. After stable clock, wait tCKSRX before issuing SRX command. 7. Starting with the self-refresh exit command, CKE must continuously be registered high until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when selfrefresh mode was entered, the ODT signal must continuously be registered low until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when self-refresh mode was entered, ODT signal can be registered low or high. 8. Wait tXS, then set mode registers with appropriate values (especially an update of CL, CWL and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, then DRAM is ready for next command.
Ta
CK /CK
tMOD
tCKSRE
tCKSRX
tXS
tMOD
MRS Valid
Tb
Tc Tc+1 Tc+2
Td
Te
Tf Tf+1 Tf+2
Tg Tg+1
Th
Command
MRS
SRE NOP
SRX
tCKESR
CKE
ODT
Change Frequency
DLL Switch Sequence from DLL-on to DLL-off
Preliminary Data Sheet E1494E50 (Ver. 5.0)
82
EDJ1104BDSE, EDJ1108BDSE
DLL “off” to DLL “on” Procedure To Switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.) 2. Enter Self-refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the self-refresh exit command, CKE must continuously be registered high until all tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self-refresh mode was entered, the ODT signal must continuously be registered low until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered low or high. 6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL. 7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset. 8. Wait tMRD, and then set mode registers with appropriate values (especially an update of CL, CWL and WR may be necessary. After tMOD is satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK.) 9. Wait for tMOD, and then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL). In addition, wait also for tZQoper in case a ZQCL command was issued.
Ta CK /CK
tCKSRE
tCKSRX
tXS
tMRD
MRS
Tb
Tc Tc+1Tc+2
Td
Te
Tf Tf+1 Tf+2
Tg
tDLLK
tMRD
MRS
Command
SRE NOP
SRX
MRS
Valid
tCKESR
CKE
ODTLoff + 1x tCK
ODT
Change Frequency
DLL Switch Sequence from DLL-Off to DLL-On
Preliminary Data Sheet E1494E50 (Ver. 5.0)
83
EDJ1104BDSE, EDJ1108BDSE
Additive Latency (MR1) A posted /CAS read or write command when issued is held for the time of the Additive Latency (AL) before it is issued inside the device. The read or write posted /CAS command may be issued with or without auto precharge. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). The value of AL is also added to compute the overall Write Latency (WL). MRS (1) bits A4 and A3 are used to enable Additive latency.
M RS1 A4 0 0 1 1 A3 0 1 0 1 AL* 0 ( posted CAS disabled) CL − 1 CL − 2 R eserved
Note: AL has a value of CL − 1 or CL − 2 as per the CL value programmed in the /CAS latency MRS setting.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
84
EDJ1104BDSE, EDJ1108BDSE
Write Leveling (MR1) For better signal integrity, DDR3 memory module adopts fly by topology for the commands, addresses, control signals and clocks. The fly by topology has benefits for reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes Controller hard to maintain tDQSS, tDSS and tDSH specification. Therefore, the controller should support ’write leveling’ in DDR3 SDRAM to compensate the skew. Write leveling is a scheme to adjust DQS to CK relationship by the controller, with a simple feedback provided by the DRAM. The memory controller involved in the leveling must have adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay established through this exercise would ensure tDQSS, tDSS and tDSH specification. A conceptual timing of this scheme is shown as below.
Source diff_Clock diff_DQS Destination
diff_Clock diff_DQS DQ X 0 0
Push DQS to capture 0-1 transition
DQ X 1 1
Write leveling concept DQS, /DQS driven by the controller during leveling mode must be terminated by the DRAM, based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations ×4, ×8. DRAM Setting for Write Leveling and DRAM Termination Function in That Mode DRAM enters into Write leveling mode if A7 in MR1 set 1. And after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set 0 (MR1 Setting Involved in the Leveling Procedure table). Note that in write leveling mode, only DQS/DQS terminations are activated and deactivated via ODT pin, not like normal operation (refer to the DRAM Termination Function in The Leveling Mode table) [MR1 Setting Involved in the Leveling Procedure]
F unction Write leveling enable O utput buffer mode (Qoff) MR1 bit A7 A12 Enable 1 0 Disable 0 1 1 Note
Note: 1. Output buffer mode definition is consistent with DDR2 [DRAM Termination Function in The Leveling Mode]
O DT pin@DRAM De-asserted A sserted DQS, /DQS termination Off On DQs termination Off Off
Note: In Write Leveling Mode with its output buffer disabled (MR1 [bit7] = 1 with MR1 [bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1 [bit7] = 1 with MR1 [bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
85
EDJ1104BDSE, EDJ1108BDSE
Write Leveling Procedure Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the DRAM to sample CK driven from controller. tWLMRD timing is controller dependent. DRAM samples CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS delay setting and launches the next DQS, /DQS pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS delay setting and write leveling is achieved for the device. The below figure describes detailed timing diagram for overall procedure and the timing parameters are shown in below figure.
tWLS T1
tWLS
T2
tWLH
CK*5 /CK Command
*2 *2
MRS
tWLH
*3 *4
NOP NOP NOP NOP NOP NOP NOP NOP
*3
NOP NOP NOP
tMOD
ODT
tWLDQSEN
*6 *6 tDQSL (min.) tDQSH (min.) tDQSL (min.)
tDQSH (min.)
diff_DQS*4
tWLOE
All DQs*1
tWLMRD
tWLO
tWLO
Notes:1. DDR3 SDRAM drives leveling feedback on all DQs. 2. MRS : Load MR1 to enter write leveling mode. 3. NOP : NOP or deselec 4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference points are the zero crossing. DQS is shown with solid line, /DQS is shown with dotted line. 5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line. 6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL (min.) as defined for regular writes; the max pulse width is system dependent.
Timing Details Write Leveling Sequence
Preliminary Data Sheet E1494E50 (Ver. 5.0)
86
EDJ1104BDSE, EDJ1108BDSE
Write Leveling Mode Exit The following sequence describes how the Write Leveling Mode should be exited: 1. After the last rising strobe edge(see T111), stop driving the strobe signals (see ~T128). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (T145). 2. Drive ODT pin low (tIS must be satisfied) and continue registering low (see T128). 3. After the RTT is switched off: disable Write Level Mode via MR command (see T132). 4. After tMOD is satisfied (T145), any valid commands may be registered. (MR commands may already be issued after tMRD (T136).
T111 T112 T116 T117 T128 T131 T132 T136 T145
CK, /CK
Command
WL_off
MRS
Valid
tMOD
BA
tIS
1
Valid
Valid Valid
tMRD
ODT
tODTL_off
RTT_DQS-/DQS DQS-/DQS RTT_DQ
tWLO + tWLOE
DQ
Result = 1
Timing Details Write leveling Exit
Preliminary Data Sheet E1494E50 (Ver. 5.0)
87
EDJ1104BDSE, EDJ1108BDSE
TDQS, /TDQS function (MR1) TDQS (Termination Data Strobe) is a feature of ×8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. TDQS is not supported in ×4 configurations. When enabled via the mode register, the same termination resistance function is applied to the TDQS and /TDQS pins that are applied to the DQS and /DQS pins. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided and the /TDQS pin is not used. See Table TDQS, /TDQS function for details. The TDQS function is available in ×8 DDR3 SDRAM only and must be disabled via the mode register A11 = 0 in MR1 for ×4 configurations. [TDQS, /TDQS function]
A 11@MR1 0 1 TDQS enable Disable E nable
Notes: 1. If TDQS is enabled, the DM function is disabled. 2. When not used, TDQS function can be disabled to save termination power. 3. TDQS function is only available for ×8 DRAM and must be disabled for ×4. [Function matrix]
A 11@MR1 (TDQS enable) 0 1 DM/TDQS DM T DQS NU/ /TDQS High-Z /TDQS
Preliminary Data Sheet E1494E50 (Ver. 5.0)
88
EDJ1104BDSE, EDJ1108BDSE
Extended Temperature Usage (MR2) [Mode Register Description]
F ield Bits Description Description Auto self-refresh (ASR) (Optional) when enabled, DDR3 SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation If ASR = 1, SRT bit must be set to 0
ASR
A6
0 1
Manual SR Reference (SRT) ASR enable (optional)
S RT
A7
0 1
Normal operating temperature range Extended operating temperature range
Partial Array Self-Refresh (PASR) Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure of MR2 programming will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. /CAS Write Latency (CWL) The /CAS Write Latency is defined by MR2 bits [A3, A5], as shown in figure of MR2 programming. /CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + /CAS Write Latency (CWL); WL = AL + CWL. For more information on the sup-ported CWL and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. For detailed Write operation refer to “WRITE Operation”. Auto Self-Refresh Mode - ASR Mode (optional) DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6 = 1 and MR2 bit A7 = 0. The DRAM will manage self-refresh entry in either the Normal or Extended (optional) Temperature Ranges. In this mode, the DRAM will also manage self-refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0. If the ASR mode is not enabled (MR2 bit A6 = 0), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during self-refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Self- Refresh Temperature Range - SRT If ASR = 0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0, then the DRAM will set an appropriate refresh rate for self-refresh operation in the Normal Temperature Range. If SRT = 1 then the DRAM will set an appropriate, potentially different, refresh rate to allow self-refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table for details. For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0 and the DRAM should not be operated outside the Normal Temperature Range.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
89
EDJ1104BDSE, EDJ1108BDSE
[Self-Refresh Mode Summary]
M R2 A6 0 A7 0 Self-refresh operation S elf-refresh rate appropriate for the Normal Temperature Range S elf-refresh rate appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can effect self-refresh power consumption, please refer to the Self- refresh Current for details. A SR enabled (for devices supporting ASR and Normal Temperature Range). Self-refresh power consumption is temperature dependent A SR enabled (for devices supporting ASR and Extended Temperature Range). Self-refresh power consumption is temperature dependent I llegal Allowed operating temperature range for self-refresh mode Normal (0 ° C to +85 ° C)
0
1
Normal and Extended (0 ° C to +95 ° C)
1
0
Normal (0 ° C to +85 ° C) Normal and Extended (0 ° C to +95 ° C)
1 1
0 1
Dynamic ODT (Rtt_WR) DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2 register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
90
EDJ1104BDSE, EDJ1108BDSE
Multi Purpose Register (MR3) The Multi Purpose Register (MPR) function is used to read out predefined system timing calibration bit sequence.
Memory Core
MR3 A2: MPR-off
MPR Read
Multi Purpose Register Pre-defined data for Reads
DQ, DM, DQS, /DQS Pads
Pre-defined data pattern can be loaded into Multi Purpose Register (MPR) and read out by external read command. · MR3 bit A2 defines dataflow from normal memory core or MPR. Once the dataflow defined, the MPR contents can be continuously read out by regular READ or READ with Auto Precharge command.
·
Conceptual Block Diagram of Multi Purpose Register To enable the MPR, a Mode Register set (MRS) command must be issued to MR3 register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP/tRPA met). Once the MPR is enabled, any subsequent READ or READA commands will be redirected to the multi purpose register. The resulting operation when a READ or READA command is issued is defined by MR3 bits [A1: A0] when the MPR is enabled. When the MPR is enabled, only READ or READA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power-down mode, self-refresh, and any other nonREAD/READA command are not allowed during MPR enable mode. The /RESET function is supported during MPR enable mode. [Functional Description of MR3 Bits for MPR]
M R3 A2 M PR 0 1 A [1:0] MPR-Loc D on’t care (0 or 1) M R3 A [1:0] Function Notes
Normal operation, no MPR transaction. All subsequent reads will come from DRAM array. All subsequent WRITEs will go to DRAM array. Enable MPR mode, subsequent READ/READA commands defined by MR3 1 A [1:0] bits.
Note: 1. See Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register table
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
• One bit wide logical interface via all DQ pins during READ operation Register Read on ×4: DQ [0] drives information from MPR. DQ [3:1] drive the same information as DQ [0]. Register Read on ×8: DQ [0] drives information from MPR. DQ [7:1] drive the same information as DQ [0]. Note: A standardization of which DQ is used by DDR3 SDRAM for MPR reads is strongly recommended to ensure functionality also for AMB2 on DDR3 FB-DIMM. • Addressing during Multi Purpose Register reads for all MPR agents: BA [2:0]: don’t care. A [1:0]: A [1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed A [2]: For BL8, A [2] must be equal to 0. 1 Burst order is fixed to [0,1,2,3,4,5,6,7] * For Burst Chop 4 cases, the burst order is switched on nibble base A [2] = 0, Burst order: 0,1,2,3 *1 1 A [2] = 1, Burst order: 4,5,6,7 * A [9:3]: don’t care A10(AP): don’t care A12(/BC): Selects burst chop mode on-the-fly, if enabled within MR0 A11: don’t care • Regular interface functionality during register reads: Support two burst ordering which are switched with A2 and A [1:0] = 00. Support of read burst chop (MRS and on-the-fly via A12(/BC). All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3 SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads. Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Functional Block Diagrams Figures below provide functional block diagrams for the multi purpose register in ×4, ×8 DDR3 SDRAM.
Memory Array
4× 8 4× 8
32
Copy to DQ[3:0]
8
DQ[3:0] Read Path
DQS /DQS
Q MPR
DM
NibbleLane
Functional Block Diagram of Multi Purpose Register in ×4 DDR3 SDRAM
Memory Array
8× 8 8× 8
64
Copy to DQ[7:0]
8
DQ[7:0] Read Path
DQS /DQS
Q MPR
DM
ByteLane
Functional Block Diagram of Multi Purpose Register in ×8 DDR3 SDRAM
Preliminary Data Sheet E1494E50 (Ver. 5.0)
93
EDJ1104BDSE, EDJ1108BDSE
Register Address Table The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register read. [Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register]
M R3 A [2] MR3 A [1:0] Function Read predefined pattern for system calibration Burst Length BL8 B C4 BC4 B L8 1 01 RFU B C4 BC4 B L8 1 10 RFU B C4 BC4 B L8 1 11 RFU B C4 BC4 Read Address Burst Order and Data Pattern A [2:0] 000 000 100 000 000 100 000 000 100 000 000 100 Burst order 0,1,2,3,4,5,6,7 Pre-defined pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3, Pre-defined pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined pattern [0,1,0,1] Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3, Burst order 4,5,6,7 Notes 1 1 1 1 1 1 1 1 1 1 1 1
1
00
Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Relevant Timing Parameters The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD and tMPRR. Besides these timings, all other timing parameters needed for proper operation of the DDR3 SDRAM need to be observed. [MPR Recovery Time tMPRR] Symbol Description tMPRR Multi Purpose Register Recovery Time, defined between end of MPR read burst and MRS which reloads MPR or disables MPR function
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Protocol Examples Protocol Example: Read Out Predetermined Read-Calibration Pattern Multiple reads from Multi Purpose Register, in order to do system level read timing calibration based on predetermined and standardized pattern. Protocol Steps: • Precharge All • Wait until tRP is satisfied • MRS MR3, op-code “A2 = 1 “ and “A[1:0] = 00“ Redirect all subsequent reads into the Multi Purpose Register, and load Pre-defined pattern into MPR. • Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the period MR3 A2 =1, no data write operation is allowed. • Read: A [1:0] = ‘00’ (Data burst order is fixed starting at nibble, always 00 here) A [2] = ‘0’ (For BL8, burst order is fixed as 0,1,2,3,4,5,6,7) A12(/BC) = 1 (use regular burst length of 8) All other address pins (including BA [2:0] and A10(AP)): don’t care. • After RL = AL + CL, DRAM bursts out the predefined Read Calibration Pattern. • Memory controller repeats these calibration reads until read data capture at memory controller is optimized. • After end of last MPR read burst wait until tMPRR is satisfied. • MRS MR3, op-code “A2 = 0“ and “A[1:0] = valid data but value are don’t care“ All subsequent read and write accesses will be regular READs and WRITEs from/to the DRAM array. • Wait until tMRD and tMOD are satisfied • Continue with “regular” DRAM commands, like activate a memory bank for regular read or write access,
T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T39
CK /CK
tMRD
Command
tMOD *1
READ
NOP
PALL
NOP
MRS
NOP
MRS
NOP
tRP
tMOD
tMPRR
Valid
BA A[1:0] A[2] A[9:3] A10(AP) A[11] A12(/BC) A[15:13]
3
0
3
Valid
0
*2
1
00
1
0
0
*2
0
00
0
0
0
0
Valid
Valid
Valid
Valid
Valid
0
0
0
*1
DQS, /DQS
RL
DQ
Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0]
VIH or VIL
MPR Readout of Predefined Pattern, BL8 fixed Burst Order, Single Readout
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK tMRD Command
PALL NOP MRS NOP *1 READ NOP *1 READ NOP
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
T43
tMOD
MRS NOP
tRP BA A[1:0] A[2] A[9:3] A10, AP A[11] A12(/BC) A[15:13] DQS, /DQS 1 3 0 1 00 0 0 0 0
tMOD
Valid
*2 *2
tCCD
Valid
tMPRR 3
Valid
*2 *2
0 0
0 0
0 00 0 0 0 0
Valid Valid Valid Valid Valid
*1
Valid Valid Valid Valid Valid
*1
RL RL DQ Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0]
VIH or VIL
MPR Readout of Predefined Pattern, BL8 Fixed Burst Order, Back-to-Back Readout
T0
CK
/CK
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
T43
tMRD
Command
PALL
NOP
tMOD
*1 READ
NOP *1 READ
NOP
MRS
NOP
MRS
NOP
tRP
tMOD
tCCD
Valid
Valid
*2 *3
*2 *4
tMPRR
BA A[1:0] A[2] A[9:3] A10(AP) A[11] A12(/BC) A[15:13]
3
0
1
00
1
3
Valid
0
0
0
1
0
00
0
0
0
0
Valid
Valid
Valid
Valid
Valid
*1
Valid
Valid
Valid
Valid
Valid
*1
0
0
0
0
DQS, /DQS
RL
RL
DQ
VIH or VIL
Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7
MPR Readout Predefined Pattern, BC4, Lower Nibble Then Upper Nibble
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
T0
CK, /CK
T4 T5
T9
T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31
T43
tMRD
Command
PALL
NOP
tMOD
READ
MRS
NOP
*1
NOP
READ
*1
NOP
MRS
NOP
tRP
tMOD
tCCD
Valid
Valid
tMPRR
BA A[1:0] A[2] A[9:3] A10, AP A[11] A12(/BC) A[15:13]
3
0
1
00
1
3
Valid
0
1
*2 *4
0
0
*2 *3
0
00
0
0
0
0
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0
0
0
0
*1
*1
DQS, /DQS
RL
RL
DQ
Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7
VIH or VIL
MPR Readout of Predefined Pattern, BC4, Upper Nibble Then Lower Nibble
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
Operation of the DDR3 SDRAM
Read Timing Definition Read timing is shown in the following Figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: • tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, /CK. • tDQSCK is the actual position of a rising strobe edge relative to CK, /CK. • tQSH describes the DQS, /DQS differential output high time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: • tQSL describes the DQS, /DQS differential output low time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined.
/CK
CK
tDQSCK(min.) tDQSCK(min.) tDQSCK(max.) tDQSCK(max.)
Rising Strobe Region
Rising Strobe Region
tDQSCK tQSH tQSL
tDQSCK
/DQS
DQS tQH tDQSQ tQH tDQSQ
Associated DQ Pins
READ Timing Definition
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
• • • • • CK, /CK crossing to DQS, /DQS crossing tDQSCK; rising edges only of CK and DQS tQSH; rising edges of DQS to falling edges of DQS tQSL; rising edges of / DQS to falling edges of /DQS tLZ (DQS), tHZ (DQS) for preamble/postamble (see tHZ (DQS), tLZ (DQS)
RL Measured to this point
CK /CK
tDQSCK(min.)
tDQSCK(min.)
tDQSCK(min.)
tDQSCK(min.)
tLZ(DQS)(min.)
tQSH
tQSL
tRPRE
tRPST
DQS, /DQS Early strobe
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
tDQSCK(max.)
tDQSCK(max.)
tDQSCK(max.)
tDQSCK(max.)
tLZ(DQS)(max.)
tQSH tQSL
tHZ(DQS)(max.)
tRPRE
tRPST
DQS, /DQS Late strobe
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Notes: Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min.) or tDQSCK(max.). Instead, rising strobe edge can vary between tDQSCK(min.) or tDQSCK(max.) within a burst. Likewise tLZ(DQS)(min.) and tHZ(DQS)(min.) are not tied to tDQSCK(min.) (early strobe case) and tLZ(DQS)(max.) and tHZ(DQS)(max.) are not tied to tDQSCK(max.) (late strobe case). The minimum pulse width of read preamble is defined by tRPRE(min.). The minimum pulse width of read preamble is defined by tRPST(min.).
DDR3 Clock to Data Strobe Relationship
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
• DQS, /DQS crossing to Data Output • tDQSQ; both rising/falling edges of DQS, no tAC defined
T0 /CK CK Command*3
READ
T4
T5
T6
T7
T8
T9
T10
NOP RL = AL + CL
Address*4
Bank Coln
tRPRE
tQH
tQH
tRPST
DQS, /DQS
tDQSQ(max.) tLZ(DQ)(max.) tDQSQ(max.) tHZ(DQ)(max.)
DQ*2
(Last data valid)
tLZ(DQ)(min.)
Dout n
Dout n+1
Dout n+2
Dout n+3
Dout n+4
Dout n+5
Dout n+6
Dout n+7
DQ*2
(First data no longer valid)
Dout n
Dout n+1
Dout n+2
Dout n+3
Dout n+4
Dout n+5
Dout n+6
Dout n+7
All DQS collectively
Dout n
Dout n+1
Dout n+2
Dout n+3
Dout n+4
Dout n+5
Dout n+6
Dout n+7
Data valid
Data valid
VIH or VIL Notes: 1. BL8, RL = 5(AL = 0, CL = 5). 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] and A12 = 1 during READ command at T0. 5. Output timings are referenced to VDDQ/2, and DLL on for locking. 6. tDQSQ defines the skew between DQS, /DQS to data and does not define DQS, /DQS to clock. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary(either early or late) within a busy.
DDR3 Data Strobe to Data Relationship
Preliminary Data Sheet E1494E50 (Ver. 5.0)
100
EDJ1104BDSE, EDJ1108BDSE
tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). The figure below shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled ended.
tLZ (DQS): CK-/CK rising crossing at RL-1 tLZ (DQ): CK-/CK rising crossing at RL
tHZ (DQS), tHZ (DQ) with BL8: CK-/CK rising crossing at RL + 4nCK tHZ (DQS), tHZ (DQ) with BL4: CK-/CK rising crossing at RL + 2nCK
CK
CK
/CK tLZ
VTT + 2x mV VTT + x mV tLZ (DQS), tLZ (DQ) VTT − x mV VTT − 2x mV
/CK tLZ
VOH − x mV VOH − 2x mV
tHZ (DQS), tHZ (DQ)
T2
T2
T1
VOL + 2x mV VOL + x mV
T1
tLZ (DQS), tLZ (DQ) begin point = 2 ´ T1 - T2
tHZ (DQS), tHZ (DQ) end point = 2 ´ T1 - T2
Method for Calculating Transitions and Endpoints
Preliminary Data Sheet E1494E50 (Ver. 5.0)
101
EDJ1104BDSE, EDJ1108BDSE
Read Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). • A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) • A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the Mode Register 0 (MR0), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the Mode Register 1
T0 CK /CK Command*3
READ
NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Address*4
Bank Col n
tRPRE
tRPST
DQS, /DQS
DQ*2
CL = 5
RL = AL + CL
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
VIH or VIL
Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Burst Read Operation, RL = 5
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Address*4
Bank Col n
tRPRE
tRPST
DQS, /DQS*2
DQ
AL = 4 RL = AL + CL CL = 5
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
VIH or VIL Notes: 1. BL8, RL = 9, AL = (CL − 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Burst Read Operation, RL = 9
T0 CK /CK Command*3
READ
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
tCCD
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
RL = 5
VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and T4.
READ (BL8) to READ (BL8)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ
NOP
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
tCCD
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tRPRE
tRPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout n n+1 n+2 n+3
Dout Dout Dout Dout b b+1 b+2 b+3
RL = 5
VIH or VIL Notes: 1. BC4, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and T4.
READ (BC4) to READ (BC4)
T0 CK /CK Command*3
READ
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14 T15
NOP
WRIT
NOP
tWR tBL = 4 clocks
tWTR
READ to WRIT command delay = RL + tCCD + 2tCK − WL
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Din b
Din b+1
Din b+2
Din b+3
Din b+4
Din b+5
Din b+6
Din b+7
WL = 5
VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and WRIT command T6.
READ (BL8) to WRITE (BL8)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
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EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14 T15
WRIT
NOP
tBL = 4 clocks
tWR
tWTR
READ to WRIT Command delay = RL + tCCD/2 + 2tCK − WL
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout n n+1 n+2 n+3
Din b
Din b+1
Din b+2
Din b+3
WL = 5
VIH or VIL
Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and WRIT command T4.
READ (BC4) to WRITE (BC4) OTF
T0 CK /CK Command*3
READ
NOP
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
tCCD
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3
RL = 5
VIH or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
READ (BL8) to READ (BC4) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
105
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ
NOP
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
tCCD
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tRPRE
tRPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout n n+1 n+2 n+3
Dout Dout Dout Dout Dout Dout Dout Dout b b+1 b+2 b+3 b+4 b+5 b+6 b+7
RL = 5
Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T4.
VIH or VIL
READ (BC4) to READ (BL8) OTF
T0 CK /CK Command*3
READ
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14 T15
WRIT
NOP
tWR
READ to WRIT command delay = RL + tCCD/2 + 2tCK − WL
tBL = 4 clocks
tWTR
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout n n+1 n+2 n+3
Din b
Din b+1
Din b+2
Din b+3
Din b+4
Din b+5
Din b+6
Din b+7
WL = 5
VIH or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n , Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4.
READ (BC4) to WRITE (BL8) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
106
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14 T15
WRIT
NOP
tBL = 4 clocks tWR tWTR
READ to WRIT command delay = RL + tCCD + 2tCK − WL
Address*4
Bank Col n
Bank Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, /DQS
DQ*2
RL = 5
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Din b
Din b+1
Din b+2
Din b+3
WL = 5
VIH or VIL
Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, n Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T6.
READ (BL8) to WRITE (BC4) OTF
T0 CK /CK Command*3
READ
NOP
tRTP = 4 nCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
PRE
NOP
tRP
Address*4
Bank Col n
tRPRE
tRPST
DQS, /DQS
DQ*2
CL = 5
RL = AL + CL
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
VIH or VIL
Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Burst Read Precharge Operation, RL = 5
Preliminary Data Sheet E1494E50 (Ver. 5.0)
107
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
READ
NOP
tRTP = 4 nCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
PRE
tRP
NOP
Address*4
Bank Col n
tRPRE
tRPST
DQS, /DQS*2
DQ
AL = 4
RL = AL + CL
CL = 5
Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Internal Read command starls here
VIH or VIL
Notes: 1. BL8, RL = 9, AL = (CL - 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0.
Burst Read Precharge Operation, RL = 9
Preliminary Data Sheet E1494E50 (Ver. 5.0)
108
EDJ1104BDSE, EDJ1108BDSE
Write Timing Definition
/CK*1 CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command*3
WRIT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = AL + CWL
Address*4
Bank, Col n
tDQSS tDSH tWPRE (min)
tDSH
tDSH
tDQSS(min)
DQS, /DQS
tDQSL
tDQSH (min)
tDSH tWPST (min)
tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL
tDQSL (min)
tDSS
DQ*2
Din n Din n+1
tDSS
Din n+2 Din n+3
tDSS
Din n+4 Din n+5
tDSS
Din n+6 Din n+7
tDSS
tWPRE (min)
DQS, /DQS
tDSH
tDSH
tDSH
tDSH
tWPST (min)
tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL tDQSL (min) tDQSL
tDQSH (min)
tDSS
DQ*2
Din n
tDSS
Din n+1 Din n+2
tDSS
Din n+3 Din n+4
tDSS
Din n+5 Din n+6
tDSS
Din n+7
tDQSS
tDSH
tDSH
tDSH
tDSH
tWPST (min)
tDQSS(max)
DQS, /DQS
tWPRE (min)
tDQSHtDQSLtDQSHtDQSLtDQSH tDQSLtDQSHtDQSL
tDQSH (min)
tDQSL (min)
tDSS
DQ*2
Din n
tDSS
Din n+1 Din n+2
tDSS
Din n+3 Din n+4
tDSS
Din n+5 Din n+6
tDSS
Din n+7
Notes: 1. 2. 3. 4. 5.
BL8, WL = 5 (AL = 0, CWL = 5) VIH or VIL Din n = data-in from column n. NOP commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. tDQSS must be met at each rising clock edge.
Write Timing Definition
Preliminary Data Sheet E1494E50 (Ver. 5.0)
109
EDJ1104BDSE, EDJ1108BDSE
Write Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). • A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) • A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is equal to (AL + CWL). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR).
T0 CK /CK Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NOP
WL = AL + CWL
Address*4
Bank Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
Din n
Din n+1
Din n+2
Din n+3
Din n+4
Din n+5
Din n+6
Din n+7
VIH or VIL
Notes: 1. BL8, WL = 5 (AL = 0, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0.
Burst Write Operation, WL = 5
Preliminary Data Sheet E1494E50 (Ver. 5.0)
110
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NOP
Address*4
Bank Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
AL = 4
WL = AL + CWL
CWL = 5
Din n
Din n+1
Din n+2
Din n+3
Din n+4
Din n+5
Din n+6
Din n+7
VIH or VIL
Notes: 1. BL8, WL = 9 (AL = (CL − 1), CL = 5, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRITcommand at T0.
Burst Write Operation, WL = 9
T0 CK /CK Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn
Tn+1
Tn+2
NOP
tWTR*5
READ
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
RL = 5
Notes:
1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0 and READ command at Tn. 5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7.
VIH or VIL
Write (BC4) to Read (BC4) Operation
Preliminary Data Sheet E1494E50 (Ver. 5.0)
111
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn
Tn+1
Tn+2
NOP
tWR*5
PRE
Address*4
Bank Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
Notes:
VIH or VIL 1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0. 5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
Write (BC4) to Precharge Operation
T0 CK /CK Command*3
WRIT
NOP
tCCD
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
WRIT
NOP
tBL = 4 clocks tWR tWTR
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
Din n
Din n+1
Din n+2
Din n+3
Din n+4
Din n+5
Din n+6
Din n+7
Din b
Din b+1
Din b+2
Din b+3
Din b+4
Din b+5
Din b+6
Din b+7
WL = 5
WL = 5
Notes: 1. BL8, WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0 and T4.
WRITE (BL8) to WRITE (BL8) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
112
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NOP
tCCD
WRIT
NOP
tBL = 4 clocks tWR tWTR
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
Din b
Din b+1
Din b+2
Din b+3
WL = 5
Notes: 1. BC4, WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by either MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0 and T4.
VIH or VIL
WRITE (BC4) to WRITE (BC4) OTF
T0 CK /CK
Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
tWTR
READ
NOP
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
Din n+4
Din n+5
Din n+6
Din n+7
RL = 5
Notes:
1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n = data-in from column n; DOUT b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13.
WRITE (BL8) to READ (BC4/BL8) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
113
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK
Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
tBL = 4 clocks
tWTR
READ
NOP
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
RL = 5
Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13.
VIH or VIL
WRITE (BC4) to READ (BC4/BL8) OTF
T0 CK /CK
Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
tCCD
WRIT
NOP
tBL = 4 clocks tWR tWTR
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
Din n+4
Din n+5
Din n+6
Din n+7
Din b
Din b+1
Din b+2
Din b+3
WL = 5
Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T4.
VIH or VIL
WRITE (BL8) to WRITE (BC4) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
114
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK
Command*3
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
tCCD
WRIT
NOP
tBL = 4 clocks tWR tWTR
Address*4
Bank Col n
Bank Col b
tWPRE
tWPST
tWPRE
tWPST
DQS, /DQS
DQ*2
WL = 5
Din n
Din n+1
Din n+2
Din n+3
Din b
Din b+1
Din b+2
Din b+3
Din b+4
Din b+5
Din b+6
Din b+7
WL = 5
Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4.
VIH or VIL
WRITE (BC4) to WRITE (BL8) OTF
Preliminary Data Sheet E1494E50 (Ver. 5.0)
115
EDJ1104BDSE, EDJ1108BDSE
Write Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However it is desirable for certain minor violations, that the DRAM is guaranteed not to "hang up" and error to be limited to that particular operation. For the following it will be assumed that there are no timing violations w.r.t to the write command itself (including ODT etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with this write command. In the example (Figure Write Timing Parameters) the relevant strobe edges for write burst A are associated with the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH tDQSS) be violated for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. In the example (Figure Write Timing Parameters) the relevant strobe edges for write burst A are associated with the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements starting and ending on one of these strobe edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges are associated with both bursts.
T0 CK /CK Command*3
WRIT NOP WRIT
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
NOP
Address*4
A
B
/CS
ODTL WL tDQSS tDSS tDQSL tWPRE tDSH tDQSH tWPST BL/2 + 2 + ODTL
DQS, /DQS
tDH tDS
DQ*2
VIH or VIL
Write Timing Parameters
Preliminary Data Sheet E1494E50 (Ver. 5.0)
116
EDJ1104BDSE, EDJ1108BDSE
Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. DM is not used during read cycles.
T1 DQS /DQS DQ
T2
T3
T4
T5
T6
in
in
in
in
in
in
in
in
DM Write mask latency = 0
Data Mask Timing
/CK CK [tDQSS(min.)] Command
WRIT
WL
tWR
NOP
tDQSS
DQS, /DQS DQ DM
WL
in0
in2 in3
[tDQSS(max.)]
tDQSS
DQS, /DQS DQ DM
in0
in2 in3
Data Mask Function, WL = 5, AL = 0 shown
Preliminary Data Sheet E1494E50 (Ver. 5.0)
117
EDJ1104BDSE, EDJ1108BDSE
Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10, BA0, BA1 and BA2 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits]
A 10 L L L L L L L L H BA0 L H L H L H L H × BA1 L L H H L L H H × BA2 L L L L H H H H × Precharged Bank(s) Bank 0 only B ank 1 only B ank 2 only B ank 3 only B ank 4 only B ank 5 only B ank 6 only B ank 7 only A ll banks 0 to 7
Remark: H: VIH, L: VIL, ×: VIH or VIL
Preliminary Data Sheet E1494E50 (Ver. 5.0)
118
EDJ1104BDSE, EDJ1108BDSE
Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto precharge function is engaged. During auto precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Burst Read with Auto Precharge If A10 is high when a Read Command is issued, the Read with Auto precharge function is engaged. The DDR3 SDRAM starts an auto precharge operation on the rising edge which is (AL + tRTP) cycles later from the read with AP command when tRAS (min.) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point of auto precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst Write with Auto precharge If A10 is high when a write command is issued, the Write with auto precharge function is engaged. The DDR3 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time (tWR). The bank-undergoing auto precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
119
EDJ1104BDSE, EDJ1108BDSE
Auto-Refresh The refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires refresh cycles at an average periodic interval of tREFI. When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters a refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the refresh command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during a refresh command. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the refresh command and the next valid command, except NOP or DESL, must be greater than or equal to the minimum refresh cycle time tRFC(min) as shown in the following figure. Note that the tRFC timing parameter depends on memory density. In general, a refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 refresh commands can be postponed during operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. In case that 8 refresh commands are postponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 × tREFI. A maximum of 8 additional refresh commands can be issued in advance (“pulled in”), with each one reducing the number of regular refresh commands required later by one. Note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 × tREFI. At any given time, a maximum of 16 REF commands can be issued within tREFI. Before entering self-refresh mode, all postponed refresh commands must be executed.
T0 /CK CK
VIH
T1
T2
T3
CKE
≥ tRP
≥ tRFC
≥ tRFC
Command
PRE
NOP
REF
REF
NOP
Any Command
Refresh Command Timing
tREFI
9 × tRER t
tRFC
8 × REF-Commands postponed
Postponing Refresh Command
tREFI
9 × tRER t
tRFC
8 × REF-Commands postponed
Pulling-in Refresh Command
Preliminary Data Sheet E1494E50 (Ver. 5.0)
120
EDJ1104BDSE, EDJ1108BDSE
Self-Refresh The self-refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a built-in timer to accommodate self-refresh operation. The Self-Refresh Entry (SELF) command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Before issuing the self-refresh entry command, the DDR3 SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self-refresh entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior to the self-refresh entry command or using MRS to MR1 command. Once the self-refresh entry command is registered, CKE must be held low to keep the device in self-refresh mode. The DLL is automatically disabled upon entering Self-refresh and is automatically enabled (including a DLL-Reset) upon exiting self-refresh. When the DDR3 SDRAM has entered self-refresh mode all of the external control signals, except CKE and /RESET, are “don’t care”. For proper self-refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VREFCA and VREFDQ) must be at valid levels. The DRAM initiates a minimum of one refresh command internally within tCKESR period once it enters self-refresh mode. The clock is internally disabled during self-refresh operation to save power. The minimum time that the DDR3 SDRAM must remain in self-refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock tCKSRE clock cycles after self-refresh entry is registered, however, the clock must be restarted and stable tCKSRX clock cycles before the device can exit self-refresh operation. To protect DRAM internal delay on CKE line to block the input signals, one NOP (or DESL) command is needed after self-refresh entry. The procedure for exiting self-refresh requires a sequence of events. First, the clock must be stable tCKSRX prior to CKE going back high. Once a Self-Refresh Exit command (SREX, combination of CKE going high and either NOP or DESL on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements (TBD) must be satisfied. CKE must remain high for the entire self-refresh exit period tXSDLL for proper operation except for self-refresh reentry. Upon exit from self-refresh, the DDR3 SDRAM can be put back into Self-refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or DESL commands must be registered on each positive clock edge during the self-refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self-refresh mode. Upon exit from self-refresh, the DDR3 SDRAM requires a minimum of one extra refresh command before it is put back into self-refresh mode.
Ta Tb Tc Tc+1Tc+2 Td Te Tf Tf+1 Tf+2 Tg Tg+1 Th Th+1
CK, /CK tRP
tCKSRE
tCKSRX
tXSDLL
*4
Command
PALL
tXS
SREX
SELF NOP
*1
*2
*2
*3 *3
Valid Valid
Valid Valid
tCKESR
CKE
ODTLoff + 0.5 x tCK
ODT Notes: 1. 2. 3. 4. Only NOP or DESL commands. Valid commands not requiring a locked DLL. Valid commands requiring a locked DLL. One NOP or DESL commands.
Self-Refresh Entry and Exit Timing
Preliminary Data Sheet E1494E50 (Ver. 5.0)
121
EDJ1104BDSE, EDJ1108BDSE
Power-Down Mode Power-down is synchronously entered when CKE is registered low (along with NOP or DESL command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in active power-down mode. Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT, CKE and /RESET. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or DESL commands are needed during the CKE switch off and cycle(s) after this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. [Power-Down Entry Definitions]
S tatus of DRAM MR0 bit A12 DLL On PD Exit Fast Relevant Parameters tXP to any valid command tXP to any valid command. Since it is in precharge state, commands here will be ACT, AR, MRS, PRE or PALL . tXPDLL to commands who need DLL to operate, such as READ, READA or ODT control line. tXP to any valid command Active Don’t Care (A bank or more Open)
P recharged 0 (All banks Precharged)
Off
Slow
P recharged (All Banks Precharged)
1
On
Fast
Also the DLL is disabled upon entering precharge power-down for slow exit mode, but the DLL is kept enabled during precharge power-down for fast exit mode or active power-down. In power-down mode, CKE low, RESET high and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care” (If RESET goes low during power-down, the DRAM will be out of PD mode and into reset state). CKE low must be maintained until tPD has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or DESL command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC Characteristics table of this data sheet.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
122
EDJ1104BDSE, EDJ1108BDSE
Timing Diagrams for Proposed CKE with Power-Down Entry, Power-Down Exit
/CK CK Command
BA
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
Tx
Tx+1
READ
Valid
NOP
NOP
tRDPDEN
tCPDED tIS
CKE
VIH
RL = CL + AL = 5 (AL = 0)
tPD
out 2 out out 3 4
out 3 out out 5 6 out 7
DQ(BL8)
DQ(BC4)
out 0
out 0
out 1
out out 1 2
Power-Down Entry after Read and Read with Auto Precharge
T0 CK /CK Command BA
WRITA
Valid
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T14
T15
T16
T17
T18
Tn
NOP
NOP
NOP
tCPDED tIS
CKE
tWRAPDEN
WL=5
DQ(BL8) DQ(BC4)
in 0 in 1 in 2 in 3
in 4 in 5 in 6 in 7
tWR*
tPD
in 0
in 1
in 2
in 3
Note: tWR is programmed through MRS.
Start Internal Precharge
Power-Down Entry After Write with Auto Precharge
Preliminary Data Sheet E1494E50 (Ver. 5.0)
123
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command BA
WRITE
Valid
NOP
NOP
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tx
Tx+1 Tx+2 Tx+3
tCPDED
tIS
CKE
tWRPDEN
WL=5
tWR
tPD
DQ(BL8) DQ(BC4)
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
Power-Down Entry after Write
T0
CK /CK
T1
Tn Tn+1
Tx
Ty
tIH
tPD
tIH
CKE
tIS
tIS
tCPDED
Command
Valid NOP NOP
tCKE (min.)
NOP NOP NOP NOP NOP Valid NOP NOP NOP NOP N
tXP
Enter power-down mode Exit power-down
Note: Valid command at T0 is ACT, NOP, DESL or precharge with still one bank remaining open after completion of precharge command.
Active Power-Down Entry and Exit Timing Diagram
T0
CK /CK
tIH
T1
Tn
Tn+1
Tx
Ty
tPD
tIH
CKE
tIS
tIS
tCPDED
Command
NOP NOP
tCKE (min.)
NOP NOP NOP NOP NOP Valid NOP NOP NOP1 NOP N
Enter power-down mode
tXP Exit power-down
Precharge Power-Down (Fast Exit Mode) Entry and Exit
Preliminary Data Sheet E1494E50 (Ver. 5.0)
124
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK
tIH
tIH
T1
Tn
Tn+1
Tx
Ty
CKE
tIS
tIS
tPD
tCPDED
tCKE (min.)
NOP
NOP
NOP NOP
NOP NOP
Valid NOP Valid
NOP NO
Command
NOP NOP
NOP
tXP
tXPDLL
Enter power-down mode
Exit power-down
Precharge Power-Down (Slow Exit Mode) Entry and Exit
T0 CK /CK Command
REF
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
tCPDED
tREFPDEN
tIS
CKE
Refresh Command to Power-Down Entry
T0 CK /CK Command
ACT
T1
T2
T3
T4
Tn
Tn+1
Tn+2
End
NOP
NOP
tCPDED
tPD
tACTPDEN
tIS
CKE
Active Command to Power-Down Entry
Preliminary Data Sheet E1494E50 (Ver. 5.0)
125
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command
PRE/ PALL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
End
NOP
NOP
tCPDED
tPREPDEN
tIS
CKE
Precharge/Precharge All Command to Power-Down Entry
T0
CK /CK Command
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tn+7
MRS
NOP
NOP
NOP
NOP
NOP
tCPDED
tMRSPDEN
tIS
CKE
MRS Command to Power-Down Entry
Preliminary Data Sheet E1494E50 (Ver. 5.0)
126
EDJ1104BDSE, EDJ1108BDSE
Timing Values tXXXPDEN Parameters
S tatus of DRAM Idle or Active I dle or Active A ctive A ctive A ctive A ctive A ctive I dle I dle Last Command before CKE_low Activate Precharge READ/READA WRIT for BL8MRS, BL8OTF, BC4OTF WRIT for BC4MRS Parameter tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN Parameter Value 1 1 RL + 4 + 1 Unit nCK nCK nCK
WL + 4 + (tWR/tCK (avg)) n CK 1 * WL + 2 + (tWR/tCK n CK 1 (avg))* WL + 4 + WR* + 1 WL + 2 + WR* + 1 1 tMOD
2 2
WRITA for BL8MRS, BL8OTF, BC4OTF tWRAPDEN WRITA for BC4MRS Refresh Mode Register Set tWRAPDEN tREFPDEN tMRSPDEN
n CK n CK nCK
Notes: 1. tWR is defined in ns, for calculation of tWRPDEN, it is necessary to round up tWR / tCK to next integer. 2. WR in clock cycles as programmed in mode register. Power-Down Entry and Exit Clarification Case 1: When CKE registered low for power-down entry, tPD must be satisfied before CKE can be registered high for powerdown exit. Case 1a: After power-down exit, tCKE must be satisfied before CKE can be registered low again.
T0
CK /CK
tIH
tIH
T1
Tn
Tn+1
Tx
Ty
CKE
tIS
tIS
tPD
tCKE
tCPDED
Command
NOP NOP NOP
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP N
Enter power-down
Exit power-down
Power-Down Entry/Exit Clarifications (1)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
127
EDJ1104BDSE, EDJ1108BDSE
Case 2: For certain CKE intensive operations, for example, repeated "PD Exit - Refresh - PD Entry" sequence, the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated. Therefore the following conditions must be met in addition to tPD in order to maintain proper DRAM operation when Refresh commands is issued in between PD Exit and PD Entry. Power-down mode can be used in conjunction with Refresh command if the following conditions are met: 1. tXP must be satisfied before issuing the command 2. tXPDLL must be satisfied (referenced to registration of PD exit) before next power-down can be entered.
T0 T1 Tn Tn+1 Tx Ty
CK /CK
tIH
tIH
CKE
tIS
tIS
tCPDED
tXPDLL (min.)
tCKE (min.)
tPD Command
NOP NOP NOP
NOP
NOP
REF NOP NOP NOP NOP NOP NOP NOP
tXP
Enter power-down
Exit power-down
Power-Down Entry/Exit Clarifications (2) Case 3: If an early PD Entry is issued after Refresh command, once PD Exit is issued, NOP or DESL with CKE high must be issued until tRFC from the refresh command is satisfied. This means CKE cannot be de-asserted twice within tRFC window.
T0 CK /CK tIH CKE tIS tPD tCPDED Command
REF NOP NOP
T1
Tn
Tn+1
Tx
Ty
tIH
tIS tXPDLL tCKE (min.)
NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid N
tRFC (min.) Enter power-down Exit power-down
Note: * Synchronous ODT Timing starts at the end of tXPDLL (min.)
Power-Down Entry/Exit Clarifications (3)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
128
EDJ1104BDSE, EDJ1108BDSE
Input Clock Frequency Change during Precharge Power-Down Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (Spread Spectrum Clocking) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to SelfRefresh mode and tCKSRE has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the self-refresh entry and exit specifications must still be met as outlined in Self-Refresh section. The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit mode.) ODT must be at a logic low ensuring RTT is in an off state prior to entering Precharge Power-down mode and CKE must be at a logic low. A minimum of tCKSRE must occur after CKE goes low before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable low levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL relock period, ODT must remain low. After the DLL lock time, the DRAM is ready to operate with new clock frequency. This process is depicted in the figure Clock Frequency Change in Precharge Power-Down Mode.
Previous clock frequency T0 /CK CK tIH CKE tCPDED Command
NOP NOP NOP NOP NOP MRS NOP Valid
New clock frequency Tb Tc Tc+1 Td Td+1 Te Te+1
T1
T2
Ta
tIS tCKSRE tCKSRX
Address tAOFPD/tAOF ODT DQS, /DQS DQ High-Z High-Z tXP
DLL RESET
Valid
tDLLK
DM
Enter precharge power-down mode
Frequency change
Exit precharge power-down mode
Notes: 1. Applicable for both slow exit and fast exit precharge power-down. 2. tCKSRE and tCKSRX are self-refresh mode specifications but the values they represent are applicable here. 3. tAOFPD and tAOF must be satisfied and outputs high-z prior to T1; refer to ODT timing for exact requirements.
Clock Frequency Change in Precharge Power-Down Mode
Preliminary Data Sheet E1494E50 (Ver. 5.0)
129
EDJ1104BDSE, EDJ1108BDSE
On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, /DQS and DM for ×4 and ×8 configuration (and TDQS, /TDQS for ×8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown in figure Functional Representation of ODT.
ODT To other circuitry like RCV, ... VDDQ/2 RTT Switch DQ, DQS, DM, TDQS
Functional Representation of ODT The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information, see below. The value of RTT is determined by the settings of mode register bits (see MR1 programming figure in the section Programming the Mode Register). The ODT pin will be ignored if the Mode Register MR1 is programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table The ODT Mode is enabled if either of MR1 bits A2 or A6 or A9 are non-zero. In this case the value of RTT is determined by the settings of those bits. Application: Controller sends WRIT command together with ODT asserted. • One possible application: The rank that is being written to provide termination. • DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) • DRAM does not use any write or read command decode information • The Termination Truth Table is shown in the Termination Truth Table [Termination Truth Table]
O DT pin 0 1 DRAM Termination State OFF O N, (OFF, if disabled by MR1 bits A2, A6 and A9 in general)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
130
EDJ1104BDSE, EDJ1108BDSE
Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are: • Active mode • Idle mode with CKE high • Active power-down mode (regardless of MR0 bit A12) • Precharge power-down mode if DLL is enabled during precharge power-down by MR0 bit A12. In synchronous ODT mode, RTT will be turned on or off ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL – 2; ODTLoff = WL – 2. ODT Latency and Posted ODT In Synchronous ODT mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL − 2; ODTLoff = CWL + AL − 2. For details, refer to DDR3 SDRAM latency definitions. [ODT Latency Table]
P arameter ODT turn-on Latency O DT turn-off Latency Symbol ODTLon ODTLoff Value WL – 2 = CWL + AL – 2 WL – 2 = CWL + AL – 2 Unit nCK nCK
Synchronous ODT Timing Parameters In synchronous ODT mode, the following timing parameters apply (see Synchronous ODT Timing Examples (1)): ODTLLow, ODTLLoff, tAON,(min.), (max.), tAOF,(min.),(max.) Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min ) is the point in time when the device starts to turn-off the ODT resistance. Maximum RTT turn-off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL4) or ODTH8 (BL8) after the Write command (see figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a Write command until ODT is registered low.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
131
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK CKE
ODTH4 (min.)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15
END
ODT
AL = 3
AL = 3
IntODT
ODTLon = CWL + AL – 2
ODTLoff = CWL + AL – 2
CWL – 2
tAON (max.) tAON (min.)
tAOF (max.) tAOF (min.)
RTT
RTT
Synchronous ODT Timing Examples (1): AL=3, CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6
T0 CK /CK CKE Command
WRS4
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18
ODTH4
ODTH4
ODTH4
ODT
ODTLoff = WL – 2
ODTLoff = WL – 2
ODTLon = WL – 2
ODTLon = WL – 2
tAON (max.) tAON (min.)
tAOF (max.) tAOF (min.)
RTT
tAOF (max.) tAOF (min.)
DRAM_RTT
RTT
tAON (max.) tAON (min.)
Synchronous ODT Timing Examples (2)*: BC4, WL = 7
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BC4) or ODTH8 (BL8) after write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered high at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the write command at T7.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
132
EDJ1104BDSE, EDJ1108BDSE
ODT during Reads As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may nominally not be enabled until one clock cycle after the end of the post-amble as shown in the example in the figure below. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example in the figure below. ODT must be disabled externally during Reads by driving ODT low. (example: CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL -2 = 8; ODTLoff = CWL + AL - 2 = 8)
T0 CK /CK Command Address
READ
A
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T13 T14 T15 T16 End
RL = AL + CL
ODT
ODTLoff = WL – 2 = CWL + AL – 2
ODTLon = WL – 2 = CWL + AL – 2
tAOF (max.) tAOF (min.) tAON (min.) tAON (max.)
RTT
DRAM_RTT
DQS, /DQS DQ
RTT
out out out out out out out out 01234567
Example of ODT during Reads
Preliminary Data Sheet E1494E50 (Ver. 5.0)
133
EDJ1104BDSE, EDJ1108BDSE
Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the “Dynamic ODT” feature as described as follows: Functional Description: The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to ’1’. The function and is described as follows: • Two RTT values are available: RTT_Nom and RTT_WR. The value for RTT_Nom is pre-selected via bits A[9,6,2] in MR1 The value for RTT_WR is pre-selected via bits A[10,9] in MR2 • During operation without write commands, the termination is controlled as follows: Nominal termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. • When a write command (WRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows: A latency ODTLcnw after the write command, termination strength RTT_WR is selected. A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. Table Latencies and Timing Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which are relevant for the on-die termination control in Dynamic ODT mode: When ODT is asserted, it must remain high until ODTH4 is satisfied. If a write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BC4) or ODTH8 (BL8) after the write command (see the figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. [Latencies and Timing Parameters Relevant for Dynamic ODT]
P arameters ODT turn-on Latency Symbols ODTLon Defined from Registering external ODT signal high Registering external ODT signal low Registering external write command Registering external write command Registering external write command registering ODT high registering Write with ODT high registering Write with ODT high ODTLcnw ODTLcwn Defined to Turning termination on Definition for all DDR3 speed bins ODTLon = WL – 2.0 Unit nCK
O DT turn-off Latency
ODTLoff
Turning termination off Change RTT strength from RTT_Nom to RTT_WR Change RTT strength from RTT_WR to RTT_Nom Change RTT strength from RTT_WR to RTT_Nom ODT registered low ODT registered low ODT registered low RTT valid
ODTLoff = WL – 2.0
nCK
O DT latency for changing ODTLcnw from RTT_Nom to RTT_WR O DT latency for change from RTT_WR to RTT_Nom (BC4) O DT latency for change from RTT_WR to RTT_Nom (BL8) M inimum ODT high time after ODT assertion M inimum ODT high time after Write (BC4) M inimum ODT high time after Write (BL8) R TT change skew ODTLcwn4
ODTLcnw = WL – 2.0 nCK ODTLcwn4 = 4 + ODTLoff ODTLcwn8 = 6 + ODTLoff ODTH4 (min.) = 4 ODTH4 (min.) = 4 ODTH8 (min.) = 6 0.3ns to 0.7ns
nCK
ODTLcwn8 ODTH4 ODTH4 ODTH8 tADC
nCK nCK nCK nCK tCK (avg)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
134
EDJ1104BDSE, EDJ1108BDSE
Mode Register Settings for Dynamic ODT Mode: The table Mode Register for RTT Selection shows the mode register bits to select RTT_Nom and RTT_WR values. [Mode Register for RTT Selection]
M R1 A9 0 0 0 0 1 1 1 1 A6 0 0 1 1 0 0 1 1 A2 0 1 0 1 0 1 0 1 RTT_Nom (RZQ) o ff R ZQ/4 R ZQ/2 R ZQ/6 R ZQ/12* R ZQ/8*
2 2
MR2 RTT_Nom (Ω) off 60 120 40 20 30 Reserved Reserved A10 0 0 1 1 A9 0 1 0 1 RTT_WR (RZQ) RTT_WR* (Ω)
1
Dynamic ODT OFF: Write does not affect RTT value RZQ/4 RZQ/2 Reserved 60 120 Reserved
R eserved R eserved
Notes: 1. RZQ = 240Ω. 2. If RTT_Nom is used during WRITEs, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
ODT Timing Diagrams
T0 CK /CK
ODTLcnw
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
Command
WRS4
ODTH4
ODTH4
ODT
ODTLon
tAON (min.)
tADC (min.)
RTT_WR
ODTLoff
tADC (min.)
RTT_Nom
tAOF (min.)
RTT
RTT_Nom
tAON (max.)
tADC (max.)
tADC (max.)
tAOF (max.)
ODTLcwn4
DQS, /DQS DQ
WL
in in in in 0123
Dynamic ODT: Behavior with ODT Being Asserted Before and after the Write* Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the write command. In this example ODTH4 would be satisfied if ODT is low at T8 (4 clocks after the write command).
Preliminary Data Sheet E1494E50 (Ver. 5.0)
135
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK Command
ODTH4
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ODT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
RTT_Nom
RTT
tAON (max.)
tAOF (max.)
DQS, /DQS DQ
Dynamic ODT*: Behavior without Write Command; AL = 0, CWL = 5 Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal.
T0 CK /CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ODTLcnw
Command
WRS8
ODTH8
ODT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
RTT
tADC (max.)
ODTLcwn8
RTT_WR
tAOF (max.)
DQS, /DQS DQ
WL
in 0
in 1 in 2 in 3 in 4 in 5 in 6 in 7
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 6 Clock Cycles Note: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH8 = 6 is exactly satisfied.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
136
EDJ1104BDSE, EDJ1108BDSE
T0 CK /CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
ODTLcnw
Command
WRS4
ODTH4
ODT
ODTLon
ODTLoff
tAON (min.)
tADC (min.)
tAOF (min.)
RTT_WR
RTT_Nom
RTT
tADC (max.)
ODTLcwn4
tADC (max.)
tAOF (max.)
DQS, /DQS DQ
WL
in 0
in 1 in 2 in 3
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for a Duration of 6 Clock Cycles, Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal.
T0 CK /CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
ODTLcnw
Command
WRS4
ODTH4
ODT
ODTLon
tAON (min.)
tAOF (min.)
ODTLoff
RTT
tADC (max.)
RTT_WR
tAOF (max.)
ODTLcwn4
DQS, /DQS DQ
WL
in 0
in 1 in 2 in 3
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 4 Clock Cycles Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
137
EDJ1104BDSE, EDJ1108BDSE
Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLL-on mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Precharge power-down mode if DLL is disabled during precharge power-down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is not delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply (see figure Asynchronous ODT Timings): tAONPD (min.), (max.), tAOFPD (min.),(max.) Minimum RTT turn-on time (tAONPD (min.)) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn-on time (tAONPD (max.)) is the point in time when the ODT resistance is fully on. tAONPD (min.) and tAONPD (max.) are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPD (min.)) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn-off time (tAOFPD (max.)) is the point in time when the on-die termination has reached high impedance. tAOFPD (min.) and tAOFPD (max.) are measured from ODT being sampled low.
CK /CK CKE
tIH
tIS
tIH
tIS
ODT
tAONPD (max.)
tAOFPD (min.)
DRAM_RTT
tAONPD (min.)
RTT
tAOFPD (max.)
Asynchronous ODT Timings on DDR3 SDRAM with Fast ODT Transition: AL is Ignored In precharge power-down, ODT receiver remains active, however no read or write command can be issued, as the respective address/command receivers may be disabled. [Asynchronous ODT Timing Parameters for All Speed Bins]
S ymbol tAONPD t AOFPD Parameters min. max. 8.5 8.5 Unit ns ns Asynchronous RTT turn-on delay (power-down with DLL frozen) 2 Asynchronous RTT turn-off delay (power-down with DLL frozen) 2
[ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period]
D escription ODT to RTT turn-on delay min. min {ODTLon × t CK + tAON(min.); tAONPD(min.) } m in { (WL − 2 .0) × t CK + tAON(min.); tAONPD(min.) } min { ODTLoff × t CK +tAOF(min.); tAOFPD(min.) } m in { (WL − 2 .0) × t CK +tAOF(min.); tAOFPD(min.) } WL − 1 .0 max. max {ODTLon × t CK + tAON(max.); tAONPD(max.) } max {(WL − 2 .0) × t CK + tAON(max.); tAONPD(max.) } max { ODTLoff × t CK + tAOF(max.); tAOFPD(max.) } max {(WL − 2 .0) × t CK + tAOF(max.); tAOFPD(max.) }
O DT to RTT turn-off delay
t ANPD
Preliminary Data Sheet E1494E50 (Ver. 5.0)
138
EDJ1104BDSE, EDJ1108BDSE
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0 there is a transition period around power-down entry, where the DDR3 SDRAM may show either synchronous or asynchronous ODT behavior. This transition period ends when CKE is first registered low and starts tANPD before that. If there is a Refresh command in progress while CKE goes low, then the transition period ends tRFC after the refresh command. tANPD is equal to (WL − 1.0) and is counted (backwards) from the clock cycle where CKE is first registered low. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period.
CK /CK Command CKE
PD entry transition period
tANPD
REF
NOP NOP
ODT ODT_A_sync
ODTLoff
tRFC
tAOF (max.)
tAOF (min.)
DRAM_RTT_A_sync ODT_B_tran
RTT
ODTLoff + tAOFPD (max.) tAOFPD (max.)
ODTLoff + tAOFPD (min.)
tAOFPD (min.)
DRAM_RTT_B_tran ODT_C_async
tAOFPD (max.) tAOFPD (min.)
DRAM_RTT_C_async
RTT
Synchronous to Asynchronous Transition During Precharge Power-Down (with DLL Frozen) Entry (AL = 0; CWL = 5; tANPD = WL − 1 = 4)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
139
EDJ1104BDSE, EDJ1108BDSE
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0, there is also a transition period around power-down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL − 1.0) and is counted backward from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)). See ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period table. Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response.
T1 CK /CK Command CKE PD exit transition period ODT_C_async tANPD tAOFPD (max.) tAOFPD (min.) DRAM_RTT_C_async ODT_B_tran tAOFPD (min.) ODTLoff + tAOF (min.) ODTLoff + tAOF (max.) tAOFPD (max.) DRAM_RTT_B_tran ODT_A_sync ODTLoff tAOF (max.) tAOF (min.) DRAM_RTT_A_sync
RTT RTT
T3
T5
T7
T9
T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 T33 T35
NOP NOP
tXPDLL
Asynchronous to Synchronous Transition during Precharge Power-Down (with DLL Frozen) Exit (CL = 6; AL = CL - 1; CWL = 5; tANPD= WL − 1 = 9)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
140
EDJ1104BDSE, EDJ1108BDSE
Asynchronous to Synchronous ODT Mode during Short CKE high and Short CKE Low Periods If the total time in precharge power-down state or idle state is very short, the transition periods for power-down entry and power-down exit may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period). If the total time in idle state is very short, the transition periods for power-down exit and power-down entry may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down exit transition period to the end of the power-down entry transition period. Note that in the bottom part of figure below it is assumed that there was no refresh command in progress when idle state was entered.
CK /CK Command CKE
REF
NOP
NOP
NOP NOP
tANPD
tRFC PD entry transition period
PD exit transition period
tANPD
tXPDLL
short CKE low transition period
CKE
tANPD
tANPD
tXPDLL
tXPDLL short CKE high transition period
Transition Period for Short CKE Cycles with Entry and Exit Period Overlapping (AL = 0, WL = 5, tANPD = WL − 1 = 4)
Preliminary Data Sheet E1494E50 (Ver. 5.0)
141
EDJ1104BDSE, EDJ1108BDSE
ZQ Calibration ZQ calibration command is used to calibrate DRAM RON and ODT values. DDR3 SDRAM needs longer time to calibrate RON and ODT at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM I/O which gets reflected as updated RON and ODT values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection (Tsens × Tdriftrate) + (Vsens × Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/°C, VSens = 0.15%/mV, Tdriftrate = 1°C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as:
0.5 = 0.133 = 128ms (1.5 × 1) + (0.15 × 15)
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper or tZQCS. The quiet time on the DRAM channel allows in accurate calibration of RON and ODT. Once DRAM calibration is achieved the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh. Upon selfrefresh exit, DDR3 SDRAM will not perform an I/O calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self-refresh exit is tXS. In dual rank systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper or tZQinit or tZQCS between ranks.
CK Command A10 Address
ZQCL
A10 = H
X
NOP/DESL
Valid
ZQCS
A10 = L
X
NOP/DESL
Valid
CKE
tZQinit or tZQ oper
tZQCS
DQ Bus*2
Hi-Z
Activities
Hi-Z
Activities
Notes: 1. ODT must be disabled via ODT signal or MRS during calibration procedure. 2. All device connected to DQ bus should be High impedance during calibration.
ZQ Calibration
Preliminary Data Sheet E1494E50 (Ver. 5.0)
142
EDJ1104BDSE, EDJ1108BDSE
ZQ External Resistor Value and Tolerance DDR3 SDRAM has a 240Ω, ±1% tolerance external resistor connecting from the DDR3 SDRAM ZQ pin to ground. The resister can be used as single DRAM per resistor.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
143
EDJ1104BDSE, EDJ1108BDSE
Package Drawing
78-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
7.50 ± 0.10 INDEX MARK
0.20 S B
10.60 ± 0.10
0.20 S A
0.20 S 1.20 max. S 0.10 S 0.32 ± 0.05
B
78-φ0.45 ± 0.05
φ0.15 M S A B
INDEX MARK
1.6 6.4
0.8
9.6
A
0.8
ECA-TS2-0305-01
Preliminary Data Sheet E1494E50 (Ver. 5.0)
144
EDJ1104BDSE, EDJ1108BDSE
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDJ1104BDSE, EDJ1108BDSE. Type of Surface Mount Device EDJ1104BDSE, EDJ1108BDSE: 78-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E1494E50 (Ver. 5.0)
145
EDJ1104BDSE, EDJ1108BDSE
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E1494E50 (Ver. 5.0)
146
EDJ1104BDSE, EDJ1108BDSE
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1494E50 (Ver. 5.0)
147
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