DATA SHEET
256M bits SDRAM
EDS2732AABJ-6B (8M words × 32 bits)
Specifications
• Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V • Clock frequency: 166MHz (max.) • 1KB page size ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A7 • Four internal banks for concurrent operation • Interface: LVTTL • Burst lengths (BL): 1, 2, 4, 8, full page • Burst type (BT): ⎯ Sequential (1, 2, 4, 8, full page) ⎯ Interleave (1, 2, 4, 8) • /CAS Latency (CL): 2, 3 • Precharge: auto precharge operation for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/64ms ⎯ Average refresh period: 15.6μs • Operating ambient temperature range ⎯ TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS
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Features
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC A3 A6 A12 A9 NC VSS
F
VSS DQM3
G
A4 A5 A8 CKE NC
• ×32 organization • Single pulsed /RAS • Burst read/write operation and burst read/single write operation capability • Byte control by DQM
Document No. E0507E40 (Ver. 4.0) Date Published December 2005 (K) Japan Printed in Japan URL: http://www.elpida.com
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H
A7
J
CLK
K
DQM1 /WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
Pr
L M N P R
VDDQ DQ8
VSSQ DQ10 DQ9 VSSQ DQ12 DQ14 DQ11 VDDQ VSSQ DQ13 DQ15 VSS
VDDQ VSSQ DQ4 VDD DQ0 DQ2
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2004-2005
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A0 to A12 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC
(Top view) Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
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EDS2732AABJ-6B
Ordering Information
Part number EDS2732AABJ-6B-E EDS2732AABJ-6BL-E Supply voltage 3.3V Organization (words × bits) Internal Banks 8M × 32 4 Clock frequency MHz (max.) 166 166 /CAS latency 3 3 Package 90-ball FBGA
Part Number
E D S 27 32 A A BJ - 6B L - E
Elpida Memory Type Environment Code E: Lead Free Spec.Detail Blank: Normal L: Low Power Speed 6B: 166MHz/CL3
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D: Monolithic Device
Product Family S: SDRAM
Density / Bank 27: 256M/4-bank, 8K Rows Organization 32: x32
Power Supply, Interface A: 3.3V, LVTTL Die Rev.
Data Sheet E0507E40 (Ver. 4.0)
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Package BJ: FBGA(Board Type)
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EDS2732AABJ-6B
CONTENTS Specifications ................................................................................................................................................ 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................... 9 Pin Function ................................................................................................................................................ 10 Command Operation................................................................................................................................... 11 Simplified State Diagram ............................................................................................................................ 19 Mode Register Configuration ...................................................................................................................... 20 Power-up sequence .................................................................................................................................... 22 Operation of the SDRAM ............................................................................................................................ 23 Timing Waveforms ...................................................................................................................................... 39 Package Drawing........................................................................................................................................ 45 Recommended Soldering Conditions ......................................................................................................... 46
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Data Sheet E0507E40 (Ver. 4.0)
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EDS2732AABJ-6B
Electrical Specifications
• All voltages are referenced to VSS (GND). • After power up, execute power up sequence and initialization sequence before proper device operation is achieved (refer to the Power up sequence). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Symbol VT VDD IOS PD TA Tstg Rating –0.5 to VDD + 0.5 (≤ 4.6 (max.)) –0.5 to +4.6 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Note
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Storage temperature Parameter Supply voltage Input high voltage Input low voltage
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol VDD, VDDQ min. 3.0 0 2.0 –0.3 max. 3.6 0 VDD + 0.3 0.8 Unit V V V V Notes 1 2 3 4
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VSS, VSSQ
VIH VIL
Notes: 1. 2. 3. 4.
The supply voltage with all VDD and VDDQ pins must be on the same level. The supply voltage with all VSS and VSSQ pins must be on the same level. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns). VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
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Data Sheet E0507E40 (Ver. 4.0)
EDS2732AABJ-6B
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter /CAS latency Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current Refresh current Symbol IDD1 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4 IDD5 Grade max. 110 3 2 20 9 4 3 50 40 180 300 3 -XXL 1 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Test condition Burst length = 1 tRC = tRC (min.) CKE = VIL, tCK = tCK (min.) CKE = VIL, tCK = ∞ CKE, /CS = VIH, tCK = tCK (min.) CKE = VIH, tCK = ∞, /CS = VIH CKE = VIL, tCK = tCK (min.) CKE = VIL, tCK = ∞ CKE, /CS = VIH, tCK = tCK (min.) CKE = VIH, tCK = ∞, /CS = VIH tCK = tCK (min.), BL = 4 tRC = tRC (min.) VIH ≥ VDD – 0.2V VIL ≤ 0.2V VIH ≥ VDD – 0.2V VIL ≤ 0.2V Notes 1, 2, 3 6 7 4 8 1, 2, 6 2, 7 1, 2, 4 2, 8 1, 2, 5 3
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Self refresh current Self refresh current (L-version)
Data Sheet E0507E40 (Ver. 4.0)
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. Input signals are VIH or VIL fixed.
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IDD6 IDD6
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EDS2732AABJ-6B
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. –1 –1.5 2.4 — max. 1 1.5 — 0.4 Unit µA µA V V Test condition 0 ≤ VIN ≤ VDD 0 ≤ VOUT ≤ VDD, DQ = disable IOH = –2 mA IOL = 2 mA Notes
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter Input capacitance Symbol CI1 CI2 CI/O Pins CLK Address, CKE, /CS, /RAS, /CAS, /WE, DQM DQ min. 1.5 1.5 3.0 typ. — — — max. 3.0 3.0 5.5 Unit pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 3, 4
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Data input/output capacitance
Notes: 1. 2. 3. 4.
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing. DQM = VIH to disable DOUT. This parameter is sampled and not 100% tested.
Data Sheet E0507E40 (Ver. 4.0)
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EDS2732AABJ-6B
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-6B Parameter System clock cycle time (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK Data-out hold time CLK to Data-out low impedance Symbol tCK tCK tCH tCL tAC tOH tLZ tHZ tSI tHI tRC tRAS tRCD tRP tDPL tDAL tRRD tT tREF min. — 6 2.5 2.5 — 2.0 0 — 1.5 0.8 60 42 18 18 12 2CLK + 18ns 12 0.5 — max. — — — — 5.4 — — 5.4 — — — 120000 — — — — — 5 64 ns ns ms 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1 1, 2 1, 2 1, 2, 3 1, 4 1 1 1 1 1 1 1
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Input setup time Input hold time Last data into active latency Transition time (rise and fall) Refresh period (4096 refresh cycles)
CLK to Data-out high impedance
Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period
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Notes: 1. 2. 3. 4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V. Access time is measured at 1.4V. Load condition is CL = 30pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
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Data Sheet E0507E40 (Ver. 4.0)
EDS2732AABJ-6B
Test Conditions • Input and output timing reference levels: 1.4V • Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
I/O CL tT
tT
Output load Relationship Between Frequency and Minimum Latency
Parameter -6B 166 Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lDAL 6 3 10 7 3 2 2 1 Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Notes 1 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
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Frequency (MHz) tCK (ns) Self refresh exit time (CL = 3) (CL = 3) DQM to data in DQM to data out CKE to CLK disable /CS to command disable
Data Sheet E0507E40 (Ver. 4.0)
Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Last data in to active command (Auto precharge, same bank) Self refresh exit to command input
Precharge command to high impedance (CL = 2)
Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CL = 2) Column command to column command Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
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Pr
5 lSEC lHZP 10 — 3 lHZP lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lMRD lCDD lPEC 1 — –2 1 0 0 2 1 2 0 1
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tCK tCK
tCK
tCK
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tCK tCK tCK tCK tCK
EDS2732AABJ-6B
Block Diagram
CLK CKE Clock Generator Bank 3 Bank 2 Bank 1 Address
Row Decoder
Mode Register
Row Address Buffer & Refresh Counter
Bank 0
Sense Amplifier
Control Logic
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Command Decoder
/CS
/RAS /CAS /WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Data Sheet E0507E40 (Ver. 4.0)
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EDS2732AABJ-6B
Pin Function
CLK (input pin) CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE (input pins) CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends operation. When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS (input pins) /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 to A12 (input pins) Row Address is determined by A0 to A12 at the CLK (clock) rising edge in the active command cycle. Column Address is determined by A0 to A7 at the CLK rising edge in the read or write command cycle. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal. (See Bank Select Signal Table) [Bank Select Signal Table]
Bank 0 Bank 1 Bank 2 Bank 3 BA0 L
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Data Sheet E0507E40 (Ver. 4.0)
Remark: H: VIH. L: VIL.
DQM (input pins) DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 to DQ31 (input/output pins) DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
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H L H
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10
BA1 L L H H
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EDS2732AABJ-6B
Command Operation
Command Truth Table The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE Function Device deselect No operation Burst stop Read Read with auto precharge Write Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS n–1 H H H H H H H H H H H n × × × × × × × × × × × /CS H L L L L L L L L L L /RAS × H H H H H H L L L L /CAS × H H L L L L H H H L /WE × H L H H L L H L L L BA1,BA0 A10 × × × V V V V V V × L × × × L H L H V L H L
A0 to A12
× × × V V V V V × × V
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Write with auto precharge Bank activate Precharge select bank Precharge all banks Mode register set
Data Sheet E0507E40 (Ver. 4.0)
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input. Device deselect command [DESL] When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal status is held. No operation [NOP] This command is not an execution command. However, the internal operations continue. Burst stop command [BST] This command can stop the current burst operation.
Column address strobe and read command [READ] This command starts a read operation. In addition, the start address of burst read is determined by the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. Column address strobe and write command [WRIT] This command starts a write operation. When the burst write mode is selected, the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). Write with auto-precharge [WRITA] This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation.
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EDS2732AABJ-6B
Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
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Data Sheet E0507E40 (Ver. 4.0)
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SELF] This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS] The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
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EDS2732AABJ-6B
DQM Truth Table
CKE Function Data write / output enable Data mask / output disable DQ0 to DQ7 write enable/output enable DQ8 to DQ15 write enable/output enable DQ16 to DQ23 write enable/output enable DQ24 to DQ31 write enable/output enable DQ0 to DQ7 write inhibit/output disable DQ8 to DQ15 write inhibit/output disable DQ16 to DQ23 write inhibit/output disable DQ24 to DQ31 write inhibit/output disable Symbol ENB MASK ENB0 ENB1 ENB2 ENB3 MASK0 MASK 1 MASK 2 MASK 3 n–1 H H H H H H H H H H n × × × × × × × × × × DQM 0 L H L × × × H × × × 1 L H × L × × × H × × 2 L H × × L × × × H × 3 L H × × × L × × × H
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CKE Truth Table
Current state Activating Any Clock suspend Idle Idle Self refresh Idle Power down Function
Data Sheet E0507E40 (Ver. 4.0)
Remark: H: VIH. L: VIL. ×: VIH or VIL Write: lDID is needed. Read: lDOD is needed.
CKE Symbol n–1 H L L REF SELF H H L L n L L H H L H L /CS × × × L L L H L H H L /RAS × × × L L H × H × × H /CAS × × × L L H × H × × H /WE × × × H H H × H × × H Address × × × × × × × × × × ×
Remark: H: VIH. L: VIL. ×: VIH or VIL
L
Clock suspend mode Clock suspend mode exit Self refresh entry Self refresh exit Power down entry Power down exit
Clock suspend mode entry
CBR (auto) refresh command
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H L H L L H H H
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EDS2732AABJ-6B
Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the SDRAM. The following table assumes that CKE is high.
Current state Precharge /CS H L L L L L L L L /RAS × H H H H L L L L × H H H H L /CAS × H H L L H H L L × H H L L H /WE × H L H L H L H L × H L H L H L H L × Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT Operation Enter IDLE after tRP Enter IDLE after tRP ILLEGAL ILLEGAL*3 ILLEGAL*3 ILLEGAL*3 NOP*5 ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL*4 ILLEGAL*4 Bank and row active NOP Refresh Mode register set*8 NOP NOP ILLEGAL Begin read*6 Begin write*6 Other bank active ILLEGAL on same bank*2 Precharge*7
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Idle H L L L L L L L L Row active H L L L L L L L L Read H L L L L L L L L
Data Sheet E0507E40 (Ver. 4.0)
L
L H L × H H H H L L L L × H H H H L L L L L × L L H H L L H H L L × H H L L H H L L
Pr
H L H L BA, CA, A10 BA, CA, A10 BA, RA H L H L × H L H L H L H L BA, A10 × × MODE × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE
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PRE, PALL REF, SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS
ILLEGAL ILLEGAL
Continue burst to end Continue burst to end
Burst stop Continue burst read to /CAS latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*2
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Term burst read and Precharge ILLEGAL ILLEGAL
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EDS2732AABJ-6B
Current state Read with autoprecharge
/CS H L L L L L L L
/RAS × H H H H L L L L × H H H H L L
/CAS × H H L L H H L L × H H L L H H
/WE × H L H L H L H L × H L H L H L H L × H L
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × ×
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST
Operation Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*3 ILLEGAL*3 Other bank active ILLEGAL on same bank*2 ILLEGAL*3 ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burst write and Precharge*1 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*3 ILLEGAL*3 Other bank active ILLEGAL on same bank*3 ILLEGAL*3 ILLEGAL ILLEGAL
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L Write H L L L L L L L L Write with autoprecharge H L L L L L L L L Refresh (auto-refresh) H L L L L L L L L
Data Sheet E0507E40 (Ver. 4.0)
L
L L L L × H H H H L L L L × H H H H L L L L × H H L L H H L L × H H L L H H L L
Pr
H L BA, CA, A10 BA, CA, A10 BA, RA H L H L × H L H L H L H L BA, A10 × × MODE × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE
READ/READA WRIT/WRITA ACT
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PRE, PALL REF, SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS
Enter IDLE after tRC
Enter IDLE after tRC ILLEGAL*4 ILLEGAL*4 ILLEGAL*4
ILLEGAL ILLEGAL*4
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ILLEGAL ILLEGAL
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EDS2732AABJ-6B
Current state Mode register set
/CS H L L L L L L L L
/RAS × H H H H L L L L
/CAS × H H L L H H L L
/WE × H L H L H L H L
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS
Operation NOP NOP ILLEGAL ILLEGAL*4 ILLEGAL*4 Bank and row active*9 NOP Refresh*9 Mode register set*8
Remark: Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9.
H: VIH. L: VIL. ×: VIH or VIL An interval of tDPL is required between the final valid data input and the precharge command. If tRRD is not satisfied, this operation is illegal. Illegal for same bank, except for another bank. Illegal for all banks. NOP for same bank, except for another bank. Illegal if tRCD is not satisfied. Illegal if tRAS is not satisfied. MRS command must be issued after DOUT finished, in case of DOUT remaining. Illegal if lMRD is not satisfied.
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Data Sheet E0507E40 (Ver. 4.0)
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EDS2732AABJ-6B
Command Truth Table for CKE
CKE Current State Self refresh n–1 n H L L L L L Self refresh recovery H H H × H H H H L H H H H L L L L × H H L /CS × H L L L × H L L L H L L L × H L × /RAS /CAS /WE Address × × H H L × × H H L × H H L × × × × H × × H L × × × H L × × H L × × × H × × × H L L × × × × × × × × × × × × × × × × × H × × × × H L × × × × × × × × × × × × × × × × × × Operation INVALID, CLK (n – 1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Continue self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK (n – 1) would exit power down EXIT power down EXIT power down Continue power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) Refresh Notes
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H H H H H L L L Power down H All banks idle H H H H H H H H H H L L Row active Any state other than listed above H L H H L L
Data Sheet E0507E40 (Ver. 4.0)
Remark: H: VIH. L: VIL. ×: VIH or VIL Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle. Clock suspend can be entered only from following states, row active, read, read with autoprecharge, write and write with auto precharge. 2. Must be legal command as defined in Function Truth Table.
L
H H L L L L L H H H H L L L L L H L × × H L H L H L L L H L × H L L L × × × × × × × × L L × × × × × × × ×
Pr
× × × × H L L × × × × × × × × H L × × × × × × × × × × × × × × × ×
OPCODE Refer to operations in Function Truth Table Begin power down next cycle Refer to operations in Function Truth Table Refer to operations in Function Truth Table Self refresh 1
od
Exit power down next cycle Power down Clock suspend Maintain clock suspend
OPCODE Refer to operations in Function Truth Table 1 1 2
Refer to operations in Function Truth Table
Refer to operations in Function Truth Table Begin clock suspend next cycle Exit clock suspend next cycle
t uc
17
EDS2732AABJ-6B
Clock suspend mode entry The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ with Auto-precharge suspend The data being output is held (and continues to be output). WRITE suspend and WRIT with Auto-precharge suspend In this mode, external signals are not accepted. However, the internal state is held.
EO
Data Sheet E0507E40 (Ver. 4.0)
Clock suspend During clock suspend mode, keep the CKE to Low. Clock suspend mode exit The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF] When this command is input from the IDLE state, the SDRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. Self-refresh entry [SELF] When this command is input during the IDLE state, the SDRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self-refresh exit When this command is executed during self-refresh mode, the SDRAM can exit from self-refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit When this command is executed at the power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
L
Pr
18
od
t uc
EDS2732AABJ-6B
Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_
EO
WRITE SUSPEND WRITEA SUSPEND POWER APPLIED
ACTIVE CLOCK SUSPEND
ACTIVE
IDLE POWER DOWN
CKE_ CKE ROW ACTIVE
BST
BST
WRITE Write WRITE WITH AP READ READ WITH AP READ WITH AP WRITE
READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE READA SUSPEND READ SUSPEND
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Data Sheet E0507E40 (Ver. 4.0)
L
CKE_ CKE CKE_ CKE
WRITE
WRITE WITH AP
WRITE WITH AP
PRECHARGE
Automatic transition after completion of command. Transition resulting from command input.
Pr
WRITEA PRECHARGE PRECHARGE POWER ON PRECHARGE PRECHARGE
od
19
t uc
EDS2732AABJ-6B
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. BA1, BA0, A8, A9, A10, A11, A12: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and burst write: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of the burst length.
EO
BA1 BA0 A12 0 1 1 X X X 1 0 1 X X X X X X X X X X X X X X X
Data Sheet E0507E40 (Ver. 4.0)
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the /CAS latency. A3: (BT): A burst type is specified. A2, A1, A0: (BL): These pins specify the burst length.
A11 A10 A9 A8 A7 0 A6 A5 LMODE A4 A3 BT A2 A1 BL A0
BA1 BA0 A12 A11 0 0 0 0
L
OPCODE A6 0 0 0 0 1 A5 0 0 1 1 X A10 0 X X X X X X A9 0 0 0 0 0 1 1 0 0 0 1 0 1
A4 CAS latency 0 1 0 1 R R 2 3
A3 Burst type 0 Sequential Interleave A2 A1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 1
Burst length BT=0 1 2 4 8 R R R F.P. BT=1 1 2 4 8 R R R R
Pr
X R A8 Write mode 0 Burst read and burst write R R R R Burst read and single write R
Mode Register Set Timing
od
20
F.P.: Full Page R is Reserved (inhibit) X: 0 or 1
t uc
EDS2732AABJ-6B
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequential Interleave 0, 1, 1, 0, 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 A1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequential A0 0 1 0 1 Sequential 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
EO
1 1 0 1 1 0 1 1
Data Sheet E0507E40 (Ver. 4.0)
Burst Sequence
Full page burst is available only for sequential addressing. The addressing sequence is started from the column address that is asserted by read/write command. And the address is increased one by one. It is back to the address 0 when the address reaches at the end of address 511. “Full page burst” stops the burst read/write with burst stop command.
L
Pr od t uc
21
EDS2732AABJ-6B
Power-up sequence
Power-up sequence The SDRAM should be goes on the following sequence with power up. The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence. The CKE and DQM is driven to high between power stabilizes and the initialization sequence. This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these pins go high before power up, the large current flows from these pins to VDD through the diodes. Initialization sequence When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.
Power up sequence 100 μs 0V Low Low Low Initialization sequence 200 μs
EO
VDD, VDDQ CKE, DQM CLK /CS, DQ
Data Sheet E0507E40 (Ver. 4.0)
L Pr
Power stabilize
Power-up sequence and Initialization sequence
od t uc
22
EDS2732AABJ-6B
Operation of the SDRAM
Read/Write Operations Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register.
CLK
EO
Command Address DQ CL = 2 CL = 3
CLK Command Address
ACT Row
tRCD
READ
ACT
BL = 1
DQ
BL = 2 BL = 4
out 0 out 1 out 2
BL = 8
Data Sheet E0507E40 (Ver. 4.0)
L
Row
Column
out 0
out 1 out 0
out 2 out 1
out 3 out 2 out 3 CL = /CAS latency Burst Length = 4
Pr
/CAS Latency
tRCD
READ
od t uc
BL : Burst Length /CAS Latency = 2
Column
out 0 out 0 out 1
out 0 out 1 out 2 out 3
out 3 out 4 out 5 out 6 out 7
Burst Length
23
EDS2732AABJ-6B
Write operation Burst write or single write mode is selected by the OPCODE of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address and the bank select address at the write command set cycle.
CLK
tRCD
Command Address
ACT
WRIT
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
in 0 in 0 in 0 in 0 in 1 in 1 in 1
in 2 in 2
EO
DQ
in 3 in 3 in 4 in 5 in 6 in 7
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
Data Sheet E0507E40 (Ver. 4.0)
L
CLK Command Address DQ
tRCD WRIT
ACT
Pr
Row Column
in 0
Single write
od t uc
24
EDS2732AABJ-6B
Auto Precharge Read with auto-precharge In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is required before execution of the next command. [Clock cycle time]
/CAS latency 3 2
CLK
Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output
EO
CL=2 Command ACT DQ CL=3 Command ACT DQ
READA lRAS out0 out1 out2 out3
ACT
lAPR READA lRAS out0 out1 out2 out3 ACT
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
lAPR
".
Write with auto-precharge In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is required between the final valid data input and input of next command.
Command
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
Data Sheet E0507E40 (Ver. 4.0)
L
CLK
ACT
Burst Read (BL = 4)
Pr
WRITA
ACT
lRAS DQ
Burst Write (BL = 4)
od
in0 in1 in2 in3 lDAL
t uc
25
EDS2732AABJ-6B
CLK Command
ACT ACT
WRITA
lRAS DQ in lDAL Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
EO
Data Sheet E0507E40 (Ver. 4.0)
Single Write
L Pr od t uc
26
EDS2732AABJ-6B
Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command.
CLK Command DQ (CL = 2) DQ (CL = 3)
READ BST High-Z
out
out
out
out
out
out
High-Z
EO
CLK Command DQ
Data Sheet E0507E40 (Ver. 4.0)
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command.
WRITE in in in in
BST
High-Z
L
Burst Stop at Write
Pr od t uc
27
EDS2732AABJ-6B
Command Intervals Read command to Read command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK Command
Address
BS
ACT READ READ
Row
Column A Column B
DQ
EO
CLK Command
Address
out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout
Bank0 Active
CL = 3 BL = 4 Bank 0
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
BS
DQ
Bank0 Active
Data Sheet E0507E40 (Ver. 4.0)
L
ACT ACT
Row 0
Row 1
READ READ
Column A Column B
READ to READ Command Interval (different bank)
Pr
Bank3 Bank0 Bank3 Active Read Read Bank0 Bank3 Dout Dout
out A0 out B0 out B1 out B2 out B3
CL = 3 BL = 4
od t uc
28
EDS2732AABJ-6B
Write command to Write command interval 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
CLK Command
Address
ACT WRIT WRIT
Row
Column A Column B
BS
DQ
in A0 Bank0 Active in B0 in B1 in B2 in B3
EO
CLK Command
ACT
Column =A Column =B Write Write
Burst Write Mode BL = 4 Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
Address
BS
DQ
Bank0 Active
Data Sheet E0507E40 (Ver. 4.0)
L
ACT
Row 0
Row 1
WRIT
WRIT
Column A Column B
WRITE to WRITE Command Interval (different bank)
Pr
in A0 in B0 in B1 in B2 in B3 Bank3 Bank0 Bank3 Active Write Write
Burst Write Mode BL = 4
od t uc
29
EDS2732AABJ-6B
Read command to Write command interval 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK Command
CL=2
READ WRIT
DQM
CL=3
in B0 High-Z in B3
DQ (input)
in B1
in B2
DQ (output)
BL = 4 Burst write
EO
DQ
Data Sheet E0507E40 (Ver. 4.0)
READ to WRITE Command Interval (1)
CLK
READ WRIT
Command
DQM
out
2 clock
out out out out in in in in in in in in
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input.
L
CL=2 CL=3
READ to WRITE Command Interval (2)
Pr
30
od t uc
EDS2732AABJ-6B
Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed.
CLK Command DQM
DQ (input)
WRIT
READ
in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3
Burst Write Mode CL = 2 BL = 4 Bank 0
EO
DQ (output)
CLK Command DQM DQ (input) DQ (output)
/CAS Latency Column = B Dout
WRITE to READ Command Interval (1)
WRIT
READ
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
Data Sheet E0507E40 (Ver. 4.0)
L
in A0 Column = A Write
in A1 out B0 out B1 out B2 out B3 Burst Write Mode CL = 2 BL = 4 Bank 0
Pr
Column = B Read
/CAS Latency
Column = B Dout
WRITE to READ Command Interval (2)
od
31
t uc
EDS2732AABJ-6B
Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK Command BS DQ bank0 Read A bank3 Read ". out A0 out A1 out B0 out B1 CL= 3 BL = 4 READA READ
Note: Internal auto-precharge starts at the timing indicated by "
EO
CLK Command BS DQ
Data Sheet E0507E40 (Ver. 4.0)
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts 2 clocks later from the second command.
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command (the same bank) is illegal.
L
WRITA in A0 bank0 Write A in A1
WRIT
in B0 bank3 Write
in B1
in B2
in B3 BL= 4
Write with Auto Precharge to Write Command Interval (Different bank)
Pr
32
".
od t uc
EDS2732AABJ-6B
Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK Command BS CL = 2 DQM CL = 3 in B0 in B1 in B2 in B3 READA WRIT
DQ (input)
EO
CLK Command BS DQM DQ (input) DQ (output)
Data Sheet E0507E40 (Ver. 4.0)
DQ (output) bank0 ReadA bank3 Write
High-Z BL = 4 ".
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
WRITA in A0 bank0 WriteA
Note: Internal auto-precharge starts at the timing indicated by "
Write with Auto Precharge to Read Command Interval (Different bank)
Pr
READ
od
out B0 out B1
out B2
out B3 CL = 3 BL = 4 ".
bank3 Read
t uc
33
EDS2732AABJ-6B
Read command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution.
CLK
Command
READ
PRE/PALL
DQ
out A0
out A1
out A2
out A3
CL=2
lEP = -1 cycle
EO
CLK Command DQ
CLK Command DQ CLK Command DQ
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
READ
PRE/PALL
out A0
out A1
out A2
out A3
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0507E40 (Ver. 4.0)
L
READ READ
CL=3
lEP = -2 cycle
Pr
PRE/PALL High-Z out A0 lHZP = 2 PRE/PALL out A0 lHZP =3
od
High-Z
t uc
34
EDS2732AABJ-6B
Write command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK Command DQM WRIT
PRE/PALL
DQ
in A0
in A1
in A2
tDPL
EO
CLK Command DQM DQ
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
WRIT
PRE/PALL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
Data Sheet E0507E40 (Ver. 4.0)
L
in A0
in A1
in A2
in A3
tDPL
Pr od t uc
35
EDS2732AABJ-6B
Bank active command interval 1. Same bank: The interval between the two bank active commands must be no less than tRC. 2. In the case of different bank active commands: The interval between the two bank active commands must be no less than tRRD.
CLK Command ACT ACT
Address
ROW
ROW
BS
tRC
Bank 0 Active
EO
Data Sheet E0507E40 (Ver. 4.0)
Bank 0 Active
Bank Active to Bank Active for Same Bank
CLK ACT ROW:0 ACT ROW:1
Command Address
Mode register set to Bank active command interval The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
L
BS
Command Address
tRRD Bank 0 Active Bank 3 Active
Mode register set to Bank active command interval
Pr
MRS OPCODE lMRD Mode Register Set
Bank Active to Bank Active for Different Bank
od
ACT
BS & ROW
Bank Active
t uc
36
EDS2732AABJ-6B
DQM Control The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM/LDQM is different during reading and writing. Reading When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks. Writing Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0 clock.
EO
CLK DQM DQ
CLK DQM DQ
Data Sheet E0507E40 (Ver. 4.0)
High-Z out 0 out 1 out 3
lDOD = 2 Latency
Reading
L
in 0
Pr
in 1
in 3
lDID = 0 Latency
od
Writing
t uc
37
EDS2732AABJ-6B
Refresh Auto-refresh All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode.
EO
Others
Data Sheet E0507E40 (Ver. 4.0)
Note: tREF (max.) / refresh cycles.
Power-down mode The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
L
Pr
38
od t uc
EDS2732AABJ-6B
Timing Waveforms
Read Cycle
tCK tCH t CL
CLK
t RC VIH
CKE
tRCD tSI tHI tSI tHI
tRAS tSI tHI
t RP tSI tHI
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
tSI tHI tSI tHI tSI tHI tSI tHI
EO
/CAS /WE BS A10 Address DQM DQ (input) DQ (output)
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
Data Sheet E0507E40 (Ver. 4.0)
L
tSI
tAC t AC tOH
Bank 0 Active Bank 0 Read
tHI
Pr
tAC tAC tOH tOH tLZ
Bank 0 Precharge
tHZ
tOH
/CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL = VOH or VOL
od t uc
39
EDS2732AABJ-6B
Write Cycle
tCK tCH tCL
CLK
tRC
VIH
CKE
tRCD tSI tHI tSI tHI tSI tHI tSI tHI tRAS tRP
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
tSI tHI tSI tHI tSI tHI tSI tHI
/CAS
EO
/WE BS A10 Address DQM DQ (input) DQ (output)
0
tSI tHI
tSI tHI tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI
Mode Register Set Cycle
1 2
L
tSI Bank 0 Active
tHI
t HI
tSI
tHI tSI
tHI
tSI
tHI
tDPL
Pr
Bank 0 Write
Bank 0 Precharge
CL = 2 BL = 4 Bank 0 access = VIH or VIL
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
lRP
Precharge If needed
od t uc
b+3 b’ b’+1 b’+2 b’+3 lRCD = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL valid code R: b C: b C: b’ b High-Z lMRD
Mode register Set Bank 3 Active
VIH
lRCD
Bank 3 Read
Output mask
Data Sheet E0507E40 (Ver. 4.0)
40
EDS2732AABJ-6B
Read Cycle/Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank 0 Active Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIH
Read cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
R:a
C:a
R:b a
C:b a+1 a+2 a+3
Bank 3 Bank 0 Read Precharge
C:b' b
High-Z
Bank 3 Read
C:b" b'+1 b" b"+1 b"+2 b"+3
Bank 3 Precharge
b+1 b+2 b+3 b'
Bank 3 Read
CKE /CS
VIH
/RAS /CAS
Write cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
EO
/WE BS Address R:a DQM DQ (output) DQ (input)
Bank 0 Active
C:a
R:b
C:b
High-Z
C:b'
C:b"
a
Bank 0 Write
a+1 a+2 a+3
Bank 3 Active
b
Bank 3 Write
b+1 b+2 b+3 b'
Bank 0 Precharge Bank 3 Write
b'+1 b"
Bank 3 Write
b"+1 b"+2 b"+3
Bank 3 Precharge
Read/Single Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
Bank 0 Active
CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
Data Sheet E0507E40 (Ver. 4.0)
L
1 2 3
VIH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pr
C:a R:b a a
Bank 0 Read Bank 3 Active
R:a
C:a' C:a
a+1 a+2 a+3
od
a
Bank 0 Bank 0 Write Read
a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
VIH
t uc
C:b C:c b c
Bank 0 Precharge
R:a
C:a
R:b
C:a a a a+1 a+3
Bank 0 Write
Bank 0 Active
Bank 0 Read
Bank 3 Active
Bank 0 Bank 0 Write Write
Read/Single write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
41
EDS2732AABJ-6B
Read/Burst Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output) a
Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a' a a+1 a+2 a+3
Clock suspend
a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
EO
Bank 0 Active
Bank 0 Write
CKE /CS
VIH
/RAS /CAS
/WE BS
Address DQM
R:a
C:a
R:b
C:a a a a+1 a+3
Bank 0 Write Bank 0 Precharge
L
Bank 0 Active Bank 0 Read
DQ (input) DQ (output)
a+1 a+2 a+3
Bank 3 Active
Read/Burst write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Pr
3 4 5 6 7 8 9 10 11 High-Z
Auto Refresh Cycle
0 1 2
12
13
14
15
16
17
18
19
20
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
A10=1
od
R:a
VIH
C:a
t uc
a a+1
Active Bank 0 Read Bank 0
t RP
Precharge If needed Auto Refresh
t RC
Auto Refresh
t RC
Refresh cycle and Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
Data Sheet E0507E40 (Ver. 4.0)
42
EDS2732AABJ-6B
Self Refresh Cycle
CLK CKE /CS /RAS /CAS /WE BS Address DQM
A10=1
lSREX
CKE Low
EO
DQ (input) DQ (output)
High-Z
t RP
Self refresh entry command Self refresh exit ignore command or No operation
t RC
Next clock enable Self refresh entry command
t RC
Auto Next clock refresh enable
Precharge command If needed
Self refresh cycle /RAS-/CAS delay = 3 CL = 3 BL = 4 = VIH or VIL
Clock Suspend Mode
0
tSI
tHI
tSI
L
1 2 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
Pr
C:a R:b a a+1 a+2
High-Z
Active clock Bank0 suspend end Read Bank3 Active
Read suspend start
Read suspend end
R:a
C:b b b+1 b+2 b+3
a+3
Bank0 Active clock Active suspend start
Bank3 Read
Bank0 Precharge
Earliest Bank3 Precharge
od
C:b
High-Z
CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank0 Active
Active clock suspend start
Write cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
R:a
C:a R:b
t uc
Earliest Bank3 Precharge
a
a+1 a+2
Write suspend start
a+3 b
Write suspend end
b+1 b+2 b+3
Active clock Bank0 Bank3 supend end Write Active
Bank3 Bank0 Write Precharge
Data Sheet E0507E40 (Ver. 4.0)
43
EDS2732AABJ-6B
Power Down Mode
CLK CKE /CS /RAS /CAS /WE BS Address
A10=1
CKE Low
R: a
EO
Initialization Sequence
CLK CKE /CS /RAS
0 VIH
DQM
DQ (input)
High-Z
DQ (output) tRP
Precharge command If needed Power down entry
Power down /RAS-/CAS delay = 3 mode exit Active Bank 0 /CAS latency = 3
Power down cycle Burst length = 4 = VIH or VIL
L
1 2 3 valid VIH tRP All banks Precharge
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
Pr
t RC Auto Refresh Auto Refresh
/CAS /WE Address DQM DQ
code
Valid
High-Z tRC lMRD Bank active If needed
od
44
Mode register Set
t uc
Data Sheet E0507E40 (Ver. 4.0)
EDS2732AABJ-6B
Package Drawing
90-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
0.2 S A
8.0 ± 0.1
0.2 S B
EO
Data Sheet E0507E40 (Ver. 4.0)
13.0 ± 0.1
INDEX AREA
INDEX MARK
L
0.1 S
0.8
0.2 S
1.14 max.
S
Pr
B A
0.8 0.8 1.6 0.9
0.35 ± 0.05
90-φ0.45 ± 0.05
φ0.08 M S A B
od t uc
ECA-TS2-0096-01
45
EDS2732AABJ-6B
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS2732AABJ. Type of Surface Mount Device EDS2732AABJ: 90-ball FBGA < Lead free (Sn-Ag-Cu) >
EO
Data Sheet E0507E40 (Ver. 4.0)
L Pr od t uc
46
EDS2732AABJ-6B
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
EO
2 3
Data Sheet E0507E40 (Ver. 4.0)
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
L
Pr
47
CME0107
od t uc
EDS2732AABJ-6B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Data Sheet E0507E40 (Ver. 4.0)
L
Pr
48
M01E0107
od t uc
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