DATA SHEET
512M bits XDR™ DRAM
EDX5116ADSE (32M words × 16 bits)
Overview
The EDX5116ADSE is a 512M bits XDR™ DRAM organized as 32M words × 16 bits. It is a general-purpose high-performance memory device suitable for use in a broad range of applications. The use of Differential Rambus Signaling Level (DRSL) technology permits 4000/3200 Mb/s transfer rates while using conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of 8000/6400 MB/s. XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granularity. The device’s eight banks support up to four interleaved transactions. It is packaged in 104-ball FBGA compatible with Rambus XDR DRAM pin configuration. • Low power • 1.8V Vdd • Programmable small-swing I/O signaling (DRSL) • Low power PLL/DLL design • Powerdown self-refresh support • Per pin I/O powerdown for narrow-width operation
Pin Configuration
L 1
DQN3 DQN9 VDD GND VDD
K
J
H
G
F Row
E
GND
D
VDD
C
SDI
B
A
2
DQ3
1
DQ9 VDD DQN15 DQ15
2
3
CFM
4
5
6
GND
7
DQN8 DQN2 DQ8 DQ2
3 4 5 6 7 8
P
DQ5 DQN5 DQN5 VDD RQ10
RSRV RSRV VDD
DQN7 RQ0 DQN4 DQ7 RQ4 DQN14 VTERM GND GND DQ4 RQ3 DQN3 VTERM VDD DQ3 DQ14 VDD GND
N
GND GND RQ11 VDD DQ5 CFMN DQ1 DQN1 VDD VTERM GND GND VDD VDD VREF GND VDD VTERM RQ10GND RQ8 RQ6 RQ4 RQ2 RQ0 GND VDD GND VDD RQ7 RQ6 GND
GND
M VDD L K J
GND
VDD
RQ11 VDD RQ9 RQ7 CFMN RQ5
GND GND VDD GND CFM GND
Column
9 10
H G F
Features
• Highest pin bandwidth available 4000/3200 Mb/s Octal Data Rate (ODR) Signaling • Bi-directional differential RSL (DRSL) - Flexible read/write bandwidth allocation - Minimum pin count • On-chip termination -Adaptive impedance matching -Reduced system cost and routing complexity Highest sustained bandwidth per DRAM device • 8000/6400 MB/s sustained data rate • Eight banks: bank-interleaved transactions at full bandwidth • Dynamic request scheduling • Early-read-after-write support for maximum efficiency • Zero overhead refresh Dynamic width control • EDX5116ADSE supports × 16, × 8 and × 4 mode Low latency • 2.0/2.5 ns request packets • Point-to-point data interconnect for fastest possible flight time • Support for low-latency, fast-cycle cores
11 12 13 14 15 16
GND
GND
RQ3 VDD RQ1
VDD VTERM GND GND GND GND VDD
E VDD D
DQN7 DQ7
GND RST GND GND SD0 CMD RQ9 DQN13 VDD DQ0 DQN0 DQ13 CMD RQ8
VREF RQ5
SCK RQ1
SD1 VDD DQN12 DQN6 DQ6
C B A
DQN2 DG2 RQ2 GND DQ12 VTERM
GND VDD DQN11 DQN1 SCK DQ11 DQ4 DQN4 GND DQ1 VDD VDD GND
GND RST DQN0 DQN10 DQ10
DQN6 DQ6 VDD SDO DQ0
A16
A8
Top view of package
•
• •
Doc. No. E1033E40 (Ver. 4.0) Date Published September 2009 (K) Japan Printed in Japan URL: http://www.elpida.com
©Elpida Memory, Inc.
2007-2009
EDX5116ADSE
Ordering Information
Part number EDX5116ADSE-4D-E EDX5116ADSE-3C-E EDX5116ADSE-3B-E EDX5116ADSE-3A-E Organization 4M × 16 × 8 banks Bandwidth (1/tBIT)*1 Latency (tRAC)*2 4.0G 3.2G 3.2G 3.2G 34 35 35 27 Bin D C B A Package 104-ball FBGA
Notes:1. Data rate measured in Mbit/s per DQ differential pair. Note that tBIT = tCYCLE/8 2. Read access time tRAC (= tRCD-R + tCAC) measured in ns.
Part Number
E D X 51 16 A D SE - 4D - E
Elpida Memory Type D: Monolithic Device Product Family X: XDR DRAM Density 51: 512M (x 16bit) Organization 16: x16bit Power Supply, Interface A: 1.8V, DRSL Environment Code E: Lead Free (RoHS compliant) Speed 4D: 4.0G (tRAC = 34, D Bin) 3C: 3.2G (tRAC = 35, C Bin) 3B: 3.2G (tRAC = 35, B Bin) 3A: 3.2G (tRAC = 27, A Bin) Package SE: FBGA Die Rev.
Data Sheet E1033E40 (Ver. 4.0) 2
EDX5116ADSE
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a signal name denotes the complementary signal of a differential pair. A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bitwindows on each signal, while the DQ bus uses a set of 16 bitwindows on each signal. In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) comFigure 1 XDR DRAM Device Write and Read Transactions T0 CFM CFMN RQ11..0
ACT WR a0 a1 WR a2
mand. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second request packet at clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command. This causes the data packet D(a2) at edge T6 to be also written to column Ca2. A final request packet at clock edge T14 contains a precharge (PRE) command. The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD -W, tCC , and tWRP . In addition, the spacing between the request packets and data packets are constrained by the tCWD parameter. The spacing of the CFM/CFMN clock edges is constrained by tCYCLE.
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t DQ15..0 RCD-W DQN15..0
tCC tCWD
D(a1) D(a2)
tWRP
PRE a3
tCYCLE
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
ACT a0 RD a1 RD a2 PRE a3 Q(a1) Q(a2)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
tRCD-R
tCC
tRDP
tCAC
Transaction a: RD a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command. The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD -R, tCC , and tRDP . In addition, the spacing between the request and data packets are constrained by the tCAC parameter.
Data Sheet E1033E40 (Ver. 4.0) 3
EDX5116ADSE
Table of Contents
Overview ....................................................................... 1 Features ........................................................................ 1 Pin Configuration ......................................................... 1 Ordering Information ................................................... 2 Part Number .................................................................2 General Description ......................................................3 Table of Contents .........................................................4 Pin Description .............................................................7 Block Diagram ..............................................................8 Request Packets ......................................................... 10 Request Packet Formats ................................................. 10 Request Field Encoding .................................................. 12 Request Packet Interactions ........................................... 14 Request Interaction Cases .............................................. 15 Dynamic Request Scheduling ........................................ 20 Memory Operations .................................................... 22 Write Transactions .......................................................... 22 Read Transactions ........................................................... 24 Interleaved Transactions ................................................. 26 Read/Write Interaction .................................................. 28 Propagation Delay ........................................................... 28 Register Operations .................................................... 32 Serial Transactions ........................................................... 32 Serial Write Transaction ................................................. 32 Serial Read Transaction .................................................. 32 Register Summary ............................................................ 34 Maintenance Operations ............................................ 40 Refresh Transactions ....................................................... 40 Interleaved Refresh Transactions .................................. 40 Calibration Transactions ................................................. 42
Power State Management ............................................... 44 Initialization ...................................................................... 46 XDR DRAM Initialization Overview .......................... 47 XDR DRAM Pattern Load with WDSL Reg ............. 48 Special Feature Description ....................................... 50 Dynamic Width Control ................................................. 50 Write Masking .................................................................. 52 Multiple Bank Sets and the ERAW Feature ................ 54 Simultaneous Activation ................................................. 56 Simultaneous Precharge ................................................. 57 Operating Conditions ................................................ 58 Electrical Conditions ....................................................... 58 Timing Conditions .......................................................... 59 Operating Characteristics .......................................... 60 Electrical Characteristics ................................................ 60 Supply Current Profile .................................................... 61 Timing Characteristics .................................................... 62 Timing Parameters .......................................................... 62 Receive/Transmit Timing ......................................... 64 Clocking ............................................................................ 64 RSL RQ Receive Timing ................................................ 65 DRSL DQ Receive Timing ............................................ 66 DRSL DQ Transmit Timing ......................................... 68 Serial Interface Receive Timing ..................................... 70 Serial Interface Transmit Timing .................................. 71 Package Description .................................................. 72 Package Parasitic Summary ............................................ 72 Package Drawing ............................................................ 74 Package Pin Numbering ................................................. 75 Recommended Soldering Conditions ....................... 76
Data Sheet E1033E40 (Ver. 4.0) 4
EDX5116ADSE
List of Tables
Pin Description .............................................................7 Request Field Description .......................................... 10 OP Field Encoding Summary .................................... 12 ROP Field Encoding Summary .................................. 12 POP Field Encoding Summary .................................. 13 XOP Field Encoding Summary .................................. 13 Packet Interaction Summary ...................................... 14 SCMD Field Encoding Summary ............................... 32
Initialization Timing Parameters .............................. 47 XDR DRAM WDSL-to-Core/DQ/SC Map ............... 48 Core Data Word-to-WDSL Format ............................ 49 Electrical Conditions .................................................. 58 Timing Conditions ..................................................... 59 Electrical Characteristics ........................................... 60 Supply Current Profile .................................................61 Timing Characteristics ............................................... 62 Timing Parameters .................................................... 62 Package Parasitic Summary........................................ 72
Data Sheet E1033E40 (Ver. 4.0) 5
EDX5116ADSE
List of Figures
XDR DRAM Device Write and Read Transactions .....3 512Mb (8x4Mx16) XDR DRAM Block Diagram ..........9 Request Packet Formats ..............................................11 ACT-, RD-, WR-, PRE-to-ACT Packet Interactions . 16 ACT-, RD-, WR-, PRE-to-RD Packet Interactions ... 17 ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 18 ACT-, RD, WR-, PRE-to-PRE Packet Interactions .. 19 Request Scheduling Examples ................................... 21 Write Transactions ..................................................... 23 Read Transactions ...................................................... 25 Interleaved Transactions ............................................ 27 Write/Read Interaction .............................................. 29 Propagation Delay ...................................................... 31 Serial Write Transaction ............................................. 33 Serial Read Transaction — Selected DRAM .............. 33 Serial Read Transaction — Non-selected DRAM ..... 33 Serial Identification (SID) Register ............................ 34 Configuration (CFG) Register .................................... 35 Power Management (PM) Register ............................ 35 Write Data Serial Load (WDSL) Control Register ..... 35 RQ Scan High (RQH) Register ................................. 36 RQ Scan Low (RQL) Register .................................... 36 Refresh Bank (REFB) Control Register ..................... 36 Refresh High (REFH) Row Register ......................... 37 Refresh Middle (REFM) Row Register ..................... 37 Refresh Low (REFL) Row Register ........................... 37 IO Configuration (IOCFG) Register .......................... 37
Current Calibration 0 (CC0) Register ........................ 38 Current Calibration 1 (CC1) Register ......................... 38 Read Only Memory 0 (ROM0) Register .................... 38 Read Only Memory 1 (ROM1) Register .................... 38 TEST Register ............................................................ 39 Delay (DLY) Control Register ................................... 39 Refresh Transactions ..................................................41 Calibration Transactions ............................................ 43 Power State Management .......................................... 45 Serial Interface System Topology .............................. 46 Initialization Timing for XDR DRAM[k] Device .... 46 Multiplexers for Dynamic Width Control .................. 50 D-to-S and S-to-Q Mapping for Dynamic Width Control 51 Byte Mask Logic ........................................................ 52 Write-Masked (WRM) Transaction Example ........... 53 Write/Read Interaction — No ERAW Feature ......... 54 Write/Read Interaction — ERAW Feature ............... 54 XDR DRAM Block Diagram with Bank Sets .......... 55 Simultaneous Activation — tRR-D Cases ................. 56 Simultaneous Precharge — tPP-D Cases .................. 57 Clocking Waveforms .................................................. 64 RSL RQ Receive Waveforms ..................................... 65 DRSL DQ Receive Waveforms .................................. 67 DRSL DQ Transmit Waveforms ................................ 69 Serial Interface Receive Waveforms ........................... 70 Serial Interface Transmit Waveforms .........................71 Equivalent Circuits for Package Parasitic ................. 73 CSP x16 Package - Pin Numbering (top view) .......... 75
Data Sheet E1033E40 (Ver. 4.0) 6
EDX5116ADSE
Pin Description
Table 1 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These include VDD and GND for the core and interface logic, VREF for receiving input signals, and VTERM for driving output signals. The next group of pins are used for high bandwidth memory accesses. These include DQ15..0 and DQN15..0 for carrying
Table 1 Pin Signal VDD GND VREF VTERM DQ15..0 DQN15..0 RQ11..0 CFM CFMN RST CMD SCK SDI SDO RSRV I/O I/O I/O I I I I I I I O Type DRSLa DRSLa RSLa DIFFCLK a DIFFCLK a RSLa RSLa RSLa RSLa CMOSa No. of pins 22 24 1 4 16 16 12 1 1 1 1 1 1 1 2 104
read and write data signals, RQ11..0 for carrying request signals, and CFM and CFMN for carrying timing information used by the DQ, DQN, and RQ signals. The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the state of the device, CMD for carrying command signals, SDI, and SDO for carrying register read data, and SCK for carrying the timing information used by the RST, SDI, SDO, and CMD signals. Description
Description
Supply voltage for the core and interface logic of the device. Ground reference for the core and interface logic of the device. Logic threshold reference voltage for RSL signals. Termination voltage for DRSL signals. Positive data signals that carry write or read data to and from the device. Negative data signals that carry write or read data to and from the device. Request signals that carry control and address information to the device. Clock from master — Positive interface clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. Clock from master — Negative interface clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. Reset input — This pin is used to initialize the device. Command input — This pin carries command, address, and control register write data into the device. Serial clock input — Clock source used for reading from and writing to the control registers. Serial data input — This pin carries control register read data through the device. This pin is also used to initialize the device. Serial data output — This pin carries control register read data from the device. This pin is also used to initialize the device. Reserved pins — Follow Rambus XDR system design guidelines for connecting RSRV pins
Total pin count per package
a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1. All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
Data Sheet E1033E40 (Ver. 4.0) 7
EDX5116ADSE
Block Diagram
A block diagram of the XDR DRAM device is shown in Figure 2. It shows all interface pins and major internal blocks. The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals: 1/tCYCLE, 2/tCYCLE, and 16/tCC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These virtual signals show the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual memory component. The RQ11..0 pins receive the request packet. Two 12-bit words are received in one tCYCLE interval. This is indicated by the 2/ tCYCLE clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request packet. These 24 bits are loaded into a register (clocked by the 1/tCYCLE clocking signal) and decoded by the Decode Block. The VREF pin supplies a reference voltage used by the RQ receivers. Three sets of control signals are produced by the Decode Block. These include the bank (BA) and row (R) addresses for an activate (ACT) command, the bank (BR) and row (REFr) addresses for a refresh activate (REFA) command, the bank (BP) address for a precharge (PRE) command, the bank (BR) address for a refresh precharge (REFP) command, and the bank (BC) and column (C and SC) addresses for a read (RD) or write (WR or WRM) command. In addition, a mask (M) is used for a masked write (WRM) command. These commands can all be optionally delayed in increments of tCYCLE under control of delay fields in the request. The control signals of the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined by core timing parameters, in this case 1/tRR, 1/tPP, and 1/tCC (1/4, 1/4, and 1/2 the frequency of CFM in the -3200 component). These registers may be loaded at any tCYCLE rising edge. Once loaded, they should not be changed until a tRR, tPP, or tCC time later because timing paths of the memory core need time to settle. A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associated sense amp array for the bank. Sensing a row is also
referred to as “opening a page” for the bank. Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to a state in which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank. After a bank is given an ACT command and before it is given a PRE command, it may receive read (RD) and write (WR) column commands. These commands permit the data in the bank’s associated sense amp array to be accessed. For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank is written with the data received from the DQ15..0 pins. The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is read. The data is transmitted onto the DQ15..0 pins. The DQ15..0 pins receive the write data packet (D) for a write transaction. 16 sixteen-bit words are received in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 1:16 Demux Block that assembles the 16x16-bit write data packet. The write data is then driven to the selected Sense Amp Array Bank. 16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15..0 pins transmit this read data packet (Q) in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 16:1 Mux Block. The VTERM pin supplies a termination voltage for the DQ pins. The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address, and control needed to write the control registers. The read data for the these registers is accessed through the SDO/SDI pins. These pins are also used to initialize the device. The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and receive circuits of the device. The control registers also supply bank (REFB) and row (REFr) addresses for refresh operations.
Data Sheet E1033E40 (Ver. 4.0) 8
EDX5116ADSE
Figure 2 512Mb (8x4Mx16) XDR DRAM Block Diagram RQ11..0 12 VREF 1 CFM CFMN RST,SCK,CMD,SDI SDO 4 1
2/tCYCLE 1:2 Demux 12 reg 12 Decode COL logic 7 6+4 RD,WR delay
{0..1}*tCYCLE
12 12 1/tCYCLE
1/tCYCLE 2/tCYCLE 16/ tCC
Control Registers
PRE logic 3 3 PRE delay
{0..3}*tCYCLE
ACT logic 12 3
REFB,REFr
Power Mode Logic Calibration Logic Refresh Logic Initialization Logic
WIDTH
...
ACT delay
{0..1}*tCYCLE
1/tRR 3 12 1/tPP reg 3
23
decode
1
...
ACT ACT ROW ROW
Bank Array Bank 0
16x16*26*212
R,REFr
reg
BA,BR,REFB
1
23
decode
1
...
PRE PRE
Bank 0
BP,BR,REFB
1
16x16*26 1/tCC reg BC C reg SC M 16x16 Byte Mask (WR) Dynamic Width Demux (WR) 16x16 D[15:0][15:0]
...
...
Bank (2 - 1) 16x16*26
3
...
23
decode
1
...
R/W R/W COL COL
Sense Amp Array
16x16*26 Sense Amp 0
3 6 4 8
1
...
Sense Amp (23 - 1) 16x16 16x16
...
16x16 Q[15:0][15:0]
S[15:0][15:0] WIDTH Dynamic Width Mux (RD) 16x16
16 1:16 Demux 16 termination 16/tCC 16:1 Mux 16
2 VTERM
16 DQ15..0
16 DQN15..0
Data Sheet E1033E40 (Ver. 4.0) 9
...
... ... ...
16
16/tCC
EDX5116ADSE
Request Packets
A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet formats, field encodings and packet interactions.
mand. In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the activate (ACT) command. In the COL packet, a bank address (BC), column address (C), sub-column address (SC), command delay (DELC), and subopcode (WRX) are specified for the read (RD) and write (WR) commands. In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), and mask field (M) are specified for the masked write (WRM) command. In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP) are specified for the precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the refresh (REF) commands. In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands.
Request Packet Formats
There are five types of request packets: 1. 2. 3. 4. 5. ROWA — specifies an ACT command COL — specifies RD and WR commands COLM — specifies a WRM command ROWP — specifies PRE and REF commands COLX — specifies the remaining commands
Table 2 describes fields within different request packet types. Various request packet type formats are illustrated in Figure 3. Each packet type consists of 24 bits sampled on the RQ11..0 pins on two successive edges of the CFM/CFMN clock. The request packet formats are distinguished by the OP3..0 field. This field also specifies the operation code of the desired comTable 2 Request Field OP3..0 DELA BA2..0 R11..0 WRX DELC BC2..0 C9..4 SC3..0 M7..0 POP2..0 BP2..0 ROP2..0 RA7..0 XOP3..0 Packet Types ROWA/ROWP/COL/COLM/COLX ROWA ROWA ROWA COL COL COL/COLM COL/COLM COL/COLM COLM ROWP ROWP ROWP ROWP COLX
Field Description
Description
4-bit operation code that specifies packet format. (Encoded commands are in Table 3 on page 12). Delay the associated row activate command by 0 or 1 tCYCLE . 3-bit bank address for row activate command. 12-bit row address for row activate command. Specifies RD (=0) or WR (=1) command. Delay the column read or write command by 0 or 1 tCYCLE . 3-bit bank address for column read or write command. 6-bit column address for column read or write command. 4-bit sub-column address for dynamic width (see “Dynamic Width Control” on page 50). 8-bit mask for masked-write command WRM. 3-bit operation code that specifies row precharge command with a delay of 0 to 3 tCYCLE. (Encoded commands are in Table 5 on page 13). 3-bit bank address for row precharge command. 3-bit operation code that specifies refresh commands. (Encoded commands are in Table 4 on page 12). 8-bit refresh address field (specifies BR bank address, delay value, and REFr load value 4-bit extended operation code that specifies calibration and powerdown commands. (Encoded commands are in Table 6 on page 13).
Data Sheet E1033E40 (Ver. 4.0) 10
EDX5116ADSE
Figure 3 Request Packet Formats T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..0 DQN15..0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
ACT a0
RD a1
WRM a2
PRE a3
PDN -
ROWA Packet tCYCLE
CFM CFMN
COL Packet tCYCLE
COLM Packet tCYCLE
ROWP Packet tCYCLE
COLX Packet tCYCLE
RQ11 RQ10 RQ9 RQ8 RQ7 RQ6 RQ5 RQ4 RQ3 RQ2 RQ1 RQ0
OP 3 OP 2 R 9 R 10 R 11 rsrv
DEL A R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 rsrv
OP 3 OP 2 OP 1 OP 0 WR X C 8 C 9 rsrv
DEL C rsrv
OP 3 M 3 M 2 M 1 M 0 C 8 C 9 rsrv
M 7 M 6 M 5 M 4 C 7 C 6 C 5 C 4 SC 3 SC 2 SC 1 SC 0
OP 3 OP 2 OP 1 OP 0 POP 1 POP 0 rsrv
POP 2 ROP 2 ROP 1 ROP 0 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
OP 3 OP 2 OP 1 OP 0 rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
C 7 C 6 C 5 C 4 SC 3 SC 2 SC 1 SC 0
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
XOP 3 XOP 2 XOP 1 XOP 0
rsrv
BA 2 BA 1 BA 0
BC 2 BC 1 BC 0
BC 2 BC 1 BC 0
BP 2 BP 1 BP 0
rsrv
rsrv
rsrv
rsrv
Data Sheet E1033E40 (Ver. 4.0) 11
EDX5116ADSE
Request Field Encoding
Operation-code fields are encoded within different packet types to specify commands. Table 3 through Table 6 provides packet type and encoding summaries. Table 3 shows the OP field encoding for the five packet types. The COLM and ROWA packets each specify a single command: ACT and WRM. The COL, COLX, and ROWP packets
Table 3 OP OP [3:0] 0000 0001 Packet COL Command NOP RD WR 0010 0011 COLX ROWP CALy PREx REFy,LRRr 01xx 1xxx ROWA COLM ACT WRM No operation. Column read (WRX=0). Column C9..4 of sense amp in bank BC2..0 is read to DQ bus after (tCAC+DELC)*tCYCLE. Column write (WRX=1). Write DQ bus to column C9..4 of sense amp in bank BC2..0 after (tCWD+DELC)*tCYCLE XOP3..0 specifies a calibrate or powerdown command — see Table 6 on page 13. POP2..0 specifies a row precharge command — see Table 5 on page 13. ROP2..0 specifies a row refresh command or load REFr register command — see Table 4 on page 12. Row activate command. Row R11..0 of bank BA2..0 is placed into the sense amp of the bank after DELA*tCYCLE. Column write command (masked) — mask M7..0 specifies which bytes are written.
each use additional fields to specify multiple commands: WRX, XOP, and POP/ROP, respectively. The COLM packet specifies the masked write command WRM. This is like the WR unmasked write command, except that a mask field M7..0 indicates whether each byte of the write data packet is written or not written. The ROWA packet specifies the row activate command ACT. The COL packet uses the WRX field to specify the column read and column write (unmasked) commands.
Field Encoding Summary
Description
Encoding of the ROP field in the ROWP packet is shown in Table 4. The first encoding specifies a NOPR (no operation) command. The REFP command uses the RA field to select a bank to be precharged. The REFA and REFI commands use the RA field and REFH/M/L registers to select a bank and
Table 4 ROP ROP[2:0] 000 001 Command NOPR REFP No operation
row to be activated for refresh. The REFI command also increments the REFH/M/L register. The REFP, REFA, and REFI commands may also be delayed by up to 3*tCYCLE using the RA[7:6] field. The LRR0, LRR1, and LRR2 commands load the REFH/M/L registers from the RA[7:0] field.
Field Encoding Summary
Description
Refresh precharge command. Bank RA2..0 is precharged. This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]). Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp. This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]). Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp. This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]). R[11:0] field of REFH/M/L register is incremented after the activate command has completed. Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field. Load Refresh Middle Row register (REFM). RA[3:0] is stored in R[11:8] field. Load Refresh High Row register — not used with this device. Reserved
010
REFA
011
REFI
100 101 110 111
LRR0 LRR1 LRR2 -
The REFH/M/L registers are also referred to as the REFr reg-
isters. Note that only the bits that are needed for specifying the
Data Sheet E1033E40 (Ver. 4.0) 12
EDX5116ADSE
refresh row (12 bits in all) are implemented in the REFr registers — the rest are reserved. Note also that the RA2..0 field that specifies the refresh bank address is also referred to as BR2..0. See “Refresh Transactions” on page 40. Table 5 shows the POP field encoding in the ROWP packet. The first encoding specifies a NOPP (no operation) command.
Table 5 POP POP [2:0] 000 001 010 011 100 101 110 111 Command NOPP PRE0 PRE1 PRE2 PRE3 No operation. Reserved. Reserved. Reserved. Row precharge command — Bank BP2..0 is precharged. This command is delayed by 0*tCYCLE. Row precharge command — Bank BP2..0 is precharged. This command is delayed by 1*tCYCLE. Row precharge command — Bank BP2..0 is precharged. This command is delayed by 2*tCYCLE. Row precharge command — Bank BP2..0 is precharged. This command is delayed by 3*tCYCLE.
There are four variations of PRE (precharge) command. Each uses the BP field to specify the bank to be precharged. Each also specifies a different delay of up to 3*tCYCLE using the POP[1:0] field. A precharge command may be specified in addition to a refresh command using the ROP field.
Field Encoding Summary
Description
Table 6 shows the XOP field encoding in the COLX packet. This field encodes the remaining commands. The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See “CalibraTable 6 XOP XOP [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Command Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Command and Description
tion Transactions” on page 42. The PDN command causes the device to enter a power-down state. See “Power State Management” on page 44.
Field Encoding Summary
XOP [3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Command CALC CALZ CALE PDN Command and Description Current calibration command. Impedance calibration command. End calibration command (CALC). Reserved. Enter powerdown power state. Reserved. Reserved. Reserved.
Data Sheet E1033E40 (Ver. 4.0) 13
EDX5116ADSE
Request Packet Interactions
A summary of request packet interactions is shown in Table 7. Each case is limited to request packets with commands that perform memory operations (including refresh commands). This includes all commands in ROWA, ROWP, COL, and COLM packets. The commands in COLX packets are described in later sections. See “Maintenance Operations” on page 40. Request packet/command “a” is followed by request packet/ command “b”. The minimum possible spacing between these two packet/commands is 0*tCYCLE. However, a larger time interval may be needed because of a resource interaction between the two packet/commands. If the minimum possible spacing is 0*tCYCLE, then an entry of “No limit” is shown in the table. Note that the spacing values shown in the table are relative to the effective beginning of a packet/command. The use of the delay field with a command will delay the position of the effective packet/command from the position of the actual packet/ command. See “Dynamic Request Scheduling” on page 20.
Table 7 Packet
Any of the packet/command encodings under one of the four operation types is equivalent in terms of the resource constraints. Therefore, both the horizontal columns (packet “a”) and vertical rows (packet “b”) of the interaction table are divided into four major groups. The four possible operation types for request packets a and b include: ; [A] Activate Row • • • ; ; [R] Read Column [W] Write Column • • • ; [P] Precharge Row • • ROWA/ACT ROWP/REFA ROWP/REFI COL/RD COL/WR COLM/WRM ROWP/PRE ROWP/REFP
Interaction Summary
Second packet/command to bank Bb
Activate Row [A] ROWA - ACT Bb ROWP - REFA Bb ROWP - REFI Bb Case AAd: tRR Case AAs: tRC
Read Column [R] COL - RD Bb
Write Column [W] COL - WR Bb COLM - WRM Bb Case AWd: No limit Case AWs: tRCD-W
Precharge Row [P] ROWP - PRE Bb ROWP - REFP Bb Case APd: No limit Case APs: tRAS
First packet/command to bank Ba
Activate Row [A] ROWA - ACT Ba ROWP - REFA Ba ROWP - REFI Ba Read Column [R] COL - RD Ba Write Column [W] COL - WR Ba COLM - WRM Ba Precharge Row [P] ROWP - PRE Ba ROWP - REFP Ba See Examples: Ba,Bb different Ba,Bb same
Case ARd: No limit Case ARs: tRCD-R
Ba,Bb different Ba,Bb same Ba,Bb different Ba,Bb same Ba,Bb different Ba,Bb same
Case RAd: No limit Case RAs:b tRDP+tRP Case WAd: No limit Case WAsb: tWRP+tRP Case PAd: No limit Case PAs: tRP Figure 4
Case RRd: tCC Case RRs: tCC Case WRdc t∆WR Case WRs:c t∆WR Case PRd: No limit Case PRs:d tRP+tRCD-R Figure 5
Case RWd:a t∆RW Case RWs: a t∆RW Case WWd: tCC Case WWs: tCC Case PWd: No limit Case PWs:d tRP+tRCD-W Figure 6
Case RPd: No limit Case RPs: tRDP Case WPd: No limit Case WPs: tWRP Case PPd: tPP Case PPs: tRC Figure 7
a. t∆RW is equal to tCC + tRW-BUB,XDRDRAM+ tCAC - tCWD and is defined in Table 17. This also depends upon propagation delay - See “Propagation Delay” on page 28. b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands. c. t∆WR is defined in Table 17. d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.
Data Sheet E1033E40 (Ver. 4.0) 14
EDX5116ADSE
The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the same, or they may be different. These two subcases for each interaction are shown along the vertical axis on the left. There are 32 possible interaction cases altogether. The table gives each case a label of the form “xyz”, where “x” and “y” are one of the four operation types (“A” for Activate, “R” for Read, “W” for Write, or “P” for Precharge) for the first and second request, respectively, and “z” indicates the same bank (“s”) or different bank (“d”). Along the horizontal axis at the bottom of the table are cross references to four figures (Figure 4 through Figure 7). Each figure illustrates the eight cases in the corresponding vertical column. Thus, Figure 4 shows the eight cases when the second request is an activate operation (“A”). In the following discussion of the cases, only those in which the interaction interval is greater than tCYCLE will be described. minimum interval between two read operations. The interaction interval for the WRd and WRs cases is t∆WR. This is the write-to-read time parameter and represents the minimum interval between a write and a read operation to any banks. See “Read/Write Interaction” on page 28. The interaction interval for the PRs case is tRP+ tRCD-R. An activate operation must be inserted between the precharge and the read operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval between an activate and read operation to a bank is tRCD-R. In Figure 6, the interaction interval for the AWs case is tRCD-W. This is the row-to-column-write timing parameter and represents the minimum interval between an activate operation and a write operation to a bank. The interaction interval for the RWd and RWs cases is t∆RW . This is the read-to-write time parameter and represents the minimum interval between a read and a write operation to any banks. See “Read/Write Interaction” on page 28. The interaction interval for the WWd and WWs cases is tCC. This is the column-to-column time parameter and represents the minimum interval between two write operations. The interaction interval for the PWs case is tRP + tRCD-W . An activate operation must be inserted between the precharge and the write operation. The minimum interval between a precharge and an activate operation to a bank is tRP . The minimum interval between an activate and a write operation to a bank is tRCD-W . In Figure 7, the interaction interval for the APs case is tRAS . This parameter is the minimum activate-to-precharge time to a bank. The interaction intervals for the RPs and WPs cases are tRDP and tWDP, respectively. These are the read- or write-to-precharge time parameters to a bank. The interaction interval for the PPd case is tPP . This parameter is the precharge-to-precharge time and the minimum interval between precharge commands to different banks of a device. The interaction interval for the PPs case is tRC. This is the row cycle time parameter and the minimum interval between precharge commands to same banks of a device. An activate operation must be inserted between the two activate operations. This activate operation must be placed a time tRP after the first, and a time tRAS before the second precharge.
Request Interaction Cases
In Figure 4, the interaction interval for the AAd case is tRR . This parameter is the row-to-row time and is the minimum interval between activate commands to different banks of a device. The interaction interval for the AAs case is tRC . This is the row cycle time parameter and is the minimum interval between activate commands to same banks of a device. A precharge operation must be inserted between the two activate operations. The interaction interval for the RAs case is tRDP + tRP . A precharge operation must be inserted between the read and activate operation. The minimum interval between a read and a precharge operation to a bank is tRDP . The minimum interval between a precharge and an activate operation to a bank is tRP . The interaction interval for the WAs case is tWDP + tRP . A precharge operation must be inserted between the read and the activate operation.The minimum interval between a write and a precharge operation to a bank is tWDP. The minimum interval between a precharge and an activate operation to a bank is tRP . The interaction interval for the PAs case is tRP . The minimum interval between a precharge and an activate operation to a bank is tRP . In Figure 5, the interaction interval for the ARs case is tRCD-R. This is the row-to-column-read time parameter and represents the minimum interval between an activate operation and a read operation to a bank. The interaction interval for the RRd and RRs cases is tCC . This is the column-to-column time parameter and represents the
Data Sheet E1033E40 (Ver. 4.0) 15
EDX5116ADSE
Figure 4 ACT-, RD-, WR-, PRE-to-ACT Packet Interactions T0 CFM CFM CFMN CFMN RQ11..0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
ACT a
tRR
ACT b
ACT a
tRAS tRC
PRE a
tRP
ACT b
DQ15..0 DQ15..0 DQN15..0 DQN15..0 AAd Case (activate-activate-different bank) a: ROWA Packet with ACT,Ba,Ra Ba = Bb / b: ROWA Packet with ACT,Bb,Rb AAs Case (activate-activate-same bank) a: ROWA Packet with ACT,Ba,Ra Ba = Bb b: ROWA Packet with ACT,Bb,Rb
T0 CFM CFM CFMN CFMN RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
RD ACT a b
RD a
tRDP
PRE a
tRP tRDP+tRP
ACT b
DQ15..0 DQ15..0 No DQN15..0 DQN15..0
limit
RAd Case (read-activate-different bank) a: COL Packet with RD,Ba,Ca b: ROWA Packet with ACT,Bb,Rb
Ba = Bb /
RAs Case (read-activate-same bank) a: COL Packet with RD,Ba,Ca b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM CFM CFMN CFMN
RQ11..0 RQ11..0
WR ACT a b WR a
tWRP tWRP+tRP
PRE a
tRP
ACT b
DQ15..0 No DQ15..0 DQN15..0 DQN15..0
limit
WAd Case (write-activate-different bank) a: COL Packet with WR,Ba,Ca Ba = Bb / b: ROWA Packet with ACT,Bb,Rb
WAs Case (write-activate-same bank) a: COL Packet with WR,Ba,Ca b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM CFM CFMN CFMN
RQ11..0 RQ11..0
PRE ACT a b PRE a
tRP
ACT b
DQ15..0 DQ15..0 DQN15..0 DQN15..0
No limit
PAd Case (precharge-activate-different bank) a: ROWP Packet with PRE,Ba Ba = Bb / b: ROWA Packet with ACT,Bb,Rb
PAs Case (precharge-activate-same bank) a: ROWP Packet with PRE,Ba Ba = Bb b: ROWA Packet with ACT,Bb,Rb
Data Sheet E1033E40 (Ver. 4.0) 16
EDX5116ADSE
Figure 5 CFM CFMN CFM ACT-, RD-, WR-, PRE-to-RD Packet Interactions T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFMN
RQ11..0
RQ11..0
DQ15..0 DQN15..0 DQ15..0
ACT RD a b
ACT a
tRCD-R
RD b
No limit
DQN15..0
ARd Case (activate-read different bank) a: ROWA Packet with ACT,Ba,Ra / Ba = Bb b: COL Packet with RD,Bb,Cb ARs Case (activate-read same bank) a: ROWA Packet with ACT,Ba,Ra b: COL Packet with RD,Bb,Cb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
RD a
tCC
RD b
RD a
tCC
RD b
DQ15..0 DQ15..0 DQN15..0 DQN15..0 RRd Case (read-read different bank) a: COL Packet with RD,Ba,Ca b: COL Packet with RD,Bb,Cb RRs Case (read-read same bank) a: COL Packet with RD,Ba,Ca b: COL Packet with RD,Bb,Cb
/ Ba = Bb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..0 DQ15..0 DQN15..0 DQN15..0
WR a
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t∆WR
RD b
WR a
t∆WR
RD b
WRd Case (write-read different bank) a: COL Packet with WR,Ba,Ca b: COL Packet with RD,Bb,Cb
Ba = Bb /
WRs Case (write-read same bank) a: COL Packet with WR,Ba,Ca b: COL Packet with RD,Bb,Cb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
PRE RD a b
PRE a
tRP tRP+tRCD-R
ACT B
tRCD-R
RD b
DQ15..0 DQ15..0 No DQN15..0 DQN15..0
limit
PRd Case (precharge-read different bank) a: ROWP Packet with PRE,Ba Ba = Bb / b: COL Packet with RD,Bb,Cb
PRs Case (precharge-read same bank) a: ROWP Packet with PRE,Ba Ba = Bb b: COL Packet with RD,Bb,Cb
Data Sheet E1033E40 (Ver. 4.0) 17
EDX5116ADSE
Figure 6 ACT-, RD-, WR-, PRE-to-WR Packet Interactions T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0
ACT WR a b ACT WR a b
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
DQ15..0 DQ15..0 No limit DQN15..0 DQN15..0 AWd Case (activate-write different bank) a: ROWA Packet with ACT,Ba,Ra / Ba = Bb b: COL Packet with WR,Bb,Cb
tRCD-W
AWs Case (activate-write same bank) a: ROWA Packet with ACT,Ba,Ra b: COL Packet with WR,Bb,Cb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..D0 DQ15..0 DQN15..0 DQN15..0
RD a
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t∆RW
WR b
tCWD
Q(a) D(b)
RD a
t∆RW
WR b
tCWD
Q(a) D(b)
tCAC
tCAC
RWs Case (read-write-same bank) a: COL Packet with RD,Ba,Ca b: COL Packet with WR,Bb,Cb
RWd Case (read-write-different bank) a: COL Packet with RD,Ba,Ca b: COL Packet with WR,Bb,Cb
tCC tCYCLE
/ Ba = Bb
tCC tCYCLE
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..0 DQ15..0 DQN15..0 DQN15..0
WR a
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCC
WR b
WR a
tCC
WR b
WWd Case (write-write different bank) a: COL Packet with WR,Ba,Ca b: COL Packet with WR,Bb,Cb
/ Ba = Bb
WWs Case (write-write same bank) a: COP Packet with WR,Ba,Ca b: COL Packet with WR,Bb,Cb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRCD-W
PRE WR a b PRE a
tRP tRP+tRCD-W
ACT WR B b
DQ15..0 DQ15..0 No limit DQN15..0 DQN15..0 PWd Case (precharge-write different bank) a: ROWP Packet with PRR,Ba / Ba = Bb b: COL Packet with WR,Bb,Cb PWs Case (precharge-write same bank) a: ROWP Packet with PRE,Ba Ba = Bb b: COP Packet with WR,Bb,Cb
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EDX5116ADSE
Figure 7 ACT-, RD, WR-, PRE-to-PRE Packet Interactions T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0
ACT PRE a b ACT a
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRAS
PRE b
DQ15..0 DQ15..0 No limit DQN15..0 DQN15..0 APd Case (activate-precharge different bank) a: ROWA Packet with ACT,Ba,Ra Ba # Bb b: ROWP Packet with PRE,Bb APs Case (activate-precharge same bank) a: ROWA Packet with ACT,Ba,Ra Ba = Bb b: ROWP Packet with PRR,Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RD PRE a b
RD a
tRDP
PRE b
DQ15..0 DQ15..0 No limit DQN15..0 DQN15..0 RPd Case (read-precharge different bank) a: COL Packet with RD,Ba,Ca Ba # Bb b: ROWP Packet with PRE,Bb RPs Case (read-precharge same bank) a: COL Packet with RD,Ba,Ca b: ROWP Packet with PRR,Bb
Ba = Bb
T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR PRE a b
WR a
tWRP
PRE b
DQ15..0 DQ15..0 No limit DQN15..0 DQN15..0 WPd Case (write-precharge different bank) a: COL Packet with WR,Ba,Ca Ba # Bb b: ROWP Packet with PRE,Bb WPs Case (write-precharge same bank) a: COL Packet with WR,Ba,Ca Ba = Bb b: ROWP Packet with PRE,Bb
T0 CFM CFM CFMN CFMN RQ11..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
PRE a
tPP
PRE b
PRE a
tRP
ACT b
tRAS tRC
PRE b
DQ15..0 DQ15..0 DQN15..0 DQN15..0 PPd Case (precharge-precharge different bank) a: ROWP Packet with PRE,Ba Ba # Bb b: ROWP Packet with PRE,Bb PPs Case (precharge-precharge same bank) a: ROWP Packet with PRE,Ba Ba = Bb b: ROWP Packet with PRE,Bb
Data Sheet E1033E40 (Ver. 4.0) 19
EDX5116ADSE
Dynamic Request Scheduling
Delay fields are present in the ROWA, COL, and ROWP packets. They permit the associated command to optionally wait for a time of one (or more) tCYCLE before taking effect. This allows a memory controller more scheduling flexibility when issuing request packets. Figure 8 illustrates the use of the delay fields. In the first timing diagram, a ROWA packet with an ACT command is present at cycle T0. The DELA field is set to “1”. This request packet will be equivalent to a ROWA packet with an ACT command at cycle T1 with the DELA field is set to “0”. This equivalence should be used when analyzing request packet interactions. In the second timing diagram, a COL packet with a RD command is present at cycle T0. The DELC field is set to “1”. This request packet will be equivalent to a COL packet with an RD command at cycle T1 with the DELC field is set to “0”. This equivalence should be used when analyzing request packet interactions. In a similar fashion, a COL packet with a WR command is present at cycle T12. The DELC field is set to “1”. This request packet will be equivalent to a COL packet with a WR command at cycle T13 with the DELC field is set to “0”. This equivalence should be used when analyzing request packet interactions. In the COL packet with a RD command example, the read data delay TCAC is measured between the Q read data packet and the virtual COL packet at cycle T1. Likewise, for the example with the COL packet with a WR command, the write data delay TCWD is measured between the D write data packet and the virtual COL packet at cycle T13. In the third timing diagram, a ROWP packet with a PRE command is present at cycle T0. The DEL field (POP[1:0]) is set to “11”. This request packet will be equivalent to a ROWP packet with a PRE command at cycle T1 with the DEL field is set to “10”, it will be equivalent to a ROWP packet with a PRE command at cycle T2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet with a PRE command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet interactions. In the fourth timing diagram, a ROWP packet with a REFP command is present at cycle T0. The DEL field (RA[7:6]) is set to “11”. This request packet will be equivalent to a ROWP packet with a REFP command at cycle T1 with the DEL field is set to “10”, it will be equivalent to a ROWP packet with a REFP command at cycle T2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet with a REFP command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet interactions. The two examples for the REFA and REFI commands are identical to the example just described for the REFP command. The ROWP packet allows two independent operations to be specified. A PRE precharge command uses the POP and BP fields, and the REFP, REFA, or REFI commands uses the ROP and RA fields. Both operations have an optional delay field (the POP field for the PRE command and the RA field with the REFP, REFA, or REFI commands). The two delay mechanisms are independent of one another. The POP field does not affect the timing of the REFP, REFA, or REFI commands, and the RA field does not affect the timing of the PRE command. When the interactions of a ROWP packet are analyzed, it must be remembered that there are two independent commands specified, both of which may affect how soon the next request packet can be issued. The constraints from both commands in a ROWP packet must be considered, and the one that requires the longer time interval to the next request packet must be used by the memory controller. Furthermore, the two commands within a ROWP packet may not reference the same bank in the BP and RA fields.
Data Sheet E1033E40 (Ver. 4.0) 20
EDX5116ADSE
Figure 8 Request Scheduling Examples ACT w/DEL=1 at T0 is equivalent to ACT w/DEL=0 at T1 T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 Note
ACT ACT DEL1 DEL0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
DEL value is specified by DELA field.
RD w/DEL=1 at T0 is equivalent to RD w/DEL=0 at T1 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WR w/DEL=1 at T12 is equivalent to WR w/DEL=0 at T13
ROWA/ACT Command
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM CFMN RQ11..0 DQ15..0 DQN15..0 Note
RD RD DEL1 DEL0 WR WR DEL1 DEL0
tCYCLE
D
tCAC
Q
tCWD
DEL value is specified by DELC field.
PRE w/DEL=3 at T0 is equivalent to PRE w/DEL =2 at T1 or PRE w/DEL=1 at T2 or PRE w/DEL=0 at T3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
COL/RD and COL/WR Commands
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM CFMN RQ11..0 DQ15..0 DQN15..0 Note
PRE PRE PRE PRE DEL3 DEL2 DEL1 DEL0
tCYCLE
DEL value is specified by {POP1, POP0} field.
ROWP/PRE Command
REFP w/DEL=3 at T0 is equivalent to REFP w/DEL=2 at T1 or REFP w/DEL=1 at T2 or REFP w/DEL=0 at T3 T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 Note
REFP REFP REFP REFP DEL3 DEL2 DEL1 DEL0 REFA REFA REFA REFA DEL3 DEL2 DEL1 DEL0
REFI w/DEL=3 at T13 is equivalent to REFI w/DEL=2 at T14 or REFI w/DEL=1 at T15 or REFI w/DEL=0 at T16 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
T1
T2
T3
T4
T5
T6
T7
T8
T9
REFI REFI REFI REFI DEL3 DEL2 DEL1 DEL0
tCYCLE
REFA w/DEL=3 at T6 is equivalent to REFA w/DEL=2 at T7 or REFA w/DEL=1 at T8 or REFA w/DEL=0 at T9
DEL value is specified by {RA7, RA6} field.
ROWP/REFP,REFA,REFI Commands
Data Sheet E1033E40 (Ver. 4.0) 21
EDX5116ADSE
Memory Operations
Write Transactions
Figure 9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how many request packets are needed to perform the access. The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba. In this case, write data may be directly written into the sense amp array for the bank, and row operations (activate or precharge) are not needed. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T0, and a second COL packet with WR command to column Ca2 of bank Ba is presented on edge T2. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of the row already sensed (a page miss). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row other than Ra. In this case, write data may be not be directly written into the sense amp array for the bank. It is necessary to close the present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T7 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on edge T9. Two write
data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba. In this case, write data may be not be directly written into the sense amp array for the bank. It is necessary to access the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T1 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on edge T3. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. After the final write command, it may be necessary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T13 a time tWRP after the last COL packet with a WR command. The decision whether to close the bank or leave it open is made by the memory controller and its page policy. The fourth timing diagram shows another example of a pageempty write transaction. This is similar to the previous example except that only a single write command is presented, rather than two write commands. This example shows that even with a minimum length write transaction, the tRAS parameter will not be a constraint. The tRAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is also constrained by the sum tRCDW+tWRP which will be larger for a write transaction. These two constraints ( tRAS and tRCD-W+tWRP) will be a function of the memory device’s speed bin and the data transfer length (the number of write commands issued between the activate and precharge commands), and the tRAS parameter could become a constraint for write transactions for future speed bins. In this example, the sum tRCD-W+tWRP is greater than tRAS by the amount ∆tRAS.
Data Sheet E1033E40 (Ver. 4.0) 22
EDX5116ADSE
Figure 9 Write Transactions T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
WR a1 WR a2
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
D(a1) D(a2)
tCC tCWD
Page-hit Write Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
PRE a3
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
ACT WR a0 a1
WR a2
tCYCLE
D(a1) D(a2)
tRP
tRCD-W
tCC tCWD
a0 = {Ba,Ra}
Transaction a: WR
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Write Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
ACT WR a0 a1
WR a2
tCWD tWRP
D(a1) D(a2)
tDP
PRE a3
tCYCLE
tRCD-W
tCC tCWD
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Write Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
ACT WR a0 a1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRAS tWRP tCWD
D(a1)
∆tRAS
PRE a3
tRP
ACT b0
tCYCLE
tRCD-W
Bb = Ba
Transaction a: WR Transaction b: WR
a0 = {Ba,Ra} b0 = {Bb,Rb}
a1 = {Ba,Ca1} b1 = {Bb,Cb1}
a2 = {Ba,Ca2} b2 = {Bb,Cb2}
a3 = {Ba} b3 = {Bb}
Page-empty Write Example - Core Limited
Data Sheet E1033E40 (Ver. 4.0) 23
EDX5116ADSE
Read Transactions
Figure 10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how many request packets are needed to perform the access. The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba. In this case, read data may be directly read from the sense amp array for the bank, and no row operations (activate or precharge) are needed. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T0, and a second COL packet with RD command to column Ca2 of bank Ba is presented on edge T2. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of the row already sensed (a page miss). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row other than Ra. In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0. An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T11 a time tRCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on edge T13. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba. In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T5 a time tRCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on edge T7. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay tCAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. After the final read command, it may be necessary to close the present row (precharge). A precharge command — PRE to bank Ba — is presented on edge T10 a time tRDP after the last COL packet with a RD command. Whether the bank is closed or left open depends on the memory controller and its page policy. The fourth timing diagram shows another example of a pageempty read transaction. This is similar to the previous example except that it uses one read command instead of two read commands. In this case, the core parameter tRAS may also be a constraint upon when the precharge command may be issued. The tRAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is also constrained by the sum tRCD-R+ tRDP and must be set to whichever is larger. These two constraints (tRAS and tRCD-R+ tRDP) will be a function of the memory device’s speed bin and the data transfer length (the number of read commands issued between the activate and precharge commands). In this example, the tRAS is greater than the sum tRCD-R+ tRDP by the amount ∆tRDP.
Data Sheet E1033E40 (Ver. 4.0) 24
EDX5116ADSE
Figure 10 Read Transactions T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
RD a1 RD a2
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
Q(a1) Q(a2)
tCC tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-hit Read Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
PRE a3 ACT a0 RD a1 RD a2
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
Q(a1) Q(a2)
tRP
tRCD-R
tCC tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Read Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
ACT a0 RD a1 RD a2 PRE a3
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
Q(a1) Q(a2)
tRCD-R
tCC
tRDP
tCAC
Transaction a: RD a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Read Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
ACT a0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRAS tRCD-R
RD a1
tRDP
∆tRDP tCAC
PRE a3
tRP
ACT b0
tCYCLE
Q(a1)
Bb = Ba
Transaction a: RD Transaction b: RD
a0 = {Ba,Ra} b0 = {Bb,Rb}
a1 = {Ba,Ca1} b1 = {Bb,Cb1}
a2 = {Ba,Ca2} b2 = {Bb,Cb2}
a3 = {Ba} b3 = {Bb}
Page-empty Read Example - Core Limited
Data Sheet E1033E40 (Ver. 4.0) 25
EDX5116ADSE
Interleaved Transactions
Figure 11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transaction is started before an earlier one is completed. The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty access; that is, a bank is in a closed state prior to an access, and is precharged after the access. With this assumption, each transaction requires the same number of request packets at the same relative positions. If banks were allowed to be in an open state, then each transaction would require a different number of request packets depending upon whether the transaction was page-empty, page-hit, or page-miss. This situation is more complicated for the memory controller, and will not be analyzed in this document. In the interleaved page-empty write example, there are four sets of request pins RQ11..0 shown along the left side of the timing diagram. The first three show the timing slots used by each of the three request packet types (ACT, COL, and PRE), and the fourth set (ALL) shows the previous three merged together. This allows the pattern used for allocating request slots for the different packets to be seen more clearly. The slots at {T0, T4, T8, T12, ...} are used for ROWA packets with ACT commands. This spacing is determined by the tRR parameter. There should not be interference between the interleaved transactions due to resource conflicts because each bank address — Ba, Bb, Bc, Bd, and Be — is assumed to be different from another. If two of the bank addresses are the same, the later transaction would need to wait until the earlier transaction had completed its precharge operation. Five different banks are needed because the effective tRC (tRC+∆tRC) is 20*tCYCLE. The slots at {T1, T3, T5 , T7 , T9 , T11 , ...} are used for COL packets with WR commands. This frequency of the COL packet spacing is determined by the tCC parameter and by the fact that there are two column accesses per row access. The phasing of the COL packet spacing is determined by the tRCDW parameter. If the value of tRCD-W required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the COL packet one tCYCLE earlier. The DQ bus slots at {T4, T6, T8, T10, ...} carry the write data packets {D(a1), D(a2), D(b1), D(b2), ....}. Two write data packets are written to a bank in each transaction. The DQ bus is completely filled with write data; no idle cycles need to be introduced because there are no resource conflicts in this example. The slots at {T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet spacing is determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tWRP parameter. If the value of tWRP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs earlier. There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets of request pins RQ11..0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different packets to be seen more clearly. The slots at {T0, T4, T8, T12, ...} are used for ROWA packets with ACT commands. This spacing is determined by the tRR parameter. There should not be interference between the interleaved transactions due to resource conflicts because each bank address — Ba, Bb, Bc, and Bd — is assumed to be different from another. Four different banks are needed because the effective tRC is 16*tCYCLE. The slots at {T5, T7, T9, T11, ...} are used for COL packets with RD commands. This frequency of the COL packet spacing is determined by the tCC parameter and by the fact that there are two column accesses per row access. The phasing of the COL packet spacing is determined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the packet one tCYCLE earlier. The DQ bus slots at {T11, T13, T15, T17, ...} carry the read data packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}. Two read data packets are read from a bank in each transaction. The DQ bus is completely filled with read data — that is, no idle cycles need to be introduced because there are no resource conflicts in this example. The slots at {T10, T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of the ROWP packet spacing is determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tRDP parameter. If the value of tRDP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs earlier.
Data Sheet E1033E40 (Ver. 4.0) 26
EDX5116ADSE
Figure 11 Interleaved Transactions The effective tRC time is increased by 4 tCYCLE T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
T0 CFM CFMN RQ11..0 (ACT) RQ11..0 (COL)
ACT a0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tRR
WR a1 WR a2
ACT b0 WR b1
tRC
WR b2
ACT c0 WR c1 WR c2
ACT d0 WR d1 WR d2
ACT e0
∆tRC
WR e1 WR e2
ACT f0 WR f1
tCYCLE
WR f2
DQ15..0 tRCD-W DQN15..0 RQ11..0 (PRE) RQ11..0 (ALL)
ACT WR a0 a1
tCC
D(a1) D(a2) D(b1) D(b2) D(c1) D(c2) PRE a3 D(d1) D(d2) PRE b3 D(e1) D(e1) PRE c3
tCWD
WR ACT WR a2 b0 b1
tWRP
WR ACT WR b2 c0 c1
∆tWRP
tRP
WR ACT WR PRE WR ACT WR PRE WR ACT WR PRE WR f1 f2 c2 d0 d1 a3 d2 e0 e1 b3 e2 f0 c3
Ba,Bb,Bc,Bd,Be are different banks. Bf = Ba
Transaction a: WR Transaction b: WR Transaction c: WR Transaction d: WR Transaction e: WR Transaction f: WR
a0 = {Ba,Ra} b0 = {Bb,Rb} c0 = {Bc,Rc} d0 = {Bd,Rd} e0 = {Be,Re} f0 = {Bf,Rf}
a1 = {Ba,Ca1} b1 = {Bb,Cb1} c1 = {Bc,Cc1} d1 = {Bd,Cd1} e1 = {Be,Ce1} f1 = {Bf,Cf1}
a2 = {Ba,Ca2} b2 = {Bb,Cb2} c2 = {Bc,Cc2} d2 = {Bd,Cd2} e2 = {Be,Ce2} f2 = {Bf,Cf2}
a3 = {Ba} b3 = {Bb} c3 = {Bc} d3 = {Bd} e3 = {Be} f3 = {Bf}
Interleaved Page-empty Write Example
T0 CFM CFMN RQ11..0 (ACT) RQ11..0 (COL) DQ15..0 DQN15..0 RQ11..0 (PRE) RQ11..0 (ALL)
ACT a0 ACT a0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
ACT b0
tRC
RD a1 RD a2
ACT c0 RD b1 RD b2
ACT d0 RD c1 RD c2
ACT e0 RD d1 RD d2
ACT f0 RD e1
tCYCLE
RD e2
tRR tRCD-R
tCAC
Q(a1) Q(a2) Q(b1) Q(b2) PRE c3 Q(c1) Q(c2) PRE d3
tCC
ACT RD b0 a1
tRDP
PRE a3
tRP
PRE b3
RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD a2 c0 b1 a3 b2 d0 c1 b3 c2 e0 d1 c3 d2 f0 e1 d3 e2
Ba,Bb,Bc,Bd are different banks. Be = Ba
Transaction a: RD Transaction b: RD Transaction c: RD Transaction d: RD Transaction e: RD
a0 = {Ba,Ra} b0 = {Bb,Rb} c0 = {Bc,Rc} d0 = {Bd,Rd} e0 = {Be,Re}
a1 = {Ba,Ca1} b1 = {Bb,Cb1} c1 = {Bc,Cc1} d1 = {Bd,Cd1} e1 = {Be,Ce1}
a2 = {Ba,Ca2} b2 = {Bb,Cb2} c2 = {Bc,Cc2} d2 = {Bd,Cd2} e2 = {Be,Ce2}
a3 = {Ba} b3 = {Bb} c3 = {Bc} d3 = {Bd} e3 = {Be}
Interleaved Page-empty Read Example
Data Sheet E1033E40 (Ver. 4.0) 27
EDX5116ADSE
Read/Write Interaction
The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will describe the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts. Figure 12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two COL packets with WR commands are presented on cycles T0 and T2. The write data packets are presented a time tCWD later on cycles T3 and T5. The device requires a time t∆WR after the second COL packet with a WR command before a COL packet with a RD command may be presented. Two COL packets with RD commands are presented on cycles T11 and T13. The read data packets are returned a time tCAC later on cycles T17 and T19. The time t∆WR is required for turning around internal bidirectional interconnections (inside the device). This time must be observed regardless of whether the write and read commands are directed to the same bank or different banks. A gap tWR-BUB,XDRDRAM will appear on the DQ bus between the end of the D(a2) packet and the beginning of the Q(b1) packet (measured at the appropriate packet reference points). The size of this gap can be evaluated by calculating the difference between cycles T2 and T17 using the two timing paths: tWR-BUB,XDRDRAM ≤ t∆WR + tCAC - tCWD - tCC In this example, the value of tWR-BUB,XDRDRAM is greater than its minimum value of tWR-BUB,XDRDRAM,MIN. The values of t∆WR and tCAC are equal to their minimum values. In the second case, the timing diagram displayed at the bottom of Figure 12 illustrates a read transaction followed by a write transaction. Two COL packets with RD commands are presented on cycles T0 and T2. The read data packets are returned a time tCAC later on cycles T6 and T8. The device requires a time t∆RW after the second COL packet with a RD command before a COL packet with a WR command may be presented. Two COL packets with WR commands are presented on cycles T10 and T12. The write data packets are presented a time tCWD later on cycles T13 and T15. The time t∆RW is required for turning around the external DQ bidirectional interconnections (outside the device). This time must be observed regardless whether the read and write commands are directed to the same bank or different banks. The time t∆RW depends upon four timing parameters, and may be evaluated by calculating the difference between cycles T2 and T13 using the two timing paths: t∆RW + tCWD = tCAC + tCC + tRW-BUB,XDRDRAM or t∆RW = (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM In this example, the values of t∆RW, tCAC, tCWD, tCC, and tRWBUB,XDRDRAM are equal to their minimum values.
Propagation Delay
Figure 13 shows two timing diagrams that display the systemlevel timing relationships between the memory component and the memory controller. The timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory component. In this case, the timing will be identical to what has already been shown in the previous sections; i.e. with all timing measured at the pins of the memory component. This timing diagram was produced by merging portions of the top and bottom timing diagrams in Figure 12. The example shown is that of a single COL packet with a write command, followed by a single COL packet with a read command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank. A timing interval t∆WR is required between the first WR command and the RD command, and a timing interval t∆RW is required between the RD command and the second WR command. There is a write data delay tCWD between each WR command and the associated write data packet D. There is a read data delay tCAC between the RD command and the associated read data packet Q. In this example, all timing parameters have assumed their minimum values except tWR-BUB,XDRDRAM. The lower timing diagram in the figure shows the case where timing skew is present between the memory controller and the memory component. This skew is the result of the propagation delay of signal wavefronts on the wires carrying the signals. The example in the lower diagram assumes that there is a propagation delay of tPD-RQ along both the RQ wires and the CFM/CFMN clock wires between the memory controller and the memory component (the value of tPD-RQ used here is 1*tCYCLE). Note that in an actual system the tPD-RQ value will be different for each memory component connected to the RQ wires. In addition, it is assumed that there is a propagation delay tPDD along the DQ/DQN wires between the memory controller and the memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay tPD-Q along the DQ/DQN wires between the memory component and the memory controller (the direction in which read data travels). The sum of these two propagation delays is also denoted by the timing parameter tPD,CYC = tPD-D+tPD-Q.
Data Sheet E1033E40 (Ver. 4.0) 28
EDX5116ADSE
Figure 12 Write/Read Interaction
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
WR a1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR a2
tCWD t∆WR
D(a1) D(a2)
tDR
RD b1
RD b2
tCYCLE tCAC
Q(b1) Q(b2)
tCWD
tCC
tWR-BUB,XDRDRAM
Transaction a: WR Transaction b: RD a1 = {Ba,Ca1} b1 = {Bb,Cb1} a2 = {Ba,Ca2} b2 = {Bb,Cb2}
Write/Read Turnaround Example
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
RD a1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RD a2
t∆RW tCAC
Q(a1) Q(a2)
WR b1
WR b2
tCYCLE tCWD
D(b1) D(b2)
tCC
tRW-BUB,XDRDRAM
Transaction a: WR Transaction b: RD a1 = {Ba,Ca1} b1 = {Bb,Cb1} a2 = {Ba,Ca2} b2 = {Bb,Cb2}
Read/Write Turnaround Example
Data Sheet E1033E40 (Ver. 4.0) 29
EDX5116ADSE
As a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are measured at the pins of the memory controller or the pins of the memory component. For example, the CFM/CFMN signals at the pins of the memory component are tPD-RQ later than at the pins of the memory controller. This is shown by the cycle numbering of the CFM/CFMN signals at the two locations — in this example cycle T1 at the memory controller aligns with cycle T0 at the memory component. All the request packets on the RQ wires will have a tPD-RQ skew at the memory component relative to the memory controller in this example. Because the tPD-D propagation delay of write data matches the tPD-RQ propagation delay of the write command, the controller may issue the write data packet D(a0) relative to the COL packet with the first write command “WR a0” with the normal write data delay tCWD. If the propagation delays between the memory controller and memory component were different for the RQ and DQ buses (not shown in this example), the write data delay at the memory controller would need to be adjusted. A propagation delay is seen by the read command — that is, the read command will be delayed by a tPD-RQ skew at the memory component relative to the memory controller. The memory component will return the read data packet Q(b0) relative to this read command with the normal read data delay tCAC (at the pins of the memory component). The read data packet will be skewed by an additional propagation delay of tPD-Q as it travels from the memory component back to the memory controller. The effective read data delay measured between the read command and the read data at the memory controller will be tCAC +tPD-RQ+tPD-Q. The tPD-RQ factor is caused by the propagation delay of the request packets as they travel from memory controller to memory component. The tPD-Q factor is caused by the propagation delay of the read data packets as they travel from memory component to memory controller. All timing parameters will be equal to their minimum values except tWR-BUB,XDRDRAM (as in the top diagram), and the timing parameters tRW-BUB,XDRDRAM and t∆RW. These will be larger than their minimum values by the amount (tPD,CYCtPD,CYC,MIN), where tPD,CYC = tPD-D+tPD-Q. This may be seen by evaluating the two timing paths between cycle T9 at the Controller and cycle T21at the XDR DRAM: t∆RW + tPD-RQ+ tCWD = tPD-RQ+ tCAC + tCC+ tRW-BUB,XDRDRAM or t∆RW= (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM The following relationship was shown for Figure 12 t∆RW ,MIN= (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM,MIN or (t∆RW - t∆RW ,MIN)= (tRW-BUB,XDRDRAM - tRWBUB,XDRDRAM,MIN) In other words, the two timing parameters tRW-BUB,XDRDRAM and t∆RW will change together. The relationship of this change to the propagation delay tPD,CYC (= tPD-D+tPD-Q) can be derived by looking at the two timing paths from T15 to T21 at the XDR DRAM: tPD-Q + tCC + tRW-BUB,XIO+ tPD-D = tCC+ tRW-BUB,XDRDRAM or tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD-D + tPD-Q or tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD,CYC in a system with minimum propagation delays: tRW-BUB,XDRDRAM,MIN = tRW-BUB,XIO + tPD,CYC,MIN and since tRW-BUB,XIO is equal to tRW-BUB,XIO,MIN in both cases, the following is true: (tPD,CYC - tPD,CYC,MIN) = (tRW-BUB,XDRDRAM - tRW-BUB,XDRDRAM,MIN) = (t∆RW - t∆RW ,MIN)= In other words, the values of the tRW-BUB,XDRDRAM,MIN and t∆RW ,MIN timing parameters correspond to the value of tPD,CYC,MIN for the system (this is equal to one tCYCLE). As tPD,CYC is increased from this minimum value, tRWBUB,XDRDRAM and t∆RW increase from their minimum values by an equivalent amount.
Data Sheet E1033E40 (Ver. 4.0) 30
EDX5116ADSE
Figure 13 Propagation Delay
XDR DRAM
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
WR a0 RD b0 WR c0 Q(b0)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE tCWD
D(c0)
t∆WR tCWD
D(a0)
t∆RW tCAC
tCC
tWR-BUB,XDRDRAM
Transaction a: WR Transaction b: RD Transaction c: WR a0 = {Ba,Ca0} b0 = {Bb,Cb0} c0 = {Bc,Cc0}
tCC
tRW-BUB,XDRDRAM
Write-Read-Write at XDR DRAM (portions of top and bottom timing diagrams of Figure 12 merged)
Controller
CFM CFMN RQ11..0 DQ15..0 DQN15..0
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR a0
t∆WR
D(a0)
RD b0
t∆RW
tCC tPD-Q
WR c0
tCYCLE tRW-BUB,XIO
D(c0)
Q(b0)
XDR DRAMT
CFM CFMN RQ11..0 DQ15..0 DQN15..0
-1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
WR a0
tPD-D tCWD
D(a0)
tCYCLE
RD b0
tPD-RQ
WR c0
tPD-D tCWD
tPD-RQ
tPD-RQ
Transaction a: WR Transaction b: RD Transaction c: WR
tCAC
a0 = {Ba,Ca0} b0 = {Bb,Cb0} c0 = {Bc,Cc0}
Q(b0)
tRW-BUB,XDRDRAMD(c0)
tCC
Write-Read-Write at Controller and XDR DRAM w/ tPD-RQ = tPD-Q = tPD-D = 1*tCYCLE
tPD-RQ
RQ
Controller
tPD-D
DQ
RQ DQ
XDR DRAM
Data Sheet E1033E40 (Ver. 4.0) 31
...
tPD-Q
...
EDX5116ADSE
Register Operations
Serial Transactions
The serial interface consists of five pins. This includes RST, SCK, CMD, SDI, and SDO. SDO uses CMOS signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI, and SDO use a timing window which surrounds the falling edge of SCK). The RST pin is used for initialization. Figure 14 and Figure 15 show examples of a serial write transaction and a serial read transaction. Each transaction starts on cycle S4 and requires 32 SCK edges. The next serial transaction can begin on cycle S36. SCK does not need to be asserted if there is no transaction.
used during either serial write transaction.
Serial Read Transaction
The serial device read transaction in Figure 15 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This indicates that the remaining 28 bits constitute a serial transaction. The next two bits are the SCMD[1:0] field. This field contains the serial command, and the bits “10” in the case of a serial device read transaction. The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed. The next eight bits are the SADR[7:0] field and contain the serial address of the control register being accessed. A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn on the SDO output driver. The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin are the SRD[7:0] field. This is the read data that is accessed from the selected control register. Note the output timing convention here: bit SRD[7] is driven from a time tQ,SI,MAX after edge S26 to a time tQ,SI,MIN after edge S27. The bit is sampled in the controller by the edge S27 A final bit “0” is driven on the CMD pin to finish the serial read transaction. A serial forced read is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices preform the register read. This is used for device testing. Figure 16 shows the response of a DRAM to a serial device read transaction when its internal SID[5:0] register field doesn’t match the SID[5:0] field of the transaction. Instead of driving read data from an internal register for cycle edges S27 through S34 on the SDO output pin, it passes the input data from the SDI input pin to the SDO output pin during this same period.
Serial Write Transaction
The serial device write transaction in Figure 14 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This indicates to the XDR DRAM that the remaining 28 bits constitute a serial transaction. The next two bits are the SCMD[1:0] field. This field contains the serial command, the bits 00 in the case of a serial device write transaction. The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed. The next eight bits are the SADR[7:0] field. This field contains the serial address of the control register being accessed. A single bit “0” follows next. This bit allows one cycle for the access time to the control register. The next eight bits on the CMD pin is the SWD[7:0] field. This is the write data that is placed into the selected control register. A final bit “0” is driven on the CMD pin to finish the serial write transaction. A serial broadcast write is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices preform the register write. The SDI and SDO pins are not
Table 8 SCMD SCMD [1:0] 00 01 10 11 Command SDW SBW SDR SFR
Field Encoding Summary
Description
Serial device write — one device is written, the one whose SID[5:0] register matches the SID[5:0] field of the transaction. Serial broadcast write — all devices are written, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field Serial device read — one device is read, the one whose SID[5:0] register matches the SID[5:0] field of the transaction. Serial forced read — all devices are read, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
Data Sheet E1033E40 (Ver. 4.0) 32
EDX5116ADSE
Figure 14 Serial Write Transaction
S0 SCK RST
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
tCYC,SCK
Start
SCMD
transaction
2’h0,SID[5:0]
543 2 1 0 7 6
CMD SDI (input) SDO (output)
SADR[7:0]
543 2 1 0 ‘0’ 7 6
SWD[7:0]
5 432 1 0 ‘0’
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’‘0’ ‘0’
Figure 15
Serial Read Transaction — Selected DRAM
S0 SCK RST
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
tCYC,SCK
Start
SCMD
transaction
2’h0,SID[5:0]
43 2 10 7
CMD SDI (input) SDO (output)
SADR[7:0]
65 43 2
8’h00
1 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
SRD[7:0]
765 43 2 10
Figure 16
Serial Read Transaction — Non-selected DRAM
S0 SCK RST
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48 S28
tCYC,SCK
Start
SCMD
transaction
2’h0,SID[5:0]
43 2 10 7
SDI
8’h00
1 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
CMD SDI (input) SDO (output)
SADR[7:0]
65 43 2
tP,SI SDO combinational propagation from SDI to SDO
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
SRD[7:0]
7 6 5 432 1 0
SRD[7:0]
765 43 2 10
Data Sheet E1033E40 (Ver. 4.0) 33
EDX5116ADSE
Register Summary
Figure 17 through Figure 33 show the control registers in the memory component. The control registers are responsible for configuring the component’s operating mode, for managing power state transitions, for managing refresh, and for managing calibration operations. A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bits must be written as 0 and must be ignored when read. Write-only fields must be ignored when read Each figure displays the following register information: 1. 2. 3. 4. 5. 6. register name register mnemonic register address (SADR[7:0] value needed to access it) read-only, write-only or read-write initialization state description of each defined register field Figure 19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field is written with a 1, the memory component transitions from powerdown to active state. It is usually unnecessary to write a 0 into this field; this is done automatically by the PDN command in a COLX packet. The PST field indicates the current power state of the memory component. Figure 20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial Interface. Figure 23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is read-write and contains the bank address used by self-refresh during the powerdown state. The MBR field controls how many banks are refreshed during each refresh operation. Figure 24, Figure 25, and Figure 26 show different fields of the Refresh Row Register (high, middle, and low). This read-write field contains the row address used by self- and auto-refresh. See “Refresh Transactions” on page 40 for more details. Figure 28 and Figure 29 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and CCVALUE1 fields, respectively. These are read-write fields which control the amount of IOL current driven by the DQ and DQN pins during a read transaction. The Current Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Current Calibration 1 controls the odd-numbered DQ and DQN pins. Figure 32 shows the test registers. It is used during device testing. It is not to be read or written during normal operation. Figure 33 shows the DLY register. This is used to set the value of tCAC and tCWD used by the component. See “Timing Parameters” on page 62
Figure 17 shows the Serial Identification register. This register contains the SID[5:0] (serial identification field). This field contains the serial identification value for the device. The value is compared to the SID[5:0] field of a serial transaction to determine if the serial transaction is directed to this device. The serial identification value is set during the initialization sequence. Figure 18 shows the Configuration Register. It contains two fields. The first is the WIDTH field. This field allows the number of DQ/DQN pins used for memory read and write accesses to be adjusted. The SLE field enables data to be written into the memory through the serial interface using the WDSL register.
Figure 17 7 Serial Identification (SID) Register 6 5 4 3 2 1 0
reserved
SID[5:0]
Serial Identification Register SADR[7:0]: 000000012
Read-only register SID[7:0] resets to 000000002
SID[5:0] - Serial Identification field. This field contains the serial identification value for the device. The value is compared to the SID[5:0] field of a serial transaction to determine if the serial transaction is directed to this device. The serial identification value is set during the initialization sequence.
Data Sheet E1033E40 (Ver. 4.0) 34
EDX5116ADSE
Figure 18 7 Configuration (CFG) Register 6 5 4 3 2 1 0
rsrv
rsrv SLE rsrv
WIDTH[2:0]
Configuration Register SADR[7:0]: 000000102
Read/write register CFG[7:0] resets to 000001002
WIDTH[2:0] - Device interface width field. 0002 - Reserved. 0012 - Reserved. 0102 - x4 device width 0112 - x8 device width 1002 - x16 device width 1012, 1102, 1112 - Reserved SLE - Serial Load enable field. 02 - WDSL-path-to-memory disabled 12 - WDSL-path-to-memory enabled
Figure 19 7
Power Management (PM) Register 6 5 4 3 2 1 0
PST[1:0]
reserved
PX
Power Management Register SADR[7:0]: 000000112
Read/write register PM[7:0] resets to 000000002
PX - Powerdown exit field.(write-one-only, read=zero) 02 - Powerdown entry - do not write zero - use PDN command 12 - Powerdown exit - write one to exit PST[1:0] - Power state field (read-only). 002 - Powerdown (with self-refresh) 012 - Active/active-idle 102 - reserved 112 - reserved
Figure 20 7
Write Data Serial Load (WDSL) Control Register 6 5 4 3 2 1 0
WDSD[7:0]
Write Data Serial Load Control Register Read/write register SADR[7:0]: 000001002 WDSL[7:0] resets to 000000002 WDSD[7:0] - Writing to this register places eight bits of data into the serial-to-parallel conversion logic (the “Demux” block of Figure 2). Writing to this register “2x16” times accumulates a full “tCC” worth of write data. A subsequent WR command (with SLE=1 in CFG register in Figure 18) will write this data (rather than DQ data) to the sense amps of a memory bank. The shifting order of the write data is shown in Table 10.
Data Sheet E1033E40 (Ver. 4.0) 35
EDX5116ADSE
Figure 21 7 RQ Scan High (RQH) Register 6 5 4 3 2 1 0
reserved
RQH[3:0]
RQ Scan High Register SADR[7:0]: 000001102
Read/write register RQH[7:0] resets to 000000002
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
Figure 22 7
RQ Scan Low (RQL) Register 6 5 4 3 2 1 0
RQL[7:0]
RQ Scan Low Register SADR[7:0]: 000001112
Read/write register RQL[7:0] resets to 000000002
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
Figure 23 7
Refresh Bank (REFB) Control Register 6 5 4 3 2 1 0
MBR[1:0]
reserved
BANK[2:0]
Refresh Bank Control Register SADR[7:0]: 000010002
Read/write register REFB[7:0] resets to 000000002
BANK[2:0] - Refresh bank field. This field returns the bank address for the next self-refresh operation when in Powerdown power state. MBR[1:0] - Multi-bank and multi-row refresh control field. 002 - Single-bank refresh. 102 - Reserved 112 - Reserved 012 - Reserved
Data Sheet E1033E40 (Ver. 4.0) 36
EDX5116ADSE
Figure 24 7 Refresh High (REFH) Row Register 6 5 4 3 2 1 0
reserved
R[18:16]
Refresh High Row Register SADR[7:0]: 000010012
Read/write register REFH[7:0] resets to 000000002
reserved - Refresh row field. This field contains the high-order bits of the row address that will be refreshed during the next refresh interval. This row address will be incremented after a REFI command for auto-refresh, or when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 25 7 Refresh Middle (REFM) Row Register 6 5 4 3 2 1 0
reserved
R[11:8]
Refresh Middle Row Register SADR[7:0]: 000010102
Read/write register REFM[7:0] resets to 000000002
R[11:8] - Refresh row field. This field contains the middle-order bits of the row address that will be refreshed during the next refresh interval. This row address will be incremented after a REFI command for autorefresh, or when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 26 7 Refresh Low (REFL) Row Register 6 5 4 3 2 1 0
R[7:0]
Refresh Low Row Register SADR[7:0]: 000010112
Read/write register REFL[7:0] resets to 000000002
R[7:0] - Refresh row field. This field contains the low-order bits of the row address that will be refreshed during the next refresh interval. This row address will be incremented after a REFI command for auto-refresh, or when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 27 7 IO Configuration (IOCFG) Register 6 5 4 3 2 1 0
reserved
ODF[1:0]
IO Configuration Register SADR[7:0]: 000011112
Read/write register IOCFG[7:0] resets to 000000002
ODF[1:0] - Overdrive Function field. 00 - Nominal VOSW,DQ range 01 - reserved 10 - reserved 11 - reserved
Data Sheet E1033E40 (Ver. 4.0) 37
EDX5116ADSE
Figure 28 7 Current Calibration 0 (CC0) Register 6 5 4 3 2 1 0
reserved
CCVALUE0[5:0]
Current Calibration 0 Register SADR[7:0]: 000100002
Read/write register CC0[7:0] resets to 000011112
CCVALUE0[5:0] - Current calibration value field. This field controls the amount of current drive for the even-numbered DQ and DQN pins.
Figure 29 7
Current Calibration 1 (CC1) Register 6 5 4 3 2 1 0
reserved
CCVALUE1[5:0]
Current Calibration 1 Register SADR[7:0]: 000100012
Read/write register CC1[7:0] resets to 000011112
CCVALUE1[5:0] - Current calibration value field. This field controls the amount of current drive for the odd-numbered DQ and DQN pins.
Figure 30 7
Read Only Memory 0 (ROM0) Register 6 5 4 3 2 1 0
VENDOR[3:0] reserved
MASK[3:0]
Read Only Memory 0 Register Read-only register SADR[7:0]: 000101102 ROM0[7:0] resets to 0010mmmm MASK[3:0] - Version number of mask (00012 is first version). VENDOR[3:0] - Vendor number for component: 0010 - Elpida
Figure 31 7
Read Only Memory 1 (ROM1) Register 6 5 4 3 2 1 0
BB[1:0]
RB[2:0]
CB[2:0]
Read Only Memory 1 Register SADR[7:0]: 000101112
Read-only register ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0] RB[2:0] - Row address bits: #bits = 10 +RB[2:0] BB[1:0] - Bank address bits: #bits = 2 +BB[1:0] These three fields indicate how many column, row, and bank address bits are present. An offset of {6,10,2} is added to the field value to give the number of address bits.
Data Sheet E1033E40 (Ver. 4.0) 38
EDX5116ADSE
Figure 32 7 TEST Register 6 5 4 3 2 1 0
WTL WTE
reserved
TEST Register SADR[7:0]: 000110002 WTE - Wire Test Enable WTL - Wire Test Latch
Read/write register TEST[7:0] resets to 000000002
Figure 33 7
Delay (DLY) Control Register 6 5 4 3 2 1 0
CWD[3:0]
CAC[3:0]
DLY Register SADR[7:0]: 000111112
Read/write register DLY[7:0] resets to 001101102
CAC[3:0] - Programmed value of tCAC timing parameter: 01102 - tCAC = 6*tCYCLE 10002 - tCAC = 8*tCYCLE 01112 - tCAC = 7*tCYCLE others - Reserved. CWD[3:0] - Programmed value of tCWD timing parameter: 00112 - tCWD = 3*tCYCLE 01002 - tCWD = 4*tCYCLE others - Reserved. Following SADR [7:0] registers are reserved: 000100102, 000100112, 000101002, 000101012, 000110012, 000110102, 000110112, 000111002, 000111012, 100000002100011112.
Data Sheet E1033E40 (Ver. 4.0) 39
EDX5116ADSE
Maintenance Operations
Refresh Transactions
Figure 34 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP packet on clock edge T0. The REFA command causes the row addressed by the REFr register (REFH/REFM/REFL) to be opened (sensed) and placed in the sense amp array for the bank. Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank address and delay value, and both cause the selected bank to open (to become sensed.) The difference is that the ACT command is accompanied by a row address in the ROWA packet, while the REFA and REFI commands use a row address in the REFr register (REFH/REFM/REFL). After a time tRAS, a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be closed (precharged), leaving the bank in the same state as when the refresh transaction began. Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value, and both cause the selected bank to close (to become precharged). After a time tRP , another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the same in this example). This starts a second refresh cycle. Each refresh transaction requires a total time tRC= tRAS+ tRP , but refresh transactions to different banks may be interleaved like normal read and write transactions. Each row of each bank must be refreshed once in every tREF interval. This is shown with the fourth ROWP packet with a
REFA command in the top timing diagram.
Interleaved Refresh Transactions
The lower timing diagram in Figure 34 represents one way a memory controller might handle refresh maintenance in a real system. A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are presented starting at edge T0. The packets are spaced with intervals of tRR. Each REFA or REFI command is addressed to a different bank (Ba through Bh) but uses the same row address from the REFr (REFH/REFM/REFL) register. The eighth REFI command uses this address and then increments it so the next set of eight REFA/REFI commands will refresh the next set of rows in each bank. A series of eight ROWP packets with REFP commands are presented effectively at edge T10 (a time tRAS after the first ROWP packet with a REFA command). The packets are spaced with intervals of tPP. Like the REFA/REFI commands, each REFP command is addressed to a different bank (Ba through Bh). This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions may be interleaved with the refresh transactions before and after the burst to prevent any loss of bus efficiency. In other words, a ROWA packet with ACT command for a read or write could have been presented at edge T-4 (a time tRR before the first refresh transaction starts at edge T0). Also, a ROWA packet with ACT command for a read or write could have been presented at edge T36 (a time tRR after the last refresh transaction starts at edge T32). In both cases, the other request packets for the interleaved read or write accesses (the precharge commands and the read or write commands) could be slotted in among the request packets for the refresh transactions.
Data Sheet E1033E40 (Ver. 4.0) 40
EDX5116ADSE
Figure 34 Refresh Transactions T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 Transaction a: REF Transaction b: REF Transaction c: REF
REFA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRAS tRC
REFP
tRP
REFA
REFA
tCYCLE
a0
a1
b0
c0
tREF
a0 = {Ba,REFR} b0 = {Bb,REFR} c0 = {Bc,REFR} a1 = {Ba} b1 = {Bb} c1 = {Bc}
Bb = Ba Bc/Rc = Ba/Ra
Refresh Transaction
T0 CFM CFMN RQ11..0 (ACT) RQ11..0 (PRE) RQ11..0 (ALL) DQ15..0 DQN15..0
REFA REFA
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tRR
REFA
REFA
REFA
REFA
REFA
a0
b0
c0
REFP
d0
REFP
e0
REFP
f0
REFP
a1
REFA REFA REFP REFA
b1
REFP REFA
c1
REFP REFA
d1
REFP
a0
b0
c0
a1
d0
b1
e0
c1
f0
d1
T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CFM CFMN RQ11..0 (ACT) RQ11..0 (PRE) RQ11..0 (ALL) DQ15..0 DQN15..0
REFA REFA
This REFI increments REFR
REFI
REFA
tCYCLE
REFP REFP
g0
REFP
h0
REFP
i0
e1
REFP REFA
f1
REFP REFA
g1
REFP
h1
REFP
g0
e1
h0
f1
i0
g1
h1
Ba,Bb,Bc,Bd, Be,Bf,Bg and Bh are different banks.
Bi = Ba
Transaction a: REF Transaction b: REF Transaction c: REF Transaction d: REF Transaction e: REF Transaction f: REF Transaction g: REF Transaction h: REF Transaction i: REF
a0 = {Ba,REFR} b0 = {Bb,REFR} c0 = {Bc,REFR} d0 = {Bd,REFR} e0 = {Be,REFR} f0 = {Bf,REFR} g0 = {Bg,REFR} h0 = {Bh,REFR} i0 = {Ba,REFR+1}
a1 = {Ba} b1 = {Bb} c1 = {Bc} d1 = {Bd} e1 = {Be} f1 = {Bf} g1 = {Bg} h1 = {Bh} i1 = {Bi}
Interleaved Refresh Example
Data Sheet E1033E40 (Ver. 4.0) 41
EDX5116ADSE
Calibration Transactions
Figure 35 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported: calibration of the output current level IOL for each DQi and DQNi pin. The output current calibration sequence is shown in the upper diagram. It begins when a period of tCMD-CALC is observed after the last RQ packet (with command “CMD a” in this example). No request packets should be issued in this period. A COLX packet with a”CALC b” command is then issued to start the current calibration sequence. A period of tCALCE is observed after this packet. No request packets should be issued during this period. A COLX packet with a “CALE c” command is then issued to end the current calibration sequence. A period of tCALE-CMD is observed after this packet. No request packets should be issued during this period. The first request packet may then be issued (with command “CMD d” in this example). A second current calibration sequence must be started within an interval of tCALC. In this example, the next COLX packet with a “CALC e” command starts a subsequent sequence. The dynamic termination calibration sequence is shown in the lower diagram. Note that this memory component does not use this sequence; termination calibration is performed during the manufacturing process. However, the termination sequence shown will be issued by the controller for those memory components which do use a periodic calibration mechanism. It begins when a period of tCMD-CALZ is observed after the packet at edge T0 (with command CMDa in this example). No request packets should be issued in this period. A COLX packet with a CALZ command is then issued at edge T3 to start the termination calibration sequence. A second period of tCALZE is observed after this packet. No request packets should be issued during this period. A COLX packet with a CALE command is then issued at edge T6 to end the termination calibration sequence. A third period of tCALE-CMD is observed after this packet. No request packets should be issued during this period. The first request packet may be issued at edge T12 (with command CMDd in this example). A second termination calibration sequence must be started within an interval of tCALZ. In this example, the next COLX packet with a CALZ command occurs at edge T20. Note that the labels for the CFM clock edges (of the form Ti) are not to scale, and are used to identify events in the diagrams.
Data Sheet E1033E40 (Ver. 4.0) 42
EDX5116ADSE
Figure 35 Calibration Transactions T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..0 DQN15..0
CMD CALC
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCALCE,
CALE
tCALE-CMD,
CMD
CALC
tCYCLE
a
b
c
d
e
tCMD-CALC
tCALC
Packet a: Any CMD Packet b: CALC Packet c: CALE Packet d: Any CMD Packet e: CALC T0 CFM CFM CFMN CFMN RQ11..0 RQ11..0 DQ15..0 DQN15..0
CMD CALZ
Current Calibration Transaction
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCALZE,
CALE
tCALE-CMD,
CMD
CALZ
tCYCLE
a
b
c
d
e
tCMD-CALZ
tCALZ
Termination Calibration Transactiona
Packet a: Any CMD Packet b: CALZ Packet c: CALE Packet d: Any CMD Packet e: CALZ
a) EDX5116ADSE does not use Termination Calibration Transaction sequence.
Data Sheet E1033E40 (Ver. 4.0) 43
EDX5116ADSE
Power State Management
Figure 36 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown and Active. Powerdown state is to be used in applications in which it is necessary to shut down the CFM/ CFMN clock signals. In this state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine which performs periodic refresh operations using the REFB and REFr control registers. The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of the XDR DRAM must be precharged so they are left in a closed state. Also, all 23 banks must be refreshed using the current value of the REFr registers, and the REFr registers must NOT be incremented with the REFI command at the end of this special set of refresh transactions. This ensures that no matter what value has been left in the REFB register, no row of any bank will be skipped when automatic refresh is first started in Powerdown. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown entry process. After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of tCMD-PDN is observed. No request packets should be issued during this period. A COLX packet with the PDN command is issued after this interval, causing the XDR DRAM to enter Powerdown state after an interval of tPDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM). The CFM/CFMN clock signals may be removed a time tPDN-CFM after the COLX packet with the PDN command. When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically generate internal refresh transactions. It will cycle through all 23 state combinations of the REFB register. When the largest value is reached and the REFB value wraps around, the REFr register is incremented to the next value. The REFB and REFr values select which bank and which row are refreshed during the next automatic refresh transaction. The lower diagram shows the sequence needed for Powerdown exit. The sequence is started with a serial broadcast write (SBW command) transaction using the serial bus of the XDR DRAM. This transaction writes the value “00000001” to the Power Management (PM) register (SADR=”00000011”) of all XDR DRAMs connected to the serial bus. This sets the PX bit of the PM register, causing the XDR DRAMs to return to Active power state.
PDN
The CFM/CFMN clock signals must be stable a time tCFMbefore the end of the SBW transaction.
The XDR DRAM will enter Active state after an interval of tPDN-EXIT has elapsed from the end of the SBW transaction (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM). The first request packet may be issued after an interval of tPDN-CMD has elapsed from the end of the SBW transaction, and must contain a “REFA” command in a ROWP packet. In this example, this packet is denoted with the command “REFA 1”. No other request packets should be issued during this tPDNCMD interval. All “n” banks (in the example, n=23) must be refreshed using the current value of the REFr registers. The “nth” refresh transaction will use a “REFI” command to increment the REFr register (instead of a “REFA” command). This ensures that no matter what value has been left in the REFB register, no row of any bank will be skipped when normal refresh is restarted in Active state. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown exit process. Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the tPDN-CMD interval, no internal refresh operations are performed. As a result, an additional burst of refresh transactions must be issued after the burst of “n” transactions described above. This second burst consists of “m” refresh transactions: m = ceiling[23*212*tPDN-CMD/tREF] Where “212” is the number of rows per bank, and “23” is the number of banks. Every “nth” refresh transaction (where n=23) will use a “REFI” command (to increment the REFr register) instead of a “REFA” command.
Data Sheet E1033E40 (Ver. 4.0) 44
EDX5116ADSE
Figure 36 Power State Management
CFM CFMN RQ11..0 DQ15..0 DQN15..0
CMD
No signal
tCYCLE tCMD-PDN
PDN
tPDN-CFM
Powerdown State...
a
b a
tPDN-ENTRY
Transaction a: Last precharge command Transaction b: PDN
Powerdown Entry
S0 SCK RST
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34
Power-up transaction
Start
SCMD
tCYC,SCK
SWD[7:0]
CMD SDI (input) SDO (output)
2’h0,SID[5:0]
43 2 107
SADR[7:0]
65 43 2 1 0 ‘0’ 7
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ 5
65
43
2
1 0 ‘0’
CFM CFMN RQ11..0
No signal
tCFM-PDN
....Powerdown State
tPDN-EXIT
tCYCLE
DQ15..0 DQN15..0
tPDN-CMD
CFM CFMN
REFA REFA REFI REFP REFP REFP
RQ11..0 DQ15..0 DQN15..0
1
2
n
n-2
n-1
n
tCYCLE
tPDN-CMD
Transaction 1: REFA Transaction 2: REFA Transaction n-1: REFA Transaction n: REFI The final REFI command increments the REFr register
Powerdown Exit
Data Sheet E1033E40 (Ver. 4.0) 45
EDX5116ADSE
Initialization
Figure 37 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are transmitted by the controller and are received by each XDR DRAM device along the bus. The signals are terminated to the VTERM supply through termination components at the end farthest from the controller. The SDI input of the XDR DRAM device furthest from the controller is also terminated
Figure 37 Serial Interface System Topology VTERM
to VTERM. The SDO output of each XDR DRAM device is transmitted to the SDI input of the next XDR DRAM device (in the direction of the controller). This SDO/SDI daisy-chain topology continues to the controller, where it ends at the SRD input of the controller. All the serial interface signals are lowtrue. All the signals use RSL signaling circuits, except for the SDO output which uses CMOS signaling circuits.
RST CMD SCK
RST CMD SCK
RST CMD SCK
RST CMD SCK
SRD Controller
SDO
SDI
...
SDO
SDI
...
SDO
SDI
XDR DRAM
XDR DRAM
XDR DRAM
Figure 38 shows the initialization timing of the serial interface for the XDR DRAM[k] device in the system shown above. Prior to initialization, the RST is held at zero. The CMD input is not used here, and should also be held at zero. Note that the inputs are all sampled by the negative edge of the SCK clock input. The SDI input for the XDR DRAM[0] device is zero, and is unknown for the remaining devices.
Figure 38 Initialization Timing for XDR DRAM[k] Device
On negative SCK edge S8 the RST input is sampled one. It is sampled one on the next four edges, and is sampled zero on edge S12 a time tRST-10 after it was first sampled one. The state of the control registers in the XDR DRAM device are set to their reset values after the first edge (S8) in which RST is sampled one.
Poweron 0
tCOREINIT
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S tRST-SCK
tRST-10 tCYC,SCK
SCK RST
1 0 1 0
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDI,00 = k * tCYC,SCK
CMD SDI (input) 1 SDO (output) 1
0 1 0
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDO,11
tSDI-SDO,00
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
The SDI inputs will be sampled one within a time tRST-SDO,11 after RST is first sampled one in all the XDR DRAMs except for XDR DRAM[0]. XDR DRAM[0]’s SDI input will always
be sampled zero. XDR DRAM[k] will see its RST input sampled zero at S12, and will then see its SDI input sampled zero at S16 (after SDI had
Data Sheet E1033E40 (Ver. 4.0) 46
EDX5116ADSE
previously been sampled one). This interval (measured in tCYC,SCK units) will be equal to the index [k] of the XDR DRAM device along the serial interface bus. In this example, k is equal to 4. This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time tSDI-SDO,00 after its SDI input is sampled zero. In other words, the XDR DRAM[0] device will see RST and SDI both sampled zero on the same edge S12 (tRST-SDI,00 will be 0*tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S13). The XDR DRAM[1] device will see SDI sampled zero on edge S13 (tRST-SDI,00 will be 1*tCYC,SCK units), and will drive its
Table 9 Initialization Symbol tRST,10 tRST-SDO,11 tRST-SDI,00 Parameter Number of cycles between RST being sampled one and RST being sampled zero. Number of cycles between RST being sampled one and SDO being driven to one. Number of cycles between RST being sampled zero (after being sampled one for tRST,10,MIN or more cycles) and SDI being sampled zero. This will be equal to the index [k] of the XDR DRAM device along the serial interface bus. Number of cycles between SDI being sampled zero (after RST has been sampled one for tRST,10,MIN or more cycles and is then sampled zero) and SDO being driven to zero. The number of SCK falling edges after the first SCK falling edge in which RST is sampled one.
SDO to zero around the subsequent edge (S14). The XDR DRAM[2] device will see SDI sampled zero on edge S14 (tRST-SDI,00 will be 2*tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S15). This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state machine which measures the interval tRST-SDI,00 between the edges in which RST and SDI are both sampled zero, and uses this value to set the SID[5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to be made to the individual XDR DRAM devices. Table 9 summarizes the range of the timing parameters used for initialization by the serial interface bus. Timing Parameters
Minimum 2 1 0 Maximum 1 63 Units tCYC,SCK tCYC,SCK tCYC,SCK Figure(s) -
tSDI-SDO,00
1
1
tCYC,SCK
-
tRST-SCK
20
-
tCYC,SCK
-
XDR DRAM Initialization Overview
[1] Apply voltage toVDD, VTERM, and VREF pins. VTERM and VREF voltages must be less or equal to VDD voltage at all times. Wait a time interval tCOREINIT. [2] Assert RST, SCK, SDI, and CMD to logical zero. Then: - Pulse SCK to logical one, then to logical zero four times. - Assert RST to logical one. Reset circuit places XDR DRAM into low-power state (identical to power-on reset). - Perform remaining initialization sequence in Figure 38. [3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure 17 through Figure 33. [4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value. [5] Perform Powerdown Exit sequence shown in Figure 36. This includes the activity from SCK cycle S0 through the final REFP command. [6] Perform termination/current calibration. The CALZ/
CALE sequence shown in Figure 35 is issued 128 times, then the CALC/CALE sequence is issued 128 times. After this, each sequence is issued once every tCALZ or tCALC interval. [7] Condition the XDR DRAM banks by performing a REFA/ REFI activate and REFP precharge operation to each bank eight times. This can be interleaved to save time. The row address for the activate operation will step through eight successive values of the REFr registers. The sequence between cycles T0 and T32 in the Interleaved Refresh Example in Figure 34 could be performed eight times to satisfy this conditioning requirement.
Data Sheet E1033E40 (Ver. 4.0) 47
EDX5116ADSE
XDR DRAM Pattern Load with WDSL Reg
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning Receive Timing Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is called Write Data Serial Load (WDSL). A WDSL packet sends one-byte of serial data which is serially shifted into a holding register within the XDR DRAM. Initialization software sends a sequence of WDSL packets, each of which shifts the new byte in and advances the shifter by 8 positions. In this way, XDR DRAMs of varying widths can be loaded with a single command type.
Table 10 XDR
Each sequence of WDSL packets will load one full column of data to the internal holding register of the target XDR DRAM. Depending upon the ratio of native device width to programmed width, there may be more than one sub-column per column. After loading a full column, a series of WR commands will be issued to sequentially transfer each sub-column of the column to the XDR DRAM core(s), based upon the SC[3:0] bits. .
DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4 XDR DRAM , BL=16)
WDSL Core Word Load Order WD[n][15:0] x16
SC[3:2] =xx SC[3:2] = 0x
DQ Pins Used Core Word x4 x8 x16
x8
SC[3:2] = 1x SC[3:2] = 00 SC[3:2] = 01
x4
SC[3:2] = 10 SC[3:2] = 11
LOGICAL VIEW OF XDR DRAM DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WD[0][15:0] WD[1][15:0] WD[2][15:0] WD[3][15:0] WD[4][15:0] WD[5][15:0] WD[6][15:0] WD[7][15:0] WD[8][15:0] WD[9][15:0] WD[10][15:0] WD[11][15:0] WD[12][15:0] WD[13][15:0] WD[14][15:0] WD[15][15:0] WDSL Word 8 WDSL Word 7 WDSL Word 12 WDSL Word 3 WDSL Word 10 WDSL Word 5 WDSL Word 14 WDSL Word 1 WDSL Word 9 WDSL Word 6 WDSL Word 13 WDSL Word 2 WDSL Word 11 WDSL Word 4 WDSL Word 15 WDSL Word 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Word Written (1 = Written, 0 = Not Written) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
PHYSICAL VIEW OF XDR DRAM DQ2 DQ6 DQ14 DQ6 DQ2 DQ10 DQ2 DQ0 DQ4 DQ12 DQ4 DQ0 DQ8 DQ0 WD[14][15:0] WD[6][15:0] WD[10][15:0] WD[2][15:0] WD[12][15:0] WD[4][15:0] WD[8][15:0] WD[0][15:0] WDSL Word 15 WDSL Word 14 WDSL Word 13 WDSL Word 12 WDSL Word 11 WDSL Word 10 WDSL Word 9 WDSL Word 8 1 1 1 1 1 1 1 1
Word Written (1 = Written, 0 = Not Written) 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0
Data Sheet E1033E40 (Ver. 4.0) 48
EDX5116ADSE
Table 10 XDR
DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4 XDR DRAM , BL=16)
WDSL Core Word Load Order WD[n][15:0] WD[1][15:0] WD[9][15:0] WD[5][15:0] WD[13][15:0] WD[3][15:0] WD[11][15:0] WD[7][15:0] WD[15][15:0] WDSL Word 7 WDSL Word 6 WDSL Word 5 WDSL Word 4 WDSL Word 3 WDSL Word 2 WDSL Word 1 WDSL Word 0 x16
SC[3:2] =xx SC[3:2] = 0x
DQ Pins Used Core Word x4 DQ1 x8 DQ1 x16 DQ1 DQ9 DQ5 DQ5 DQ13 DQ3 DQ3 DQ3 DQ11 DQ7 DQ7 DQ15
x8
SC[3:2] = 1x SC[3:2] = 00 SC[3:2] = 01
x4
SC[3:2] = 10 SC[3:2] = 11
1 1 1 1 1 1 1 1
1 0 1 0 1 0 1 0
0 1 0 1 0 1 0 1
1 0 0 0 1 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 0 0 1 0 0 0 1
.
Table 11 Core DQ Serialization Order CFM/PCLK Cycle Symbol (Bit) Time Bit Transmitted on DQ pins t0 D0 t1 D1 t2 D2 Cycle 0 t3 D3 t4 D4 t5 D5 t6 D6 t7 D7 t8 D8 t9 D9 t10 D10 Cycle 1 t11 D11 t12 D12 t13 D13 t14 D14 t15 D15
Data Word-to-WDSL Format
WDSL Byte/Bit Transfer Order Core Word WDSL Byte Order SWD Field of Serial Packet Bit Transmitted on CMD pin 7 D15 6 D11 5 D7 WDSL Byte 0 4 D3 3 D14 2 D10 1 D6 0 D2 7 D13 6 D9 5 D5 Core Word WD[n][15:0] WDSL Byte 1 4 D1 3 D12 2 D8 1 D4 0 D0
Data Sheet E1033E40 (Ver. 4.0) 49
EDX5116ADSE
Special Feature Description
Dynamic Width Control
This XDR DRAM device includes a feature called dynamic width control. This permits the device to be configured so that read and write data can be accessed through differing widths of DQ pins. Figure 39 shows a diagram of the logic in the path of the read data (Q) and write data (D) that accomplishes this. The read path is on the right of the figure. There are 16 sets of S signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is configured for maximum width operation (using the WIDTH[2:0] field in the CFG register), each set of 16 S signals goes to one of the 16 DQ pins (via the Q[15:0][15:0] read bus) and are driven out in the 16 time slots for a read data packet. When the XDR DRAM device is configured for a width that is less than the maximum, some of the DQ pins are used and the rest are not used. The SC[3:0] field of the COL request packets select which S[15:0][15:0] signals are passed to the Q[15:0][15:0] read bus and driven as read data. Figure 40 shows the mapping from the S bus to the Q bus as a function of the WIDTH[2:0] register field and the SC[3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH[2:0]. In each table, there is an entry in the left column for each valid value of SC[3:0]. This field should be treated as an extension of the C[9:4] column address field. The right hand column shows which set of S[15:0][15:0]
Figure 39 Multiplexers for Dynamic Width Control
signals are mapped to the Q read data bus for a particular value of SC[3:0]. For example, assume that the WIDTH[2:0] value is “010”, indicating a device width of x4. Looking at the appropriate table in Figure 40, it may be seen that in the SC[3:0] field, the SC[1:0] sub-column address bits are not used. The remaining SC[3:0] address bit(s) selects one of the 64-bit blocks of S bus signals, causing them to be driven onto the Q[3:0][15:0] read data bus, which in turn is driven to the DQ3..0/DQN3..0 data pins. The Q[15:4][15:0] signals and DQ15..4/DQN15..4 data pins are not used for a device width of x4. The write path is shown on the left side of Figure 39. As before, there are 16 sets of S signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is configured for maximum width operation (using the WIDTH[2:0] field in the CFG register), each set of 16 S signals is driven from one of the 16 DQ pins (via the D[15:0][15:0] write bus) from each of the 16 time slots for a write data packet. Figure 40 also shows the mapping from the D bus to the S bus as a function of the WIDTH[2:0] register field and the SC[3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH[2:0]. In each table, there is an entry in the left column for each valid value of SC[3:0]. This field should be treated as an extension of the C[9:4] column address field. The right hand column shows which set of S[15:0][15:0] signals are mapped from the D write data bus for a particular value of SC[3:0].
S[15:0][15:0] 16x16 8 M[7:0] 4+3 WIDTH[2:0] SC[3:0] Byte Mask (WR) 16x16 D1[15:0][15:0] Dynamic Width Mux (RD) 16x16 Q[15:0][15:0] 4+3 WIDTH[2:0] SC[3:0] 16x16
Dynamic Width Demux (WR) 16x16 D[15:0][15:0]
Data Sheet E1033E40 (Ver. 4.0) 50
EDX5116ADSE
The block diagram in Figure 39 indicates that the Dynamic Width logic is positioned after the serial-to-parallel conversion (demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the data transmitter block (see also the block diagram in Figure 2). The block diagram is shown in this manner so the functionality of the logic
Figure 40
can be made as clear as possible. Some implementations may place this logic in the data receiver and transmitter blocks, performing the mapping in Figure 40 on the serial data rather than the parallel data. However, this design choice will not affect the functionality of the Dynamic Width logic; it is strictly an implementation decision.
D-to-S and S-to-Q Mapping for Dynamic Width Control a WIDTH[2:0]=001 (x2 device width) a 000x 00x 001x 01x 010x 10x 011x 11x 100x SC[2:0] 101x 110x 111x SC[3:0] S[1:0][15:0] S[4,0][15:0] S[3:2][15:0] S[5,1][15:0] S[5:4][15:0] S[6,2][15:0] S[7:6][15:0] S[7,3][15:0] S[9:8][15:0] D[1:0][15:0] Q[1:0][15:0] S[11:10][15:0] S[13:12][15:0] S[15:14][15:0] D[1:0][15:0] Q[1:0][15:0] 0xxx 1xxx SC[3:0] S[7:0][15:0] S[15:8][15:0] D[7:0][15:0] Q[7:0][15:0] WIDTH[2:0]=011 (x8 device width)
WIDTH[2:0]=000 (x1 device width) 0000 000 0001 001 0010 010 0011 011 0100 100 0101 101 0110 110 0111 111 1000 SC[2:0] 1001 S[0][15:0] S[1][15:0] S[2][15:0] S[3][15:0] S[4][15:0] S[5][15:0] S[6][15:0] S[7][15:0] S[8][15:0] D[0][15:0] Q[0][15:0] S[9][15:0]
S[10][15:0] 1010 WIDTH[2:0]=010 (x4 device width) 1011 0xx 1100 1xx 1101 SC[2:0] 1110 1111 SC[3:0] S[11][15:0] S[6,2,4,0][15:0] S[12][15:0] S[7,3,5,1][15:0] S[13][15:0] D[3:0][15:0] S[14][15:0] Q[3:0][15:0] S[15][15:0] D[0][15:0] Q[0][15:0]
WIDTH[2:0]=011 (x8 device width) WIDTH[2:0]=010 (x4 device width) xxx 00xx SC[2:0] 01xx 10xx 11xx SC[3:0] S[7:0][15:0] S[3:0][15:0] D[7:0][15:0] S[7:4][15:0] Q[7:0][15:0] S[11:8][15:0] S[15:12][15:0] D[3:0][15:0] Q[3:0][15:0]
WIDTH[2:0]=100 (x16 device width)
xxxx SC[3:0]
S[15:0][15:0] D[15:0][15:0] Q[15:0][15:0]
A16 A8 a) EDX5116ADSE does not support ×1 and ×2 device width.
Data Sheet E1033E40 (Ver. 4.0) 51
EDX5116ADSE
Write Masking
Figure 41 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This masking logic permits individual bytes of a write data packet to be written or not written according to the value of an eight bit write mask M[7:0]. In Figure 41, there are 16 sets of 16 bit signals forming the D1[15:0][15:0] input bus for the Byte Mask block. These are treated as 2x16 8-bit bytes: D1[15][15:8] D1[15][7:0] ... D1[1][15:8] D1[1][7:0] D1[0][15:8]
Figure 41 Byte Mask Logic S[15][7:0] WE-MSB [15] 1 NE Compare 8 8
D1[15][15:8]
D1[0][7:0] The eight bits of each byte is compared to the value in the byte mask field (M[7:0]). If they are not equal (NE), then the corresponding write enable signal (WE) is asserted and the byte is written into the sense amplifier. If they are equal, then the corresponding write enable signal (WE) is deasserted and the byte is not written into the sense amplifier. In the example of Figure 41, a WRM command performs a masked write of a 32-byte data packet to a single memory device connected to the RQ bus (and receiving the command). It is the job of the memory controller to search the 32 bytes to find an eight bit data value that is not used and place it into the M[7:0] field. This will always be possible because there are 256 possible 8-bit values and there are only 32 possible values used in the bytes in the data packet.
S[15][15:8]
S[0][15:8] WE-LSB [15] 1 NE Compare 8 8 WE-MSB [0] 1 NE Compare 8 8 D1[0][15:8] 8 D1[0][15:8]
S[0][7:0] WE-LSB [0] 1 NE Compare 8 8 D1[0][7:0] 8 D1[0][7:0]
8
8
8
8
8
8
8
8
M[7:0] 8
D1[15][7:0] 8 D1[15][7:0]
D1[15][15:8]
S[15:0][15:0] 16x16 8 M[7:0] 4+3 WIDTH[2:0] SC[3:0] Byte Mask (WR) 16x16 D1[15:0][15:0] Dynamic Width Mux (RD) 16x16 Q[15:0][15:0] 4+3 WIDTH[2:0] SC[3:0] 16x16
Dynamic Width Demux (WR) 16x16 D[15:0][15:0]
Note that other systems might use a data transfer size that is different than the 32 bytes per tCC interval per RQ bus that is used in the example in Figure 41.
Figure 42 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two successive WR commands in COL packets. The one difference
Data Sheet E1033E40 (Ver. 4.0) 52
EDX5116ADSE
is that the COLM packet includes a M[7:0] field that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be written. This requires that the alignment of bytes within the data packet be defined, and also that the bit numbering within each byte be defined (note that this was not necessary for the unmasked WR command).
Figure 42 Write-Masked (WRM) Transaction Example T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
WRM a1 WRM a2 RD a1 D(a1) D(a2)
In the figure, bytes are contained within a single DQ/DQN pin pair — this is necessary so the dynamic width feature can be supported. Thus, each pin pair carries two bytes of each data packet. Byte[0] is transferred earlier than byte[16+0], and bit [0] of each byte (corresponding to M[0]) is transferred first, followed by the remaining bits in succession).
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
Q(a1)
tCC tCWD tCAC
Bit- and Byte-numbering convention for write and read data packets. Byte [0] DQ0 DQN0
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
Byte [16+0]
[10] [11] [12] [13] [14] [15]
Byte [1] DQ1 DQN1
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
Byte [16+1]
[10] [11] [12] [13] [14] [15]
...
Byte [15] DQ15 DQN15
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
...
Byte [16+15]
[10] [11] [12] [13] [14] [15]
Data Sheet E1033E40 (Ver. 4.0) 53
EDX5116ADSE
Multiple Bank Sets and the ERAW Feature
Figure 45 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the odd bank set) according to the least-significant bit of the bank address field. This XDR DRAM supports a feature called “Early Read After Write” (hereafter called “ERAW”). The logic that accepts commands on the RQ11..0 signals is capable of operating these two bank sets independently. In addition, each bank set connects to its own internal “S” data bus (called S0 and S1). The receive interface is able to drive write data onto either of these internal data buses, and the transmit interface is able to sample read data from either of these internal data buses. These capabilities will permit the delay between a write column operation and a read column operation to be reduced, thereby improving performance.
Figure 43 Write/Read Interaction — No ERAW Feature
Figure 43 shows the timing previously presented in Figure 12, but with the activity on the internal S data bus included. The write-to-read parameter t∆WR ensures that there is adequate turnaround time on the S bus between D(a2) and Q(c1). When ERAW is supported with odd and even bank sets, the t∆WR,MIN parameter must be obeyed when the write and read column operations are to the same bank set, but a second parameter t∆WR-D permits earlier column operations to the opposite bank set. Figure 44 shows how this is possible because there are two internal data buses S0 and S1. In this example, the four column read operations are made to the same bank Bb, but they could use different banks as long as they all belonged to the bank set that was different from the bank set containing Ba (for the column write operations).
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 S[15:0] [15:0]
WR a1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR a2 D(a1)
t∆WR
D(a2)
RD c1
RD c2
tCYCLE tCAC
Q(c1) Q(c2)
tWR-BUB,XDRDRAM
tCC
D(a1) D(a2)
tCWD
turnaround
Q(c1) Q(c2)
tCC
Transaction a: WR Transaction c: RD Figure 44
a1 = {Ba,Ca1} c1 = {Bc,Cc1}
a2 = {Ba,Ca2} c2 = {Bc,Cc2}
Write/Read Interaction — ERAW Feature
T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 S0[15:0] [15:0] S1[15:0] [15:0]
WR a1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
WR a2
RD b1 D(a1)
t∆WR-D tCWD
tCAC
RD b2
RD b3
RD b4 Q(b1)
RD c1 Q(b2) Q(b3) Q(b4) Q(c1)
tCYCLE
D(a2)
tCC tWR-BUB,XDRDRAM
D(a1) D(a2)
turnaround
Q(c1)
tCC
Q(b1)
Q(b2)
Q(b3)
Q(b4)
Bank Restrictions Bb is in different bank set than Ba Bc is in same bank set as Ba
Transaction a: WR Transaction b: RD Transaction c: RD
a1 = {Ba,Ca1} b1 = {Bb,Cb1} c1 = {Bc,Cc1}
a2 = {Ba,Ca2} b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
b4 = {Bb,Cb4}
Data Sheet E1033E40 (Ver. 4.0) 54
EDX5116ADSE
Figure 45 XDR DRAM Block Diagram with Bank Sets RQ11..0 12
1:2 Demux Reg COL decode 6 3 PRE decode 3 ACT decode 3 12
16x16*26*212
Odd Bank Array Bank 0
16x16*26*212 1 1 ACT ACT ROW ROW PRE PRE
6
Even Bank Array Bank 0
...
ACT ACT ROW
...
...
...
1
ACT logic
1 12 12 1
12 ROW 12 1
Bank 1
PRE
3
...
Bank(2 -1)
PRE
1
6
PRE logic
1
Bank 0
...
...
...
Bank (2 -2)
...
3
Sense Amp Array
16x16*26 R/W
1
1
R/W
Sense Amp 1
1 6 6
1 6 6 16x16
COL COL
3-1)
COL logic
R/W COL COL
Sense Amp 0
...
...
Sense Amp(2
WR odd 16x16
WR even
RD even
RD odd 16x16
Byte Mask (WR) Dynamic Width Demux (WR) 16x16 D[15:0][15:0] 16 1:16 Demux 16 16/tCC 16:1 Mux 16 Dynamic Width Mux (RD) Q[15:0][15:0] 16x16 16
16 DQ15..0
16 DQN15..0
Data Sheet E1033E40 (Ver. 4.0) 55
...
...
...
16x16 S1[15:0][15:0]
16x16
... ... ...
...
16x16*26
16x16*2
16x16*2
16x16*26
Sense Amp Array
16x16*26
R/W
...
3 Sense Amp (2 -2)
...
16x16 S0[15:0][15:0]
... ...
16/tCC
EDX5116ADSE
Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in Figure 45, another feature may be supported, in addition to ERAW. This feature is simultaneous activation, and the timing of several cases is shown in Figure 46. The tRR parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The tRR-D parameter specifies the minimum spacing between packets with activation commands to different bank sets in a XDR DRAM with multiple bank sets. In Figure 46, Case 4 shows an example when both tRR and tRRD must be at least 4*tCYCLE. In such a case, activation commands to different bank sets satisfy the same constraint as activation commands to the same bank set. In Figure 46, Case 2 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 2*tCYCLE. In such a case, an activation command to one bank set may be inserted
Figure 46 Simultaneous Activation — tRR-D Cases Case 4: tRR-D = 4*tCYCLE REFA & ACT have same tRR T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 a Case 1: tRR-D = 1*tCYCLE REFA fits between two ACT T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
ACT REFA ACT REFA ACT ACT ACT REFA
between two activation commands to a different bank set. In Figure 46, Case 1 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 1*tCYCLE. As in the previous case, an activation command to one bank set may be inserted between two activation commands to a different bank set. In this case, the middle activation command will not be symmetrically placed relative to the two outer activation commands. In Figure 46, Case 0 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 0*tCYCLE. This means that two activation commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two commands. See “Dynamic Request Scheduling” on page 20. In the example shown, the packet with the REFA command is received one cycle before the command with the ACT command, and the REFA command includes a one cycle delay. Both activation commands will be issued internally to different bank sets on the same CFM clock edge.
a Case 2: tRR-D = 2*tCYCLE REFA fits between two ACT T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
T1
T2
T3
T4
T5
T6
T7
T8
tRR-D
tRR-D
ACT
ACT
REFA
ACT
tCYCLE
tRR-D tRR
Case 0: tRR-D = 0*tCYCLE REFA simultaneous with ACT (REFA uses delay=1*tCYCLE) T7 T8 T9 a
note - REFA is directed to bank set different from two ACT
T1
T2
T3
T4
T5
T6
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
tCYCLE
tRR-D tRR
tRR-D
note - REFA is directed to bank set different from two ACT
tRR
note - REFA is directed to bank set different from ACT at T12
a) EDX5116ADSE does not support these cases. The minimum value of tRR-D is 4.
Data Sheet E1033E40 (Ver. 4.0) 56
EDX5116ADSE
Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in Figure 45, another feature may be supported, in addition to ERAW and simultaneous activation. This feature is simultaneous precharge, and the timing of several cases is shown in Figure 47. The tPP parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The tPP-D parameter specifies the minimum spacing between packets with precharge commands to different bank sets in a XDR DRAM with multiple bank sets. In Figure 47, Case 4 shows an example when both tPP and tPPD must be at least 4*tCYCLE. In such a case, precharge commands to different bank sets satisfy the same constraint as precharge commands to the same bank set. In Figure 47, Case 2 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 2*tCYCLE. In such a case, a precharge command to one bank set may be inserted
Figure 47 Simultaneous Precharge — tPP-D Cases Case 4: tPP-D = 4*tCYCLE REFP & PRE have same tRR T0 CFM CFMN RQ11..0 DQ15..0 DQN15..0
PRE REFP
between two precharge commands to a different bank set. In Figure 47, Case 1 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 1*tCYCLE. As in the previous case, a precharge command to one bank set may be inserted between two precharge commands to a different bank set. In this case, the middle precharge command does not have to be symmetrically placed relative to the two outer precharge commands. In Figure 47, Case 0 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 0*tCYCLE. This means that two precharge commands may be issued on the same CFM clock edge. This is possible by using the delay mechanism in one of the two commands. See “Dynamic Request Scheduling” on page 20. It is also possible by taking advantage of the fact that two independent precharge commands may be encoded within a single ROWP packet. In the example shown, the ROWP packet contains both a REFP command and a PRE command. Both precharge commands will be issued internally to different bank sets on the same CFM clock edge.
Case 2: tPP-D = 2*tCYCLE REFP fits between two PRE T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
T1
T2
T3
T4
T5
T6
T7
T8
tPP-D
tPP-D
PRE
PRE
REFP
PRE
tCYCLE
tPP-D tPP
Case 1: tPP-D = 1*tCYCLE REFP fits between two PRE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
note - REFP is directed to bank set different from two PRE a
Case 0: tPP-D = 0*tCYCLE REFP simultaneous with PRE
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM CFMN RQ11..0 DQ15..0 DQN15..0
PRE REFP PRE PRE REFP PRE
tCYCLE
tPP-D tPP
tPP-D
note - REFP is directed to bank set different from two PRE
tPP
note - REFP is directed to bank set different from PRE at T12
a) EDX5116ADSE does not support case0. The minimum value of tPP-D is 1.
Data Sheet E1033E40 (Ver. 4.0) 57
EDX5116ADSE
Operating Conditions
Electrical Conditions
Table 12 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory component. The first section of parameters is concerned with absolute voltages, storage, and operating temperatures, and the power supply, reference, and termination voltages. The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF,RSL.
The third section of parameters determines the input voltage levels for the RSL SI (serial interface) signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF,RSL. The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are specified by a common-mode value and a swing value. The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and low voltage are specified by a common-mode value and a swing value. Conditions
Minimum - 0.300 - 0.500 - 50 0 1.800 - 0.090 VTERM,RSL a - 0.450 - 0.025 1.200 - 0.060 VREF,RSL - 0.450 VREF,RSL + 0.150 0.8 VREF,RSL - 0.450 VREF,RSL + 0.200 0.8 VTERM,DRSL VISW,CFM/2 - 0.020 0.150 VTERM,DRSLVISW,DQ/2 - 0.020 0.050 Maximum 1.500 2.300 100 100 1.800 + 0.090 VTERM,RSLa - 0.450 + 0.025 1.200 + 0.060 VREF,RSL - 0.150 VREF,RSL + 0.450 1.2 VREF,RSL - 0.200 VREF,RSL + 0.450 1.2 VTERM,DRSL VISW,CFM/2 + 0.020 0.300 VTERM,DRSLVISW,DQ/2 + 0.020 0.300 Unit V V °C °C V V
Table 12 Electrical Symbol VIN,ABS VDD,ABS TSTORE TJ VDD VREF,RSL Parameter Voltage applied to any pin (except VDD) with respect to GND Voltage on VDD with respect to GND Storage temperature Junction temperature under bias during normal operation Supply voltage applied to VDD pins during normal operation RSL - Reference voltage applied to VREF pin
VTERM,DRSL VIL,RQ VIH,RQb RA,RQ VIL,SI VIH,SIb RA,SI VICM,CFM VISW,CFM VICM,DQ VISW,DQ
DRSL - Termination voltage applied to VTERM pins RSL RQ inputs -low voltage RSL RQ inputs -high voltage RSL RQ inputs - data asymmetry: RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ) RSL Serial Interface inputs -low voltage RSL Serial Interface inputs -high voltage RSL Serial Interface inputs - data asymmetry: RA,SI = (VIH,SI-VREF,RSL)/(VREF,RSL-VIL,SI) CFM/CFMN input - common mode
V V V
-
V V
-
V
CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CFMb- VIL,CFM) DRSL DQ inputs - common mode
V V
DRSL DQ inputs - high-low swing: VISW,DQ = (VIH,DQb - VIL,DQ)
V
a. VTERM,RSL is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component. b. VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system.
Data Sheet E1033E40 (Ver. 4.0) 58
EDX5116ADSE
Timing Conditions
Table 13 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is concerned with parameters for the clock signals. The second section of parameters is concerned with parameters for the request signals. The third section of parameters is concerned
Table 13 Timing
Symbol tCYCLE or tCYC,CFM tR,CFM, tF,CFM tH,CFM, tL,CFM tR,RQ, tF,RQ tS,RQ, tH,RQ Parameter and Other Conditions CFM RSL clock - cycle time CFM/CFMN input - rise and fall time - use minimum for test. CFM/CFMN input - high and low times RSL RQ input - rise/fall times (20% - 80%) - use minimum for test. RSL RQ input to sample points (set/hold) @ 2.500 ns > tCYCLE ≥ 2.000 ns @ 3.333 ns > tCYCLE ≥ 2.500 ns @ 3.830 ns ≥ tCYCLE ≥ 3.333 ns -4000 -3200
with parameters for the write data signals. The fourth section of parameters is concerned with parameters for the serial interface signals. The fifth section is concerned with all other parameters, including those for refresh, calibration, power state transitions, and initialization.
Conditions
Minimum 2.000 2.500 0.080 40% 0.080 0.170 0.200 0.275 0.020 0.055 0.065 0.080 -0.080 Maximum 3.830 3.830 0.200 60% 0.260 0.074 +0.080 ns ns tCYCLE tCYCLE tCYCLE ns ns ns tCYCLE ns ns ns tCYCLE ns ns ns tCYC,SCK ns ns ns tCYC,SCK Units Figure(s) Figure 48 Figure 48 Figure 48 Figure 49 Figure 49
tIR,DQ, tIF,DQ tS,DQ, tH,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test. DRSL DQ input to sample points (set/hold) @ 2.500 ns > tCYCLE ≥ 2.000 ns @ 3.333 ns > tCYCLE ≥ 2.500 ns @ 3.830 ns ≥ tCYCLE ≥ 3.333 ns
Figure 50
Figure 50
tDOFF,DQ tCYC,SCK
DRSL DQ input delay offset (fixed) to sample points Serial Interface SCK input - cycle time
Figure 50 Figure 52
-4000 -3200
16 20 40% -
5.0 60% 5.0 -
tR,SCK, tF,SCK tH,SCK, tL,SCK tIR,SI, tIF,SI tS,SI,tH,SI
Serial Interface SCK input - rise and fall times Serial Interface SCK input - high and low times Serial Interface CMD,RST,SDI input - rise and fall times Serial Interface CMD,RST,SDI input to SCK clock edge - set/hold time -4000 -3200
Figure 52 Figure 52 Figure 52 Figure 52
4 5 10
tDLY,SI-RQ
Delay from last SCK clock edge for register operation to first CFM edge with RQ packet. Also, delay from last CFM edge with RQ packet to the first SCK clock edge for register operation. Refresh interval. Every row of every bank must be accessed at least once in this interval with a ROW-ACT, ROWP-REF or ROWP-REFI command. Average refresh command interval. ROWP-REFA or ROWP-REFI commands must be issued at this average rate. This depends upon tREF and the number of banks and rows: tREFA-REFA,AVG = tREF/(NB*NR) = tREF/(23*212). Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands which can be issued consecutively at the minimum command spacing. Refresh/increment command interval. The interval between two ROWP-REFI commands. Refresh burst interval. The interval between a burst of NREFA,BURST,MAX ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or ROWP-REFI command. Interval between VDD power-on and stable to the first RQ or serial transaction for core initialialization. Current and termination calibration interval
-
tREF tREFA-REFA,AVG
-
16 tREFA-REFA,AVG = 488
ms ns
Figure 34 -
NREFA,BURST
-
128
commands
-
tREFI-REFI tBURST-REFA
16
40
-
tCYCLE
tCYCLE
-
tCOREINIT tCALC, tCALZ
1.500 -
100
ms ms
Figure 35
Data Sheet E1033E40 (Ver. 4.0) 59
EDX5116ADSE
Table 13 Timing
Symbol tCMD-CALC, tCMD-CALZ, tCALCE, tCALZE tCALE-CMD tCMD-PDN tPDN-CFM tCFM-PDN tPDN-CMD
Conditions (Continued)
Minimum 4 16 12 24 16 16 16 4096 Maximum Units tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Figure(s) Figure 35 Figure 35 Figure 35 Figure 36 Figure 36 Figure 36 Figure 36
Parameter and Other Conditions Delay between packet with any command and CALC/CALZ packet w/ PRE or REFP command w/ any other command
Delay between CALC/CALZ packet and CALE packet Delay between CALE packet and packet with any command Last command before PDN entry RSL CFM/CFMN stable after PDN entry RSL CFM/CFMN stable before PDN exit First command after PDN exit (includes lock time for CFM/CFMN)
Operating Characteristics
Electrical Characteristics
Table 14 summarizes all electrical parameters (temperature, current, and voltage) that characterize this memory component. The only exception is the supply current values (IDD) under different operating conditions covered in the Supply Current Profile section. The first section of parameters is concerned with the thermal characteristics of the memory component.
Table 14 Electrical Symbol ΘJC II,RSL IREF,RSL VOSW,DQ RTERM,DQ VOL,SI VOH,SI Parameter Junction-to-case thermal resistancea
The second section of parameters is concerned with the current needed by the RQ pins and VREF pin. The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced by the DQ pins when driving read data. This section is also concerned with the current needed by the VTERM pin, and with the resistance levels produced for the internal termination components that attach to the DQ pins. The fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals. Characteristics
Minimum -10 -10 0.200 40.0 0.0 VTERM,RSLb - 0.250 0.5 10 10 0.400 60.0 0.250 VTERM,RSLb Maximum Units °C/Watt µA µA V Ω V V
RSL RQ or Serial Interface input current @ (VIN=VIH,RQ,MAX) VREF,RSL current @ VREF,RSL,MAX flowing into VREF pin DRSL DQ outputs - high-low swing: VOSW,DQ = (VOH,DQ-VOL,DQN) or (VOH,DQN-VOL,DQ) DRSL DQ outputs - termination resistance RSL serial interface SDO output - low voltage RSL serial interface SDO output - high voltage
a. The package is mounted on a thermal test board which is defined JEDEC Standard JESD 51-9. b. VTERM,RSL is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component.
Data Sheet E1033E40 (Ver. 4.0) 60
EDX5116ADSE
Supply Current Profile
In this section, Table 15 summarizes the supply currents (IDD and ITERM,DRSL) that characterize this memory component.
Table 15 Supply Power State and Steady State Transaction Rates Device in PDN, self-refresh enabled. a Device in STBY. This is for a device in STBY with no packets on the Channela ACT command every tRR, PRE command every tPP a IDD,WR ACT command every tRR, PRE command every tPP, WR command every tCC.a IDD,RD ACT command every tRR, PRE command every tPP, RD command every tCCa ITERM,DRSL,WR ITERM,DRSL,RD WR command every tCC.b, RD command every tCC.b 145/85/55 250/140/85 145/85/55 250/140/85 mA mA 1180/1030/960 980/860/800 mA 1130/980/880 930/810/730 mA
These parameters are shown under different operating conditions.
Current Profile
Maximum @tCYCLE= 2.000 ns @ x16/x8/x4 width 30/30/30 300/300/300 Maximum @tCYCLE= 2.500 ns @ x16/x8/x4 width 25/25/25 250/250/250 Units
Symbol
IDD,PDN IDD,STBY IDD,ROW
mA mA
610/610/610
500/500/500
mA
a. IDD current @ VDD,MAX flowing into VDD pins
b. ITERM,DRSL current @ VTERM,DRSL,MAX flowing into VTERM pins
Data Sheet E1033E40 (Ver. 4.0) 61
EDX5116ADSE
Timing Characteristics
Table 16 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parameters that are speed-bin dependent. Refer to the Timing Parameters section for more information. The first section of parameters pertains to the timing of the DQ pins when driving read data.
Table 16 Timing Symbol tQ,DQ Parameter and Other Conditions DRSL DQ output delay (variation across 16 Q bits on each DQ pin) from drive points - output delay @ 2.500 ns > tCYCLE ≥ 2.000 ns @ 3.333 ns > tCYCLE ≥ 2.500 ns @ 3.830 ns ≥ tCYCLE ≥ 3.333 ns DRSL DQ output delay offset (a fixed value for all 16 Q bits on each DQ pin) from drive points - output delay DRSL DQ output - rise and fall times (20%-80%). Serial SCK-to-SDO output delay @ CLOAD,MAX = 15 pF -4000 -3200 tP,SI tOR,SI, tOF,SI tPDN-ENTRY tPDN-EXIT Serial SDI-to-SDO propagation delay @ CLOAD,MAX = 15 pF Serial SDO output rise/fall (20%-80%) @ CLOAD,MAX = 15 pF Time for power state to change after PDN entry Time for power state to change after PDN exit
The second section of parameters is concerned with the timing for the serial interface signals when driving register read data. The third section of parameters is concerned with the time intervals needed by the interface to transition between power states.
Characteristics
Minimum Maximum Units Figure(s)
-0.055 -0.065 -0.080
+0.055 +0.065 +0.080
ns ns ns
Figure 51
tQOFF,DQ tOR,DQ, tOF,DQ tQ,SI
0.000 0.020
+0.200 0.040
tCYCLE tCYCLE ns ns ns ns tCYCLE tCYCLE
Figure 51 Figure 51 Figure 53
2 2 0
12 15 15 10 16 -
Figure 53 Figure 53 Figure 36 Figure 36
Timing Parameters
Table 17 summarizes the timing parameters that characterize the core logic of this memory component. These timing parameters will vary as a function of the component’s speed
Table 17 Timing Symbol
tRC
bin. The four sections deal with the timing intervals between packets with, respectively, row-row commands, row-column commands, column-column commands, and column-row commands. Parameters
Min (A)
16 16 19 23
Parameter and Other Conditions
Row-cycle time: interval between tRC successive ROWA-ACT or tRC-R, 2tCC = tRCD-R + tCC+ tRDP + tRPa ROWP-REFA or ROWP-REFI tRC-W, 2tCC, noERAW = tRCD-W ,noERAW+ tCC+ tWRP + tRPa activate commands to the same tRC-W, 2tCC, ERAW = tRCD-W,ERAW + tCC+ tWRP + tRPa bank. Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command and a ROWP-PRE or ROWP-REFP precharge command to the same bank. Note that tRAS,MAX is 64 us for all timing bins. Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank. Precharge-to-precharge time: interval between successive ROWPPRE or ROWP-REFP precharge commands to different banks. tPP tPP-Db
Min (B)
20 20 24 28
Min (C)
24 24 24 28
Min (D)
30 30 30 34
Units
tCYCLE
Figure(s)
Figure 4 Figure 7
tRAS
10
13
17
21
tCYCLE
Figure 4 Figure 7 Figure 4 Figure 7 Figure 4 Figure 7
tRP tPP
6 4 1
7 4 1
7 4 1
9 4 1
tCYCLE tCYCLE
Data Sheet E1033E40 (Ver. 4.0) 62
EDX5116ADSE
Table 17 Timing Symbol
tRR
Parameters (Continued)
Min (A)
tRR tRR-Dc 4 4 5 1 5 6 3 2 3
Parameter and Other Conditions
Row-to-row time: interval between ROWA-ACT or ROWPREFA or ROWP-REFI activate commands to different banks.
Min (B)
4 4 7 3 7 7 3 2 3
Min (C)
4 4 7 3 7 7 3 2 3
Min (D)
4 4 9 5 9 8 3 2 3
Units
tCYCLE
Figure(s)
Figure 4 Figure 7 Figure 4 Figure 7 Figure 4 Figure 7 Figure 10 Figure 9 Figure 4 Figure 7 Figure 13
tRCD-R tRCD-W tCAC tCWD tCC tRW-BUB, XDRDRAM tWR-BUB, XDRDRAM t∆RW t∆WR
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COLRD read command to the same bank. Row-to-column-write delay: interval between a ROWA-ACT activate tRCD-W, noERAW command and a COL-WR or COL-WRM write command to the same bank. tRCD-W, ERAW Column access delay: interval from COL-RD read command to Q read data Column write delay: interval from a COL-WR or COLM-WRM write command to D write data. Column-to-column time: interval between successive COL-RD commands, or between successive COL-WR or COLM-WRM commands. Read-to-write bubble time: interval between the end of a Q read data packet and the start of D write data packet (the end of a data packet is the time interval tCC after its start). Write-to-read bubble time: interval between the end of a D writed data and the start of Q read data packet (the end of a data packet is the time interval tCC after its start). Read-to-write time: interval between a COL-RD read command and a COL-WR or COLMWRM write command.d Write-to-read time: interval between a COL-WR or COLM-WRM write command and a COL-RD read command. t∆WR t∆WR-De
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
3 8
3 9
3 9
4 10
Figure 13 Figure 12
9 2 3 10 6 7 16 16 16
10 2 4 12 7 9 20 20 20
10 2 4 12 7 9 24 24 24
10 2 6 14 7 11 24 24 24
Figure 12 Figure 44 Figure 4 Figure 7 Figure 4 Figure 7 Figure 12 Figure 9 Table 4 Table 4 Table 4
tRDP tWRP tDR tDP tLRRn-LRRn tREFx-LRRn tLRRn-REFx
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE precharge command to the same bank. Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a ROWP-PRE precharge command to the same bank. Write data-to-read time: interval between the start of D write data and a COL-RD read command to the same bank. Write data-to-precharge time: interval between D write data and ROWP-PRE precharge command to the same bank. Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command. f Interval between ROWP-REFx command and a subsequent ROWP-LRRn command. Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
a. The tRC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon how many column accesses (each requiring tCC) are performed in each row access (tRC). The table lists the special cases (tRC-R, 2tCC, tRC-W, 2tCC, noERAW, tRC-W, 2tCC, ERAW) in which two column accesses are performed in each row access. All other parameters are minimum. b. tPP-D is the tPP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 57. c. tRR-D is the tRR parameter for activates to different bank sets. See “Simultaneous Activation” on page 56. d. See “Propagation Delay” on page 28. e. t∆WR-D is the t∆WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 54. Also, note that the value of t∆WR-D may not take on the values {3,5,7} within the range{t∆WR-D,MIN, ... t∆WR,MIN-1}. t∆WR-D may assume any value ≥t∆WR,MIN. f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,ROWP-LRR2} ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,ROWP-REFP}
Data Sheet E1033E40 (Ver. 4.0) 63
EDX5116ADSE
Receive/Transmit Timing
Clocking
Figure 48 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magnified view of these pins. This diagram shows only one clock cycle. CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals — a low voltage represents a logical zero and a high voltage represents a logical one. There are two crossing points in each clock cycle. The primary crossing point includes the high-voltage-to-lowvoltage transition of CFM (indicated with the arrowhead in the
Figure 48 Clocking Waveforms
diagram). The secondary crossing point includes the low-voltage-to-high-voltage transition of CFM. All timing events on the RSL signals are referenced to the first set of edges. Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram, this is how the clock-cycle time (tCYCLE or tCYC,CFM), clock-low time (tL,CFM) and clock-high time (tH,CFM) are measured. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR,CFM) and fall time (tF,CFM) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL,CFM + 0.2*(VIH,CFM-VIL,CFM) 80% = VIL,CFM + 0.8*(VIH,CFM-VIL,CFM)
tCYCLE or tCYC,CFM tL,CFM CFM tH,CFM logic 1 VIH,CFM 80%
CFMN
20% VIL,CFM logic 0 tR,CFM tF,CFM
Data Sheet E1033E40 (Ver. 4.0) 64
EDX5116ADSE
RSL RQ Receive Timing
Figure 49 shows a timing diagram for the RQ11..0 request pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition. The RQ11..0 signals are low-true: a high voltage represents a logical zero and a low voltage represents a logical one. Timing events on the RQ11..0 pins are measured to and from the point that the signal reaches the level of the reference voltage VREF,RSL. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR,RQ)
Figure 49 RSL RQ Receive Waveforms
and fall time (tF,RQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL,RQ + 0.2*(VIH,RQ-VIL,RQ) 80% = VIL,RQ + 0.8*(VIH,RQ-VIL,RQ) There are two data receiving windows defined for each RQ11..0 signal. The first of these (labeled “0”) has a set time, tS,RQ , and a hold time, tH,RQ , measured around the primary CFM/CFMN crossing point. The second (labeled “1”) has a set time (tS,RQ) and a hold time (tH,RQ) measured around a point 0.5*tCYCLE after the primary CFM/CFMN crossing point.
tCYCLE CFM
CFMN [1/2]•tCYCLE tS,RQ tH,RQ tS,RQ tH,RQ logic 0 VIH,RQ 80% VREF,RSL 20% VIL,RQ logic1
RQ0
0
1
tR,RQ
tF,RQ
...
[1/2]•tCYCLE tS,RQ tH,RQ tS,RQ tH,RQ logic 0 VIH,RQ 80% VREF,RSL 20% VIL,RQ logic 1
RQ11
0
1
tR,RQ
tF,RQ
Data Sheet E1033E40 (Ver. 4.0) 65
EDX5116ADSE
DRSL DQ Receive Timing
Figure 50 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/ CFMN crossing point in which CFM makes its high-voltageto-low-voltage transition. The DQ15..0/DQN15..0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also differential — timing events on the DQ15..0/DQN15..0 pins are measured to and from the point that each differential pair crosses. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tIR,DQ) and fall time (tIF,DQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL,DQ + 0.2*(VIH,DQ-VIL,DQ) 80% = VIL,DQ + 0.8*(VIH,DQ-VIL,DQ) There are 16 data receiving windows defined for each DQ15..0/DQN15..0 pin pair. The receiving windows for a particular DQi/DQNi pin pair is referenced to an offset parameter tDOFF,DQi (the index “i” may take on the values {0, 1, ..15} and refers to each of the DQ15..0/DQN15..0 pin pairs). The tDOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin pair. The 16 receiving windows are placed at times tDOFF,DQi+(j/8)*tCYCLE (the index “j” may take on the values {0,1, 2, ..15} and refers to each of the receiving windows for the DQi/DQNi pin pair). The offset values tDOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range {tDOFF,MIN ,tDOFF,MAX}. Furthermore, each offset value tDOFF,DQi is static and will not change during system operation. Its value can be determined at initialization. The 16 receiving windows (j=0..15) for the first pair DQ0/ DQN0 are labeled “0” through “15”. Each window has a set time (tS,DQ) and a hold time (tH,DQ) measured around a point tDOFF,DQ0+(j/8)*tCYCLE after the primary CFM/CFMN crossing point. The 16 receiving windows (j=0..15) for each of the other pairs DQi/DQNi are also labeled “0” through “15”. Each window has a set time (tS,DQ) and a hold time (tH,DQ) measured around a point tDOFF,DQi+(j/8)*tCYCLE after the primary CFM/ CFMN crossing point.
Data Sheet E1033E40 (Ver. 4.0) 66
EDX5116ADSE
Figure 50 DRSL DQ Receive Waveforms
tCYCLE CFM
...
tDOFF,MAX tDOFF,MIN tDOFF,DQ0 i = {0,1,2,3,4,5,...15} j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
CFMN
[(j)/8]•tCYCLE tS,DQ tH,DQ logic 1 VIH,DQ 80%
14 15
DQ0
0 1 2 3 4 5 6
...
j
...
DQN0 tIR,DQ tIF,DQ
20% VIL,DQ logic 0
...
tDOFF,DQi
[(j)/8]•tCYCLE tS,DQ tH,DQ logic 1 VIH,DQ 80%
14 15
DQi
0 1 2 3 4 5 6
...
j
...
DQNi tIR,DQ tIF,DQ
20% VIL,DQ logic 0
...
tDOFF,DQ15 [(j)/8]•tCYCLE tS,DQ tH,DQ logic 1 ” VIH,DQ 80%
14 15
DQ15
0 1 2 3 4 5 6
...
j
...
DQN15 tIR,DQ tIF,DQ
20% VIL,DQ logic 0
Data Sheet E1033E40 (Ver. 4.0) 67
EDX5116ADSE
DRSL DQ Transmit Timing
Figure 51 shows a timing diagram for transmitting read data on the DQ15..0/DQN15..0 data pins of the memory component. This diagram represents a magnified view of these pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition. The DQ15..0/ DQN15..0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also differential — timing events on the DQ15..0/DQN15..0 pins are measured to and from the point that each differential pair crosses. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tOR,DQ) and fall time (tOF,DQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VOL,DQ + 0.2*(VOH,DQ-VOL,DQ ) 80% = VOL,DQ + 0.8*(VOH,DQ-VOL,DQ ) There are 16 data transmitting windows defined for each DQ15..0/DQN15..0 pin pair. The transmitting windows for a particular DQi/DQNi pin pair are referenced to an offset parameter tQOFF,DQi (the index “i” may take on the values {0, 1, ..15} and refers to each of the DQ15..0/DQN15..0 pin pairs). The tQOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin pair. The offset values tQOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range {tQOFF,MIN ,tQOFF,MAX}. Furthermore, each offset value tQOFF,DQi is static; its value will not change during system operation. Its value can be determined at initialization time. The 16 transmitting windows (j=0..15) for the first pair DQ0/ DQN0 are labeled “0” through “15”. Each window begins at the time (tQOFF,DQ0+tQ,DQ,MAX+((j - 0.5)/8)*tCYCLE ) and ends at the time (tQOFF,DQ0+tQ,DQ,MIN+((j+0.5)/8)*tCYCLE ) measured after the primary CFM/CFMN crossing point. The 16 transmitting windows (j=0..15) for the other pairs DQi/DQNi are also labeled “0” through “15”. Each window begins at the time (tQOFF,DQi+tQ,DQ,MAX+((j - 0.5)/8)*tCYCLE ) and ends at the time (tQOFF,DQi+tQ,DQ,MIN+((j+0.5)/ 8)*tCYCLE ) measured after the primary CFM/CFMN crossing point. Note that when no read data is to be transmitted on the DQ/ DQN pins (and no other component is transmitting on the external DQ/DQN wires), then the voltage level on the DQ/ DQN pins will follow the voltage reference value VTERM,DRSL on the VTERM pin. The logical value of each DQ/DQN pin pair in this no-drive state will be “1/1”; when read data is driven, each DQ/DQN pin pair will have either the logical value of “1/0” or “0/1”.
Data Sheet E1033E40 (Ver. 4.0) 68
EDX5116ADSE
Figure 51 DRSL DQ Transmit Waveforms
tCYCLE CFM
...
tQOFF,MAX tQOFF,MIN tQOFF,DQ0 [(j+0.5)/8]•tCYCLE [(j-0.5)/8]•tCYCLE tQ,DQ,MAX tQ,DQ,MIN logic “1” VOH,DQ 80%
15
CFMN i = {0,1,2,3,4,5,...15} j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
DQ0
0 1 2 3 4 5 6 7
...
j
...
14
DQN0 tOR,DQ tOF,DQ
20% VOL,DQ logic “0”
...
tQOFF,DQi
[(j+0.5)/8]•tCYCLE [(j-0.5)/8]•tCYCLE tQ,DQ,MAX tQ,DQ,MIN logic “1” VOH,DQ 80%
15
DQi
0 1 2 3 4 5 6 7
...
j
...
14
DQni tOR,DQ tOF,DQ
20% VOL,DQ logic “0”
...
tQOFF,DQ15
[(j+0.5)/8]•tCYCLE [(j-0.5)/8]•tCYCLE tQ,DQ,MAX tQ,DQ,MIN logic “1” VOH,DQ 80%
15
DQ15
0 1 2 3 4 5 6 7
...
j
...
14
DQN15 tOR,DQ tOF,DQ
20% VOL,DQ logic “0”
Data Sheet E1033E40 (Ver. 4.0) 69
EDX5116ADSE
Serial Interface Receive Timing
Figure 52 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins only a few clock cycles. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tR,SCK and tIR,SI) and fall time (tF,SCK and tIF,SI) of the signals
Figure 52 Serial Interface Receive Waveforms
are measured from the 20% and 80% points of the full-swing levels. 20% = VIL,SI + 0.2*(VIH,SI-VIL,SI) 50% = VIL,SI + 0.5*(VIH,SI-VIL,SI) 80% = VIL,SI + 0.8*(VIH,SI-VIL,SI) There is one receiving window defined for each serial interface signal (RST,CMD and SDI pins). This window has a set time (tS,RQ) and a hold time (tH,RQ) measured around the falling edge of the SCK clock signal.
tCYC,SCK tL,SCK tH,SCK logic 0 VIH,SI 80% SCK VREF,RSL 20% VIL,SI tF,SCK tR,SCK logic 1
tS,SI
tH,SI
logic 0 VIH,SI 80% VREF,RSL 20% VIL,SI
RST CMD SDI tIR,SI tIF,SI
logic 1
Data Sheet E1033E40 (Ver. 4.0) 70
EDX5116ADSE
Serial Interface Transmit Timing
Figure 53 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. Timing events are measured to and from the VREF,RSL level. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tOR,SI) and fall time (tOF,SI) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VOL,SI + 0.2*(VOH,SI-VOL,SI) 50% = VOL,SI + 0.5*(VOH,SI-VOL,SI) 80% = VOL,SI + 0.8*(VOH,SI-VOL,SI)
Serial Interface Transmit Waveforms
There is one transmit window defined for the serial interface data signal (SDO pins). This window has a maximum delay time (tQ,SI,MAX) from the falling edge of the SCK clock signal and a minimum delay time (tQ,SI,MIN) from the next falling edge of the SCK clock signal. When the memory component is not selected during a serial device read transaction, it will simply pass the information on the SDI input to the SDO output. This combinational propagation delay parameter is tP,SI. The tCYC,SCK will need to be increased during a serial read transaction (relative to the tCYC,SCK value for a serial write transaction) because of the accumulated propagation delay through all of the XDR DRAM devices on the serial interface. During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the tCYC,SCK value can be set to the same value as for serial write transactions. See “Initialization” on page 46.
Figure 53
tCYC,SCK tL,SCK tH,SCK logic 0 VIH,SI 80% VREF,RSL 20% VIL,SI tR,SCK tQ,SI,MAX tP,SI SDO tQ,SI,MIN logic 1
SCK
tF,SCK
logic 0 VOH,SI 80% VREF,RSL 20% VOL,SI
tOR,SI
tOF,SI
logic 1
Combinational propagation from SDI to SDO when the device is not selected during a serial device read transaction.
logic 0 VIH,SI 80% VREF,RSL 20% VIL,SI logic 1
SDI
Data Sheet E1033E40 (Ver. 4.0) 71
EDX5116ADSE
Package Description
Package Parasitic Summary
Table 18 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory component. Most of the parameters have maximum values only, however some have both maximum and minimum values. The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance
values. The second group of parameters are for the RQ request pins. They include inductance, mutual inductance, capacitance, and resistance values. There are also limits on the spread in inductance and capacitance values allowed in any one memory component. The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance, capacitance, and resistance values. There are also limits on the spread in inductance and capacitance values allowed in any one memory component.The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values.
Table 18 Package Parasitic Summary (package parasitic values are measured on randomly-sampled devices)
Symbol LVTERM LI ,CFM CI ,CFM RI ,CFM LI ,RQ CI ,RQ RI ,RQ L12,RQ ∆LI,RQ ∆CI,RQ ZPKG,DQ CI ,DQ ∆CI,DQ RI ,DQ LI ,SI CI ,SI Parameter and Other Conditions VTERM pin - effective input inductance per four bits CFM/CFMN pins - effective input inductanceb CFM/CFMN pins - effective input capacitanceb CFM/CFMN pins - effective input resistance RSL RQ pins - effective input inductanceb RSL RQ pins - effective input capacitanceb RSL RQ pins - effective input resistance Mutual inductance between adjacent RSL RQ signals Difference in LI,RQ between any RSL RQ pins of a single device Difference in CI between CFM/CFMN average and RSL RQ pins of single device DRSL DQ pins - package differential impedance note - package trace length should be less than 10mm long. DRSL DQ pins - effective input capacitancea Difference in CI between DQi and DQNi of each DRSL paira DRSL DQ pins - effective input resistance Serial Interface effective input inductanceb Serial Interface effective input capacitanceb (RST, SCK, CMD) (SDI,SDO) Minimum 1.8 4 1.8 4 -0.12 70 4 1.7 Maximum 2.2 5.0 2.4 18 5.0 2.4 18 1.8 1.8 +0.12 130 1.8 0.06 40 8.0 3.0 7.0 Units nH nH pF Ω nH pF Ω nH nH pF Ω pF pF Ω nH pF pF
a. This is the effective die input capacitance, and does not include package capacitance. b. CFM/RQ/SI should include package capacitance / Inductance, only DQ does not include package Capacitance. This value is a combination of the device IO circuitry and package capacitance & inductance.
Data Sheet E1033E40 (Ver. 4.0) 72
EDX5116ADSE
Figure 54 Equivalent Circuits for Package Parasitic Pad RQ Pin LI,RQ CI,RQ L12,RQ RI,RQ RQ Pin GND Pin L12,RQ RQ Pin
Pad Pad
ZPKG,DQ/2 ZPKG,DQ/2
DQ Pin DQN Pin
CI,DQ RI,DQ
CI,DQ RI,DQ RTERM,DQ RTERM,DQ GND Pin
Pad
Pad
LI,CFM CFM Pin LI,CFM
CI,CFM
CI,CFM
CFMN Pin
RI,CFM
RI,CFM GND Pin
Pad
LI,SI SCK,CMD,RST Pin SDI,SDO Pin CI,SI GND Pin
Data Sheet E1033E40 (Ver. 4.0) 73
EDX5116ADSE
Package Drawing
104-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm 14.56 ± 0.1 INDEX MARK 0.2 S B
15.18 ± 0.1
0.2 S A 0.10 S 1.05 ± 0.1 S 0.40 ± 0.05
0.10 S
B 104-φ0.50 ± 0.05 φ0.12 M S A B
INDEX MARK
2.0 12.0
0.8
12.7 ECA-TS2-0206-01
A
Data Sheet E1033E40 (Ver. 4.0) 74
1.27
EDX5116ADSE
Package Pin Numbering
Figure 55 summarizes the device package’s pin assignments.
Figure 55 CSP x16 Package - Pin Numbering (top view)
L not used when width is x1,x2,x4 1 DQN3
K
1J P N DQ5
VDD VDD
H 2
G 3 VDD
F 4
E 5 GND
D 6
C 7
B
A not used when width is x1,x2,x4 DQN2
DQN9
DQ5N VDD
RQ10
GND
DQ7N VTERM
VDD
DQ7
GND
SDI
DQN8
2
DQ3
DQ9
DQ8
DQ2
not used when width is x1DQN15 3
4 DQ15
GND
VDD
GND
RQ0 DQN4
DQN5
CFM
RSRV
RQ4
not used when DQN14 width is x1,x2
DQ14
M
DQ5 VDD VDD
DQ1
GND
DQ1N
RQ11 CFMN RSRV
DQ3N
RQ3
DQ3
GND DQ4
5
L K J H G F
GND VDD VDD
VTERM
RQ10 RQ8 GND RQ6 RQ4 RQ2 RQ0
GND VDD GND
VDD
RQ11
VDD
GND VDD GND CFM GND VDD
VTERM
VDD
VDD
6
GND
GND
GND
RQ9 VDD RQ7 CFMN RQ5 RQ3
GND
GND
7
8
VREF GND VDD GND
GND
9
10
11
GND
VTERM
GND
GND
VDD
VTERM
GND
12
VDD
GND
E D C B A
RST
VDD
RQ1
RQ7 VREF
GND
GND GND VDD
13
DQN7
DQN13
SD0 VDD
CMD DQ0
CMD RQ9
RQ8 DQ0N
SCK RQ1
RQ2 DQ2N
SDI VDD
GND DQ2
DQN12
not used when DQN6 width is x1,x2
DQ6
14
DQ7
DQ13
RQ6
RQ5
DQ12
not15 used when width is x1,x2,x4
16 DQ11
DQN11
DQN1
SCK GND GND
VDD DQ4N
VDD VDD GND
VTERM DQ6N
VDD
RST GND SDO
DQN0
DQ1
DQ4
DQ6
DQ0
not used when width is x1,x2,x4
DQ10
DQN10
A16
A8
Data Sheet E1033E40 (Ver. 4.0) 75
EDX5116ADSE
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDX5116ADSE. Type of Surface Mount Device EDX5116ADSE: 104-ball FBGA < Lead free (Sn-Ag-Cu) >
Data Sheet E1033E40 (Ver. 4.0) 76
EDX5116ADSE
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E1033E40 (Ver. 4.0) 77
EDX5116ADSE
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No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1033E40 (Ver. 4.0) 78
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