HB56UW873E-F

HB56UW873E-F 64MB Buffered EDO DRAM DIMM 8-Mword × 72-bit, 4k Refresh, 1 Bank Module (9 pcs of 8M × 8 components) EO Description Features E0102H10 (1st edition) (Previous ADE-203-1125B (Z)) Jan. 31, 2001 The HB 56UW 873E belongs to 8 B yte DI MM (D ual In- line Memory Module) fa mily, and has bee n deve loped as an optimiz ed main memory solution for 4 and 8 B yte proc essor applica tions. The HB 56UW 873E is a 8M × 72 dynamic RAM module, mounted 9 pieces of 64-Mbit DRAM (HM5165805) sealed in TSOP package and 2 piec es of 16-bit line drive r sea led in TS SOP pac kage . The HB 56UW 873E off ers Extende d Da ta Out (ED O) Page Mode as a high speed access mode. An outline of the HB56UW873E is 168-pin socket type package (dual lea d out). The ref ore, the HB 56UW 873E make s high density mounting possible without surf ace mount tec hnology. The HB 56UW 873E provide s common data inputs and outputs. De coupling ca pac itor s ar e mounted beside each TSOP on the its module board. • 168-pin socket type package (Dual lead out)  Lead pitch: 1.27 mm • Single 3.3 V supply: 3.3V ± 0.3V • High speed  Access time: tRAC = 50/60 ns (max)  Access time: tCAC = 18/20 ns (max) • Low power dissipation  Active mode: 4.41 W/3.76 W (max)  Standby mode (TTL): 100.8 mW (max) • Buffered input except RAS and DQ • 4 byte interleave enabled, dual address input (A0/B0) • EDO page mode capability • 4,096 refresh cycle: 64 ms Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. L This Product become EOL in August, 2005. Pr uc od t HB56UW873E-F • 2 variations of refresh  RAS -only refresh  CAS -before-RAS refresh EO Ordering Information Type No. HB56UW873E-5F HB56UW873E-6F 50 ns 60 ns Access time Package 168-pin dual lead out socket type Contact pad Gold Pin Arrangement L 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin Pr Pin name VSS Pin No. 85 VSS OE2 RE2 CE4 NC WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC 86 87 88 89 DQ36 DQ37 DQ38 DQ39 VCC 90 91 92 93 DQ40 DQ41 DQ42 94 95 DQ43 DQ44 VSS 96 97 98 99 DQ45 DQ46 DQ47 DQ48 100 101 DQ49 168 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pin name Pin No. 127 128 129 130 Pin name VSS NC NC NC Data Sheet E0102H10 2 uc od 131 NC 132 PDE 133 VCC 134 135 NC NC 136 137 DQ54 DQ55 VSS 138 139 140 141 142 DQ56 DQ57 DQ58 DQ59 VCC 143 t HB56UW873E-F Pin Arrangement (cont) Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name VCC Pin No. 60 Pin name DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS Pin No. 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Pin name VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC Pin No. 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 Pin name DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 EO DQ14 DQ15 DQ16 DQ17 VSS 61 62 63 64 65 NC NC 66 67 VCC WE0 CE0 NC RE0 OE0 VSS A0 A2 A4 A6 A8 A10 NC VCC NC NC 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 L DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 (VSS ) VCC Data Sheet E0102H10 3 Pr 116 VSS 117 118 119 A1 A3 A5 120 A7 121 122 123 A9 A11 NC 124 VCC NC 125 126 B0 uc od 165 PD6 166 PD8 167 ID1 (VSS ) 168 VCC t HB56UW873E-F Pin Description Pin name Function Address input (D0 to D8) : Row address (D0 to D8) : Column address (D0 to D8) : Refresh address (D0 to D8) : Data-in/Data-out Row address strobe (RAS ) Column address strobe (CAS ) Read/Write enable Output enable A0 to A11, B0 A0 to A11, B0 A0 to A10, B0 A0 to A11, B0 EO A0 to A11, B0 DQ0 to DQ71 RE0 , RE2 CE0 , CE4 WE0 , WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC Presence Detect Pin Assignment Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Pin No. 79 163 80 164 81 165 82 166 1 : High level (driver output) 0 : Low level (driver output) L Ground ID bit 50 ns 1 0 1 1 1 0 0 0 Power supply Presence detect Presence detect enable Data Sheet E0102H10 4 Pr No connection PDE = Low 60 ns 1 0 1 1 1 1 1 0 PDE = High All uc od High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z t HB56UW873E-F Block Diagram EO RE0 CE0 WE0  OE0 DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 A0 B0 A1 to A11 VCC VSS 0.22 µF × 11 pcs RE2 CE4 WE2 OE2 OE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 OE CAS RAS WE I/O I/O I/O D5 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D6 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D7 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D8 I/O I/O I/O I/O I/O OE CAS RAS WE I/O I/O I/O D0 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D1 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D2 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D3 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D4 I/O I/O I/O I/O I/O L D0 to D4 D5 to D8 D0 to D8 OE Data Sheet E0102H10 5 Pr DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 OE DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 OE PD1 to PD8 VCC VSS VCC VCC VCC VCC VSS VCC VSS VSS D0 to D8, 16-bit line driver D0 to D8,16-bit line driver * D0 to D8 OE OE uc od PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 : HM5165805 : 16-bit line driver t HB56UW873E-F Absolute Maximum Ratings EO Parameter Power supply voltage relative to VSS Short circuit output current Power dissipation Storage temperature range Symbol VT VCC Iout Pt Tstg Value –0.5 to +4.6 –0.5 to +4.6 50 10 –55 to +125 Unit V V mA W °C Terminal voltage on any pin relative to VSS DC Operating Conditions Parameter Supply voltage L VCC VSS VIH VIL Ta Symbol Min 3.0 0 2.0 –0.3 Typ 3.3 0 — — Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V °C Notes 1, 2 2 1 1 Input high voltage Input low voltage Ambient temperature range Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Data Sheet E0102H10 6 Pr 0 — uc od t HB56UW873E-F DC Characteristics EO Parameter Operating current Standby current I CC1 I CC2 RAS -only refresh current Standby current CAS -before-RAS refresh current EDO page mode current Input leakage current I CC3 I CC5 I CC6 I CC7 I LI Output leakage current I LO Output high voltage Output low voltage VOH VOL 0 Parameter Input capacitance (Address) Input capacitance (CAS , WE, OE) Input capacitance (RAS ) I/O capacitance (DQ) HB56UW873E 50 ns Max 1225 28 60 ns Min — — Max 1045 28 Unit mA mA Test conditions t RC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min 0 V ≤ Vin ≤ VCC + 0.3 V 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Low Iout = 2 mA 1, 3 2 1 Notes 1, 2 Symbol Min — — — 14.5 — 14.5 mA Notes: 1. I CC depends on output load condition when the device is selected, I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Symbol CI1 CI2 CI3 CI/O Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. L — — — — –5 –5 2.4 1225 55 1225 1000 5 5 VCC 0.4 — — — — 1045 55 1045 910 5 5 mA mA mA mA µA µA Data Sheet E0102H10 7 Pr –5 –5 2.4 0 VCC 0.4 V V Typ — — — — 20 20 55 20 uc od Max Unit pF pF pF Notes 1 1 1 pF 1, 2 t HB56UW873E-F AC Characteristics (Ta = 0 to 70°C, VCC = 3.3 V ±0.3 V, VSS = 0 V)*1, *2, *19 EO Test Conditions • • • • • Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) 8 Input rise and fall times: 2 ns Input levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) L t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 50 ns Max — — — 60 ns Min 104 40 10 Max — — — 10000 10000 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes Symbol Min 84 30 8 Data Sheet E0102H10 Pr 50 8 5 8 0 8 10000 10000 60 10 — 5 — 10 — 0 — 10 14 12 20 40 10 20 12 10 18 38 10 18 0 0 2 32 20 — — — — — — 0 0 50 2 uc od 40 25 — — — — 3 4 5 — — ns ns 6 6 50 ns 7 t HB56UW873E-F Read Cycle 50 ns Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH — — — — 0 0 50 0 30 15 2 3 3 Max 50 18 30 18 — — — — — — — — — 60 ns Min — — — — 0 0 60 0 35 18 2 3 3 Max 60 20 35 20 — — — — — — — — — 20 20 — — 15 20 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 EO Parameter Access time from RAS Access time from CAS Access time from OE Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Read command hold time from RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time L t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t WCS t WCH t WP t RWL t CWL t DS t DH Pr — — 18 18 — — — 18 3 20 — 3 — — 18 13 13 18 — — — — 20 15 50 ns 60 ns Symbol Min 0 8 8 18 8 0 13 Max — Min 0 — — — — 10 10 20 10 — 0 — 15 Data Sheet E0102H10 uc od Max — Unit ns Notes 14 — — — — ns ns ns ns — ns 15 Write Cycle Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time t 9 — ns 15 HB56UW873E-F Read-Modify-Write Cycle 50 ns Symbol Min t RWC t RWD t CWD t AWD t OEH 116 72 30 42 13 Max — — — — — 60 ns Min 140 84 34 49 15 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes EO Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time OE hold time from WE Column address to WE delay time L t CSR t CHR t WRP t WRH t RPC t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC t OEP Refresh Cycle 50 ns Max — — 60 ns Min 10 10 Max — — — — — Unit ns ns ns ns ns Notes Parameter Symbol Min 10 8 5 8 5 CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Pr — 5 — 10 — 5 50 ns 60 ns Symbol Min 20 — — 33 3 8 5 28 8 8 Max — Min 25 100000 — 33 — — — — 40 3 10 — 5 — — — 35 10 10 Data Sheet E0102H10 EDO Page Mode Cycle uc od Max — Unit ns Notes 20 100000 ns ns ns 16 40 — 9, 17 — ns 9, 22 — ns — ns — — — ns ns ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Write pulse width during CAS precharge t WPE OE precharge time t 10 HB56UW873E-F EDO Page Mode Read-Modify-Write Cycle 50 ns Symbol Min t HPRWC t CPW 57 45 Max — — 60 ns Min 68 54 Max — — Unit ns ns 14 Notes EO Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Refresh Parameter Symbol t REF Max 64 Unit ms Notes 4096 cycles L Refresh period Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max). 11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. Data Sheet E0102H10 11 Pr uc od t HB56UW873E-F 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. EO 12 L Data Sheet E0102H10 Pr uc od t HB56UW873E-F Timing Waveform *23 ; tDZO tOEA tOED OE tCAC tAA tRAC tCLZ tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout Data Sheet E0102H10 13 EO Read Cycle RAS tT CAS tASR tRAH Address Row WE Din tRC tRAS tRP tCSH tRCD tRSH tCAS tCRP L tRAD tASC tRCS tDZC tRAL tCAL tCAH Pr Column tRCHR tRCH High-Z tRRH uc od tCDD tWED tRDD t HB56UW873E-F Early Write Cycle EO RAS tT CAS tASR tRAH Address Row WE Din Dout 14 tRC tRAS tRP tCSH tRCD tRSH tCAS tCRP L tASC tWCS tDS tCAH Data Sheet E0102H10 Pr Column tWCH uc od High-Z* * t WCS t WCS (min) tDH Din t HB56UW873E-F Delayed Write Cycle*18 ; tDZO tOED tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout Data Sheet E0102H10 EO RAS tT CAS tASR tRAH Address Row WE Din tRC tRAS tRP tCSH tRCD tRSH tCAS tCRP L tASC tRCS tDZC High-Z tCAH Column Pr tCWL tRWL tWP uc od tDS tDH Din t 15 HB56UW873E-F Read-Modify-Write Cycle*18 ; tDZO tOED tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0102H10 16 EO RAS tT CAS tASR tRAH Address Row WE Din tRWC tRAS tRP tRCD tCAS tCRP L tRAD tASC tRCS tDZC tCAH Column Pr tCWD tAWD tRWD tDS High-Z tCWL tRWL tWP tDH uc od Din t HB56UW873E-F RAS-Only Refresh Cycle ; EO RAS tRC tRAS tRP tT tRPC tCRP tCRP CAS L tASR tRAH Row tOFR tOFF Address Pr High-Z Dout Data Sheet E0102H10 17 uc od t HB56UW873E-F CAS-Before-RAS Refresh Cycle ; 18 EO tRP RAS tRPC tCP CAS WE Address tOFR tOFF Dout tRC tRAS tRP tRAS tRC tRP tT tRPC tCHR tCP tCSR tCHR tCRP tCSR L tWRP tWRH High-Z Data Sheet E0102H10 tWRP tWRH Pr uc od t HB56UW873E-F EDO Page Mode Read Cycle (1) ; tWEZ tCAC tRAC tOEA tDOH tOHO tOEA Dout EO RAS t RP t RASP t CP t HPC t CAS t RCH t RCS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP tT t CSH RSH CAS t CAS tCAS t RRH t RCH t RCS t RCHR WE tASR Address tRAH tASC Row tCAH t WPE t ASC t CAH Column 2 t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 tDZC Din tDZO L Column 1 t CAL High-Z tOEA tCAC tAA tCPA Dout 1 t WED t CAL t CAL tRDD tCDD Pr tCOL t OEP tAA tCAC tOEZ tOHO tCPA tAA tCAC Dout 2 Dout 2 tCOP tOED tOEP OE tCPA tAA tOEZ tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0102H10 19 uc od Dout 3 Dout 4 t HB56UW873E-F EDO Page Mode Read Cycle (2) ; tOHO tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA Dout EO RAS t RP t RASP t HPC t CAS tHPC t CP t CAS t RCHC t CP t HPC tRSH tCAS t RRH t RCH t CRP tT t CSH t CP CAS t CAS t RCS WE tASR Address tRAH tASC Row tDZC L tCAH Column 1 t CAL Column 2 High-Z tOEA tCAC tAA tCPA Dout 1 t ASC t CAH t ASC t CAH Column 3 t CAL t CAL tASC t RAL t CAH Column 4 t WED t CAL tRDD tCDD Pr tCOL t OEP tAA tCAC tOEZ tCPA tAA tCAC Dout 2 Dout 2 Din tDZO tCOP tOED tOEP OE tCPA tAA tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0102H10 20 uc od Dout 3 Dout 4 t HB56UW873E-F EDO Page Mode Early Write Cycle EO RAS tT tRCD CAS tASR tRAH Address Row WE Din Dout tRASP tRP tCSH tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP L tASC tCAH Column 1 tWCS tWCH tDS tDH Din 1 tASC tCAH tASC tCAH Column 2 Column N Data Sheet E0102H10 21 Pr tWCS tWCH tDS tDH Din 2 High-Z* tWCS tWCH uc od tDS tDH Din N * t WCS t WCS (min) t HB56UW873E-F EDO Page Mode Delayed Write Cycle*18 ; OE tCLZ tCLZ tCLZ tOEZ tOEZ EO RAS tT tRCD CAS tRAD tASR tRAH tRASP tRP tCP tCAS tHPC tCAS tCP tRSH tCAS tCRP tCSH Address Row L tASC tCAH tASC tCAH tASC tCAH Column 1 tCWL Column 2 tCWL Column N tCWL tRWL Pr tRCS tRCS tWP tDZC tDS tDH tDH tRCS WE tWP tDZC tDS tWP tDZC tDS tDH uc od Din 2 Din N tOED tOEP tOEH Din tDZO tOED Din 1 tDZO tOEP tOEH tDZO tOED tOEP tOEH tOEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout t Data Sheet E0102H10 22 HB56UW873E-F EDO Page Mode Read-Modify-Write Cycle *18 ; ; t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z EO RAS tT t RCD CAS t RASP t RP t HPRWC t CP t CAS t CAS t CP t RSH t CRP t CAS L t RAD t CAH Column 1 t ASR t ASC t RAH Row t ASC t CAH Column 2 t ASC t CAH Column N Address t RWD t AWD t CWD WE t RCS t WP t DS t DZC Pr t CWL t CPW t CWL t RCS t CPW t AWD t CWD t CWL t RWL t AWD t CWD t RCS t WP t DS t DZC t WP t DS t DZC uc od t DH t DH Din 2 Din N t OEP t OEH t DH Din t DZO t OED t OEP t OEH Din 1 t DZO t OED t DZO t OED t OEP t OEH OE t OHO t OHO t OHO Dout Dout 1 Dout 2 Dout N t 23 Data Sheet E0102H10 HB56UW873E-F EDO Page Mode Mix Cycle (1) *20 ; tOEP tWED OE EO RAS t RP t RASP t CRP tCAS tCWL t RCS tCPW tAWD tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL t DS t DH tRDD tCDD t RCS tRSH t RRH t RCH tT t CP t CAS t CP tCAS t CP CAS t CAS t CSH t RCD t WCS t WCH L tCAH Column 1 Column 2 t DH Din 1 WE tASR Address t ASC tRAH Row t ASC t CAH tASC t CAL t DS Din Pr High-Z tOED tCPA tAA tOEA tCPA tAA tCAC t DOH Dout 2 Dout 3 Din 3 tCPA t OEZ tAA tOFR tWEZ tOEZ uc od tCAC tOHO tOFF tOH tCAC t OHO tOEA Dout 4 Dout t Data Sheet E0102H10 24 HB56UW873E-F EDO Page Mode Mix Cycle (2) *20 EO RAS t RP t RASP tT t CSH t CP t CAS t CP tCAS tCWL t RCS tCPW t ASC t CAH Column 3 t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS t DH tRSH t CRP CAS t CAS t RCD t RCHR t RCS t RCH tWCS t WCH t RRH t RCH WE tASR Address t ASC tRAH Row L tCAH Column 1 t CAL Column 2 t DS High-Z t OEP tOED tAA tOEA tCAC tOEZ t OHO Dout 1 t ASC t CAH t DH tRDD tCDD Pr Din 2 tOED tCOL t OEA tCPA tAA tCAC Dout 3 Din Din 3 t OEP tCOP tWED OE tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOFF tOH tOHO uc od tOEZ t OHO Dout 4 tRAC Dout t Data Sheet E0102H10 25 HB56UW873E-F Physical Outline 3.00 0.118 C B 54.61 2.150 A 1.27 ± 0.10 0.050 ±0.004 8.89 0.350 11.43 0.450 36.83 1.450 Back side 2 – φ 3.00 2 – φ 0.118 85 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 168 4.00 0.157 17.78 0.700 Detail A 2.54 min 0.100 min 1.27 0.050 0.25 max 0.010 max Detail B and C 3.175 0.125 1.00 ± 0.05 0.039 ± 0.002 3.125 ± 0.125 0.123 ± 0.005 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 Data Sheet E0102H10 26 25.40 1.000 4.00 min 0.157 min EO HB56UW873E Series Front side 3.00 0.118 133.35 5.250 127.35 5.014 Unit: mm inch 4.00 max 0.157 max ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 84 ;; ;; ;; ;; ;; ;; ;; L Pr uc od t HB56UW873E-F Cautions EO 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. L Data Sheet E0102H10 27 Pr uc od t