HM5112805FLTD-6

HM5112805FLTD-6, HM5113805FLTD-6 128M EDO DRAM (16-Mword × 8-bit) 8k refresh/4k refresh EO Description Features E0176H10 (Ver. 1.0) Jul. 12, 2001 The HM5112805F L, HM5113805F L ar e 128M-bit dynamic R AMs orga nized as 16, 777,216-w ord × 8-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology. HM5112805F L, HM5113805F L off er Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. They are packaged in 32-pin plastic TSOPII. • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 60 ns (max) • Power dissipation  Active: 720 mW (max) (HM5112805F) 792 mW (max) (HM5113805F)  Standby : 1.8 mW (max) (CMOS interface) (L-version) • EDO page mode capability • Refresh cycles  RAS -only refresh 8192 cycles/64 ms (HM5112805F) 4096 cycles/64 ms (HM5113805F)  CBR/Hidden refresh 4096 cycles/64 ms (HM5112805F, HM5113805F) This product became EOL in December, 2006. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. L Pr uc od t HM5112805FLTD-6, HM5113805FLTD-6 • 4 variations of refresh  RAS -only refresh  CAS -before-RAS refresh  Hidden refresh  Self refresh (L-version) • Battery backup operation (L-version) EO Ordering Information Type No. HM5112805FLTD-6 HM5113805FLTD-6 2 Access time Package 400-mil 32-pin plastic TSOP II (TTP-32DF) 60 ns 60 ns L Data Sheet E0176H10 Pr uc od t HM5112805FLTD-6, HM5113805FLTD-6 Pin Arrangement (HM5112805F) EO Pin Description Pin name A0 to A12 Function I/O0 to I/O7 RAS CAS WE OE VCC VSS NC Data input/output Row address strobe Write enable Output enable Power supply Ground No connection 32-pin TSOP 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE A12 A11 A10 A9 A8 A7 A6 VCC I/O0 I/O1 I/O2 I/O3 NC VCC WE Address input — Row/Refresh address A0 to A12 — Column address A0 to A10 Column address strobe L RAS A0 A1 A2 A3 A4 A5 10 11 12 13 14 15 16 VCC (Top view) Data Sheet E0176H10 Pr VSS uc od t 3 HM5112805FLTD-6, HM5113805FLTD-6 Pin Arrangement (HM5113805F) EO Pin Description Pin name A0 to A11 Function I/O0 to I/O7 RAS CAS WE OE VCC VSS NC Data input/output Row address strobe Write enable Output enable Power supply Ground No connection 4 32-pin TSOP 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE NC A11 A10 A9 A8 A7 A6 VCC I/O0 I/O1 I/O2 I/O3 NC Address input — Row/Refresh address A0 to A11 — Column address A0 to A11 Column address strobe L VCC WE RAS A0 A1 A2 A3 A4 A5 10 11 12 13 14 15 16 VCC (Top view) Data Sheet E0176H10 Pr VSS uc od t HM5112805FLTD-6, HM5113805FLTD-6 Block Diagram (HM5112805F) Row decoder Row decoder EO A0 A1 to • • • Column address buffers A10 Row address buffers A11 A12 RAS Column address buffers • • • Row address buffers Column decoder 16M array Upper pellet 16M array I/O buffers 16M array I/O1 I/O3 I/O4 I/O6 L CAS 16M array Data Sheet E0176H10 5 Pr Timing and control WE OE Timing and control Column decoder 16M array 16M array 16M array 16M array Lower pellet uc od I/O buffers I/O0 I/O2 I/O5 I/O7 t HM5112805FLTD-6, HM5113805FLTD-6 Block Diagram (HM5113805F) Row decoder Row decoder EO A0 A1 to A10 • • • Column address buffers Row address buffers A11 RAS Column address buffers • • • Row address buffers 6 Column decoder 16M array Upper pellet 16M array I/O buffers 16M array I/O1 I/O3 I/O4 I/O6 L CAS 16M array Data Sheet E0176H10 Pr Timing and control WE OE Timing and control Column decoder 16M array 16M array 16M array 16M array Lower pellet uc od I/O buffers I/O0 I/O2 I/O5 I/O7 t HM5112805FLTD-6, HM5113805FLTD-6 Operation Table EO RAS H L L L CAS × WE × L L L L H L* L* × 2 2 OE × L × H L to H × × H I/O 0 to I/O 7 High-Z Dout Din Din Dout/Din High-Z High-Z High-Z Operation Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS -only refresh cycle CAS -before-RAS refresh cycle or Self refresh cycle (L-Version) Read cycle (Output disabled) L L H to L H L H to L L H L H VT VCC Iout PT Tstg Symbol VCC VSS VIH VIL Ta L Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle Pr Symbol Value –0.5 to +4.6 50 1.0 –55 to +125 Min 3.0 0 2.0 Typ 3.3 0 0 — — –0.3 0 — Absolute Maximum Ratings Parameter Unit V V mA W Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current Power dissipation Storage temperature –0.5 to VCC + 0.5 (≤ 4.6 V (max)) uc od °C Max Unit Notes 3.6 V 1, 2 V 2 VCC + 0.3 0.8 70 V 1 V 1 ˚C DC Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. t Data Sheet E0176H10 7 HM5112805FLTD-6, HM5113805FLTD-6 DC Characteristics (HM5112805FL) EO Parameter Operating current* * Standby current (L-version) 1, 2 HM5112805FL -6 Min — — Max 200 500 Unit mA µA Test conditions t RC = min CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ VCC + 0.3 V 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Symbol I CC1 I CC2 RAS -only refresh current* 2 Standby current* 1 I CC3 I CC5 — — — — — 200 10 200 200 2.5 mA mA mA mA mA CAS -before-RAS refresh current I CC6 EDO page mode current* * Battery backup current* 4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 1, 3 Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. L I CC7 I CC10 I CC11 — I LI I LO VOH VOL –5 –5 2.4 0 Data Sheet E0176H10 Pr 1.6 mA 5 5 µA µA VCC 0.4 V V uc od Low Iout = 2 mA t 8 HM5112805FLTD-6, HM5113805FLTD-6 DC Characteristics (HM5113805FL) EO Parameter Operating current* * Standby current (L-version) 1, 2 HM5113805FL -6 Min — — Max 220 500 Unit mA µA Test conditions t RC = min CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ VCC + 0.3 V 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Symbol I CC1 I CC2 RAS -only refresh current* 2 Standby current* 1 I CC3 I CC5 — — — — — 220 10 220 200 2.5 mA mA mA mA mA CAS -before-RAS refresh current I CC6 EDO page mode current* * Battery backup current*4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 1, 3 Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. L I CC7 I CC10 I CC11 — I LI I LO VOH VOL –5 –5 2.4 0 Data Sheet E0176H10 Pr 1.6 mA 5 5 µA µA VCC 0.4 V V Typ — — — Max 7 7 8 uc od Low Iout = 2 mA Unit pF pF pF Notes 1 1 1, 2 t 9 HM5112805FLTD-6, HM5113805FLTD-6 AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19 EO Test Conditions • • • • • Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) 10 Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) L Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT HM5112805FL/HM5113805FL -6 Min 104 40 10 60 10 0 Max — — — Unit ns ns ns ns ns ns ns ns ns Notes Data Sheet E0176H10 Pr 10000 10000 — — — — 10 0 10 14 12 15 40 5 15 0 0 2 45 30 — — — — — — 50 uc od ns ns 3 4 ns ns ns ns ns ns 5 6 6 ns 7 t HM5112805FLTD-6, HM5113805FLTD-6 Read Cycle EO Parameter Access time from RAS Access time from CAS Access time from OE Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Read command hold time from RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time HM5112805FL/HM5113805FL -6 Symbol t RAC t CAC t AA t OEA t RCS t RCH Min — — — — 0 0 60 0 30 18 0 3 3 Max 60 15 30 15 — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 21 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 L t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD Data Sheet E0176H10 11 Pr — — 15 15 — — 15 3 — — 15 15 15 15 — — uc od 13, 21 13 t HM5112805FLTD-6, HM5113805FLTD-6 Write Cycle EO Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time HM5112805FL/HM5113805FL -6 Symbol t WCS t WCH t WP t RWL t CWL t DS Min 0 10 10 15 10 0 10 Max — — — — — — — Unit ns ns ns ns ns ns ns 15 15 Notes 14 Read-Modify-Write Cycle HM5112805FL/HM5113805FL -6 L t DH Symbol t RWC t RWD t CWD t AWD t OEH Symbol t CSR t CHR t WRP t WRH t RPC Pr Min Max 140 79 34 49 15 — — — — — -6 Min 5 10 0 10 5 Max — — — — — Data Sheet E0176H10 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Unit ns ns ns ns ns Notes 14 14 14 uc od Unit Notes ns ns ns ns ns Refresh Cycle HM5112805FL/HM5113805FL Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time t 12 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Cycle EO Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge CAS hold time referred OE CAS to OE setup time Output data hold time from CAS low Read command hold time from CAS precharge OE precharge time Parameter WE delay time from CAS precharge HM5112805FL/HM5113805FL -6 Symbol t HPC t RASP t CPA t CPRH t DOH t COL Min 25 — — 35 3 10 5 35 10 10 Max — 100000 35 — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns 9, 22 Notes 20 16 9, 17 Write pulse width during CAS precharge t WPE t OEP EDO Page Mode Read-Modify-Write Cycle EDO page mode read-modify-write cycle t HPRWC time t CPW L t COP t RCHC Symbol Symbol t REF Symbol t REF Pr -6 Min Max 68 54 — — Max 64 Max 64 HM5112805FL/HM5113805FL Unit ns ns Notes uc od 14 Unit ms Notes 8192 cycles Unit ms Notes 4096 cycles Refresh(HM5112805F) Parameter Refresh period (L-version) Refresh(HM5113805F) Parameter Refresh period (L-version) t Data Sheet E0176H10 13 HM5112805FLTD-6, HM5113805FLTD-6 Self Refresh Mode (L-version) HM5112805FL/HM5113805FL -6 Symbol t RASS t RPS t CHS Min 100 110 –50 Max — — — Unit µs ns ns Notes 25 25 EO Parameter RAS pulse width (self refresh) CAS hold time (self refresh) RAS precharge time (self refresh) 14 Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max). 11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. L Data Sheet E0176H10 Pr uc od t HM5112805FLTD-6, HM5113805FLTD-6 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6µs after exiting from self refresh mode. 24. In case of entering from RAS -only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25 At t RASS > 100 µs, self refresh mode is activated, and not activated at t RASS < 10 µs. It is undefined within the range of 10 µs ≤ t RASS ≤ 100 µs. For t RASS ≥ 10 µs, it is necessary to satisfy t RPS. 26. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. EO L Data Sheet E0176H10 15 Pr uc od t HM5112805FLTD-6, HM5113805FLTD-6 Timing Waveforms*26 ; tDZO tOEA tOED OE tCAC tAA tRAC tCLZ tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout Data Sheet E0176H10 16 EO Read Cycle RAS tT CAS tASR tRAH Address Row WE Din tRC tRAS tRP tCSH tRCD tRSH tCAS tCRP L tRAD tASC tRCS tDZC tRAL tCAL tCAH Pr Column tRCHR tRCH High-Z tRRH uc od tCDD tWED tRDD t HM5112805FLTD-6, HM5113805FLTD-6 Early Write Cycle EO RAS tT CAS tASR tRAH Address Row WE Din Dout tRC tRAS tRP tCSH tRSH tCAS tCRP tRCD L tASC tWCS tDS Din tCAH Data Sheet E0176H10 17 Pr Column tWCH uc od High-Z* * t WCS t WCS (min) tDH t HM5112805FLTD-6, HM5113805FLTD-6 Delayed Write Cycle*18 ; tDZO tOED tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout Data Sheet E0176H10 18 EO RAS tT CAS tASR tRAH Address Row WE Din tRC tRAS tRP tCSH tRSH tCAS tCRP tRCD L tASC tRCS tDZC High-Z tCAH Column Pr tCWL tRWL tWP uc od tDS tDH Din t HM5112805FLTD-6, HM5113805FLTD-6 Read-Modify-Write Cycle*18 ; tDZO tOED tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0176H10 EO RAS tT CAS tASR tRAH Address Row WE Din tRWC tRAS tRP tRCD tCAS tCRP L tRAD tASC tRCS tDZC tCAH Column Pr tCWD tAWD tRWD tDS High-Z tCWL tRWL tWP tDH uc od Din t 19 HM5112805FLTD-6, HM5113805FLTD-6 RAS-Only Refresh Cycle ; 20 EO RAS tRC tRAS tRP tT tRPC tCRP tCRP CAS L tASR tRAH Row tOFR tOFF Address Pr High-Z Dout Data Sheet E0176H10 uc od t HM5112805FLTD-6, HM5113805FLTD-6 CAS-Before-RAS Refresh Cycle ; EO tRP RAS tT tRPC tCP tCSR CAS tWRP WE Address tOFR tOFF Dout tRC tRAS tRP tRAS tRC tRP tRPC tCHR tCP tCSR tCHR tCRP L tWRH High-Z Data Sheet E0176H10 tWRP tWRH Pr uc od t 21 HM5112805FLTD-6, HM5113805FLTD-6 Hidden Refresh Cycle ; Dout Dout Data Sheet E0176H10 22 EO RAS tT tRCD tRC tRAS tRP tRC tRAS tRC tRP tRAS tRP tRSH tCHR tCRP CAS tASR tRAH L tRAD tRAL tASC tCAH Address Row Column Pr High-Z tOEA tCAC tAA tCLZ tRRH tRCH tRCS WE tDZC tWED tCDD tRDD uc od tOED tOFF tOEZ tWEZ tOHO tOH tOFR tOHR Din tDZO OE tRAC t HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read Cycle (1) ; tWEZ tCAC tRAC tOEA tDOH tOHO tOEA Dout EO RAS t RP t RASP t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP tT t CSH RSH CAS t CAS tCAS t RRH t RCH t RCS t RCHR t RCH t RCS WE tASR Address tRAH tASC Row tCAH t WPE t ASC t CAH Column 2 t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 Column 1 t CAL L High-Z tOEA tCAC tAA tCPA tAA tCAC Dout 1 t WED t CAL t CAL tRDD tCDD tDZC Din Pr tCOL t OEP tOEZ tOHO tCPA tAA tCAC Dout 2 Dout 2 Dout 3 tDZO tCOP tOED tOEP OE tCPA tAA tOEZ tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0176H10 23 uc od Dout 4 t HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read Cycle (2) ; tOHO tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA Dout EO RAS t RP t RASP t HPC t CAS tHPC t CP t CAS t RCHC t CP t HPC tRSH tCAS t RRH t RCH t CRP tT t CSH t CP CAS t CAS t RCS WE L tCAH t ASC t CAH Column 2 t CAL High-Z tOEA tCAC tAA tCPA tAA tCAC Dout 1 tASR Address tRAH tASC Row t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL t CAL tRDD tCDD tDZC Pr tCOL t OEP tOEZ tCPA tAA tCAC Dout 2 Dout 2 Dout 3 Din tDZO tCOP tOED tOEP OE tCPA tAA tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0176H10 24 uc od Dout 4 t HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Early Write Cycle EO RAS tT tRCD CAS tASR tRAH tASC Address Row tWCS WE tDS Din Dout tRASP tRP tCSH tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP L tCAH Column 1 tWCH tDH Din 1 tASC tCAH tASC tCAH Column 2 Column N Data Sheet E0176H10 25 Pr tWCS tWCH tWCS tDS tDH tDS Din 2 High-Z* tWCH uc od tDH Din N * t WCS t WCS (min) t HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Delayed Write Cycle*18 ; OE tCLZ tCLZ tCLZ tOEZ tOEZ EO RAS tT tCSH tRCD CAS tRAD tASR tRAH tRASP tRP tCP tCAS tHPC tCAS tCP tRSH tCAS tCRP L tASC tCAH tASC tCAH tASC tCAH Address Row Column 1 tCWL Column 2 tCWL Column N tCWL tRWL Pr tRCS tRCS tWP tDZC tDS tDH tDH tRCS WE tWP tDZC tDS tWP tDZC tDS tDH uc od Din 2 Din N tOED tOEP tOEH Din tDZO tOED Din 1 tDZO tOEP tOEH tDZO tOED tOEP tOEH tOEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout t Data Sheet E0176H10 26 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read-Modify-Write Cycle*18 ; ; t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z EO RAS tT t RCD CAS t RASP t RP t HPRWC t CP t CAS t CP t RSH t CRP t CAS t CAS t RAD t ASR t ASC t RAH Row L t CAH Column 1 t ASC t CAH Column 2 t ASC t CAH Column N Address Pr t CWL t CPW t CWL t RCS t RWD t AWD t CPW t CWD t CWL t RWL t AWD t AWD t CWD WE t RCS t CWD t RCS t WP t DS t DZC t WP t DS t DZC t WP t DS t DZC t DH t DH t DH uc od Din 2 Din N t OEP t OEH Din t DZO t OED Din 1 t OEP t OEH t DZO t OED t DZO t OED t OEP t OEH OE t OHO t OHO t OHO Dout Dout 1 Dout 2 Dout N t 27 Data Sheet E0176H10 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Mix Cycle (1)* 20 ; tOEP tWED OE EO RAS t RP t RASP t CRP tCAS tCWL t RCS tCPW tAWD tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL t DS t DH Din 3 tRDD tCDD tRSH t RRH t RCH tT t CP t CAS t CP tCAS t CP CAS t CAS t CSH t RCD t WCS t WCH t RCS WE L tCAH t ASC t CAH Column 2 t CAL t DH Din 1 High-Z tCPA tAA tOEA tCAC Dout 2 tASR Address t ASC tRAH Row tASC Column 1 t DS Din Pr tOED tCPA tAA t OEZ t DOH tCAC t OHO Dout 3 tCPA tAA tOFR tWEZ tOEZ tCAC uc od tOHO tOFF tOH tOEA Dout 4 Dout t Data Sheet E0176H10 28 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Mix Cycle (2) *20 EO RAS t RP t RASP tT t CSH t CP t CAS t CP tCAS tCWL t RCS tCPW t ASC t CAH Column 3 t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS t DH tRSH t CRP CAS t CAS t RCD t RCHR t RCS t RCH tWCS t WCH t RRH t RCH WE L tCAH t ASC t CAH Column 2 t CAL t DS t DH High-Z Din 2 t OEP tOED tCOL tAA tOEA tCAC tOEZ t OHO Dout 1 tASR Address t ASC tRAH Row Column 1 tRDD tCDD Pr tOED t OEA tCPA tAA tCAC tOEZ Dout 3 Din Din 3 t OEP tCOP tWED OE tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOFF tOH tOHO uc od t OHO Dout 4 tRAC Dout t Data Sheet E0176H10 29 HM5112805FLTD-6, HM5113805FLTD-6 Self Refresh Cycle (L-version)* 23, 24, 25 ; ; tRPC tCP tCSR CAS tWRP WE tOFR tOFF Dout 30 ; High-Z Data Sheet E0176H10 EO tRP RAS tT tRASS tRPS tCRP tCHS L tWRH Pr uc od t HM5112805FLTD-6, HM5113805FLTD-6 Package Dimensions 1 *0.42 ± 0.08 0.40 ± 0.06 1.27 M 16 0.21 10.16 0.10 *0.12 ± 0.05 0.10 ± 0.04 0.05 ± 0.05 1.20 Max 0° – 5° 0.50 ± 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) TTP-32DF — — 0.54 g Data Sheet E0176H10 31 0.45 EO HM5112805FLTD HM5113805FLTD (TTP-32DF) 20.95 21.35 Max 32 1.15 Max As of January, 2001 Unit: mm 17 L 0.80 Pr 11.76 ± 0.20 uc od t HM5112805FLTD-6, HM5113805FLTD-6 Cautions EO 32 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party ’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party ’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. L Data Sheet E0176H10 Pr uc od t