HM5113165FTD-6

HM5113165FTD-6 128M EDO DRAM (8-Mword × 16-bit) 4k refresh EO Description Features Type No. HM5113165FTD-6 E0177H10 (Ver. 1.0) Jul. 5, 2001 The HM5113165F is 128M-bit dynamic R AM orga nized as 8, 388,608-w ord × 16-bit. It has re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology. HM5113165F off ers Extende d Da ta Out (EDO) Page Mode as a high speed access mode. It is packaged in 50-pin plastic TSOPII. • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 60 ns (max) • Power dissipation ⎯ Active: 828 mW (max) ⎯ Standby : 3.6 mW (max) (CMOS interface) • EDO page mode capability • Refresh cycles ⎯ RAS -only refresh 4096 cycles /64 ms ⎯ CBR/Hidden refresh 4096 cycles /64 ms • 4 variations of refresh ⎯ RAS -only refresh ⎯ CAS -before-RAS refresh ⎯ Hidden refresh • 2CAS -byte control Ordering Information Access time 60 ns Package Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. L This product became EOL in December, 2006. Pr od 400-mil 50-pin plastic TSOP II (TTP-50DE) t uc HM5113165FTD-6 Pin Arrangement (HM5113165F Series) 50-pin TSOP VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS EO Pin Description Pin name A0 to A11 Function I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC L Data input/output Row address strobe Write enable Output enable Power supply Ground No connection 2 Address input — Row/Refresh address A0 to A11 — Column address A0 to A10 Column address strobe Pr (Top view) Data Sheet E0177H10 od t uc HM5113165FTD-6 Block Diagram A0 Column decoder • • • Column address buffers Row decoder 8M array 8M array 8M array 8M array 8M array 8M array 8M array 8M array Upper pellet Row decoder EO A1 to A10 A11 • • • I/O buffers I/O8 to I/O15 Row address buffers L Column address buffers Row address buffers Pr Timing and control RAS UCAS LCAS WE Timing and control 8M array 8M array 8M array 8M array 8M array 8M array 8M array 8M array Data Sheet E0177H10 OE Lower pellet od Column decoder t uc I/O buffers I/O0 to I/O7 3 HM5113165FTD-6 Operation Table RAS H L L L L L L L L L L L L L H to L L LCAS × L H UCAS WE × H L × H H H L* L* L* 2 2 2 OE × L L L × × × H H H I/O 0 to I/O 7 High-Z Dout High-Z Dout Din × Din Din × Din Dout/Din High-Z Dout/Din High-Z High-Z I/O 8 to I/O 15 Operation High-Z High-Z Dout Dout × Din Din × Din Din High-Z Dout/Din Dout/Din High-Z High-Z RAS -only refresh cycle CAS -before-RAS refresh cycle Read cycle (Output disabled) Read-modify-write cycle Delayed write cycle Early write cycle Standby Read cycle EO L L L H L L H L L H L L H L L H L H L L H L L H L L 4 L* 2 L* L* 2 2 Notes: 1. H: VIH (inactive) L: VIL (active) ×: VIH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. UCAS controls the upper pellet (I/O 8 to 15) only, and LCAS controls the lower pellet (I/O 0 to 7) only. Therefore, mode, read/write and High-Z control are done independently by each UCAS, LCAS . L H to L H to L H to L × H H × × H L to H L to H L to H Pr High-Z High-Z Data Sheet E0177H10 od t uc HM5113165FTD-6 Absolute Maximum Ratings Parameter Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current Power dissipation Symbol VT VCC Iout PT Tstg Value –0.5 to VCC + 0.5 (≤ 4.6 V (max)) –0.5 to +4.6 50 1.0 –55 to +125 Unit V V mA W °C EO Storage temperature Parameter Supply voltage Input high voltage Input low voltage DC Operating Conditions Ambient temperature range Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. L Symbol VCC VSS VIH VIL Min 3.0 0 2.0 –0.3 0 Typ 3.3 0 — — — Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V ˚C Notes 1, 2 2 1 1 Pr Ta Data Sheet E0177H10 od t uc 5 HM5113165FTD-6 DC Characteristics HM5113165F -6 Parameter Symbol I CC1 I CC2 Min — — Max 230 4 Unit mA mA Test conditions t RC = min TTL interface RAS , UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min 0 V ≤ Vin ≤ VCC + 0.3 V 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Low Iout = 2 mA EO Operating current* * Standby current 1, 2 — 1 mA RAS -only refresh current* 2 Standby current* 1 CAS -before-RAS refresh current EDO page mode current* 1, * 3 Input leakage current Output leakage current Output high voltage Output low voltage Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Min — — — Typ — — — Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS , UCAS and LCAS = VIH to disable Dout. L I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL — — 230 10 mA mA — — 230 200 mA mA µA µA V Pr –5 –5 5 5 2.4 0 VCC 0.4 Data Sheet E0177H10 od V Max 7 7 7 t uc Unit pF pF Notes 1 1 pF 1, 2 6 HM5113165FTD-6 AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19 Test Conditions • • • • • Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) EO Parameter RAS precharge time CAS precharge time RAS pulse width CAS pulse width RAS hold time CAS hold time OE to Din delay time Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5113165F -6 Symbol t RC t RP t CP Min 104 40 10 60 10 0 Max — — — 10000 10000 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 23 23 3 4 23 Notes Random read or write cycle time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time OE delay time from Din CAS delay time from Din Transition time (rise and fall) L Pr t RAS t CAS t ASR t RAH 10 0 t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 10 14 12 15 40 5 15 0 0 2 Data Sheet E0177H10 od 45 30 — — — — — — 50 t uc 23 5 6 6 ns 7 7 HM5113165FTD-6 Read Cycle HM5113165F -6 Parameter Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ Min — — — — 0 0 60 0 30 18 0 3 3 Max 60 15 30 15 — — — — — — — — — 15 15 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 23 12, 23 EO Access time from OE WE to Din delay time 8 Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE RAS to Din delay time L Pr t OH t OHO t OFF — — t OEZ t CDD 15 3 t OHR t OFR t WEZ t WED t RDD — — 15 15 Data Sheet E0177H10 od 15 15 — — t uc HM5113165FTD-6 Write Cycle HM5113165F -6 Parameter Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 15 10 0 10 Max — — — — — — — Unit ns ns ns ns ns ns ns 23 15, 23 15, 23 Notes 14, 23 23 EO Data-in setup time Data-in hold time Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Read-Modify-Write Cycle Read-modify-write cycle time RAS to WE delay time CAS to WE delay time OE hold time from WE Column address to WE delay time Refresh Cycle L HM5113165F -6 Pr Symbol Min t RWC 140 79 34 49 15 t RWD t CWD t AWD t OEH HM5113165F -6 Symbol t CSR t CHR t WRP t WRH t RPC Min 5 10 0 10 5 Data Sheet E0177H10 Max — — — — — Unit ns ns ns ns ns Notes 14 14 14 od Max — — — — — t uc Unit Notes ns ns 23 23 ns ns ns 23 9 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time HM5113165FTD-6 EDO Page Mode Cycle HM5113165F -6 Parameter Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 25 — — 35 3 10 5 35 10 10 Max — 100000 35 — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns 9, 22 Notes 20 16 9, 17, 23 EO OE precharge time Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Write pulse width during CAS precharge t WPE t OEP EDO Page Mode Read-Modify-Write Cycle EDO page mode read-modify-write cycle t HPRWC time WE delay time from CAS precharge t CPW L Pr HM5113165F -6 Symbol od Min Max 68 54 — — Max 64 Unit ms Unit ns ns Notes 14, 23 Refresh Parameter Refresh period Symbol t REF Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . t uc Notes 4096 cycles Data Sheet E0177H10 10 HM5113165FTD-6 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max). 11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. t ASC, t CAH , t RCS , t WCS , t WCH, t CSR , t RPC , t CRP , t CHR, t RCH, t CPA, t CPW , t CWL, t DH, t DS, t CHS and t CP are determined by each of UCAS / LCAS independently. 24. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. EO L Pr Data Sheet E0177H10 od t uc 11 HM5113165FTD-6 Timing Waveforms*24 Read Cycle ; t uc tOED tOEZ tOHO tOFF tOH tOFR tOHR tWEZ tDZO tOEA OE tCAC tAA tRAC tCLZ Dout Dout Data Sheet E0177H10 12 EO RAS CAS Address WE Din tRC tRAS tRP tCSH tT tRCD tRSH tCAS tCRP L tASR Row tRAD tASC tRAL tCAL tCAH tRAH Pr Column tRCHR tRCS tDZC High-Z tRRH tRCH od tCDD tRDD tWED HM5113165FTD-6 Early Write Cycle tRC tRAS tRP EO RAS CAS Address WE Din Dout tCSH tRCD tT tRSH tCAS tCRP L tASR tRAH Row tASC tCAH Pr Column tWCS tWCH od tDH tDS Din t uc * t WCS t WCS (min) 13 High-Z* Data Sheet E0177H10 HM5113165FTD-6 Delayed Write Cycle*18 tRC tRAS tRP ; tDZO tOED tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout Data Sheet E0177H10 14 EO RAS CAS Address WE Din tCSH tRCD tT tRSH tCAS tCRP L tASR tRAH Row tASC tCAH Column tCWL tRWL tWP Pr tRCS tDZC tDS High-Z od tDH Din t uc HM5113165FTD-6 Read-Modify-Write Cycle*18 tRWC tRAS tRP ; tDZO tOED tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0177H10 EO RAS CAS Address WE Din tT tRCD tCAS tCRP tRAD tASC tCAH L tASR Row tRAH Column tRCS tCWD tAWD tRWD tCWL tRWL tWP Pr tDZC tDS High-Z od tDH Din t uc 15 HM5113165FTD-6 RAS-Only Refresh Cycle tRC tRAS tRP ; 16 EO RAS CAS Address tT tCRP tRPC tCRP tASR Row tRAH Dout L tOFR tOFF Pr High-Z Data Sheet E0177H10 od t uc HM5113165FTD-6 CAS-Before-RAS Refresh Cycle tRC tRP tRAS tRP tRAS tRC tRP ; EO RAS CAS WE Address tOFF Dout tT tRPC tCP tCSR tCHR tRPC tCP tCSR tCHR tCRP L tOFR tWRP tWRH tWRP tWRH Pr Data Sheet E0177H10 17 od High-Z t uc HM5113165FTD-6 Hidden Refresh Cycle tRC tRAS tRC tRAS tRC tRP tRAS tRP tRP ; Dout Dout Data Sheet E0177H10 18 EO RAS tT tRSH tRCD tCHR tCRP CAS tRAD tRAL tCAH Address WE Din tDZO tOEA OE tCAC tAA tRAC tCLZ L tASR tRAH tASC Row Column Pr tRCS tRRH tRCH tDZC tWED tCDD tRDD od High-Z tOFR tOHR tOED t uc tOFF tOEZ tWEZ tOHO tOH HM5113165FTD-6 EDO Page Mode Read Cycle (1) t RP RAS t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP ; tWEZ tCAC tRAC tOEA tDOH tOHO tOEA Dout EO CAS WE RSH tCAS t RRH t RCH tASR tRAH tASC tCAH t WPE t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED L Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA Dout 1 Address t CAL tRDD tCDD Din Pr tCOL t OEP tCPA tAA tCAC tOEZ tOHO Dout 2 tCOP tOEP tOED OE tCPA tCPA tAA tCAC tAA tOEZ tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0177H10 19 od Dout 2 Dout 3 Dout 4 t uc HM5113165FTD-6 EDO Page Mode Read Cycle (2) t RP RAS t RASP t HPC t CAS tHPC t CP t CAS t RCHC t RCS t CP t HPC tRSH tCAS t RRH t RCH t CRP ; tOHO tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA Dout EO tT CAS WE t CSH t CAS t CP tASR tRAH tASC tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED L Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA Address t CAL tRDD tCDD Pr tCOL t OEP tCPA tAA tCAC tOEZ Dout 1 Dout 2 Din tCOP tOEP tOED OE tCPA tAA tCAC tCPA tAA tOFR tOHR tOEZ tOHO tOFF tOH Data Sheet E0177H10 20 od Dout 2 Dout 3 Dout 4 t uc HM5113165FTD-6 EDO Page Mode Early Write Cycle tRASP tRP EO RAS tT CAS tASR tRAH Address Row WE Din Dout tCSH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP L tASC tCAH tASC tCAH tASC tCAH Column 1 Column 2 Column N Pr tWCS tWCH tWCS tWCH tDS tDH tDS tDH Din 1 Din 2 High-Z* tWCS tWCH Data Sheet E0177H10 21 od tDS tDH Din N t uc * t WCS t WCS (min) HM5113165FTD-6 EDO Page Mode Delayed Write Cycle*18 tRASP ; OE tCLZ tCLZ tCLZ tOEZ tOEZ EO RAS tT CAS tASR tRP tCP tCSH tRCD tCAS tHPC tCAS tCP tRSH tCAS tCRP tRAD Address Dout L tRAH tASC tCAH tASC tCAH tASC tCAH Row Column 1 tCWL Column 2 tCWL tRCS Column N tCWL tRWL tRCS Pr tRCS tWP tDZC tDS tWP tDZC tDS tDH WE tWP tDZC tDS tDH od tDH Din tDZO tOED Din 1 tOEP tOEH Din 2 Din N tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH t uc tOEZ High-Z Invalid Dout Invalid Dout Invalid Dout Data Sheet E0177H10 22 HM5113165FTD-6 EDO Page Mode Read-Modify-Write Cycle*18 t RASP ; ; t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z EO RAS t RP tT t HPRWC t CP t RCD t CAS t CAS t CP t RSH t CRP t CAS CAS Address WE Din t DZO t OED OE t OHO Dout L t RAD t ASR t ASC t RAH Row t RCS t CAH t ASC t CAH Column 2 t ASC t CAH Column N Column 1 Pr t RWD t AWD t CWL t CPW t CWD t RCS t CWL t RCS t CPW t AWD t CWD t CWL t RWL t AWD t CWD t WP t DS t DZC t WP t DS t DZC t WP t DS t DZC t DH Din N od t DH Din 2 t DH Din 1 t OEP t OEH t DZO t OED t OEP t OEH t DZO t OED t OEP t OEH t uc t OHO Dout N t OHO Dout 1 Dout 2 Data Sheet E0177H10 23 HM5113165FTD-6 EDO Page Mode Mix Cycle (1) *20 t RP RAS t RASP t CRP tCAS tCWL t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 3 tOED tOEP tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS tRSH t RRH t RCH ; OE EO tT CAS WE t CP t CAS t CSH t WCS t WCH t CAS t CP tCAS t CP t RCD L tASR t ASC tRAH Row Column 1 t DS t DH Din 1 tASC Address Pr High-Z tCPA tAA tOEA tCPA tAA tCAC t DOH Dout 2 Din tCPA t OEZ tAA tOFR tWEZ tOEZ od tCAC t OHO tOEA Dout 3 tCAC tOHO tOFF tOH Dout Dout 4 t uc Data Sheet E0177H10 24 HM5113165FTD-6 EDO Page Mode Mix Cycle (2)* 20 t RP RAS t RASP EO tT CAS WE t CSH t CAS t RCHR t CP t CAS t CP tCAS tCWL t RCS tCPW t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH t CRP t RCD t RCS t RCH tWCS t WCH t RRH t RCH tASR t ASC tRAH L tCAH Row Column 1 t CAL High-Z tAA tOEA tCAC tRAC t OHO Dout 1 t ASC t CAH Column 2 t ASC t CAH Column 3 Address t DS t DH t DH Din 3 t OEP tOED tCOP tRDD tCDD Pr Din 2 t OEP tOED tCOL t OEA tOEZ tCPA tAA Din tWED OE tCPA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 od tCAC tOEZ t OHO Dout 3 tAA tCAC tOEA Dout t uc Data Sheet E0177H10 25 HM5113165FTD-6 Package Dimensions HM5113165FTD Series (TTP-50DE) 0.10 *0.12 ± 0.05 0.10 ± 0.04 0.05 ± 0.05 1.20 Max 0.50 ± 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) TTP-50DE — — 0.56 g Data Sheet E0177H10 26 0.45 EO 50 1 *0.30 ± 0.10 0.28 ± 0.05 As of January, 2001 Unit: mm 20.95 21.35 Max 26 0.80 25 0.13 M 11.76 ± 0.20 0° – 5° 0.80 1.075 Max 10.16 L Pr od t uc HM5113165FTD-6 Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. EO L Pr Data Sheet E0177H10 od C Elpida Memory, Inc. 2001 t uc 27