HM5116405

EO Description Features HM5116405 Series HM5117405 Series 16 M EDO DRAM (4-Mword × 4-bit) 4 k Refresh/2 k Refresh The HM5116405 Series, HM5117405 Series are CMOS dynamic RAMs organized 4,194,304-word × 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5116405 Series, HM5117405 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have package variations of standard 26-pin plastic SOJ and standard 26-pin plastic TSOP II. • Single 5 V (±10%) • Access time: 50 ns/60 ns/70 ns (max) • Power dissipation  Active mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series) : 550 mW/495 mW/440 mW (max) (HM5117405 Series)  Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Long refresh period  4096 refresh cycles : 64 ms (HM5116405 Series) : 128 ms (L-version)  2048 refresh cycles : 32 ms (HM5117405 Series) : 128 ms (L-version) • 3 variations of refresh  RAS -only refresh  CAS -before-RAS refresh  Hidden refresh Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. LP E0151H10 (Ver. 1.0) (Previous ADE-203-633D (Z)) Jul. 6, 2001 (K) ro du ct HM5116405 Series, HM5117405 Series • Battery backup operation (L-version) • Test function  16-bit parallel test mode EO Type No. HM5116405S-5 HM5116405S-6 HM5116405S-7 HM5116405LS-5 HM5116405LS-6 HM5116405LS-7 HM5117405S-5 HM5117405S-6 HM5117405S-7 HM5117405LS-5 HM5117405LS-6 HM5117405LS-7 HM5116405TS-5 HM5116405TS-6 HM5116405TS-7 HM5116405LTS-5 HM5116405LTS-6 HM5116405LTS-7 HM5117405TS-5 HM5117405TS-6 HM5117405TS-7 HM5117405LTS-5 HM5117405LTS-6 HM5117405LTS-7 2 Ordering Information Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB) LP Data Sheet E0151H10 ro du ct HM5116405 Series, HM5117405 Series EO VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC Pin Arrangement HM5116405S/LS Series HM5116405TS/LTS Series 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 Pin Description Pin name A0 to A11 Function Address input — Row/Refresh address A0 to A11 — Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Write enable Output enable Power supply Ground LP 8 9 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 10 11 12 13 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS ro du ct 3 I/O1 to I/O4 RAS CAS WE OE VCC VSS Data Sheet E0151H10 HM5116405 Series, HM5117405 Series Pin Arrangement HM5117405S/LS Series HM5117405TS/LTS Series EO VCC I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 Pin Description Pin name A0 to A10 Function Address input — Row/Refresh address A0 to A10 — Column address A0 to A10 Data input/Data output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection LP 8 9 19 18 17 16 15 14 A8 A7 A6 A5 A4 10 11 12 13 VSS (Top view) A10 A0 A1 A2 A3 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS ro VCC (Top view) du ct I/O1 to I/O4 RAS CAS WE OE VCC VSS NC Data Sheet E0151H10 4 HM5116405 Series, HM5117405 Series Row decoder EO A0 A1 to A9 • • • • • • A10 A11 Block Diagram (HM5116405 Series) RAS CAS WE OE Timing and control LP Column buffers address Row address buffers Column decoder 4M array 4M array I/O buffers 4M array I/O1 to I/O4 Data Sheet E0151H10 5 ro 4M array du ct HM5116405 Series, HM5117405 Series Block Diagram (HM5117405 Series) RAS CAS WE OE Row decoder EO A0 A1 to A10 • • • • • • 6 Timing and control LP Column buffers address Row address buffers Column decoder 4M array 4M array I/O buffers 4M array I/O1 to I/O4 Data Sheet E0151H10 ro 4M array du ct HM5116405 Series, HM5117405 Series EO Parameter Power dissipation Parameter Supply voltage Input high voltage Input low voltage Note: Absolute Maximum Ratings Symbol VT VCC Iout PT Topr Tstg Value –1.0 to +7.0 –1.0 to +7.0 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Operating temperature Storage temperature Recommended DC Operating Conditions (Ta = 0 to +70˚C) Symbol Min 4.5 2.4 –1.0 Typ 5.0 — — Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 VCC VIH 1. All voltage referred to VSS . LP VIL Data Sheet E0151H10 7 ro du ct HM5116405 Series, HM5117405 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 5 V ± 10%, VSS = 0 V) (HM5116405 Series) HM5116405 -5 Symbol 2 EO Parameter 1 -6 -7 Test conditions t RC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 µs t RAS ≤ 0.3 µs 0 V ≤ Vin ≤ 7 V 0 V ≤ Vin ≤ 7 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Min Max Min Max Min Max Unit — — 90 2 — — 80 2 — — 70 2 mA mA Operating current* , * Standby current I CC1 I CC2 LP — I CC2 — I CC3 I CC5 — — I CC6 — — — I CC10 I LI I LO VOH VOL 2.4 0 1 — 1 — 1 mA Standby current (L-version) 150 — 150 — 150 µA RAS -only refresh current*2 Standby current* 1 90 5 — — 80 5 — — 70 5 mA mA ro 90 80 — — 80 70 350 — –10 10 –10 10 VCC 2.4 0.4 0 0.4 CAS -before-RAS refresh current — — 70 65 mA mA EDO page mode current*1, * 3 I CC7 Battery backup current 350 — 350 µA Input leakage current Output leakage current Output high voltage Output low voltage –10 10 –10 10 –10 10 –10 10 µA µA VCC 2.4 0 Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Data Sheet E0151H10 8 du VCC 0.4 V V ct HM5116405 Series, HM5117405 Series EO Parameter 1 DC Characteristics (Ta = 0 to +70˚C, VCC = 5 V ± 10%, VSS = 0 V) (HM5117405 Series) HM5117405 -5 Symbol I CC1 I CC2 -6 -7 Test conditions t RC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 µs t RAS ≤ 0.3 µs 0 V ≤ Vin ≤ 7 V 0 V ≤ Vin ≤ 7 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Min Max Min Max Min Max Unit — — 100 — 2 — 90 2 — — 80 2 mA mA Operating current* , * 2 Standby current LP — I CC2 — I CC3 I CC5 — — I CC6 — — — I CC10 I LI I LO VOH VOL 2.4 0 1 — 1 — 1 mA Standby current (L-version) 150 — 150 — 150 µA RAS -only refresh current*2 Standby current* 1 100 — 5 — 90 5 — — 80 5 mA mA CAS -before-RAS refresh current 100 — — 90 — — 80 75 mA mA ro 90 80 350 — –10 10 –10 10 VCC 2.4 0.4 0 0.4 EDO page mode current*1, * 3 I CC7 Battery backup current 350 — 350 µA Input leakage current Output leakage current Output high voltage Output low voltage –10 10 –10 10 –10 10 –10 10 µA µA VCC 2.4 0 Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Data Sheet E0151H10 9 du VCC 0.4 V V ct HM5116405 Series, HM5117405 Series Capacitance (Ta = 25˚C, VCC = 5 V ±10%) Parameter Symbol CI1 CI2 Typ — — — Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Input capacitance (Address) Input capacitance (Clocks) EO 10 Output capacitance (Data-in, Data-out) CI/O Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. LP Data Sheet E0151H10 ro du ct HM5116405 Series, HM5117405 Series EO Test Conditions • • • • • Parameter RAS pulse width CAS pulse width RAS hold time CAS hold time AC Characteristics (Ta = 0 to +70˚C, VCC = 5 V ±10%, VSS = 0 V) *1, *2 , *18 Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116405/HM5117405 -5 Min 84 30 7 50 7 0 7 0 7 Max — — — -6 Min 104 40 10 Max — — — -7 Min 124 50 13 Max — — — Unit ns ns ns Notes Random read or write cycle time RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) LP Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 10000 60 10000 70 10000 13 — — — — 45 0 10 0 13 14 10000 ns 10000 ns — — — — 52 35 — — — — — — 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Data Sheet E0151H10 11 ro — — — — 11 9 10 35 5 13 0 0 2 37 25 — — — — — — 50 10000 10 0 10 0 10 14 du 12 13 40 30 — — 12 13 45 5 — 5 15 — 18 0 0 — — 0 0 2 50 2 ct HM5116405 Series, HM5117405 Series Read Cycle EO Parameter 12 HM5116405/HM5117405 -5 Symbol t RAC t CAC t AA Min — — — — 0 0 50 0 25 15 0 3 3 Max 50 13 25 13 — — — — — — — — — -6 Min — — — — 0 0 60 0 30 18 0 3 3 — — 15 3 — — Max 60 15 30 15 — — — — — — — — — 15 15 — — 15 15 — — — -7 Min — — — — 0 0 70 0 35 23 0 3 3 — — 18 3 — — Max 70 18 35 18 — — — — — — — — — 15 15 — — 15 15 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20 Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time LP t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Data Sheet E0151H10 ro — — 13 13 — 13 3 — — — 13 13 50 13 13 — — — du 15 15 60 18 18 70 ct HM5116405 Series, HM5117405 Series EO Write Cycle Parameter Data-in setup time Data-in hold time Parameter HM5116405/HM5117405 -5 Symbol t WCS t WCH t WP t RWL t CWL t DS Min 0 7 7 7 7 0 7 Max — — — — — — — -6 Min 0 10 10 10 10 0 10 Max — — — — — — — -7 Min 0 13 10 13 13 0 13 Max — — — — — — — Unit ns ns ns ns ns ns ns 15 15 Notes 14 Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Read-Modify-Write Cycle Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE LP t DH Symbol t RWC t RWD t CWD t AWD t OEH Symbol t WRH t RPC HM5116405/HM5117405 -5 Min Max -6 Min 135 79 34 49 15 Max — — — — — -7 Min 161 92 40 57 18 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes ro 111 67 30 42 13 — — — — — -5 Min 5 7 0 7 5 Max — — — — — du -6 -7 Min Max Min 5 — 5 10 — 10 0 10 5 — — — 0 10 5 Refresh Cycle HM5116405/HM5117405 Parameter Max — — — Unit ns ns ns Notes CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR WE setup time (CBR refresh cycle) t WRP WE hold time (CBR refresh cycle) RAS precharge to CAS hold time ct — ns — ns 13 Data Sheet E0151H10 HM5116405 Series, HM5117405 Series EDO Page Mode Cycle HM51W16405/HM51W17405 -5 Symbol t HPC t RASP t CPA Min Max 20 — — 28 3 7 5 28 — -6 Min Max 25 — -7 Min Max 30 — Unit ns Notes 21 16 9, 17, 20 EO Parameter Parameter Parameter Parameter Refresh period 14 EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge 100000 — 28 — — — — — — 35 3 10 5 35 100000 — 35 — — — — — — 40 3 13 5 40 100000 ns 40 — — — — — ns ns ns ns ns ns RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time t COL Read command hold time from CAS precharge EDO Page Mode Read-Modify-Write Cycle HM5116405/HM5117405 -5 -6 Min 68 54 Max — — -7 Min 79 62 Max Unit ns ns 14 Notes EDO page mode read- modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW Test Mode Cycle *19 Test mode WE setup time Test mode WE hold time Refresh (HM5116405 Series) Symbol t REF t REF Max 64 128 Refresh period (L-version) LP t COP t RCHC Symbol Symbol t WTS t WTH 9, 17 Data Sheet E0151H10 ro Min Max 57 45 — — -5 Min 0 7 Max — — HM5116405/HM5117405 -6 du -7 Min Max Min 0 — 0 10 — 10 Unit ms ms Max — — Unit ns ns Notes ct Notes 4096 cycles 4096 cycles HM5116405 Series, HM5117405 Series EO Parameter Refresh period Refresh (HM5117405 Series) Symbol t REF t REF Max 32 128 Unit ms ms Notes 2048 cycles 2048 cycles Refresh period (L-version) Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS -before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M ×4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS -before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. LP Data Sheet E0151H10 15 ro du ct HM5116405 Series, HM5117405 Series Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS before- RAS refresh cycle or RAS -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). Data output turns off and becomes high impedance from later risting edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. EO 16 LP Data Sheet E0151H10 ro du ct HM5116405 Series, HM5117405 Series EO Read Cycle RAS Timing Waveforms*23 t RC t RAS t RP LP t RCD tT t RAD t ASR t RAH Row t RCS t RAC t CSH t RSH t CAS t CRP CAS t RAL t CAL t CAH t ASC Address Column t RRH t RCH ro t RCHR High-Z t OEA t CAC t CLZ WE t WED t CDD t RDD t DZC du t OED Dout Din t DZO OE t AA t OEZ t OHO t OFF t OH t OFR t OHR ct t WEZ Dout Data Sheet E0151H10 17 HM5116405 Series, HM5117405 Series Early Write Cycle EO RAS CAS Address WE Din Dout 18 tRC tRAS tRP tCSH tRCD tT tRSH tCAS tCRP LP tASR tRAH tASC Row tWCS tDS tCAH Column Data Sheet E0151H10 ro tWCH du High-Z* tDH Din ct * t WCS t WCS (min) HM5116405 Series, HM5117405 Series   t OEZ t CLZ Dout High-Z Invalid Dout EO RAS CAS Address WE Din OE Delayed Write Cycle*18 t RC t RAS t RP t CSH t RCD tT t RSH t CAS t CRP LP t ASR t RAH t ASC Row t RCS t DZC t DZO t CAH Column t CWL t RWL t WP High-Z Data Sheet E0151H10 19 ro t DS t OED t DH du Din t OEH ct HM5116405 Series, HM5117405 Series Read-Modify-Write Cycle*18 t RWC t RAS EO RAS CAS Address WE Din OE Dout t RP tT t RCD t CAS t CRP LP t RAD t ASR tRAH Row t RCS t ASC t CAH Column t CWD t AWD t RWD tCWL t RWL t WP Data Sheet E0151H10 20 ro t DZC High-Z t DH t DS Din du t OED t OEH t DZO t OEA t CAC t AA t RAC ct High-Z t OEZ t OHO Dout t CLZ HM5116405 Series, HM5117405 Series !  EO RAS CAS Address Dout RAS-Only Refresh Cycle t RC t RAS t RP tT t CRP t RPC t CRP t OFF LP t ASR Row t OFR t RAH High-Z Data Sheet E0151H10 21 ro du ct HM5116405 Series, HM5117405 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP  , tT CAS t CP t WRP t WRH t CP WE Address t OFR EO RAS Dout 22 t RPC t CSR t CHR t RPC t CRP LP t OFF Data Sheet E0151H10 ro High-Z du ct HM5116405 Series, HM5117405 Series   WE t DZC High-Z EO RAS tT CAS Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP t RSH t CHR t CRP t ASR t RAH Address Row LP t RCD t RAD t RAL t ASC t CAH Column t RCS t DZO t CAC t AA t RAC t CLZ t RRH t WRH t WRP t WRP tWRH t RRH t RCH ro t WED t CDD t RDD du Dout Din t OED t OEA OE t OFF t OH t OEZ t WEZ t OHO ct t OFR t OHR Dout Data Sheet E0151H10 23 HM5116405 Series, HM5117405 Series EDO Page Mode Read Cycle t RP t RASP t CP t CAS t RCHR t RCH t RCS t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP 
 OE EO RAS t RNCD tT t CSH RSH CAS tCAS t RRH t RCH t RCS WE tASR Address tRAH tASC Row tDZC Din tDZO LP tCAH Column 1 t CAL High-Z tOEA tCPA tCAC tAA tWEZ tRAC Dout 1 t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED t CAL tRDD tCDD tCOL tCOP tOED ro tAA tCAC tOEZ tOHO tOEA Dout 2 tCPA tCPA tAA tCAC tAA tOEZ tOFR tOHR tOEZ tCAC tDOH tOHO tOEA tOHO tOFF tOH du Dout 2 Dout 3 Dout Dout 4 ct Data Sheet E0151H10 24 HM5116405 Series, HM5117405 Series EO RAS tT CAS tASR Address WE Din Dout EDO Page Mode Early Write Cycle tRASP tRP tCSH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP Row LP tRAH tASC tCAH Column 1 tWCS tWCH tDS tDH Din 1 tASC tCAH tASC tCAH Column 2 Column N Data Sheet E0151H10 25 ro tWCS tDS Din 2 High-Z* tWCH tWCS tWCH tDH tDS tDH du Din N ct * t WCS t WCS (min) HM5116405 Series, HM5117405 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP       t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ EO RAS tT CAS t CP t CSH t RCD t CAS t HPC t CAS t CP t RSH t CAS t CRP LP t RAD t ASC t RAH t CAH Column 1 t RCS t WP t DZC t DS Din 1 t DZO Invalid Dout t ASR t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL Address Row t CWL t RCS ro t DH t DZO Invalid Dout WE t WP t DH Din 2 t WP t DZC t DS t DH Din N t DZC t DS Din du t DZO ct Dout High-Z Invalid Dout Data Sheet E0151H10 26 HM5116405 Series, HM5117405 Series *    OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC EO RAS tT CAS EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP t HPRWC t CP t CAS t CP t RCD t CAS t RSH t CAS t CRP LP t RAD t ASC t RAH t CAH Column 1 t RWD t AWD t CWD t RCS t WP t DS t DZC Din 1 t DZO t OED t ASR t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address Row t CWL t RCS ro t DH t DZO t OED t CLZ Dout 2 WE t WP t DS t DZC t DH Din 2 t WP t DS t DZC t DH Din N Din du t DZO t OEH t OEZ t CLZ t OED t OEH t OEH ct t OEZ High-Z t CLZ t OEZ Dout Dout 1 Dout N Data Sheet E0151H10 27 HM5116405 Series, HM5117405 Series EDO Page Mode Mix Cycle (1) t RP t RASP t CRP tCAS tRSH t RCS tCPW tAWD tASC t CAH Column 3 t CAL t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH   OE EO RAS tT t CP t CAS t CSH t CAS t CP tCAS t CP CAS t RCD LP t WCS t WCH t RCS tCAH Column 1 t CAL t DH Din 1 WE tASR Address t ASC tRAH Row t ASC t CAH Column 2 tASC t DS Din ro tCPA tAA tOEA tCAC Dout 2 tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH t DOH tCAC t OHO tOEA du Dout 3 Dout Dout 4 ct Data Sheet E0151H10 28 HM5116405 Series, HM5117405 Series EO RAS EDO Page Mode Mix Cycle (2) t RNCD t RASP t RP tT t CSH t CAS t CAS t CP tCAS t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH t CRP CAS t RCD t RCS WE tASR Address t ASC tRAH Row LP t RCHR tCAH Column 1 t CAL t DS High-Z tOED tAA tOEA tCAC tOEZ t OHO Dout 1 t RCH tWCS t WCH t RCS t RRH t RCH t ASC t CAH Column 2 t CAL t DH t ASC t CAH Column 3 t CAL tRDD tCDD ro Din 2 tCOL Din tWED OE t OEA tCPA tAA tCAC tOEZ tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 du Dout 3 tRAC t OHO Dout ct Data Sheet E0151H10 29 HM5116405 Series, HM5117405 Series Test Mode Cycle *19 *,** Reset Cycle EO RAS CAS WE Set Cycle** Test Mode Cycle Normal Mode LP Data Sheet E0151H10 * CBR or RAS-only refresh ** Address, Din, OE: H or L ro du ct 30 HM5116405 Series, HM5117405 Series tT CAS t CP t WTS t WTH WE Address t OFR     Dout t OFF Data Sheet E0151H10 31 SSP CC@ , R P B @  , t CP High-Z EO RAS Test Mode Set Cycle t RC t RP t RAS t RP t RPC t CSR t CHR t RPC t CRP LP ro du ct HM5116405 Series, HM5117405 Series Package Dimensions HM5116405S/LS Series HM5117405S/LS Series (CP-26/24DB) Unit: mm 1 3.50 ± 0.26 68 0.74 13 2.65 ± 0.12 6.79 – 0.18 + 0.19 8.51 ± 0.13 0.80 +0.25 –0.17 Hitachi Code JEDEC EIAJ Weight (reference value) 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 2.54 0.10 7.62 ± 0.13 EO 32 Dimension including the plating thickness Base material dimension LP 26 16.90 17.27 Max 21 19 14 Data Sheet E0151H10 ro CP-26/24DB Conforms Conforms 0.8 g du ct HM5116405 Series, HM5117405 Series 1 68 1.27 13 7.62 0.10 0.145 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 1.20 Max 2.54 0.50 ± 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-26/24DA Conforms — 0.30 g Data Sheet E0151H10 33 0.68 EO HM5116405TS/LTS Series HM5117405TS/LTS Series (TTP-26/24DA) Unit: mm 26 17.14 17.54 Max 21 19 14 0.42 ± 0.08 0.40 ± 0.06 LP 0.21 M 1.15 Max 0.80 9.22 ± 0.20 0° – 5° ro du ct HM5116405 Series, HM5117405 Series Cautions EO 34 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. LP Data Sheet E0151H10 ro du ct