HM5118165LTT-7

EO Description Features HM5118165 Series 16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh E0154H10 (Ver. 1.0) (Previous ADE-203-636D (Z)) Jul. 6, 2001 (K) The HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II. • Single 5 V (±10%) • Access time : 50 ns/60 ns/70 ns (max) • Power dissipation  Active mode : 1045 mW/935 mW/825 mW (max)  Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Refresh cycles  1024 refresh cycles : 16 ms : 128 ms (L-version) • 4 variations of refresh  RAS -only refresh  CAS -before-RAS refresh  Hidden refresh  Self refresh (L-version) • 2CAS -byte control • Battery backup operation (L-version) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. LP ro du ct HM5118165 Series Ordering Information Type No. Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 50-pin plastic TSOP II (TTP-50/44DC) Package 400-mil 42-pin plastic SOJ (CP-42D) HM5118165J-5 HM5118165J-6 HM5118165J-7 EO HM5118165LJ-5 HM5118165LJ-6 HM5118165LJ-7 HM5118165TT-5 HM5118165TT-6 HM5118165TT-7 HM5118165LTT-5 HM5118165LTT-6 HM5118165LTT-7 2 LP Data Sheet E0154H10 ro du ct HM5118165 Series EO VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC Pin Arrangement HM5118165J/LJ Series VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 (Top view) 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS HM5118165TT/LTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 V SS I/O15 I/O14 I/O13 I/O12 V SS I/O11 I/O10 I/O9 I/O8 NC 1 2 3 4 5 6 7 8 9 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 (Top view) LP 10 11 12 13 14 15 16 17 18 19 20 21 ro VSS du ct 3 Pin Description Pin name A0 to A9 Function Address input — Row/Refresh address A0 to A9 — Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC Data Sheet E0154H10 HM5118165 Series Block Diagram Row decoder EO A0 A1 to A9 • • • • • • 4 RAS UCAS LCAS WE OE Timing and control Column buffers address Row address buffers LP Column decoder 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array I/O buffers I/O0 to I/O15 Data Sheet E0154H10 ro du ct HM5118165 Series EO Truth Table RAS H L L L L L L L L L L L L L H to L H to L H to L L D L LCAS D H L L H L L H H L L H L L H L H H L L L L L H L L H L L H L H L L UCAS WE D H H H L *2 2 2 2 2 2 OE D L L L D D D H H H Output Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Operation Standby Lower byte Read cycle Upper byte Word Lower byte Early write cycle Upper byte Word Lower byte Delayed write cycle Upper byte Word Lower byte Read-modify-write cycle Upper byte Word Word Word Word Word Read cycle (Output disabled) RAS -only refresh cycle CAS -before-RAS refresh cycle or Self refresh cycle (L-version) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS . (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS . ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. LP L* L* L* L* L* H to L H to L H to L D L to H L to H L to H D D D D H D D D H Data Sheet E0154H10 5 ro Open du ct HM5118165 Series Absolute Maximum Ratings Parameter Symbol VT VCC Iout PT Topr Tstg Value –1.0 to +7.0 –1.0 to +7.0 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation EO Storage temperature Parameter Supply voltage Input high voltage Input low voltage Parameter Operating current* * Standby current 1, Operating temperature Recommended DC Operating Conditions (Ta = 0 to +70°C) Symbol Min 4.5 2.4 –1.0 Typ 5.0 — — Max 5.5 6.5 0.8 Unit V V V Notes 1, 2 1 1 VCC VIH Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5118165 -5 Symbol 2 LP VIL I CC1 I CC2 — — — I CC2 — Min Max Min Max Min Max Unit 200 — 2 — 170 — 2 — 150 mA 2 mA ro -6 1 — 1 150 — -7 du — 1 mA 150 µA Test conditions t RC = min TTL interface RAS , UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z ct Standby current (L-version) 150 — Data Sheet E0154H10 6 HM5118165 Series EO Parameter Standby current* 1 DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont.) HM5118165 -5 Symbol 2 -6 -7 Test conditions t RC = min RAS = VIH, UCAS, LCAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 125 µs t RAS ≤ 0.3 µs CMOS interface RAS , UCAS, LCAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 7 V 0 V ≤ Vout ≤ 7 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Min Max Min Max Min Max Unit — — 200 — 5 — 170 — 5 — 150 mA 5 mA RAS -only refresh current* I CC3 I CC5 CAS -before-RAS refresh current EDO page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) 4 Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS , UCAS and LCAS = VIH to disable Dout. LP I CC6 — — — I CC10 I CC11 — I LI I LO VOH VOL 2.4 0 190 — 185 — 500 — 170 — 165 — 500 — 150 mA 145 mA 500 µA 300 — 300 — 300 µA –10 10 –10 10 Data Sheet E0154H10 7 ro –10 10 –10 10 VCC 2.4 0.4 0 0.4 — — — –10 10 –10 10 VCC 0.4 µA µA V V VCC 2.4 0 du Typ Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 ct HM5118165 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18, *19, *20 Test Conditions • • • • • EO Parameter RAS precharge time CAS precharge time RAS pulse width CAS pulse width RAS hold time CAS hold time OE to Din delay time 8 Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5118165 -5 Min 84 30 7 50 7 0 7 0 7 Max — — — -6 Min 104 40 10 Max — — — -7 Min 124 50 13 Max — — — Unit ns ns ns Notes Random read or write cycle time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time OE delay time from Din CAS delay time from Din Transition time (rise and fall) LP Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 10000 60 10000 70 10000 13 — — — — 45 0 10 0 13 14 10000 ns 10000 ns — — — — 52 35 — — — — — — 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 23 22 5 6 6 7 21 21 3 4 Data Sheet E0154H10 ro — — — — 11 9 10 35 5 13 0 0 2 37 25 — — — — — — 50 10000 10 0 10 0 10 14 du 12 13 40 30 — — 12 13 45 5 — 5 15 — 18 0 0 — — 0 0 2 50 2 ct HM5118165 Series EO Read Cycle Parameter Access time from OE Output data hold time WE to Din delay time HM5118165 -5 Symbol t RAC t CAC t AA t OEA t RCS Min — — — — 0 0 50 0 25 15 0 3 3 Max 50 13 25 13 — — — — — — — — — -6 Min — — — — 0 0 60 0 30 18 0 3 3 — — 15 Max 60 15 30 15 — — — — — — — — — 15 15 — — 15 15 — — — -7 Min — — — — 0 0 70 0 35 23 0 3 3 — — 18 3 — — Max 70 18 35 18 — — — — — — — — — 15 15 — — 15 15 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 27 13 5 27 27 27 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 21 12, 22 Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE RAS to Din delay time RAS next CAS delay time LP t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Data Sheet E0154H10 9 ro — — 13 13 — 13 3 — — — 13 13 50 13 13 — — — 3 — — du 15 15 60 18 18 70 ct HM5118165 Series Write Cycle EO Parameter Data-in setup time Data-in hold time Parameter HM5118165 -5 Symbol t WCS t WCH t WP t RWL t CWL t DS Min 0 7 7 7 7 0 7 Max — — — — — — — -6 Min 0 10 10 10 10 0 10 Max — — — — — — — -7 Min 0 13 10 13 13 0 13 Max — — — — — — — Unit ns ns ns ns ns ns ns 23 15, 23 15, 23 Notes 14, 21 21 Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Read-Modify-Write Cycle Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE LP t DH Symbol t RWC t RWD t CWD t AWD t OEH Symbol t RPC -5 Min Max -6 Min Max — — — — — -7 Min 161 92 40 57 18 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes ro 111 67 30 42 13 — — — — — HM5118165 -5 Min 5 7 5 Max — — — 135 79 34 49 15 du -6 -7 Min Max Min 5 — 5 10 — 10 5 — 5 Refresh Cycle Parameter Max — — Unit ns ns Notes 21 22 CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR RAS precharge to CAS hold time ct — ns 21 Data Sheet E0154H10 10 HM5118165 Series EO Parameter Parameter EDO Page Mode Cycle HM5118165 -5 Symbol t HPC t RASP t CPA Min Max 20 — — 28 3 7 5 28 — -6 Min Max 25 — -7 Min Max 30 — Unit ns Notes 25 16 9, 17, 22 EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge 100000 — 28 — — — — — — 35 3 10 5 35 100000 — 35 — — — — — — 40 3 13 5 40 100000 ns 40 — — — — — ns ns ns ns ns ns RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time t COL Read command hold time from CAS precharge EDO Page Mode Read-Modify-Write Cycle EDO page mode read-modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW LP t COP t RCHC Symbol t REF t REF 9 HM5118165 -5 ro Min Max 57 45 — — 16 -6 Min Max — — -7 Min 79 62 Max — — Unit ns ns 14, 22 Notes 68 54 du Unit ms ms Refresh Parameter Refresh period Refresh period (L-version) Symbol Max Note 1024 cycles 1024 cycles 128 ct Data Sheet E0154H10 11 HM5118165 Series Self Refresh Mode (L-version) HM5118165L -5 Symbol t RASS t RPS t CHS Min 100 90 –50 Max — — — -6 Min 100 110 –50 Max — — — -7 Min 100 130 –50 Max — — — Unit µs ns ns Notes 28, 29, 30, 31 EO Parameter 12 RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD ≥ tRAD (max) + tAA (max) – tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. LP Data Sheet E0154H10 ro du ct HM5118165 Series EO 20 All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS . 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS . 23. t CWL, t DH, t DS and t CSH should be satisfied by both UCAS and LCAS . 24. t CP is determined by the time that both UCAS and LCAS are high. 25. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH , and between t OFR and t OFF. 28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use t RPS instead of tRP. 29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL. LP Data Sheet E0154H10 13 ro du ct HM5118165 Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. UCAS /LCAS are allowed under the following conditions. However skew between EO RAS UCAS LCAS WE 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. LP Delayed write Early write ro RAS UCAS du t UL LCAS 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. ct Data Sheet E0154H10 14 HM5118165 Series EO Read Cycle RAS Timing Waveforms*32 t RC t RAS t RP LP t RCD tT t RAD t ASR t RAH Row t RCS t RAC t CSH t RSH t CAS t CRP UCAS LCAS t RAL t CAL t CAH t ASC Address Column t RRH t RCH ro t RCHR High-Z t OEA t CAC t CLZ WE t WED t CDD t RDD t DZC du t OED Dout Din t DZO OE t AA t OEZ t OHO t OFF t OH t OFR t OHR ct t WEZ Dout Data Sheet E0154H10 15 HM5118165 Series Early Write Cycle EO RAS UCAS LCAS Address WE Din Dout 16 tRC tRAS tRP tCSH tRCD tT tRSH tCAS tCRP LP tASR tRAH tASC Row tWCS tDS tCAH Column Data Sheet E0154H10 ro tWCH du High-Z* tDH Din ct * t WCS t WCS (min) HM5118165 Series   t OED OE EO RAS UCAS LCAS Address WE Din Dout Delayed Write Cycle*18 t RC t RAS t RP t CSH t RCD tT t RSH t CAS t CRP LP t ASR t RAH t ASC Row t RCS t DZC t DZO t CLZ t CAH Column t CWL t RWL t WP High-Z Data Sheet E0154H10 ro Invalid Dout t DS t DH t OEZ du Din t OEH High-Z ct 17 HM5118165 Series Read-Modify-Write Cycle*18 t RWC t RAS EO RAS UCAS LCAS Address WE Din OE Dout t RP tT t RCD t CAS t CRP LP t RAD t ASR t RAH Row t RCS t ASC t CAH Column t CWD t AWD t RWD tCWL t RWL t WP Data Sheet E0154H10 18 ro t DZC High-Z t DH t DS Din du t OED t OEH t DZO t OEA t CAC t AA t RAC ct High-Z t OEZ t OHO Dout t CLZ HM5118165 Series !  EO RAS RAS-Only Refresh Cycle t RC t RAS t RP tT t CRP t RPC t CRP LP t ASR Row t OFR UCAS LCAS t RAH Address t OFF Dout High-Z Data Sheet E0154H10 19 ro du ct HM5118165 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP t RAS t RC t RP  "  LCAS Address t OFR t OFF EO RAS UCAS Dout 20 tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR LP Data Sheet E0154H10 ro High-Z du ct HM5118165 Series EO RAS tT UCAS LCAS Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP t RSH t CHR t CRP t ASR t RAH Address Row LP t RCD t RAD t RAL t ASC t CAH Column t RCS WE t RRH t RCH ro t OEA t CAC t CLZ t DZC t WED t CDD t RDD High-Z du Dout Din t DZO t OED OE t AA t RAC t OFF t OH t OEZ t WEZ t OHO ct t OFR t OHR Dout Data Sheet E0154H10 21 HM5118165 Series EDO Page Mode Read Cycle t RP t RASP t CSH t CAS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP 
 OE EO RAS t RNCD tT RSH UCAS LCAS tCAS t RRH t RCH t RCS WE tASR Address tRAH tASC Row tDZC Din tDZO LP tCAH Column 1 t CAL High-Z tOEA tCPA tCAC tAA tWEZ tRAC Dout 1 t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED t CAL tRDD tCDD ro tCOL tAA tCAC tOEZ tOHO tOEA Dout 2 tCOP tOED tCPA tCPA tAA tCAC tAA tOEZ tOFR tOHR tOEZ tCAC tDOH tOHO tOEA tOHO tOFF tOH du Dout 2 Dout 3 Dout Dout 4 ct Data Sheet E0154H10 22 HM5118165 Series   OE EO RAS EDO Page Mode Read Cycle (2CAS) t RP t RASP t HPC t CAS tHPC t CP t RNCD tT t CSH t CAS t CP t CP t HPC tRSH tCAS t CRP LCAS LP tCAH Column 1 t CAL High-Z tOEA tCPA tCAC tAA tRAC Dout 1 UCAS t CAS t RCHC t RRH t RCH t RCS WE tASR Address tRAH tASC Row t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED t CAL tRDD tCDD ro tCOL tAA tCAC tOEZ tOHO tDOH tOEA Dout 2 tDZC Din tDZO tCOP tOED tCPA tAA tOEZ tOFR tOHR tOEZ tOHO tOFF tOH du tOHO Dout 2 tCAC L Dout Dout 4 tCPA tAA tCAC tOEA ct U Dout Dout 1 Dout 3 Dout 4 Data Sheet E0154H10 23 HM5118165 Series EDO Page Mode Early Write Cycle tRASP tRP EO RAS tT UCAS LCAS tASR Address WE Din Dout 24 tCSH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP Row LP tRAH tASC tCAH Column 1 tWCS tWCH tDS tDH Din 1 tASC tCAH tASC tCAH Column 2 Column N Data Sheet E0154H10 ro tWCS tDS Din 2 High-Z* tWCH tWCS tWCH tDH tDS tDH du Din N ct * t WCS t WCS (min) HM5118165 Series       t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ EO RAS tT UCAS LCAS EDO Page Mode Delayed Write Cycle*18 t RASP t RP t CP t CSH t RCD t CAS t HPC t CAS t CP t RSH t CAS t CRP LP t RAD t ASC t RAH t CAH Column 1 t RCS t WP t DZC t DS Din 1 t DZO Invalid Dout t ASR t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL Address Row t CWL t RCS ro t DH t DZO Invalid Dout WE t WP t DH Din 2 t WP t DZC t DS t DH Din N t DZC t DS Din du t DZO ct Dout High-Z Invalid Dout Data Sheet E0154H10 25 HM5118165 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP *    OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC EO RAS tT UCAS LCAS t HPRWC t CP t CAS t CP t RCD t CAS t RSH t CAS t CRP LP t RAD t ASC t RAH t CAH Column 1 t RWD t AWD t CWD t RCS t WP t DZC t DS Din 1 t DZO t OED t ASR t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address Row t CWL t RCS ro t DH t DZO t OED t CLZ Dout 2 WE t WP t DH Din 2 t WP t DZC t DS t DH Din N t DZC t DS Din du t DZO t OEH t OEZ t CLZ t OED t OEH t OEH ct t OEZ High-Z t CLZ t OEZ Dout Dout 1 Dout N Data Sheet E0154H10 26 HM5118165 Series   tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH EO RAS EDO Page Mode Mix Cycle (1) t RP t RASP t CRP tCAS tRSH t RCS tCPW tAWD tASC t CAH Column 3 t CAL t DS t DH Din 3 tOED tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH tT t CP t CAS t CSH t CAS t CP t CP tCAS UCAS LCAS t RCD t WCS WE tASR Address t ASC tRAH Row LP t WCH t RCS tCAH Column 1 t DH Din 1 t ASC t CAH Column 2 tASC t DS Din High-Z ro tCAC Dout 2 OE du t DOH tCAC t OHO Dout 3 tOEA Dout Dout 4 ct Data Sheet E0154H10 27 HM5118165 Series EDO Page Mode Mix Cycle (2) t RP t RASP EO RAS t RNCD tT t CSH t CAS t RCHR t CP t CAS t CP tCAS t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH t CRP UCAS LCAS t RCD t RCS WE tASR Address tRAH Row t ASC LP t RCH tCAH Column 1 t CAL t DS High-Z tOED tAA tOEA tCAC tOEZ t OHO Dout 1 tWCS t WCH t RCS t RRH t RCH t ASC t CAH Column 2 t ASC t CAH Column 3 t CAL t DH tRDD tCDD ro Din 2 tCOL Din tWED OE t OEA tCPA tAA tOEZ tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 du tCAC Dout 3 tRAC t OHO Dout ct Data Sheet E0154H10 28 HM5118165 Series  ,  t CSR UCAS LCAS t OFR t OFF Dout + *  $   High-Z Data Sheet E0154H10 29 EO RAS Self Refresh Cycle (L-version)* 28, 29, 30, 31 t RASS t RP t RPS tT t RPC t CP t CRP t CHS LP ro du ct HM5118165 Series Package Dimensions HM5118165J/LJ Series (CP-42D) Unit: mm 27.06 27.43 Max 22 10.16 ± 0.13 3.50 ± 0.26 21 1 1.30 Max 0.80 +0.25 –0.17 0.43 ± 0.10 0.41 ± 0.08 1.27 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-42D Conforms — 1.75 g 0.10 Dimension including the plating thickness Base material dimension Data Sheet E0154H10 30 2.50 ± 0.12 0.74 11.18 ± 0.13 EO 42 LP ro du ct HM5118165 Series 11 15 1 0.80 25 10.16 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 3.20 0.10 0.13 ± 0.05 0.50 ± 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-50/44DC Conforms — 0.50 g Data Sheet E0154H10 31 0.68 EO 50 HM5118165TT/LTT Series (TTP-50/44DC) Unit: mm 20.95 21.35 Max 40 36 26 0.27 ± 0.07 0.13 M 0.25 ± 0.05 1.15 Max LP 0.80 11.76 ± 0.20 0° – 5° ro du ct HM5118165 Series Cautions EO 32 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. LP Data Sheet E0154H10 ro du ct