HM5165165FJ-6

HM5164165F Series HM5165165F Series 64M EDO DRAM (4-Mword × 16-bit) 8k refresh/4k refresh EO Description Features E0099H10 (1st edition) (Previous ADE-203-1058C(Z)) Jan. 31, 2001 The HM5164165F S erie s, HM5165165F S erie s ar e 64M-bit dynamic R AMs orga nized as 4, 194,304-w ord × 16-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology. HM5164165F Series, HM5165165F Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have the package variations of standard 50-pin plastic SOJ and standerd 50-pin plastic TSOPII • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 50 ns/60 ns (max) • Power dissipation ⎯ Active: 432 mW/396 mW (max) (HM5164165F Series) : 504 mW/432 mW (max) (HM5165165F Series) ⎯ Standby : 1.8 mW (max) (CMOS interface) : 1.1 mW (max) (L-version) • EDO page mode capability • Refresh cycles ⎯ RAS -only refresh 8192 cycles /64 ms (HM5164165F, HM5164165FL) 4096 cycles /64 ms (HM5165165F, HM5165165FL) ⎯ CBR/Hidden refresh 4096 cycles /64 ms (HM5164165F, HM5164165FL, HM5165165F, HM5165165FL) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. L This product became EOL in December, 2006. Pr od t uc HM5164165F Series, HM5165165F Series • 4 variations of refresh ⎯ RAS -only refresh ⎯ CAS -before-RAS refresh ⎯ Hidden refresh ⎯ Self refresh (L-version) • 2CAS -byte control • Battery backup operation (L-version) EO Type No. HM5164165FJ-5 HM5164165FJ-6 HM5164165FLJ-5 HM5164165FLJ-6 HM5165165FJ-5 HM5165165FJ-6 HM5165165FLJ-5 HM5165165FLJ-6 HM5164165FTT-5 HM5164165FTT-6 HM5164165FLTT-5 HM5164165FLTT-6 HM5165165FTT-5 HM5165165FTT-6 HM5165165FLTT-5 HM5165165FLTT-6 2 Ordering Information Access time 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns Package 400-mil 50-pin plastic SOJ (CP-50DA) L Pr Data Sheet E0099H10 400-mil 50-pin plastic TSOP II (TTP-50DB) od t uc HM5164165F Series, HM5165165F Series Pin Arrangement (HM5164165F Series) 50-pin SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 50-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS EO Pin Description Pin name A0 to A12 Function I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC Write enable Power supply Ground L (Top view) Data input/output Row address strobe Output enable No connection Address input — Row/Refresh address A0 to A12 — Column address A0 to A8 Column address strobe Pr Data Sheet E0099H10 od (Top view) t uc 3 HM5164165F Series, HM5165165F Series Pin Arrangement (HM5165165F Series) 50-pin SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 50-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS EO Pin Description Pin name A0 to A11 Function I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC Write enable Power supply Ground 4 L (Top view) Data input/output Row address strobe Output enable No connection Address input — Row/Refresh address A0 to A11 — Column address A0 to A9 Column address strobe Pr Data Sheet E0099H10 od (Top view) t uc HM5164165F Series, HM5165165F Series Block Diagram (HM5164165F Series) RAS UCAS LCAS WE OE Row decoder EO A0 A1 to • • • A8 • • • A9 to A12 Timing and control Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array Column address buffers L Row buffers address I/O buffers I/O0 to I/O15 Pr Data Sheet E0099H10 od t uc 5 HM5164165F Series, HM5165165F Series Block Diagram (HM5165165F Series) RAS UCAS LCAS WE OE Row decoder EO A0 A1 to • • • A9 • • • A10 A11 6 Timing and control Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array Column address buffers L Row buffers address I/O buffers I/O0 to I/O15 Pr Data Sheet E0099H10 od t uc HM5164165F Series, HM5165165F Series Operation Table RAS H L L L L L L L L L L L L L H to L H to L H to L L LCAS × L H UCAS WE × H L × H H H L* L* L* L* L* L* 2 2 2 2 2 2 OE × L L L × × × H H H I/O 0 to I/O 7 High-Z Dout High-Z Dout Din × Din Din × Din Dout/Din High-Z Dout/Din High-Z High-Z High-Z High-Z I/O 8 to I/O 15 Operation High-Z High-Z Dout Dout × Din Din × Din Din High-Z Dout/Din Dout/Din High-Z High-Z High-Z High-Z RAS -only refresh cycle CAS -before-RAS refresh cycle or Self refresh cycle (L-version) Read-modify-write cycle Delayed write cycle Early write cycle Standby Read cycle EO L L L H L L H L L H L L H L L H L H H L L L H L L H L H L L Notes: 1. H: VIH (inactive) L: VIL (active) ×: VIH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS . (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write operation and output High-Z control are done independently by each UCAS, LCAS . ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS -before-RAS refresh cycle is selected. L H to L H to L H to L × H H H H × × × × H L to H L to H L to H Pr High-Z High-Z Data Sheet E0099H10 Read cycle (Output disabled) od t uc 7 HM5164165F Series, HM5165165F Series Absolute Maximum Ratings Parameter Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current Power dissipation Symbol VT VCC Iout PT Tstg Value –0.5 to VCC + 0.5 (≤ 4.6 V (max)) –0.5 to +4.6 50 1.0 –55 to +125 Unit V V mA W °C EO Storage temperature Parameter Supply voltage Input high voltage Input low voltage 8 DC Operating Conditions Ambient temperature range Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. L Symbol VCC VSS VIH VIL Min 3.0 0 2.0 –0.3 0 Typ 3.3 0 — — — Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V ˚C Notes 1, 2 2 1 1 Pr Ta Data Sheet E0099H10 od t uc HM5164165F Series, HM5165165F Series DC Characteristics (HM5164165F Series) HM5164165F -5 Parameter Symbol Min I CC1 I CC2 — — Max 120 2 -6 Min — — Max 110 2 Unit mA mA Test conditions t RC = min TTL interface RAS , UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min EO Operating current* * Standby current 1, 2 — 0.5 — 0.5 mA Standby current (L-version) RAS -only refresh current* 2 Standby current* 1 CAS -before-RAS refresh current EDO page mode current* 1, * 3 Battery backup current* 4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. L I CC2 I CC3 I CC5 I CC6 I CC7 I CC10 I CC11 I LI I LO VOH VOL — 300 — 300 µA — — 120 5 — — 110 5 mA mA Pr — — — 120 120 1.2 — — — — 500 — –5 –5 2.4 0 5 5 VCC 0.4 –5 –5 2.4 0 Data Sheet E0099H10 110 110 1.2 mA mA mA od 500 µA 5 5 VCC 0.4 µA µA V V CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs CMOS interface RAS , UCAS, LCAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ VCC + 0.3 V t uc 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Low Iout = 2 mA 9 HM5164165F Series, HM5165165F Series DC Characteristics (HM5165165F Series) HM5165165F -5 Parameter Symbol Min 1, 2 -6 Max 140 2 Min — — Max 120 2 Unit mA mA Test conditions t RC = min TTL interface RAS , UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs CMOS interface RAS , UCAS, LCAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ VCC + 0.3 V EO Operating current* * Standby current Standby current (L-version) Standby current* 1 I CC1 I CC2 — — — 0.5 — 0.5 mA I CC2 — 300 — 300 µA RAS -only refresh current* 2 CAS -before-RAS refresh current EDO page mode current* 1, * 3 Battery backup current* 4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. L I CC3 I CC5 I CC6 I CC7 I CC10 I CC11 I LI I LO VOH VOL — — 140 5 — — 120 5 mA mA Pr — — — 140 120 1.2 — — — — 500 — –5 –5 2.4 0 5 5 VCC 0.4 –5 –5 2.4 0 Data Sheet E0099H10 120 110 1.2 mA mA mA od 500 µA 5 5 VCC 0.4 µA µA V V t uc 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Low Iout = 2 mA 10 HM5164165F Series, HM5165165F Series Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Input capacitance (Address) Input capacitance (Clocks) Symbol CI1 CI2 CI/O Min — — — Typ — — — Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 EO Output capacitance (Data-in, Data-out) Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS , UCAS and LCAS = VIH to disable Dout. L Pr Data Sheet E0099H10 11 od t uc HM5164165F Series, HM5165165F Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)*1, *2, *19, *26 Test Conditions • • • • • Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) EO Parameter RAS precharge time CAS precharge time RAS pulse width CAS pulse width RAS hold time CAS hold time OE to Din delay time 12 Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5164165F/HM5165165F -5 Symbol t RC t RP t CP Min 84 30 8 Max — — -6 Min 104 40 10 60 10 0 10 0 Max — — — 10000 10000 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 27 27 3 4 30 Notes Random read or write cycle time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time OE delay time from Din CAS delay time from Din Transition time (rise and fall) L Pr — t RAS t CAS t ASR 50 8 0 8 0 8 — — — — t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 12 10 13 38 5 13 0 0 2 37 25 — — — — — — 50 Data Sheet E0099H10 10000 10000 od 10 14 12 15 40 45 30 — — 5 — 15 0 0 2 — — — 50 t uc ns 28 5 ns ns ns ns 6 6 7 HM5164165F Series, HM5165165F Series Read Cycle HM5164165F/HM5165165F -5 Parameter Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ Min — — — — 0 0 50 0 25 15 0 3 3 Max 50 13 25 13 — — — — — — — — — -6 Min — — — — 0 0 60 0 30 18 0 3 3 — — 15 3 Max 60 15 30 15 — — — — — — — — — 15 15 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 27 12, 28 EO Access time from OE WE to Din delay time Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE RAS to Din delay time L Pr t OH t OHO t OFF — — 13 13 — t OEZ t CDD 13 3 t OHR t OFR t WEZ t WED t RDD — — — 13 13 — — 13 13 Data Sheet E0099H10 od — — 15 15 — — 15 15 t uc 13 HM5164165F Series, HM5165165F Series Write Cycle HM5164165F/HM5165165F -5 Parameter Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 8 8 13 8 0 8 Max — — — — — — — -6 Min 0 10 10 15 10 0 10 Max — — — — — — — Unit ns ns ns ns ns ns ns 29 15, 29 15, 29 Notes 14, 27 27 EO Data-in setup time Data-in hold time Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Read-Modify-Write Cycle Read-modify-write cycle time RAS to WE delay time CAS to WE delay time OE hold time from WE Column address to WE delay time Refresh Cycle L HM5164165F/HM5165165F -5 -6 Min 140 79 34 49 15 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes Pr Symbol Min t RWC 116 67 30 42 13 — — — — — t RWD t CWD t AWD t OEH -5 Symbol t CSR t CHR t WRP t WRH t RPC Min 5 8 0 8 5 — — — — — Data Sheet E0099H10 Max od HM5164165F/HM5165165F -6 Max Min 5 Max — — 10 0 — 10 5 — — t uc Unit Notes ns ns 27 28 ns ns ns 27 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time 14 HM5164165F Series, HM5165165F Series EDO Page Mode Cycle HM5164165F/HM5165165F -5 Parameter Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 20 — — 28 3 8 5 28 8 8 Max — -6 Min 25 Max — Unit ns Notes 20 16 9, 17, 28 EO OE precharge time Parameter Parameter Refresh period EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time 100000 — 28 — — — — — — — — 35 3 10 5 35 10 10 100000 ns 35 — — — — — — — ns ns ns ns ns ns ns ns 9, 22 Read command hold time from CAS precharge Write pulse width during CAS precharge t WPE t OEP EDO Page Mode Read-Modify-Write Cycle EDO page mode read-modify-write cycle t HPRWC time WE delay time from CAS precharge t CPW Refresh (HM5164165F Series) L Pr -5 Symbol Min 57 45 — — Symbol t REF Max 64 Data Sheet E0099H10 HM5164165F/HM5165165F -6 Min Max Unit ns ns 14, 28 Notes od Max 68 54 — — Unit ms t uc Note 8192 cycles 15 HM5164165F Series, HM5165165F Series Refresh (HM5165165F Series) Parameter Refresh period Symbol t REF Max 64 Unit ms Note 4096 cycles EO Parameter 16 Self Refresh Mode (L-version) HM5164165FL/HM5165165FL -5 Symbol t RASS t RPS t CHS Min 100 90 –50 Max — — — -6 Min 100 110 –50 Max — — — Unit µs ns ns Notes 25 25 29 RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max). 11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. L Pr Data Sheet E0099H10 od t uc HM5164165F Series, HM5165165F Series 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6µs after exiting from self refresh mode. 24. In case of entering from RAS -only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25 At t RASS > 100 µs, self refresh mode is activated, and not activated at t RASS < 10 µs. It is undefined within the range of 10 µs ≤ t RASS ≤ 100 µs. For t RASS ≥ 10 µs, it is necessary to satisfy t RPS. 26. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 27. t ASC, t CAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS . 28. t CRP , t CHR, t RCH, t CPA and t CPW are determined by the later rising edge of UCAS or LCAS . 29. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS . 30. t CP is determined by the time that both UCAS and LCAS are high. 31. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. EO L Pr Data Sheet E0099H10 od t uc 17 HM5164165F Series, HM5165165F Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS /LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS EO UCAS LCAS WE RAS UCAS LCAS 18 Delayed write 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. L Pr Data Sheet E0099H10 Early write od t uc t UL HM5164165F Series, HM5165165F Series Timing Waveforms*31 Read Cycle ; t uc tOED tOEZ tOHO tOFF tOH tOFR tOHR tWEZ 19 tDZO tOEA OE tCAC tAA tRAC tCLZ Dout Dout Data Sheet E0099H10 EO RAS UCAS LCAS Address WE Din tRC tRAS tRP tCSH tT tRCD tRSH tCAS tCRP L tASR Row tRAD tASC tRAL tCAL tCAH tRAH Pr Column tRCHR tRCS tDZC High-Z tRRH tRCH od tCDD tRDD tWED HM5164165F Series, HM5165165F Series Early Write Cycle tRC tRAS tRP EO RAS UCAS LCAS Address WE Din Dout 20 tCSH tRCD tT tRSH tCAS tCRP L tASR tRAH Row tASC tCAH Pr Column tWCS tWCH od tDH tDS Din t uc * t WCS t WCS (min) High-Z* Data Sheet E0099H10 HM5164165F Series, HM5165165F Series Delayed Write Cycle*18 tRC tRAS tRP ; tDZO tOED tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout Data Sheet E0099H10 EO RAS UCAS LCAS Address WE Din tCSH tRCD tT tRSH tCAS tCRP L tASR tRAH Row tASC tCAH Column tCWL tRWL tWP Pr tRCS tDZC tDS High-Z od tDH Din t uc 21 HM5164165F Series, HM5165165F Series Read-Modify-Write Cycle*18 tRWC tRAS tRP ; tDZO tOED tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0099H10 22 EO RAS UCAS LCAS Address WE Din tT tRCD tCAS tCRP tRAD tASC tCAH L tASR Row tRAH Column tRCS tCWD tAWD tRWD tCWL tRWL tWP Pr tDZC tDS High-Z od tDH Din t uc HM5164165F Series, HM5165165F Series RAS-Only Refresh Cycle tRC tRAS tRP ; EO RAS tT tCRP tRPC tCRP UCAS LCAS tASR Row tRAH L tOFR tOFF Address Pr High-Z Dout Data Sheet E0099H10 23 od t uc HM5164165F Series, HM5165165F Series CAS-Before-RAS Refresh Cycle tRC tRP tRAS tRP tRAS tRC tRP ; 24 EO RAS UCAS LCAS WE Address tOFF Dout tT tRPC tCP tCSR tCHR tRPC tCP tCSR tCHR tCRP L tOFR tWRP tWRH tWRP tWRH Pr Data Sheet E0099H10 od High-Z t uc HM5164165F Series, HM5165165F Series Hidden Refresh Cycle tRC tRAS tRC tRAS tRC tRP tRAS tRP tRP ; Dout Dout Data Sheet E0099H10 EO RAS tT tRSH tRCD tCHR tCRP UCAS LCAS tRAD tRAL tCAH Address WE Din tDZO tOEA OE tCAC tAA tRAC tCLZ L tASR tRAH tASC Row Column Pr tRCS tRRH tRCH tDZC tWED tCDD tRDD od High-Z tOFR tOHR tOED t uc tOFF tOEZ tWEZ tOHO tOH 25 HM5164165F Series, HM5165165F Series EDO Page Mode Read Cycle t RP RAS t RASP tT t CSH t CAS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP ; OE EO UCAS LCAS WE RSH tCAS t RRH t RCH t RCS tASR tRAH tASC tCAH t WPE t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED L Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA tRAC Dout 1 Address t CAL tRDD tCDD Pr tCOL tOEP tCPA tAA tCAC tOEZ tWEZ tOHO tOEA Dout 2 Din tCOP tOEP tOED tCPA tCPA tAA tCAC tAA tOEZ tOFR tOHR tOEZ tOHO tOFF tOH od tDOH tOHO Dout 2 Dout 3 tCAC tOEA Dout Dout 4 t uc Data Sheet E0099H10 26 HM5164165F Series, HM5165165F Series EDO Page Mode Read Cycle (2CAS control) t RP RAS t RASP t HPC t CAS tHPC t CP t CP t HPC tRSH tCAS t CRP ; tRAC tDOH tOEA tCAC tOHO L Dout EO tT LCAS UCAS WE t CSH t CAS t CP t CAS t RCHC t RRH t RCH t RCS tASR Address L tRAH tASC tCAH Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA t ASC t CAH Column 2 t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Pr t CAL tCOL tOEP tCPA tAA tCAC tOEZ tOHO Dout 1 Dout 2 Dout 1 t CAL tRDD tCDD Din tCOP od tOEP tOEZ Dout 2 tCPA tAA tCAC Dout 3 tOED OE tCPA tAA tOFR tOHR tOEZ tOHO tOFF tOH t uc Dout 4 tOEA Dout 4 U Dout Data Sheet E0099H10 27 HM5164165F Series, HM5165165F Series EDO Page Mode Early Write Cycle tRASP tRP EO RAS tT UCAS LCAS tASR tRAH Address Row WE Din Dout 28 tCSH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP L tASC tCAH tASC tCAH tASC tCAH Column 1 Column 2 Column N Pr tWCS tWCH tWCS tWCH tDS tDH tDS tDH Din 1 Din 2 High-Z* Data Sheet E0099H10 tWCS tWCH od tDS tDH Din N t uc * t WCS t WCS (min) HM5164165F Series, HM5165165F Series EDO Page Mode Delayed Write Cycle*18 tRASP ; OE tCLZ tCLZ tCLZ tOEZ tOEZ EO RAS tT UCAS LCAS tASR tRP tCP tCSH tRCD tCAS tHPC tCAS tCP tRSH tCAS tCRP tRAD Address Dout L tRAH tASC tCAH tASC tCAH tASC tCAH Row Column 1 tCWL Column 2 tCWL tRCS Column N tCWL tRWL tRCS Pr tRCS tWP tDZC tDS tWP tDZC tDS tDH WE tWP tDZC tDS tDH od tDH Din tDZO tOED Din 1 tOEP tOEH Din 2 Din N tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH t uc tOEZ High-Z Invalid Dout Invalid Dout Invalid Dout Data Sheet E0099H10 29 HM5164165F Series, HM5165165F Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP ; OE EO RAS tT t HPRWC t CP t RCD t CAS t CAS t CP t RSH t CRP t CAS UCAS LCAS t ASR Address WE Din t DZO t OED Dout L t RAD t ASC t RAH Row t RCS t AA t OEA t CAC t RAC t CLZ t CAH t ASC t CAH Column 2 t ASC t CAH Column N Column 1 t RWD t AWD t CWL t CPW t CWL t RCS t CPW t AWD t CWD t CWL t RWL Pr t CWD t RCS t AWD t CWD t WP t WP t WP t DZC t DS t DH Din N od t DZC t DS t DH Din 2 t DZC t DS t DH Din 1 t OEP t OEH t DZO t OED t OEP t OEH t DZO t OED t OEP t OEH t uc t OHO t OEZ High-Z t OHO t OHO t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t OEZ t CLZ t OEZ t CLZ Dout 1 Dout 2 Dout N Data Sheet E0099H10 30 HM5164165F Series, HM5165165F Series EDO Page Mode Mix Cycle (1) *20 t RP RAS t RASP t CRP tCAS tCWL t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 3 tOED tOEP tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS tRSH t RRH t RCH ; OE EO tT UCAS LCAS t CP t CAS t CSH t WCS t WCH t CAS t CP tCAS t CP t RCD WE L tASR t ASC tRAH Row Column 1 t DS t DH Din 1 tASC Address Pr High-Z tCPA tAA tOEA tCPA tAA tCAC t DOH Dout 2 Din tCPA t OEZ tAA tOFR tWEZ tOEZ od tCAC t OHO tOEA Dout 3 tCAC tOHO tOFF tOH Dout Dout 4 t uc 31 Data Sheet E0099H10 HM5164165F Series, HM5165165F Series EDO Page Mode Mix Cycle (2)* 20 t RP RAS t RASP CAS tT EO UCAS LCAS WE t CSH t CAS t RCHR t CP t CAS t CP tCAS tCWL t RCS tCPW t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH t CRP t RCD t RCS t RCH tWCS t WCH t RRH t RCH tASR t ASC tRAH L tCAH Row Column 1 t CAL High-Z tAA tOEA tCAC tRAC t OHO Dout 1 t ASC t CAH Column 2 t ASC t CAH Column 3 Address t DS t DH t DH Din 3 t OEP tOED tCOP tRDD tCDD Pr Din 2 t OEP tOED tCOL t OEA tOEZ tCPA tAA Din tWED OE tCPA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 od tCAC tOEZ t OHO Dout 3 tAA tCAC tOEA Dout t uc Data Sheet E0099H10 32 HM5164165F Series, HM5165165F Series Self Refresh Cycle (L-version)* 23, 24, 25 tRASS tRP tRPS ; ; tRPC tCP tCSR UCAS LCAS tWRP WE Dout ; tOFF High-Z Data Sheet E0099H10 EO RAS tT tCRP tCHS tWRH L tOFR Pr od t uc 33 HM5164165F Series, HM5165165F Series Package Dimensions HM5164165FJ/FLJ Series HM5165165FJ/FLJ Series (CP-50DA) 1 0.47 25 3.50 ± 0.26 0.90 ± 0.26 2.55 ± 0.12 1.09 Max 10.16 ± 0.13 11.18 ± 0.13 EO 34 Unit: mm 20.95 21.38 Max 50 26 *Dimension including the plating thickness Base material dimension L *0.32 ± 0.08 0.30 ± 0.04 Pr 0.80 0.10 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-50DA Conforms — 1.2 g Data Sheet E0099H10 od t uc HM5164165F Series, HM5165165F Series HM5164165FTT/FLTT Series HM5165165FTT/FLTT Series (TTP-50DB) Unit: mm 0.10 *0.145 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 1.20 Max 0.50 ± 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-50DB — — 0.51 g Data Sheet E0099H10 35 0.68 EO 1 20.95 21.35 Max 26 50 0.80 25 0.10 *0.30 + 0.05 – 0.28 ± 0.05 0.13 M 11.76 ± 0.20 0° – 5° 10.16 L 1.15 Max 0.80 Pr od t uc HM5164165F Series, HM5165165F Series Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. EO 36 L Pr Data Sheet E0099H10 od t uc