M2S56D40AKT

DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM DESCRIPTION M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40A achieve very high speed data rate up to 166MHz(-60), 133MHz(-75A/-75) and are suitable for main memory in computer systems. FEATURES - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and data mask are referenced to both edges of DQS - 4-bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge is controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4) / A0-9(x8) / A0-8(x16) - SSTL_2 Interface - Both 66-pin TSOP Package and 64-pin Small TSOP Package M2S56D*0ATP: 0.65mm lead pitch 66-pin TSOP Package M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package - JEDEC standard - Low Power for the Self Refresh Current Ultra Low Power Version : ICC6 < 1mA ( -60UL , -75AU , -75UL ) Low Power Version : ICC6 < 2mA ( -60L , -75AL , -75L ) Operating Frequencies Max. Frequency @CL=2.0 * M2S56D20/30/40ATP - 60UL / - 60L / - 60 M2S56D20/30/40AKT - 60UL / - 60L / - 60 M2S56D20/30/40ATP - 75AU / - 75AL / - 75A M2S56D20/30/40AKT - 75AU / - 75AL / - 75A M2S56D20/30/40ATP - 75UL / - 75L / - 75 M2S56D20/30/40AKT - 75UL / - 75L / - 75 * CL = CAS(Read) Latency This Product became EOL in July, 2004.  Elpida Memory, Inc. 2003 Max. Frequency @CL=2.5 * 166MHz 133MHz 133MHz Standard DDR333B DDR266A DDR266B 133MHz 133MHz 100MHz 1 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM PIN CONFIGURATION 1 (TOP VIEW) x4 x8 x16 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP(II) 400mil width x 875mil length 0.65mm Lead Pitch ROW A0-12 Column A0-9,11(x4) A0-9 (x8) A0-8 (x16) CLK,/CLK CKE /CS /RAS /CAS /WE DQ0-15 DQS LDQS,UDQS : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe DM LDM,UDM VREF A0-12 BA0,1 VDD VDDQ VSS VSSQ : Write Mask : Reference Voltage : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output 2 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM PIN CONFIGURATION 2 (TOP VIEW) X4 X8 X 16 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS VSS DQ15 DQ7 VSSQ VSSQ DQ14 NC DQ13 DQ6 VDDQ VDDQ DQ12 NC DQ11 DQ5 VSSQ VSSQ DQ10 NC DQ9 DQ4 VDDQ VDDQ DQ8 NC VSSQ VSSQ UDQS DQS NC NC VREF VREF VSS VSS UDM DM /CLK /CLK CLK CLK CKE CKE NC NC A12 A12 A11 A11 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 VSS VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 64pin sTSOP CLK,/CLK CKE /CS /RAS /CAS /WE DQ0-15 DQS LDQS,UDQS : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe PIN PITCH 0.4 mm DM LDM,UDM VREF A0-12 BA0,1 VDD VDDQ VSS VSSQ : Write Mask : Reference Voltage : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output 3 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM PACKAGE OUTLINE OF sTSOP .05 0.125 +0.02 -0 64 33 A 10.65+0.2 *2 9.05+0.1 1 *1 32 13.1+0.1 1.2 MAX B 0.4 NOM 0.1 *3 0.16 -0.05 +0.1 0.08 M 0 - 10 0.25 0.8 (1) 0.125+0.075 0.5+0.1 0.6+0.15 Note) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 0.35 0.55 MAX Detail A (NTS) Detail B (NTS) 4 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM PIN FUNCTION SYMBOL TYPE DESCRIPTION Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh.After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. CLK, /CLK Input CKE Input /CS /RAS, /CAS, /WE Input Input A0-12 Input BA0,1 DQ0-15(x16), DQ0-7(x8), DQ0-3(x4), DQS Input Input / Output Data Input/Output: Data bus Data Strobe: Output pin during Read operation, input pin during Write Input / Output operation. Edge-aligned with read data, placed at the centered of write data to capture the write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a WRITE operations. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. DM Input VDD, VSS VDDQ, VSSQ VREF Power Supply Power Supply for the memory array and peripheral circuitry. Power Supply VDDQ and VSSQ are supplied to the Output Buffers only. Input SSTL_2 reference voltage. 5 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM BLOCK DIAGRAM DLL DQ0 - 15 UDQS,LDQS I/O Buffer QS Buffer Memory Array Bank #0 Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer Clock Buffer A0-12 BA0,1 CLK /CLK CKE Control Signal Buffer /CS /RAS /CAS /WE UDM, LDM TYPE DESIGNATION CODE M 2 S 56 D 3 0 A KT – 60 UL This rule is applied to only Synchronous DRAM family. Power Grade UL/U: Ultra Low power L: Low power, Blank: standard Speed Grade 75: 133MHz@CL=2.5,100MHz@CL=2.0 (DDR266B) 75A: 133MHz@CL=2.5,133MHz@CL=2.0 (DDR266A) 60: 166MHz@CL=2.5,133MHz@CL=2.0 (DDR333B) Package Type TP: TSOP(II), KT: sTSOP(Small TSOP) Process Generation Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 DDR Synchronous DRAM Density 56: 256M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) Mitsubishi Main Designation 6 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM BASIC FUNCTIONS The M2S56D20/30/40A provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. Refer to the command truth table for the detailed definition of commands. /CLK CLK /CS /RAS /CAS /WE CKE A10 Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates one row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (autoprecharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write (auto-precharge, WRITEA) Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated internally. After this command, the banks are precharged automatically. 7 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM COMMAND TRUTH TABLE COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE WRITEA CKE n-1 H H H H H H H CKE n X X H H H H H /CS H L L L L L L /RAS /CAS X H L L L H H X H H H H L L /WE BA0,1 X H H L L L L X X V V X V V A10 /AP X X V L H L H A0-9, 11-12 X X V X X V V Note READ H H L H L H V L V READA REFA REFS REFSX TERM MRS H H H L L H H H H L H H H H L L L H L L L H L L X H H L L L L X H H L H H H X H L L V X X X X X L H X X X X X L V X X X X X V 1 2 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. Applies only to read bursts while autoprecharge is disabled; this command is undefined (and should not be used) during read bursts while autoprecharge is enabled, as well as during write bursts. 2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-codes to be written to the selected Mode Register. 8 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (1/4) Current State /CS /RAS /CAS /WE Address IDLE H X X XX L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L L ROW ACTIVE H L L L L L L L L READ(AutoPrecharge Disabled) H L L L L L L L L L L L X H H H H L L L L X H H H H L L L L H L L X H H L L H H L L X H H L L H H L L L H L X H L H L H L H L X H L H L H L H L BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action NOP NOP ILLEGAL ILLEGAL Bank Active, Latch RA NOP Auto-Refresh Mode Register Set NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine AutoPrecharge ILLEGAL Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL Notes 2 2 4 5 5 2 3 2 9 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (2/4) Current State /CS /RAS /CAS /WE Address X X XX WRITE(Auto- H Precharge L H H HX Disabled) L H H L BA L L L L L L READ with AutoPrecharge H L L L L L L L L WRITE with AutoPrecharge H L L L L L L L L H H L L L L X H H H H L L L L X H H H H L L L L L L H H L L X H H L L H H L L X H H L L H H L L H BA, CA, A10 L BA, CA, A10 Command DESEL NOP TERM Action NOP (Continue Burst to END) Notes H BA, RA L BA, A10 HX Op-Code, L Mode-Add XX HX L BA H BA, CA, A10 L BA, CA, A10 H BA, RA L BA, A10 HX Op-Code, L Mode-Add XX HX L BA H BA, CA, A10 L BA, CA, A10 H BA, RA L BA, A10 HX Op-Code, L Mode-Add NOP (Continue Burst to END) ILLEGAL Terminate Burst, Latch CA, Begin READ / READA Read, Determine Auto-Precharge Terminate Burst, Latch CA, Begin WRITE / WRITEA Write, Determine Auto-Precharge ACT Bank Active / ILLEGAL PRE / PREA Terminate Burst, Precharge REFA ILLEGAL MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for Same Bank ILLEGAL for Same Bank Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for Same Bank ILLEGAL for Same Bank Bank Active / ILLEGAL Precharge / ILLEGAL ILLEGAL ILLEGAL 3 3 2 6 6 2 2 7 7 2 2 10 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (3/4) Current State /CS /RAS /CAS /WE Address H X X XX PRECHARGING L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L L L L X H H H L L L L X H H H L L L L H L L X H H L H H L L X H H L H H L L L BA, A10 HX Op-Code, L Mode-Add XX H L X H L X BA BA, CA, A10 BA, RA BA, A10 Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2 2 2 2 2 2 2 2 Notes 2 2 2 4 HX Op-Code, L Mode-Add XX H L X H L X BA BA, CA, A10 BA, RA BA, A10 HX Op-Code, L Mode-Add 11 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (4/4) Current State /CS /RAS /CAS /WE Address REFRESHING H X X XX L H H HX L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, L L L L Mode-Add H X X XX MODE REGISTER L H H HX SETTING L H H L BA L H L X BA, CA, A10 L L H H BA, RA L L H L BA, A10 L L L HX Op-Code, L L L L Mode-Add Command DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TERM READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRFC) NOP (Idle after tRFC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tMRD) NOP (Idle after tMRD) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries are valid only when CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of specific bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to Read with Auto-Precharge in page 28. 7. Refer to Write with Auto-Precharge in page 30. ILLEGAL = Device operation and/or data-integrity are not guaranteed. 12 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE for CKE Current State CKE n-1 CKE n H X SELFL H REFRESHING L H L H L H L H L L H X POWER L H DOWN L L H H ALL BANKS H L IDLE H L H L H L H L H L L ANY STATE other than listed above H H L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS X X H H H L X X X X X L X H H H L X X X X X /CAS X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Address X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self-Refresh (Idle after tRFC) Exit Self-Refresh (Idle after tRFC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle Exit CLK Suspend at Next Cycle Maintain CLK Suspend Notes 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. Low to High transition of CKE re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command except REFSX. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. 13 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM SIMPLIFIED STATE DIAGRAM POWER APPLIED POWER ON PREA PRE CHARGE ALL REFS SELF REFRESH MRS / EMRS MRS / EMRS MODE REGISTER SET REFSX REFA IDLE AUTO REFRESH CKEL CKEH Active Power Down CKEH ACT CKEL POWER DOWN ROW ACTIVE WRITE WRITE WRITEA READA READ READ READ BURST STOP WRITE READ TERM WRITEA READA READA WRITEA PRE PRE PRE READA PRE CHARGE Automatic Sequence Command Sequence 14 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM POWER ON SEQUENCE The following power on sequences are necessary to guarantee the proper operations of the DDR SDRAM. 1. Apply VDD before or at the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & VREF 3. Maintain stable conditions for 200us after stable power and CLK are applied, assert NOP or DSEL 4. Issue Precharge command for all banks of the device 5. Issue EMRS to program proper functions 6. Issue MRS to configure the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable conditions for 200 cycle After these sequences, the DDR SDRAM is in the idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by configuring the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tMRD from an MRS command, the DDR SDRAM is ready to accept the new command. CLK /CLK /CS /RAS /CAS /WE BA1 BA0 A12 A11 A10 A9 0 0 0 0 0 0 A8 DR A7 0 A6 A5 A4 A3 BT A2 A1 BL A0 BA0 BA1 LTMODE A11-A0 V Latency Mode 0 0 0 0 1 1 1 1 CL 00 01 10 11 00 01 10 11 /CAS Latency R R 2 R R R 2.5 R NO YES Burst Length BL 000 001 010 011 100 101 110 111 BT=0 R 2 4 8 R R R R BT=1 R 2 4 8 R R R R Burst Type DLL Reset 0 1 0 1 Sequential Interleaved R: Reserved for Future Use 15 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM EXTENDED MODE REGISTER DLL disable / enable mode can be programmed in the extended mode register (EMRS). The extended mode register stores these data until the next EMRS command, which may be issued when all banks are in idle state. After tMRD from a EMRS command, the DDR SDRAM is ready to accept the new command. CLK /CLK /CS /RAS /CAS BA1 BA0 A12 A11 A10 A9 0 1 0 0 0 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 DS A0 DD /WE BA0 BA1 A11-A0 V DLL Disable 0 1 DLL Enable DLL Disable Drive Strength 0 1 Normal Weak (Optional) 16 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM /CLK CLK Command Address DQS DQ CL= 2 BL= 4 Read Y Write Y Q0 Q1 Q2 Q3 D0 D1 D2 D3 /CAS Latency Burst Length Burst Length Initial Address BL A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 8 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 Sequential 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 2 17 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD VDDQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature TA = 25 C o Conditions with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ Ratings -0.5 to 3.7 -0.5 to 3.7 -0.5 to VDD+0.5 -0.5 to VDDQ+0.5 50 1000 0 to 70 -65 to 150 Unit V V V V mA mW o o C C DC OPERATING CONDITIONS (TA=0 to 70oC, unless otherwise noted) Symbol VDD VDDQ VREF VIH(DC) VIL(DC) VIN(DC) VID(DC) VTT Limits Unit Notes Min. Typ. Max. Supply Voltage 2.3 2.5 2.7 V Supply Voltage for Output 2.3 2.5 2.7 V Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 5 High-Level Input Voltage VREF + 0.15 VDDQ+0.3 V Low-Level Input Voltage -0.3 VREF - 0.15 V Input Voltage Level, CLK and /CLK -0.3 VDDQ + 0.3 V Input Differential Voltage, CLK and /CLK 0.36 VDDQ + 0.6 V 7 I/O Termination Voltage VREF - 0.04 VREF + 0.04 V 6 Parameter AC OVERSHOOT/UNDERSHOOT SPECIFICATION Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or euqal to The area between the undershoot signal and VSS must be less than or euqal to 5 4 3 2 1 VSS(0) -1 -2 -3 Overshoot Maximum Amplitude VDD Area (max.4.5V-ns) Specification 1.6V 1.6V 4.5 V-ns 4.5 V-ns Volts (V) Undershoot Maximum Amplitude 7.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 5.625 Time (ns) 18 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM AVERAGE SUPPLY CURRENT from VDD (TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted) Symbol Parameter/Test Conditions Organization Limits(Max.) -60 -75A / -75 100 110 120 140 10 85 95 100 115 6 Unit Notes OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; IDD0 t CK = t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank; Active-Read-Precharge; IDD1 Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA; Address and control inputs changing once per clock cycle IDD2P PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; CKE VIH (MIN); All banks idle; IDD2F CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing once per clock cycle IDD3P ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-down mode; CKE < VIL (MAX); t CK = t CK MIN ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and DQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle ALL 35 30 ALL 20 15 IDD3N ALL x4 x8 x16 x4 x8 x16 ALL -60/-75A/-75 55 180 190 220 180 190 220 150 3 2 1 270 290 330 45 140 150 180 130 140 160 140 3 2 1 215 235 270 mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank IDD4R active; Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK MIN; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; IDD4W CL=2.5; t CK = t CK MIN;DQ, DM and DQS inputs changing twice per clock cycle IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN) 9 9,21 9,22 20 20 20 IDD6 SELF REFRESH CURRENT: CKE < 0.2V -60/-75A/-75 L -60/-75AU/-75 UL x4 OPERATING CURRENT-Four bank Operation: Four bank are interleaved IDD7 with BL=4, refer to the Notes 20 x8 x16 AC OPERATING CONDITIONS AND CHARACTERISTICS (TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, Output Open, unless otherwise noted) Symbol Parameter / Test Conditions Limits Min. VREF + 0.31 VREF - 0.31 0.7 -5 -2 -16.8 16.8 VDDQ + 0.6 5 2 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 Max. Unit V V V V uA uA mA mA 7 8 Notes VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) Input Differential Voltage, CLK and /CLK VIX(AC) Input Crossing Point Voltage, CLK and /CLK IOZ II IOH IOL Off-state Output Current /Q floating Vo=0 to VDDQ Input Current / VIN=0 to VDDQ Output High Current (VOUT = VTT+0.84V) Output High Current (VOUT = VTT-0.84V) 19 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM AC TIMING REQUIREMENTS (1/2) (TA=0 to 70oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted) -60 Min. -0.70 -0.60 0.45 0.45 CL=2.5 CL=2 6 7.5 0.45 0.45 1.75 -0.70 -0.70 tCLmin or tCHmin tHPtQHS 0.55 0.75 0.35 0.35 0.2 0.2 12 0 0.4 0.25 0.75 0.75 0.8 0.8 0.4 0.9 0.6 1.1 0.6 1.25 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 0.9 0.9 0.9 0.9 0.4 0.9 0.6 1.1 0.6 0.70 0.70 0.45 tCLmin or tCHmin tHPtQHS 0.75 1.25 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 0.9 0.9 0.9 0.9 0.4 0.9 0.6 1.1 0.6 Max 0.70 0.60 0.55 0.55 15 15 Min. -0.75 -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 -0.75 0.75 0.75 0.5 tCLmin or tCHmin tHPtQHS 0.75 1.25 -75A Max 0.75 0.75 0.55 0.55 15 15 Min. -0.75 -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.75 -0.75 0.75 0.75 0.5 -75 Max 0.75 0.75 0.55 0.55 15 15 Symbol tAC tCH tCL tCK tDS tDH tDIPW tHZ tLZ AC Characteristics Parameter DQ Output Valid data delay time from CLK//CLK CLK High level width CLK Low level width CLK cycle time Input Setup time (DQ,DM) Input Hold time(DQ,DM) DQ and DM input pulse width (for each input) Data-out-high impedance time from CLK//CLK Data-out-low impedance time from CLK//CLK Unit ns ns tCK tCK ns ns ns ns ns ns ns ns ns Notes tDQSCK DQ Output Valid data delay time from CLK//CLK 26,27 26,27 14 14 tDQSQ DQ Valid data delay time from DQS tHP Clock half period tQH tQHS Output DQS valid window Data Hold Skew Factor ns tCK tCK tCK tCK tCK tCK ns ns tCK tCK ns ns ns ns tCK tCK 23,25 23,25 24,25 24,25 16 15 tDQSS Write command to first DQS latching transition tDQSH DQS input High level width tDQSL DQS input Low level width tDSS tDSH tMRD DQS falling edge to CLK setup time DQS falling edge hold time from CLK Mode Register Set command cycle time tWPRES Write preamble setup time tWPST Write postamble tWPRE Write preamble tIH tIS tIH tIS Address and Control input hold time(fast slew rate) Address and Control input hold time(fast slew rate) Address and Control input hold time(Slow slew rate) Address and Control input hold time(Slow slew rate) tRPST Read postamble tRPRE Read preamble 20 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM AC TIMING REQUIREMENTS (2/2) (TA=0 to 70oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted) -60 Min. 42 60 72 18 18 12 15 35 1 75 200 1 1 7.8 Max 120,000 Min. 45 65 75 20 20 15 15 35 1 75 200 1 1 7.8 -75A Max 120,000 Min. 45 65 75 20 20 15 15 35 1 75 200 1 1 7.8 -75 Max 120,000 Symbol tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWTR AC Characteristics Parameter Row Active time Row Cycle time(operation) Auto Ref. to Active/Auto Ref. command period Row to Column Delay Row Precharge time Act to Act Delay time Write Recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay Unit ns ns ns ns ns ns ns ns tCK ns tCK tCK tCK us Notes tXSNR Exit Self Ref. to non-Read command tXSRD Exit Self Ref. to -Read command tXPNR Exit Power down to command tXPRD Exit Power down to -Read command tREFI Average Periodic Refresh interval 18 17 Output Load Condition DQS V TT =V REF 50Ω V OUT Zo=50Ω 30pF V REF VREF DQ VREF Output Timing Measurement Reference Point CAPACITANCE (TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Limits Delta Unit Notes Min. Max. Cap.(Max.) Input Capacitance, address pin VI=1.25v 2.0 3.0 pF 11 0.50 Input Capacitance, control pin f=100MHz 2.0 3.0 pF 11 Input Capacitance, CLK pin VI=25mVrms 2.0 3.0 0.25 pF 11 I/O Capacitance, I/O, DQS, DM pin 4.0 5.0 0.50 pF 11 Parameter Test Condition 21 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM Note: 1. All voltages are referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics, may be conducted at nominal reference/supply voltage levels. However, the specifications and device operations are guaranteed for the full voltage range specified. 3. AC timing and IDD tests may use the VIL to VIH swing of up to 1.5V in the test environment. Input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 5. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +2% of the DC value. 6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK. 8. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized. 11. This parameter is sampled. VDDQ = 2.5V+0.2V, VDD = 2.5V + 0.2V , f = 100 MHz, TA = 25oC, VOUT(DC) = VDDQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input reference level for signals other than CLK//CLK, is VREF. 13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE< 0.3VDDQ is recognized as LOW. 14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and satisfies the input slew rate specifications. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 17. A maximum of eight AUTO REFRESH commands can be asserted to any given DDR SDRAM device. 18. tXPRD should be 200 tCLK when the clocks are unstable during the power down mode. 19. (no data : deleted 10/’02) (Notes continued on next page) 22 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM Note (Continued) : 20. IDD7 : Operating current is measured under the conditions (1).Four Bank are being interleaved with tRC(min),burst mode,address and control inputs on NOP edge are not changing.Iout = 0mA (2).Timing Patterns -DDR266B(-75) (133MHz,CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Setup:A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 Read :A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing 50% of data changing at every transfer -DDR266A(-75A) (133MHz,CL=2) : tCK=7.5ns, CL=2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing 50% of data changing at every transfer -DDR333B(-60) (166MHz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing 50% of data changing at every transfer *Legend: A=Active,R=Read, RA=Read with Autoprecharge ,P=Precharge, N=DESELECT 21. Low Power Version (-60L/-75AL/-75L) 22. Ultra Low Power Version (-60UL/-75AU/-75UL) 23. For command/address and CK & /CK slew rate > 1.0V/ns. 24. For command/address and CK & /CK slew rate > 0.5V/ns 25. Input Setup & Hold Time Derating for Slew Rate Input slew Rate 0.5V/ns 0.4V/ns 0.3V/ns ∆ tIS 0 +50 +100 ∆ tIH 0 +50 +100 Unit ps ps ps This derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns.The input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. 26. I/O Setup & Hold Time Derating for Slew Rate I/O Input slew Rate 0.5V/ns 0.4V/ns 0.3V/ns ∆ tDS 0 +75 +150 ∆ tDH 0 +75 +150 Unit ps ps ps This derating factor will be used to increase tDS and tDH in the case where the I/O slew rate is below 0.5V/ns.The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The I/O slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. (Notes continued on next page) 23 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM Note (Continued) : 27. I/O Setup & Hold Time Derating for Rise/Fall Delta Slew Rate Delta slew Rate +0.0ns/V +0.25ns/V +0.5ns/V ∆ tDS 0 +50 +100 ∆ tDH 0 +50 +100 Unit ps ps ps This derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. The delta Rise/Fall Rate is calculated as; {1/(Slew Rate1)} - {1/(Slew Rate2)} For example: If Slew Rate1 is 0.5V/ns and Slew Rate2 is 0.4V/ns, then delta Rise/Fall Rate = - 0.5V/ns. Using the table given, this would result in the need for an increase in tDS and tDH for 100ps. 24 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM TIMING CHART Read Operation /CLK CLK Cmd & Add. tDQSCK tCK tCH tCL tIS tIH VREF Valid Data tRPRE tQH tRPST DQS tDQSQ DQ tAC Write Operation / tDQSS=max. /CLK CLK DQS tDQSS tWPRES tDSS tDQSL tDS tDQSH tDH tWPST tWPRE DQ Write Operation / tDQSS=min. /CLK CLK DQS tDQSS tWPRES tWPRE tDQSL tDS tDQSH tDH tDSH tWPST DQ 25 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM OPERATIONAL DESCRIPTION BANK ACTIVATE (ACT) The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation interval between banks is tRRD. PRECHARGE (PRE) The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA,PRE+A10=H) is available to deactivate all banks at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=8, CL=2) /CLK CLK 2 ACT command / tRCmin tRCmin Command A0-9,11 ACT tRRD Xa ACT READ tRAS Xb tRCD Y BL/2 0 PRE tRP ACT Xb A10 BA0,1 Xa Xb 1 Xb 00 01 00 01 DQS DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Precharge all A precharge command can be issued after BL/2 time from a read command. 26 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM READ After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data. (BL : Burst Length) The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address sequence of burst data is defined by the Burst Type. A READ command may be issued to any active bank, so the row precharge time (tRP) can be hidden during the continuous burst data by interleaving the multiple banks. When A10 is high in READ command, the auto-precharge (READA) is performed. Any command (READ,WRITE,PRE,ACT) asserted to the same bank is inhibited till the internal precharge is completed. The internal precharge operation starts at BL/2 time after READA command. The next ACT command can be issued after (BL/2+tRP) time from the previous READA. Multi Bank Interleaving READ (BL=8, CL=2) /CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ /CAS latency Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8 ACT tRCD Xa Xa 00 READ ACT Y 0 00 Xb Xb 10 READ PRE Y 0 10 0 00 Burst Length 27 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM READ with Auto-Precharge (BL=8, CL=2,2.5) 0 1 2 3 4 5 6 7 8 9 10 11 12 /CLK CLK Command ACT tRCD READA BL/2 + tRP BL/2 Y 1 00 tRP A0-9,11 A10 BA0,1 DQS CL=2 DQ DQS CL=2.5 DQ Xa Xa 00 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Internal Precharge starting Timing Asserted Command READ READA WRITE(CL=2) WRITE(CL=2.5) WRITEA(CL=2) For Different Bank 3 Legal Legal 4 Legal Legal 5 Legal Legal 6 Legal Legal 7 Legal Legal 8 9 10 Legal Legal Legal Legal Legal Legal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal WRITEA(CL=2.5) Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal ACT PCG Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Operating description when new command is asserted. 28 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM WRITE After tRCD time from the bank activation, a WRITE command can be issued. 1st input data is sampled at the WRITE command with data strobe input, followed by (BL-1) data being written into RAM.The Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden during the continuous input data by interleaving the multiple banks. The write recovery time (tWR) is required from the last written data to the next PRE command. When A10 is high in a WRITE command, the auto-precharge(WRITEA) is performed. Any command (READ,WRITE,PRE,ACT) asserted to the same bank is inhibited till the internal precharge operation is completed. The next ACT command can be issued after tDAL from the last input data cycle. Multi Bank Interleaving WRITE (BL=8) /CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7 ACT Xa Xa 00 tRCD D WRITE ACT Ya 0 00 Xb Xb 10 tRCD D WRITE Yb 0 10 PRE PRE 0 00 0 10 29 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM WRITE with Auto-Precharge (BL=8) 0 1 2 3 4 5 6 7 8 9 10 11 12 /CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 ACT Xa Xa 00 D WRITEA tRCD Y 1 00 BL/2 tDAL ACT Xb Xb 00 Asserted Command READ READA WRITE WRITEA ACT PCG For Different Bank 3 Illegal Illegal Legal Legal Legal Legal 4 Illegal Illegal Legal Legal Legal Legal 5 6 7 Illegal Illegal Legal Legal Legal Legal 8 Legal Legal Legal Legal Legal Legal 9 Legal Legal Legal Legal Legal Legal 10 Legal Legal Legal Legal Legal Legal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Legal Legal Legal Operating description when new command is asserted. 30 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM BURST INTERRUPTION [Read Interrupted by Read] Burst read operation can be interrupted by the new Read command issued to any other bank. Random column access is allowed. READ to READ interval is 1CLK as the minimum. Read Interrupted by Read (BL=8, CL=2) /CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7 READ READ Yi 0 00 Yj 0 00 READ Yk 0 10 READ Yl 0 01 [Read Interrupted by precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is 1 CLK minimum. The time between PRE command to output disable is equal to the CAS Latency. As a result, READ to PRE interval determines valid data length to be outputted. The figure below shows the examples of BL=8. Read Interrupted by Precharge (BL=8) /CLK CLK Command DQS DQ Command READ PRE Q0 Q1 Q2 Q3 Q4 Q5 READ PRE CL=2.5 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ PRE 31 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM Read Interrupted by Precharge (BL=8) /CLK CLK Command DQS DQ Command READ PRE Q0 Q1 Q2 Q3 Q4 Q5 READ PRE CL=2.0 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ PRE 32 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Read Interrupted by Burst Stop] Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval is 1 CLK minimum. The time between TERM command to output disable is equal to the CAS Latency. As a result, READ to TERM interval determines valid data length to be outputted. The figure below shows example of BL=8. Read Interrupted by TERM (BL=8) /CLK CLK Command DQS DQ Command READ TERM Q0 Q1 Q2 Q3 Q4 Q5 READ TERM CL=2.5 DQS DQ Command DQS DQ Command DQS DQ Command READ Q0 Q1 Q2 Q3 Q4 Q5 Q0 Q1 Q0 Q1 Q2 Q3 READ TERM READ TERM TERM CL=2.0 DQS DQ Command DQS DQ Q0 Q1 Q0 Q1 Q2 Q3 READ TERM 33 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Read Interrupted by Write with TERM] Read Interrupted by TERM (BL=8) /CLK CLK Command READ TERM WRITE CL=2.5 DQS DQ Command READ TERM Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 WRITE CL=2.0 DQS DQ Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 34 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Write interrupted by Write] Burst write operation can be interrupted by Write to any bank. Random column access is allowed. WRITE to WRITE interval is 1 CLK minimum. Write Interrupted by Write (BL=8) /CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7 WRITE WRITE Yi 0 00 Yj 0 00 WRITE Yk 0 10 WRITE Yl 0 00 [Write interrupted by Read] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. Internal WRITE to READ command interval(tWTR) is 1 CLK minimum. The input data masked by DM in the interrupted READ cycle is "don't care". tWTR is referenced from the first positive edge after the last data input. Write Interrupted by Read (BL=8, CL=2.5) /CLK CLK Command A0-9,11 A10 BA0,1 DM QS DQ Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7 WRITE Yi 0 00 READ Yj 0 00 tWTR 35 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Write interrupted by Precharge] Burst write operation can be interrupted by precharge of the same or all bank. Random column access is allowed. tWR is referenced from the first positive CLK edge after the last data input. Write Interrupted by Precharge (BL=8, CL=2.5) /CLK CLK Command A0-9,11 A10 BA0,1 DM QS DQ Dai0 Dai1 WRITE Yi 0 00 PRE 00 tWR 36 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Initialize and Mode Register sets] Initialize and MRS /CLK CLK CKE Command A0-9,11 A10 BA0,1 DQS DQ tMRD Extended Mode Register Set 1 NOP PRE EMRS Code Code MRS Code Code PRE AR AR MRS ACT Xa 1 Code Xa Xa 10 00 00 tMRD tRP tRFC tRFC tMRD Mode Register Set, Reset DLL [AUTO REFRESH] Auto-refresh cycle is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256 Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must be in the idle state. The minimum internal between auto-refresh is tRFC . No command is allowed within tRFC time after the REFA command. Auto-Refresh /CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 tRFC NOP or DESELECT Auto Refresh on All Banks Auto Refresh on All Banks 37 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [SELF REFRESH] Self -refresh mode is entered by asserting a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). The selfrefresh mode is maintained as long as CKE is kept low. During the self-refresh mode, CKE becomes asynchronous and the only enable input. All other inputs including CLK are disabled and ignored to save the power consumption. In order to exit the self-refresh mode, the device shall be supplied the stable CLK inputs, followed by DESEL or NOP command, then asserting CKE for the period longer than tXSNR/tXSRD. Self-Refresh /CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 tXSNR Self Refresh Entry Self Refresh Exit Stable CLK X X tXSRD Y Y 38 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM [Power DOWN] The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh mode. A commands are ignored. From CKE=H to normal function, DLL recovery time is NOT required when the stable CLK is supplied during the power down mode. Power Down by CKE /CLK CLK CKE Command CKE Command ACT NOP PRE NOP Standby Power Down NOP Valid tXPNR/tXPRD Active Power Down NOP Valid [DM CONTROL] DM is defined as the data mask for write data. During writes, DM masks the input data cycle by cycle. Latency of DM to write mask is 0. DM Function(BL=8,CL=2) /CLK CLK Command DM DQS DQ D0 D1 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 WRITE READ Don't Care masked by DM=H 39 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 40 DDR SDRAM E0338M10 (Ver.1.0) (Previous Rev.1.54E) Jan. '03 CP(K) M2S56D20/ 30/ 40ATP M2S56D20/ 30/ 40AKT 256M Double Data Rate Synchronous DRAM The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 41