EM198810W

EM198810 Datasheet INTEGRATED CIRCUIT Elan Design DATA SHEET EM198810 2.4 GHz ISM Band Transceiver/Framer IC Preliminary Data Sheet ELAN MICROELECTRONICS CORP. No.12, Innovation 1st RD., Science-based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5782037(SL) 5630118 (SA2) This spec is subject to change without any notice 1 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design CONTENTS 1. 2. 3. Features Block Diagram Pins/pads name and pins/pads location 3.1 3.2 3.3 3.4 Pins name Package outline Pads name and location Order information 4. Digital Base Band Interface 4.1 4.2 SPI Command Format Register Information 4.2.1 Package type define and FIFO point set 4.2.2 Digital Interface 4.2.3 Typical Register Values 4.2.4 State Diagram 5. 6. 7. Electrical Characteristics Application Reference Design Soldering This spec is subject to change without any notice 2 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 2.4 GHZ ISM BAND TRANSCEIVER/FRAMER IC 1. FEATURES The EM198810 is a CMOS integrated circuit that performs all functions from the antenna to the microcontroller for transmission and reception of a 2.4GHz digital data. This transceiver IC integrates most of the functions required for data transmission into a single integrated circuit. Additionally, the programmability implemented reduces significantly external components count, board space requirements and external adjustments. Key Features: - Combines 2.4 GHz GFSK RF transceiver with 8-bit data framer function - Eliminates need for external software or hardware FIFO; offloads MCU for other tasks - Simple microprocessor interface – 4 wires for SPI, plus 3 wires for RST/buffer control - Each transmit, receive buffer is 64 bytes deep - Long packets are possible if buffers are read/written before overflow/underflow occurs - Always 1Mbps over-the-air symbol rate, regardless of MCU speed or architecture - Preamble can be 1 to 8 bytes - Supports 1, 2, 3, or 4 word address (up to 64 bits) - Various Payload data formats to eliminate DC offset, enhance receive clock recovery and BER - Programmable data whitening - Supports Forward Error Correction (FEC): none, 1/3, or 2/3 - Supports 16-bit CRC - Baseband output clock available - Power management for minimizing current consumption - 5x5mm QFN package with minimum RF parasitic - Lead-free packaging and dice is available on request Applications - Wireless devices that need quick time-to-market - Simple and fast wireless data networks - Cordless headsets and Cellular Phones - Wireless streaming audio - Wireless voice and VOIP - Wireless Skype earphone - Home and factory automation - Wireless security and access control - Battery Powered wireless devices This spec is subject to change without any notice 3 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 1.1 Description The Elan EM198810 IC is a low-cost, fully integrated CMOS radio frequency (RF) transceiver block, combined with a 64-byte buffered framer block. The RF transceiver block is a self-contained, fasthopping GFSK data modem, optimised for use in the widely available 2.4 GHz ISM band. It contains transmit, receive, VCO and PLL functions, including an on-chip channel filter and resonator, thus minimizing the need for external components. The receiver utilizes extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. Transmit power is digitally controlled. The low-IF receiver architecture results in sensitivity to -80dBm or better, with impressive selectivity. In normal applications, the EM198810 is connected to a low cost microcontroller(ex:EM78P451S). In normal application The on-chip framer processes and stores the RF data in the background, unloading this critical timing function from the MCU. This lowers MCU speed requirements, expedites product development time, and frees the MCU for implementing additional product features. The framer register settings determine the over-the-air formatting characteristics. Many configurations are possible, depending on the user’s specific needs. Raw transmit data is easily sent over-the-air as a complete frame of data, with preamble, address, payload, and CRC. Receiving data is just the opposite, using the preamble to train the receiver clock recovery, then the address is checked, then the data is reverse formatted for receive, followed by CRC. All of this is done in hardware to ease the programming and overhead requirements of the baseband MCU. For longer battery life, power consumption is minimized by automatic enabling of the various transmit, receive, PLL, and PA sections, depending on the instantaneous state of the chip. A sleep mode is also provided for ultra low current consumption. This product is available in 32-lead 5x5 mm JEDEC standard QFN package, featuring an exposed pad on the bottom for best RF characteristics. Lead-free RoHS compliant packaging is available on request. This spec is subject to change without any notice 4 / 18 24.Dec.2006 Vdd +1.8V RF Vdd Low Dropout Voltage Reg. SPI Bus SPI_SS SPI_CLK TX Data EM198810 Datasheet 2. Block diagram LDO_Vout LDO_Vdd Vdd_io Digital State Machine and Register Block Data Framing Buffer and Logic This spec is subject to change without any notice TX MOD_trim 2.4GHZ GFSK Transmitter CLK Analog PLL freq. control (APLL) SPI_MISO SPI_MOSI FIFO_FLAG PKT_FLAG RESET_n RXCLK TR Switch RF Synthesizer - Fig. 1 – INTEGRATED CIRCUIT 5 / 18 ANT 2.4GHZ GFSK Receiver BRCLK Clock Recov. XTALO Oscillator / Buffer XTALI Elan Design 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 3. Pins names and pins location 3.1 Pins names SYMBOL VDD VDD NC GND ANT VDD NC NC VDD VDD NC NC NC BRCLK PKT_FLAG RXCLK FIFO_FLAG VDD GND SPI_SS SPI_MOSI SPI_CLK RESET_n Type PWR PWR -GND 50ΩRF PWR --PWR PWR ---O O O O PWR GND I I I I PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Power supply voltage. DO NOT CONNECT. Reserved for factory test. Ground connection. RF input/output. Power supply voltage. DO NOT CONNECT. Reserved for factory test. Power supply voltage. DO NOT CONNECT. Reserved for factory test. DESCRIPTION SPI_MISO VDD_IO LDO_VDD LDO_OUT LOD_TUNE GND VDD XTALO XTALI GND O PWR PWR PWR -GND PWR AO AI GND 24 25 26 27 28 29 30 31 32 Exposed pad Outputs 1MHz TX symbol clock, 12MHz APLL, or crystal clock. See register definitions for details. Transmit/Receive packet process flag. Receiver symbol timing clock recovery output. Fixed at 1MHz fundamental rate. FIFO full/empty flag. Power supply voltage. Ground connection. Enable line for the SPI bus. Active low. Data input for the SPI bus. Clock line for the SPI bus. When RESET_n is low, most of the chip shuts down to conserve power. When raised high, RESET_n is used to turn on the chip,restoring all registers to their default value. Data output for the SPI bus. Vdd for the digital i/o pins. Nominally +3.3 VDC. Unregulated input to the on-chip LDO volt. regulator. +1.8V output of the on-chip LDO voltage regulator. Fine-tune for the on-chip LDO voltage regulator. Ground connection. Power supply voltage. Output of the crystal oscillator gain block. Input to the crystal oscillator gain block. Ground connection. - Table 1 – This spec is subject to change without any notice 6 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design SPI_MISO SPI_MOSI SPI_CLK GND 23 24 22 21 20 19 18 VDD VDD_IO LDO_VDD LDO_VOUT LDO_TUNE GND VDD XTALO XTALI 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 17 FIFO_FLAG RESET_n SPI_SS 16 15 14 13 12 RXCLK PKT_FLAG BRCLK NC NC NC VDD VDD EM198810 11 10 9 VDD 1 NC NC VDD GND - Figure 2 – 3.2 Package Outline QFN32 Lead Exposed Pad Package, 5x5 mm Pkg. 0.5mm Pitch (JEDEC) MO-220-A This spec is subject to change without any notice 7 / 18 VDD ANT NC 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 3.3 Pads name and location SYMBOL PLL_VDD(A) RF_VSS(A) VCO_GDD(A) nc RF_VSS(A) ANTb(A) RF_VSS(A) ANT(A) RF_VSS(A) RF_VDD(A) Injp(A) Injp(A) IF_VDD(A) VCO_VDD(A) AMS_AVDD(A) MONIp(A) MONIn(A) TP_BG_IV/TP_VTUNE(A) BRCLK(D) BPKTCTL(D) RXDATA(D) RXCLK(D) testse(D) BXTLEN(D) TEST1(D) VDD_DIG(D) VSS_DIG(D) BnDEN(D) TEST2(D) BDDATA(D) BDCLK(D) BnPWR(D) BDATA1(D) spi_select(D) VDD_IO(D) ckpha(D) LDO_VDD(A) LDO_OUT_VDD(A) LDO_TUNE(A) AMS_DVSS(A) AMS_DVDD(A) XTALO(A) XTALI(A) VCO_VSS(A) PAD no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - Table 2 Center pad position X;Y in microns 35.837 ; 1622.464 35.836 ; 1498.956 35.837 ; 1378.956 35.387 ; 1257.956 35.383 ; 1018.956 35.837 ; 897.956 35.837 ; 778.957 35.789 ; 657.956 35.835 ; 583.952 35.837 ; 418.957 35.837 ; 178.096 222.918 ; 35.006 341.926 ; 35.006 462.016 ; 35.006 581.926 ; 35.006 702.926 ; 35.006 1464.189 ; 35.005 1584.188 ; 35.006 1820.067 ; 34.006 1940.067 ; 34.006 2081.185 ; 219.891 2081.185 ; 339.891 2081.185 ; 459.891 2081.185 ; 579.891 2081.185 ; 699.891 2081.185 ; 821.027 2081.185 ; 941.027 2081.185 ; 1059.839 2081.185 ; 1179.893 2081.185 ; 1299.893 2081.185 ; 1420.890 2081.185 ; 1539.891 2081.185 ; 1659.889 1885.495 ; 1804.847 1762.415 ; 1804.847 1641.438 ; 1804.847 1445.424 ; 1804.847 1318.773 ; 1803.847 1199.684 ; 1803.847 1075.434 ; 1803.847 955.348 ; 1803.847 833.526 ; 1803.946 671.538 ; 1803.946 550.438 ; 1803.847 3.4 Order information Type number Name EM198810W QFN32 EM198810H Bare die Package Description Plastic, quad flat package; no leads; 32 terminals; body 5 x 5 x 0.8 mm available This spec is subject to change without any notice 8 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 4 Digital Base Band Interface 4.1 SPI Command Format The SPI interface is used to program the IC via the 4 pins SPI_CLK, SPI_SS, SPI_MOSI and SPI_MISO. The SPI_MOSI and SPI_CLK pins are used to load data into an internal shift register. The SPI_MOSI and SPI_CLK pins are use to send data to microcontroller. The data are loaded into the shift register and sent to microcontroller on the rising edge of the clock SPI_CLK and latched on the rising edge of the SPI_SS signal. When the SPI_SS pin is high, the data stored in the shift register is retained even if a SPI_CLK is applied. When the SPI_SS pin is low the data can be rewritten and resent. Inputs timing of the SPI_CLK, SPI_SS, SPI_MOSI and SPI_MISOD are shown in the Fig.2. Format 1 CKPHA = 0: SP I _CL K SP I _SS SP I _MO SI R/W A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D 8 D7 D6 D5 D4 D3 D2 D1 D 0 D7 D6 D5 D4 D3 D2 D1 D0 SP I _MI SO S7 S6 S5 S4 S3 S2 S1 S0 D15 D14 D13 D12 D11 D10 D9 D 8 D7 D6 D5 D4 D3 D2 D1 D 0 D7 D6 D5 D4 D3 D2 D1 D0 Format 2 CKPHA = 1: SPI_CLK SPI_SS SPI_MOSI SPI_MISO R/W A6 S7 S6 A5 A4 S5 S4 A3 A2 S3 S2 A1 S1 A0 S0 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D8 D7 D7 D6 D5 D4 D6 D5 D4 D3 D2 D3 D2 D1 D0 D1 D0 D7 D6 D7 D6 D5 D4 D5 D4 D3 D2 D3 D2 D1 D0 D1 D0 D8 - Fig. 3 – 4.2 Register Information 4.2.1 Package type define and FIFO point set preamble SYNC trailer payload CRC Automatically set FIFO write_point=0 when RX received SYNC Automatically set FIFO read_point=0 when RX received SYNC or after transmit SYNC when TX - Figure 4 – * Preamble: 1 ~ 8 bytes programmable * SYNC: 32/48/64 bits programmable as device syncword * Trailer: 4~16 bits programmable * Payload: TX/RX data, there are 4 data types: raw data, 8_10 bits, Manchester, interleave with FEC option * CRC: 16 bit CRC is option Note: For transmit, it is needed to clear FIFO write point before application write in data via access reg82[15]. This spec is subject to change without any notice 9 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 4.2.2 Digital Interface It is very simple interface with application, consisting of SPI interface plus two handshake signals (Table 2). The EM198810 SPI can only support slave mode. Pin SPI_CLK SPI_SS SPI_MOSI SPI_MISO PKT_FLAG FIFO_FLAG RESET_n Description SPI clock input SPI slave select input SPI data in SPI data out Packet TX/RX flag FIFO full/empty Reset input, active low - Table 3 - 4.2.3 Typical Register Values The following register values (Table 3) are recommended for the Elan Microelectronics details define refer to registers definitions Reg. address 0 2 4 5 9 14 16 18 19 20 21 22 23 24 25 26 48 51 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default value (Hexadecimal) 0000 00C1 0688 0041 0003 6617 0000 FC00 0014 8103 0962 2602 2602 30C0 3814 5304 1800 4000 - Table 4 Recommend value (12MHz crystal frequency) (Hexadecimal) CD51 0061 3CD0 00A1 3003 6697 F000 E000 2114 819C 6962 0402 0802 B080 7819 6704 5800 A000 For more detail description about digital base band interface, please refer to application note AN198810-1. For the latest register value recommendations, please contact Elan Microelectronics technical group. This spec is subject to change without any notice 10 / 18 24.Dec.2006 EM198810 Datasheet 4.2.4 State Diagram INTEGRATED CIRCUIT Elan Design off RESET_n = 1 sleep SPI_SS=1 reg48[2]=1 & SPI_SS=1 power on register initialization wake up idle reg7[8]=1 reg7[7]=1 tx_start wait_txsyn rx_start wait_rxsyn reg50[15:8]us tx_done reg51[15:8]us tx packet done or reg7[8]=0 tx_pa_on reg50[7:0]us rx_data rx packet done or reg7[7]=0 tx_data rx_done - Figure 5 - This spec is subject to change without any notice 11 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 5.Electrical Characteristics 5.1 Absolute Maximum Rating Parameter Operating Temp. Storage Temp. VDD_IO Supply Voltage VDD Supply Voltage Applied Voltages to Other Pins Input RF Level Output Load mismatch (Z0=50 ohm) Symbol Min. TOP -40 -55 Rating Typ. Unit Max. +85 ℃ TSTORAGE +125 ℃ VDDIO_MAX +3.7 VDC VDD_MAX +2.5 VDC VOTHER -0.3 +3.7 VDC PIN +10 dBm VSWROUT 10:1 VSWR - Table 5 Note: 1.Absoute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section below. 2.These devices are electro-static sensitive. Devices should be transported and stored in antistatic containers. Equipment and personnel contacting the devices need to be properly grounded. Cover workbenches with grounded conductive mats. 5.2 Characteristics The following specifications are guaranteed for TA=25℃, VDD=1.80±0.18VDC, unless otherwise noted: Parameter Current Consumption Current Consumption - TX Current Consumption - RX Current Consumption – DEEP IDLE Current Consumption – SLEEP Digital Inputs Logic input high Logic input low Input Capacitance Input Leakage Current Digital Outputs Logic output high Logic output low Output Capacitance Output Leakage Current Rise/Fall Time Clock Signals BRCLK output frequency Symbol IDD_TX IDD_RX IDD_D_IDLE IDD_SLP VIH VIL C_IN I_LEAK_IN VOH VOL C_OUT I_LEAK_OUT T_RISE_OUT FBRCLK Specification Min. Typ. Max. 26 25 1.9 3.5 0.8VDD_io 0 VDD_io 0.8 10 10 VDD_io 0.4 10 10 5 1, 12, or xtal Freq. 200 0 2402 12 2482 Unit Test Condition and Notes mA mA mA uA V V pF uA V V pF uA nS MHz Depends on Register settings. POUT = nominal output power RF Synthesizer and VCO: OFF (see Reg. 21) 0.8VDD_io SPI_CLK rise, fall time SPI_CLK frequency range Overall Transceiver Operating Frequency Range This spec is subject to change without any notice Tr_spi FSPI F_OP nS MHz MHz Always either: 1 MHz Tx clock, 12 MHz APLL clock (Tx, Rx, and Idle), or the buffered 12 MHz crystal oscillator frequency. Requirement for error-free register reading, writing. 12 / 18 24.Dec.2006 EM198810 Datasheet Antenna port mismatch (Z0=50Ω) VSWR_I VSWR_O INTEGRATED CIRCUIT 3MHz offset IBS_3 Out-of-Band Spurious Emission Operation OBS_O_1