EM39LV80055RD

EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION General Description The EM39LV800 is an 8M bits Flash memory organized as 512K x 16 bits. The EM39LV800 uses 2.7-3.6V power supply for Program and Erase. Featuring high performance Flash memory technology, the EM39LV800 provides a typical Word-Program time of 14 µsec and a typical Sector/Block-Erase time of 18 ms. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a greater than 10 years data retention. The EM39LV800 conforms with the JEDEC standard pin outs for x16 memories. The EM39LV800 is offered in package types of 48-ball FBGA, 48-pin TSOP, and known good dice (KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed information (see Appendix at the bottom of this specification for Ordering Information). The EM39LV800 devices are developed for applications that require memories with convenient and economical updating of program, data or configuration, e.g., DVD player, DVD R/W, WLAN, Router, Set-Top Box, etc. Features Single Power Supply Full voltage range from 2.7 to 3.6 volts for both read and write operations Sector-Erase Capability Uniform 2Kword sectors Block-Erase Capability Uniform 32Kword blocks Read Access Time Access time: 55, 70 and 90 ns Power Consumption Active current: 20 mA (Typical) Standby current: 2 µA (Typical) Erase/Program Features Sector-Erase Time: 18 ms (Typical) Block-Erase Time: 18 ms (Typical) Chip-Erase Time: 45 ms (Typical) Word-Program Time: 14µs (Typical) Chip Rewrite Time: 8 seconds (Typical) Automatic Write Timing Internal VPP Generation End-of-Program or End-of-Erase Detection Data# Polling Toggle Bit CMOS I/O Compatibility JEDEC Standard Pin-out and software command sets compatible with single-power supply Flash memory High Reliability Endurance cycles: 100K (Typical) Data retention: 10 years Package Option 48-pin TSOP 48-pin FBGA This specification is subject to change without further notice. (04.09.2004 V1.0) Page 1 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Functional Block Diagram Flash Mem ory Array X -Decoder Mem ory Address Address Buffer & Latches Y-Decoder CE# OE# W E# Control Logic I/O Buffers and Data Latches DQ15-DQ0 Figure 0a: Functional Block Diagram Pin Assignments TSOP A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Standard TSOP Figure 0b: TSOP Pin Assignments This specification is subject to change without further notice. (04.09.2004 V1.0) Page 2 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION FBGA FBGA Top View, Balls Facing Down A13 A12 A14 A15 A16 NC DQ15 VSS A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 W E# NC NC NC DQ5 DQ12 VDD DQ4 NC NC A18 NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS Figure 0c: FBGA Pin Assignments Pin Description Pin Name A0–A18 DQ15–DQ0 CE# OE# WE# VDD VSS NC 19 addresses Data inputs/outputs Chip enable Output enable Write enable 2.7 ~ 3.6 volt single power supply Device ground Pin not connected internally Function Table 1: Pin Description This specification is subject to change without further notice. (04.09.2004 V1.0) Page 3 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Device Operation The EM39LV800 uses Commands to initiate the memory operation functions. The Commands are written to the device by asserting WE# Low while keeping CE# Low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the EM39LV800 is controlled by CE# and OE#. Both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for further details. Word Program The EM39LV800 is programmed on a word-by-word basis. Before programming, the sector where the word is located must be erased completely. The Program operation is accomplished in three steps: The first step is a three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams respectively and Figure 15 for flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any command issued during the internal Program operation is ignored. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 4 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION EM39LV800 Device Operation Operation Read Program Erase Standby Write Inhibit Write Inhibit Software Mode Product Identification CE# VIL VIL VIL VIH X X VIL OE# VIL VIH VIH X VIL X VIL WE# VIH VIL VIL X X VIH VIH DQ DOUT DIN X * Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X See Table 3 High Z High Z/DOUT High Z/DOUT * X can be VIL or VIH, but no other value. Table 2: EM39LV800 Device Operation Write Command/Command Sequence The EM39LV800 provides two software methods to detect the completion of a Program or Erase cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operation is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection, when an erroneous result occurs, the software routine should include an additional two times loop to read the accessed location. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Chip Erase The EM39LV800 provides Chip-Erase feature, which allows the entire memory array to be erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 17 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 5 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Sector/Block Erase The EM39LV800 offers both Sector-Erase and Block-Erase modes. The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The sector architecture is based on uniform sector size of 2 KWord. The Block architecture is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined by using either Data# Polling or Toggle Bit method. See Figures 7 and 8 for timing waveforms. Any commands issued during the Sector or Block Erase operation are ignored. Data# Polling (DQ7) When the EM39LV800 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce the true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Program operation, the remaining data outputs may still be invalid (valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs). During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase, Block-Erase, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 14 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase, Block-Erase or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 14 for a flowchart. Data Protection The EM39LV800 provides both hardware and software features to protect the data from inadvertent write. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 6 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Hardware Data Protection Noise/Glitch Protection: VDD Power Up/Down Detection: Write Inhibit Mode: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. The Write operation is inhibited when VDD is less than 1.5V. Forcing OE# Low, CE# High, or WE# High will inhibit the Write operation. This prevents inadvertent write during power-up or power-down. Software Data Protection (SDP) The EM39LV800 provides the JEDEC approved Software Data Protection (SDP) scheme for Program and Erase operations. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, especially during the system power-up or power-down transition. Any Erase operation requires the inclusion of six-byte sequence. See Table 3 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) The EM39LV800 contains the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command, with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 4 through 6. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 7 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Software Command Sequence Command Sequence Word Program Sector Erase Block Erase Chip Erase Software ID 5,6 Entry Manufacture ID Manufacture ID Manufacture ID Device ID CFI Query Entry Software ID Exit7/CFI Exit Software ID Exit7/CFI Exit 5 1st Bus Write Cycle Addr 1 2nd Bus Write Cycle Addr 1 3rd Bus Write Cycle Addr 1 4th Bus Write Cycle Addr WA 1 5th Bus Write Cycle Addr 1 6th Bus Write Cycle Addr 1 Data 2 Data 2 Data 2 Data 2 Data 2 Data 2 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H XXH 5555H AAH AAH AAH AAH AAH AAH AAH AAH AAH AAH F0H AAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H 55H 55H 55H 55H 55H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H A0H 80H 80H 80H 90H 90H 90H 90H 90H 98H 3 Data AAH AAH AAH 2AAAH 2AAAH 2AAAH 55H 55H 55H SAX4 BAX 4 5555H 5555H 5555H 30H 50H 10H 5555H 0000H 0007F 0003H 0007F 0040H 0001F 0001H 0020H 2AAAH 55H 5555H F0H Notes: 1. Address format A14-A0 (Hex), Addresses A18-A15 can be VIL or VIH, but no other value, for the Command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence. 3. WA = Program word address. 4. SAX for Sector-Erase; uses A18-A11 address lines. BAX for Block-Erase; uses A18-A15 address lines. 5. The device does not remain in Software Product ID mode if powered down. 6. Both Software ID Exit operations are equivalent. 7. Refer to Figure 9 for more information. Table 3: Software Command Sequence This specification is subject to change without further notice. (04.09.2004 V1.0) Page 8 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION CFI Query Identification String* Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Primary OEM command set Data Query Unique ASCII string “QRY” Address for Primary Extend Table Alternate OEM command set (00H=none exists) Address for Alternate OEM extended Table (00H=none exists) * Refer to CFI publication 100 for more details. Table 4: CFI Query Identification String1 System Interface Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H VDD Min (Program/Erase) Data DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H=no VPP pin) VPP max (00H=no VPP pin) Typical time out for Word-Program 2 µs (2 =16µs) Typical time out for min size buffer program 2N µs (00H=not supported) Typical time out for individual Sector/Block-Erase 2N ms (24=16ms) Typical time out for Chip-Erase 2 ms (2 =64ms) Maximum time out for Word-Program 2 times typical (2 x2 =32µs) Maximum time out for buffer Program 2N times typical Maximum time out for individual Sector/Block-Erase 2 times typical (21x24=32ms) Maximum time out for Chip-Erase 2 times typical (2 x2 =128ms) N 1 6 N N 1 4 N 6 N 4 Table 5: System Interface This specification is subject to change without further notice. (04.09.2004 V1.0) Page 9 of 25 EM39LV800 8M Bits (512Kx16) Flash Memory SPECIFICATION Device Geometry Information Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0014H 0001H 0000H 0000H 0000H 0002H 00FFH 0000H 0010H 0000H 000FH 0000H 0000H 0001H N Data Device size=2 Byte (14H=20; 2 =1MByte) Flash Device Interface description; 0001H=x16-only asynchronous interface Maximum number of byte in multi-byte write=2N (00H=not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y+1=Number of sectors; z x 256B=sector size) y=255+1=256 sectors (00FFH=255) z=16 x 256 Bytes=4Kbyte/sector (0010H=16) Block Information (y+1=Number of blocks; z x 256B=block size) y=15+1=16 blocks (000FH=15) z=256 x 256 Bytes=64 Kbyte/block (0100H=256) 20 Table 6: Device Geometry Information Absolute Maximum Ratings NOTE Applied conditions greater than those listed under these ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this specification, are not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias ............................................................ –55°C to 125°C Storage Temperature .................................................................. –65°C to 150°C D.C. Voltage on Any Pin to Ground Potential ............................. –0.5 V to VDD+0.5V Transient Voltage (