EPVP6810

ePVP6810 VFD Controller Product Specification VERSION 1.23 ELAN MICROELECTRONICS CORP. Nov 2004 Trademark Acknowledgments IBM is a registered trademark and PS/2 is a trademark of IBM. Microsoft, MS, MS-DOS, and Windows are registered trademarks of Microsoft Corporation. © 2004 ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan, ROC, 05/26/2004 (Version 1.0) The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility for errors that may appear in this specification. ELAN Microelectronics makes no commitment to update, or to keep current, the information contained in this specification. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of the agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics products in such application is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. Specification Revision History Version 1.0 1.1 Initial version Revision Description Date 2004/5/26 2004/06/23 ADD Relevant Pins assigment Revices DC Electrical Characteristic Revices cpu Feature Describe Application notes additional remark Application notes Revised CONT register describe 1.2 1.21 1.22 1.23 2004/9/16 2004/9/24 2004/11/4 2004/11/28 Updata Pckage Information IC Name change Revised Feature register describe additional remark Application notes Revised Operation Voltage VS PLL Operation frequency ii ePVP6810 Specification Contents Read Me First! ..............................................................................................................vi 1 2. General Description...............................................................................................1 Feature....................................................................................................................1 2.1 2.2 2.3 2.4 2.5 2.6 CPU ........................................................................................................................................ 1 GPIO ....................................................................................................................................... 1 ADC ........................................................................................................................................ 2 VFD ........................................................................................................................................ 2 POR........................................................................................................................................ 2 PACKAGE .............................................................................................................................. 2 3 4 5 Application .............................................................................................................2 VFD controller ..................................................................................................................................... 2 Pin Configuration...................................................................................................3 Functional Block Diagram.....................................................................................4 5.1 Ports Mapping for HV and GPIO ............................................................................................ 5 5.1.1 HV Port Mapping ................................................................................................5 5.1.2 GPIO Port Mapping ............................................................................................5 5.2 6 7 Relevant Pins for programming mode .............................................................5 Pin Descriptions ....................................................................................................6 Function Descriptions ...........................................................................................8 7.1 7.2 Operation Registers Configuration......................................................................................... 8 Operation Registers Description ............................................................................................ 9 7.2.1 R0 (Indirect Address Register) ................................................................................... 9 7.2.2 R1 (TCC) .................................................................................................................... 9 7.2.3 R2 (Program Counter) ................................................................................................ 9 7.2.4 R3 (Status, Page Selection) ..................................................................................... 10 7.2.5 R4 (RAM Selection For Common Registers R20 ~ R3F))........................................ 11 7.2.6 R5 (PORT5 Output Data, Program Page Selection) ................................................ 11 7.2.7 R6 (PORT6 Output Data) ......................................................................................... 11 7.2.8 R7 (PORT7 Output Data, ADC , Counter1 Data ...................................................... 11 7.2.9 R8 (PORT8 Output data, Data RAM address) , Counter2_LB data ......................... 14 7.2.10 R9 (PORT9 I/O Data, Data RAM Data Buffer), Counter2_HB Data ................................................................................................... 15 e PV6810 Specification iii 7.3 7.4 7.4 7.5 7.6 7.7 7.8 7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer), ADC Output Data Buffer , Counter3 Data................................................................. 16 7.2.12 RB (PORTB I/O Data Buffer, PORT9 Switches)....................................................... 18 7.2.13 RC (PORTC I/O Data , Counter5 Data).................................................................... 19 7.2.14 RD (Interrupt Flag,)................................................................................................... 19 7.2.15 RE (Interrupt Flags, Wake-up).................................................................................. 20 7.2.16 RF (Interrupt Flags) .................................................................................................. 20 7.2.17 R10~R3F (General Purpose Registers) ................................................................... 21 Special Purpose Registers ................................................................................................... 21 7.3.1 A (Accumulator) ........................................................................................................ 21 7.3.2 CONT (Control Register) .......................................................................................... 21 7.3.3 IOC 5 (PORT5 Switches) ......................................................................................... 23 7.3.4 IOC 8 ........................................................................................................................ 23 7.3.5 IOC9 (PORT9 I/O Control) ....................................................................................... 24 7.3.6 IOCA ......................................................................................................................... 25 7.3.7 IOCB (PORTB I/O Control, PORTB Switch) ............................................................ 25 7.3.8 IOCC (PORTC I/O Control) ...................................................................................... 26 7.3.9 IOCD (Interrupt Mask, Prescaler of CN3 ~ CN5) ..................................................... 26 7.3.10 IOCE (Interrupt Mask) .............................................................................................. 27 7.3.11 IOCF (Interrupt Mask ).............................................................................................. 27 Application notes I/O Port ................................................................................................................................. 29 RESET ................................................................................................................................. 29 Wake Up............................................................................................................................... 30 7.6.1 SLEEP Mode, RA(6 ;7) = 0 + "SLEP" Instruction..................................................... 30 7.6.2 IDLE mode, RA(6 ;7) = 1 + "SLEP" Instruction. ....................................................... 30 7.6.3 Wake-up from SLEEP Mode..................................................................................... 30 7.6.4 Wake-up from IDLE Mode ........................................................................................ 31 Interrupts .............................................................................................................................. 31 Instruction Set ...................................................................................................................... 31 8 9 Segment Data Buffers .........................................................................................33 RC/Crystal OSC....................................................................................................35 9.1 9.2 9.3 9.4 9.5 General Description.............................................................................................................. 35 Features ............................................................................................................................... 35 Block Diagram ...................................................................................................................... 35 Pin Description ..................................................................................................................... 35 Electrical ............................................................................................................................... 35 10 Absolute Operation Maximum Ratings ..............................................................36 11 DC Electrical Characteristic................................................................................36 12 AC Electrical Characteristic................................................................................38 12.1 12.2 12.3 iv CPU Instruction Timing (Ta = -20°C ~ 70°C, VDD=5V, VSS=0V) ....................................... 38 AC Timing Characteristic (VDD=5V, Ta=+25°C) .................................................................. 39 ePVP6810 Operating Voltage (X Axis Min VDD ; Y Axis Main CLK) ......................... 39 ePVP6810 Specification 12.4 AC Timing Diagrams ........................................................................................................... 40 13 Key & Switch Scanning and Display Timing .....................................................41 14 Switching Characteristic Waveform ...................................................................42 14.1 Switching Characteristics (Ta = - 20 to + 70°C, VDD = 4.5 to 5.5V, VEE = VDD - 45V) .... 42 e PV6810 Specification v Read Me First! Before using the chip, spare a few minutes to take a look at the following important notes. 1. Some bits in the registers are undefined. The values in these bits are unknown and should not be used. These bits are designated with a dash “–” symbol as its bit name in this specification. 2. The following table shows the definitions of the various register designations used to identify bit types, bit name, and bit number. Some definitions will appear quite frequently in the specification. RA PAGE0 7 RAB7 R/W -0 Bit type Bit name Bit number R egister name and its page 6 RAB6 R/W -0 read/write (default value=0) 5 BAB5 R-1 4 RAB4 R/W -1 read/write (default value=1) 3 - 2 RAB2 R 1 RAB1 R-0 0 RAB0 R/W read/write (w/o default value) read only (w/o default value) (undefined) not allowed to use read only (default value=1) read only (default value=0) vi ePVP6810 Specification ePVP6810 VFD Controller 1 General Description The ePVP6810 is an 8-bit RISC type vacuum fluorescent display (VFD) controller equipped with low power consumption and high speed CMOS technology. This integrated single chip features on_chip watchdog timer (WDT), one time programming ROM (OTP), data RAM, programmable real time clock/counter, internal interrupt, power down mode, 10-bit A/D converter, IR detector, and high voltage output for VFD application. 2. Feature 2.1 CPU Clock source：Crystal Oscillator Crystal Oscillator (32.768KHz): with a external crystal 4k x 13 on chip Program ROM. 128 x 8 on chip data RAM 144 x 8 general purpose registers 16 level stack for subroutine nesting 5 channel 8-bit counters: real time clock/counter (TCC) ,COUNTER1, COUNTER3, COUNTER4, COUNTER5 1 channel 16-bit counter: COUNTER2 On-chip watchdog timer (WDT) 99.9％ single instruction cycle commands Four operation modes Mode Sleep mode Idle mode Green mode Normal mode CPU Status Turn off Turn off Turn on Turn on Main Clock Turn off Turn off Turn off Turn on 32.768kHz Clock Status Turn off Turn on Turn on Turn on Description RA(6) = 0 RA(7) = 0 + "SLEP" instruction RA(6) = 0 RA(7) = 1 +"SLEP" instruction. RA(6) = 0 RA(6) = 1 * Main clock can be programmed from 447.829k to 17.91MH by internal PLL * 8 main clocks: 447.829K, 895.658K, 1.791M , 3.582M , 7.165M , 10.747M , 14.331M and 17.91MHz 12 interrupt source, 5 external (IR , INT1~INT4 ), 8 internal ( ADC, TCC, COUNTER1~5) 2.2 GPIO GPIO 9 Port(8 bit): general purpose input/output; LED output ; interrupt function GPIO B Port(7 bit): general purpose input/output for power down/MPEG power/Reset control GPIO C Port(4 bit): general purpose input/output for switch and key scanning (6x4 matrix) 2.3 ADC This specification is subject to change without further notice. 11.28.2004 (V1.23) 1 of 50 ePVP6810 VFD Controller 6 channel 10-bit successive approximation A/D converter Internal (VDD) or external voltage reference 2.4 VFD Multiple display modes (6-segment & 12-digit to 9-segment & 9-digit) External resistor not necessary for driver outputs.(P-ch open-drain + pull-down resistor output) 2.5 POR 2.0V voltage detector for Power-on reset 2.6 PACKAGE 44-pin LQFP 3 Application VFD controller 2 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 4 Pin Configuration GPIOC0 GPIO97 GPIO96 GPIOC3 GPIOC2 GPIOC1 GPIO95 GPIO94 GPIO93 33 GPIO92 32 GPIO91 31 GPIO90 30 /RESET 29 VEE P54 (SG1/KS1) 28 27 P55 (SG2/KS2) 26 P56 (SG3/KS3) 25 P57 (SG4/KS4) 24 P64 (SG5/KS5) 23 P65 (SG6/KS6) 12 13 14 15 16 17 18 19 20 21 22 P76 (GR6) P84 (GR2) P83 (GR3) P82 (GR4) P77 (GR5) P74 (GR8) P73 (GR9) P72 (GR10/SG9) P67 (GR11/SG8) P75 (GR7) P66 (GR12/SG7) OSCI OSCO 1 VSS PB0 PB1 PB2 PB3 PB4 PB5 PB6 2 3 4 5 6 7 8 9 PLLC 44 43 42 41 40 39 38 37 36 35 34 ePVP6810 LQFP 44 VDD 10 P85 (GR1) 11 Fig. 1 Pin Assignment This specification is subject to change without further notice. 11.28.2004 (V1.23) 3 of 50 ePVP6810 VFD Controller 5 Functional Block Diagram MCU 4 P85 (GR1) … P82 (GR4) P77 (GR5) … P72 (GR10/SG9) P67 (GR11/SG8) … P66 (GR12/SG7) P65 (SG6/KS6) … P64 (SG5/KS5) P57 (SG4/KS4) … P54 (SG1/KS1) OSCI OSCO OSC OTP ADC Segment Driver/ Grid Driver/ High Breakdown Driver 6 2 GPIO9[0:7] 8 Data RAM 2 GPIOB[0:6] 7 Timer GPIO 4 GPIOC[0:4] 4 PLL IR Real Time Clock CRYXRC /RESET PLLC VDDx3 VSS VEE AVDD AVSS Fig. 2a Block Diagram XIN XOUT PLLC WDT Timer Oscillator Timing Control R1(TCC) Interrupt Control Control Sleep And Wakeup On I/O port General RAM Instruction Decoder Instruction Register R3 R5 ACC ALU R2 ROM Prescaler STACK Data RAM R4 Data & Control Bus IOC5 R5 Port5 (HV) IOC6 R6 Port6 (HV) IOC7 R7 Port7 (HV) IOC8 R8 Port8 (HV) IOC9 R9 Port9 IOCB RB PortB IOCC RC PortC Fig. 2b Block Diagram 4 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 5.1 Ports Mapping for HV and GPIO 5.1.1 HV Port Mapping Port P54 P55 P56 P57 HV Port P60 P61 P62 P63 P64 P65 P66 P67 HV Port P70 P71 P72 P73 P74 P75 P76 P77 HV Port P80 P81 P82 P83 P84 P85 P86 P87 GR4 GR3 GR2 GR1 HV – – – – SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 – – – – SEG5/KS5 SEG6/KS6 GR12/SEG7 GR11/SEG8 – – GR10/SEG9 GR9 GR8 GR7 GR6 GR5 – – – – 5.1.2 GPIO Port Mapping Port P90 P91 P92 P93 P94 P95 P96 P97 GPIO GPIO90/LED0/IR Port PB0 GPIO GPIOB0/VREF GPIOB1/AD1 GPIOB2/AD2 GPIOB3/AD3 GPIOB4/AD4 GPIOB5/AD5 GPIOB6/AD6 – Port PC0 PC1 PC2 PC3 GPIO GPIOC0/Key1 GPIOC1/Key2 GPIOC2/Key3 GPIOC3/Key4 GPIO91/LED1/INT1 PB1 GPIO92/LED2/INT2 PB2 GPIO93/LED3/INT3 PB3 GPIO94/LED4/INT4 PB4 GPIO95/LED5 GPIO96/LED6 GPIO97/LED7 PB5 PB6 - 5.2 Relevant Pins for programming mode OTP PIN NAME VDD VPP DINCK ACLK PGMB OEB DATA GND MASK ROM PIN NAME AVDD /RESTER PC3 PC2 P92 P91 P90 GND This specification is subject to change without further notice. 11.28.2004 (V1.23) 5 of 50 ePVP6810 VFD Controller 6 10 Pin Descriptions Pin Name VDD I/O # 1 Logic power supply General Purpose I/O pins: 1. Key data input to these pins is latched at the end of display cycle. 2. These pins constitute 4-bit general-purpose input/output port. 3. Programmable Internal Pull-High 4. Wake-up Function Schmitt Pull-up Description Note Pin No. 40 – 42 GPIOC0 – GPIOC3 I/O 4 11-14 (B Cell) 15-19 (B Cell) 20-22 (B Cell) 23-24 A Cell 25 ~28 C Cell GR1 – GR4 GR5 – GR9 GR10/SG19 – GR12/SG7 SG6/KS6 O O O 4 5 3 1. High voltage grid output 1. High voltage grid output 2. High voltage segment output 1. High voltage grid output 2. High voltage segment output 1. High voltage grid output 2. High voltage segment output 3. Matrix key scan output 1. High voltage segment output – SG5/KS5 SG4/KS4 – SG1/KS1 O 2 I/O 4 2. Matrix key scan output 3. General Purpose Input pins: p54~p57 1. General Purpose I/O pins 2. LED output pin (20mA) ∼ 31 38 GPIO90/LED0 – GPIO97/LED7 I/O 8 3. IR Detector 4. Interrupt Function 5. Programmable Internal Pull-High Phase Lock Loop Capacitor (connect a Capacitor 0.01 to 0.047u to the Ground). Crystal Oscillator input pin (32, 768Hz) Crystal Oscillator output pin (32, 768Hz) Connect this pin to GND of the system Low active RESET signal input Pull-down level (VDD-(-40V)max) Schmitt Pull-up 43 44 1 2 30 29 PLLC OSCI OSCO VSS /RESET VEE I I O I - 1 1 1 1 1 1 Schmitt 6 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7 Function Descriptions 7.1 Operation Registers Configuration Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F R PAGE Registers R PAGE0 Indirect addressing TCC PC Page, Status RAM bank, RSR Port5 Output data Port6 Output data Port7 Output data Port8 Output data Port9 I/O data PLL, Main clock,WDTE PortB I/O data PortC I/O data Interrupt flag Interrupt flag, Wake-up control Interrupt flag 16 bytes Common registers Bank0 ~ Bank3 Common registers (32x8 for each bank) IOC PAGE Registers IOC PAGE0 IOC PAGE1 R PAGE1 R PAGE2 Program ROM page ADC control Data RAM address Data RAM data buffer ADC output data buffer Port9 pull high PortC pull high Counter1 data Counter2 LB data Counter2 HB data Counter3 data Counter4 data Counter5 data Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Port5 switch Port9 I/O control PortB I/O control PortC I/O control Interrupt mask Interrupt mask Interrupt mask Clock source (CN2,CN1) Prescaler (CN2,CN1) Clock source (CN4,CN3) Prescaler (CN4,CN3) Clock source (CN5) Prescaler (CN5) PortB switch This specification is subject to change without further notice. 11.28.2004 (V1.23) 7 of 50 ePVP6810 VFD Controller 7.2 Operation Registers Description 7.2.1 R0 (Indirect Address Register) R0 is not a physically implemented register. It is used as indirect address pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 Mov 0x04, A Mov A, @0xAA Mov 0x00, A ;store an address at R4 for indirect address ;write data 0xAA to R20 at Bank0 through R0 7.2.2 R1 (TCC) TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register. 7.2.3 R2 (Program Counter) The structure is depicted in Fig.3 below. Generates 4k × 13 external ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k," "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2, A" allows a relative address to be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. R5(PAGE) CALL and INTERRUPT A9 A8 0000 0001 0010 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 STACK10 STACK11 STACK12 STACK13 STACK14 STACK15 STACK16 INTERRUPT ACC,R3,R5(PAGE) PC A13 A12 A11 A10 PAGE0 0000~03FF PAGE1 0400~07FF PAGE2 0800~0BFF restore store 3 bytes register 0011 PAGE13 0C00~1FFF Fig. 3 Program Counter Organization 8 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller "TBL" allows a relative address to be added to the current PC, and the contents of the ninth and tenth bits do not change. The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5 PAGE 1) upon execution of a "JMP,” "CALL,” "ADD R2, A.” or "MOV R2, A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at Page0. The CPU will automatically store ACC, R3 status, and R5 PAGE 1, and they will be restored after execution of instruction RETI. 7.2.4 R3 (Status, Page Selection) (Status Flag, Page Selection Bits) Bit 7 RPAGE1 R/W-0 Bit 6 Bit 5 Bit 4 T R Bit 3 P R Bit 2 Z R/W Bit 1 DC R/W Bit 0 C R/W RPAGE0 IOCPAGE R/W-0 R/W-0 Bit 0 (C) : Carry flag The carry flag is affected by following operation : a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in another word, if the operation has no carry-out, CF will be "0". b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow-in, the CF will be "0", in another word, if no borrow-in, CF will be "1". c. Comparision : CF is as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0". Bit 3 (P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. Event WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care Remarks Bit 4 (T) : This specification is subject to change without further notice. 11.28.2004 (V1.23) 9 of 50 ePVP6810 VFD Controller Bit 5 (IOCPAGE) : Change IOC5 ~ IOCE to another page 0/1 IOC page0 / IOC page1 Bit 6 (RPAGE0 ~ RPAGE1) : Change R5 ~ RC to another page (see Section 7.1 Operation Registers Configuration for details.) (RPAGE1, RPAGE0) (0,0) (0,1) (1,x) R page # selected R page 0 R page 1 R page 2 10 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7.2.5 R4 (RAM Selection For Common Registers R20 ~ R3F)) (RAM Selection Register) Bit 7 RB1 R/W-0 Bit 6 RB0 R/W-0 Bit 5 RSR5 R/W Bit 4 RSR4 R/W Bit 3 RSR3 R/W Bit 2 RSR2 R/W Bit 1 RSR1 R/W Bit 0 RSR0 R/W Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect address for common Registers R20 ~ R3F. RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect address mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common Registers R20 ~ R3F. These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F). Refer to Section 7.1 Operation Registers Configuration for details. 7.2.6 R5 (PORT5 Output Data, Program Page Selection) a) PAGE 0 (PORT5 Output Data Register for HV, General Purpose Input pins: p54~p57) Bit 7 P57 W-0 Bit 6 P56 W-0 Bit 5 P55 W-0 Bit 4 P54 W-0 Bit 3 Bit 2 Bit 1 Bit 0 - b) PAGE 1 (Program ROM Page Register) Bit 7 AD9 R Bit 6 AD8 R Bit 5 R/W-0 Bit 4 R/W-0 Bit 3 R/W-0 Bit 2 R/W-0 Bit 1 PS1 R/W-0 Bit 0 PS0 R/W-0 Bit 0 ~ Bit 3 (PS0 ~ PS3) : Program page selection bits PS1 PS0 0 0 1 1 0 1 0 1 Program Memory Page (Address) Page 0 Page 1 Page 2 Page 3 PAGE instruction is used to select the program page to be accessed. The selected program page is maintained by Elan compiler. PAGE instruction will change your program by inserting the instruction within program. This specification is subject to change without further notice. 11.28.2004 (V1.23) 11 of 50 ePVP6810 VFD Controller 7.2.7 R6 (PORT6 Output Data) a) PAGE 0 (PORT6 Output Data Register for HV) Bit 7 P67 W-0 Bit 6 P66 W-0 Bit 5 P65 W-0 Bit 4 P64 W-0 Bit 3 W-0 Bit 2 W-0 Bit 1 W-0 Bit 0 W-0 7.2.8 R7 (PORT7 Output Data, ADC , Counter1 Data a) PAGE 0 (PORT7 Output Data Register for HV) Bit 7 P77 W-0 Bit 6 P76 W-0 Bit 5 P75 W-0 Bit 4 P74 W-0 Bit 3 P73 W-0 Bit 2 P72 W-0 Bit 1 W-0 Bit 0 W-0 b) PAGE 1 (ADC Control Bit) Bit 7 IN2 R/W-0 Bit 6 IN1 R/W-0 Bit 5 IN0 R/W-0 Bit 4 ADCLK1 R/W-0 Bit 3 ADCLK0 R/W-0 Bit 2 ADPWR R/W-0 Bit 1 ADRES R/W-0 Bit 0 ADST R/W-0 Bit 0(ADST) : AD converter start to sample By setting to “1,” the AD will start to sample the data. This bit is automatically cleared by hardware after a sampling. Bit 1(ADRES) : Resolution selection for ADC 0 ADC is an 8-bit resolution When 8-bit resolution is selected, the most significant (MSB) 8-bit data output of the internal 10-bit ADC will be mapped to RA PAGE1. Therefore, R5 PAGE1 Bit 6 ~ 7 will be of no use. 1 ADC is 10-bit resolution When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapped to RA PAGE1 and R5 PAGE1 Bit 6 ~7. Bit 2(ADPWR) : AD converter power control, 1/0 enable/disable Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit ‘s sampling clock source. For PLL Clock = 895.658kHz ~ 17.9MHz (CLK2~CLK0 = 001 ~ 110) ADCLK1 0 0 1 1 12 of 50 11.28.2004 (V123) ADCLK0 0 1 0 1 Sampling Rate 74.6K 37.4K 18.7K 9.3K Operation Voltage >=3.5V >=3.0V >=2.5V >=2.5V This specification is subject to change without further notice. ePVP6810 VFD Controller For PLL Clock = 447.829kHz (CLK2~CLK0 = 000) ADCLK1 0 0 1 1 ADCLK0 0 1 0 1 Sampling rate 37.4K 18.7K 9.3K 4.7K Operation voltage >=3.0V >=3.0V >=2.5V >=2.5V This is a CMOS multi-channel 10-bit successive approximation A/D converter. Features: 74.6kHz maximum conversion speed at 5V Adjusted full scale input External reference voltage input or internal (VDD) reference voltage 6 analog inputs multiplexed into one A/D converter Power down mode for power saving A/D conversion complete interrupt Interrupt register, A/D control and status register, and A/D data register PLL fpll Programmable divider 1/Mx fs Divider Nx fad c 10-bit ADC ADC output ADCLK1~ADCLK0 ENPLL CLK2 ~ CLK0 Fig. 4 ADC Voltage Control Logic fpll Mx fs Nx = 1 fadcon = fadc / 12 Nx = 2 Nx = 4 Nx = 8 14.331MHz 10.747MHz 7.165MHz 3.582MHz 1.791MHz 895.658kHz 447.829kHz 16 12 8 4 2 1 1 895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 447.829kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 18.659khz 18.659khz 18.659khz 18.659khz 18.659khz 18.659khz 18.659khz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 4.665kHz Bit 5 ~ Bit 7 (IN0 ~ IN2) : Input channel selection of AD converter This specification is subject to change without further notice. 11.28.2004 (V1.23) 13 of 50 ePVP6810 VFD Controller These two bits can choose one of the three AD inputs. IN2 0 0 0 0 1 1 IN1 0 0 1 1 0 0 IN0 0 1 0 1 0 1 Input AD1 AD2 AD3 AD4 AD5 AD6 c) PAGE 2 (Counter 1 Data Register) Bit 7 CN17 R/W-0 Bit 6 CN16 R/W-0 Bit 5 CN15 R/W-0 Bit 4 CN14 R/W-0 Bit 3 CN13 R/W-0 Bit 2 CN12 R/W-0 Bit 1 CN11 R/W-0 Bit 0 CN10 R/W-0 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1 buffer that you can read and write. Counter1 is an 8-bit up-counter with 8-bit prescaler that allows you to use R7 PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value. 7.2.9 R8 (PORT8 Output data, Data RAM address) , Counter2_LB data a) PAGE 0 (PORT8 Output Data Register for HV) Bit 7 W-0 Bit 6 W-0 Bit 5 P85 W-0 Bit 4 P84 W-0 Bit 3 P83 W-0 Bit 2 P82 W-0 Bit 1 W-0 Bit 0 W-0 b) PAGE 1 (Data RAM Address Register) Bit 7 RAM_A7 R/W-0 Bit 6 RAM_A6 R/W-0 Bit 5 RAM_A5 R/W-0 Bit 4 RAM_A4 R/W-0 Bit 3 RAM_A3 R/W-0 Bit 2 RAM_A2 R/W-0 Bit 1 RAM_A1 R/W-0 Bit 0 RAM_A0 R/W-0 Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address c) PAGE 2 (Counter2 Low Byte Data Register) Bit 7 CN27 R/W Bit 6 CN26 R/W Bit 5 CN25 R/W Bit 4 CN24 R/W Bit 3 CN23 R/W Bit 2 CN22 R/W Bit 1 CN21 R/W Bit 0 CN20 R/W Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2_LB's buffer that you can read and write. Counter2 is a 16-bit up-counter with 8-bit prescaler that allows you to use R8 PAGE2 to preset and read the counter.(write preset). After an interruption, it will reload the preset value. 14 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7.2.10 R9 (PORT9 I/O Data, Data RAM Data Buffer) ,Counter2_HB Data a) PAGE 0 (PORT9 I/O Data Register) Bit 7 P97 R/W Bit 6 P96 R/W Bit 5 P95 R/W Bit 4 P94 R/W Bit 3 P93 R/W Bit 2 P92 R/W Bit 1 P91 R/W Bit 0 P90 R/W Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register You can use IOC register to define input or output each bit, and to define the pull high condition. Bit 0: 1. P90 2. LED0 3. IR Input : can be defined as Input/Output : can be defined as Output : can be defined as Input and IR is enabled (when IOCF Bit7 is set to 1) Bit 1 ~ Bit4: 1. P91~P94 3. INT1~INT4 Bit 5 ~ Bit7: 1. P95~P97 : can be defined as Input/Output 2. LED5~LED7 : can be defined as Output : can be defined as Input/Output : can be defined as Input 2. LED1~LED4 : can be defined as Output b) PAGE 1 (Data RAM Data Register) Bit 7 RAM_D7 R/W Bit 6 RAM_D6 R/W Bit 5 RAM_D5 R/W Bit 4 RAM_D4 R/W Bit 3 RAM_D3 R/W Bit 2 RAM_D2 R/W Bit 1 RAM_D1 R/W Bit 0 RAM_D0 R/W Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data c) PAGE 2 (Counter2 High Byte Data Register) Bit 7 CN215 R/W Bit 6 CN214 R/W Bit 5 CN213 R/W Bit 4 CN212 R/W Bit 3 CN211 R/W Bit 2 CN210 R/W Bit 1 CN29 R/W Bit 0 CN28 R/W Bit 0 ~ Bit 7 (CN28 ~ CN215) : Counter2_HB's buffer that you can read and write. Counter2 is a 16-bit up-counter with 8-bit prescaler that allows you to use R9 PAGE2 to preset and read the counter (write value. preset). After an interruption, it will reload the preset This specification is subject to change without further notice. 11.28.2004 (V1.23) 15 of 50 ePVP6810 VFD Controller 7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer), ADC Output Data Buffer , Counter3 Data a) PAGE 0 (PLL Enable Bit, Main Clock Selection Bits, Watchdog Timer Enable Bit) Bit 7 IDLE R/W-0 Bit 6 PLLEN R/W-0 Bit 5 CLK2 R/W-0 Bit 4 CLK1 R/W-1 Bit 3 CLK0 R/W-1 Bit 2 Bit 1 Bit 0 WDTEN R/W-0 Bit 0 (WDTEN) : W atch dog control bit You can use WDTC instruction to clear watch dog counter. The counter clock source is 32768/2 Hz. If the prescaler is assigned to TCC, Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler is assigned to WDT, the time out interval will be longer depending on the prescaler. Ratio. 0/1 Bit 1~Bit 2 : Unused Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits You can select different frequencies for the main clock with CLK1 and CLK2. All the available clock selections are listed below. PLLEN 1 1 1 1 1 1 1 1 0 CLK2 0 0 0 0 1 1 1 1 CLK1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1 Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock 447.829kHz 895.658kHz 1.791MHz 3.582MHz 7.165MHz 10.747MHz 14.331MHz 17.91MHz Don’t care CPU clock 447.829kHz (Normal mode) 895.658kHz (Normal mode) 1.791MHz (Normal mode) 3.582MHz (Normal mode) 7.165MHz (Normal mode) 10.747MHz (Normal mode) 14.331MHz (Normal mode) 17.91MHz (Normal mode) 32.768kHz (Green mode) disable/enable Don’t care Don’t care Don’t care Bit 6 (PLLEN) : PLL's power control bit which is CPU mode control register 0/1 disable PLL/enable PLL If PLL is enabled, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low frequency, 32768 Hz). 447.8293kHz ~17.9132M Hz CLK2 ~ CLK0 PLL circuit ENPLL 1 switch 0 System clock S ub-clock 32.768kHz Fig. 5 The Relation Between 32.768kHz and PLL 16 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller Bit 7 (IDLE) : SLEEP or IDLE mode control as set by SLEP instruction. 0/1 SLEEP mode/IDLE mode. This bit allows SLEP instruction to decide which power saving mode to execute. The status after wake-up and the wake-up source list is as the shown below. Wakeup Signal SLEEP Mode RA(7,6)=(0,0) + SLEP TCC time out IOCF Bit0=1 COUNTER1 time out IOCF Bit1=1 COUNTER2 time out IOCF Bit2=1 COUNTER3 time out IOCD Bit0=1 COUNTER4 time out IOCD Bit1=1 COUNTER5 time out IOCD Bit2=1 PORT90(IR function) IOCF Bit3=1 WDT time out No function No function No function No function No function No function RA(7,6)=(1,0) + SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP IDLE Mode Reset and jump 1) Wake-up to Address 0 2) Jump to next instruction after SLEP Reset and jump 1) Wake-up to Address 0 2) Next instruction PORTC(0~3)(Key1~Key4) Reset and Jump 1) Wake-up 2) Jump to next instruction after SLEP RE PAGE0 Bit3 or Bit4 or Bit5 or Bit6 = 1 to Address 0 PORT9(1~4) IOCF Bit4 or Bit5 or Bit6 =1 or Bit7=1 Reset and Jump 1) Wake-up to Address 0 2) Jump to next instruction after SLEP NOTES: 1 PORT90 wakeup function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit7). 2. PORT91 wakeup function is controlled by IOCF Bit 4. It is a falling edge trigger. 3. PORT92 ~ PORT94 wakeup functions are controlled by IOCF. They are falling edge triggers. 4. PORTC0 ~ PORTC3 wakeup functions are controlled by RE PAGE0 Bit 0 ~ Bit 3. They are falling edge triggers. b) PAGE 1 (ADC Output Data Register) Bit 7 AD7 R Bit 6 AD6 R Bit 5 AD5 R Bit 4 AD4 R Bit 3 AD3 R Bit 2 AD2 R Bit 1 AD1 R Bit 0 AD0 R Bit 0 ~ Bit 7 (AD01~ AD7) : These 8 bits are full ADC data buffer This specification is subject to change without further notice. 11.28.2004 (V1.23) 17 of 50 ePVP6810 VFD Controller c) PAGE 2 (Counter3 Data Register) Bit 7 CN37 R/W-0 Bit 6 CN36 R/W-0 Bit 5 CN35 R/W-0 Bit 4 CN34 R/W-0 Bit 3 CN33 R/W-0 Bit 2 CN32 R/W-0 Bit 1 CN31 R/W-0 Bit 0 CN30 R/W-0 Bit 0 ~ Bit 7 (CN30 ~ CN37) : Counter3's buffer that you can read and write. Counter3 is an 8-bit up-counter with 8-bit prescaler that allows you to use RA PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value. 7.2.12 RB (PORTB I/O Data Buffer, PORT9 Switches) a) PAGE 0 (PORTB I/O Data Register) Bit 7 R-0 Bit 6 PB6 R/W Bit 5 PB5 R/W Bit 4 PB4 R/W Bit 3 PB3 R/W Bit 2 PB2 R/W Bit 1 PB1 R/W Bit 0 PB0 R/W Bit 0 ~ Bit 6 (PB0 ~ PB6) : 7-bit PORTB (0~6) I/O data register You can use IOC register to define each bit as input or output. When the PORTB is switched to ADC– Bit 0: is defined as VREF Bit 1 ~ Bit 6: is defined as AD1~AD6 b) PAGE 1 (PORT9, Pull High) Bit 7 PH97 R/W-0 Bit 6 PH96 R/W-0 Bit 5 PH95 R/W-0 Bit 4 PH94 R/W-0 Bit 3 PH93 R/W-0 Bit 2 PH92 R/W-0 Bit 1 PH91 R/W-0 Bit 0 PH90 R/W-0 Bit 0 ~ Bit 7 (PH90 ~ PH97) : PORT9 Bit0 ~ Bit7 pull high control register 0 1 disable pull high function. enable pull high function c) PAGE 2 (Counter4 Data Register) Bit 7 CN47 R/W-0 Bit 6 CN46 R/W-0 Bit 5 CN45 R/W-0 Bit 4 CN44 R/W-0 Bit 3 CN43 R/W-0 Bit 2 CN42 R/W-0 Bit 1 CN41 R/W-0 Bit 0 CN40 R/W-0 Bit 0 ~ Bit 7 (CN40 ~ CN47) : Counter4 buffer that you can read and write. Counter 4 is an 8-bit up-counter with 8-bit prescaler that allows you to use RB PAGE2 to preset and read the counter.(write preset). After an interruption, it will reload the preset value. 18 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7.2.13 RC (PORTC I/O Data , Counter5 Data) a) PAGE 0 I/O Data Buffer/Serial Signal Bit 7 PC7 Bit 6 PC6 Bit 5 PC5 Bit 4 PC4 Bit 3 PC3 R/W Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 PC0 R/W Bit 0 ~ Bit 3 :1. PC0 ~ PC3 are defined as Input/Output 2. KEY1 ~ KEY4 are defined as Keyscan Input n b) PAGE 1 (PORTC, Pull High) Bit 7 R/W-0 Bit 6 R/W-0 Bit 5 R/W-0 Bit 4 R/W-0 Bit 3 PHC3 R/W-0 Bit 2 PHC2 R/W-0 Bit 1 PHC1 R/W-0 Bit 0 PHC0 R/W-0 Bit 0 ~ Bit 7 (PHC0 ~ PHC7) : PORTC Bit0 ~ Bit7 pull high control register 0 disable pull high function. 1 enable pull high function d) PAGE 2 (Counter5 Data Register) Bit 7 CN57 R/W-0 Bit 6 CN56 R/W-0 Bit 5 CN55 R/W-0 Bit 4 CN54 R/W-0 Bit 3 CN53 R/W-0 Bit 2 CN52 R/W-0 Bit 1 CN51 R/W-0 Bit 0 CN50 R/W-0 Bit 0 ~ Bit 7 (CN50 ~ CN57) : Counter5 buffer that you can read and write. Counter5 is an 8-bit up-counter with 8-bit prescaler that allows you to use RC PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value. 7.2.14 RD (Interrupt Flag,) a) PAGE 0 (Interrupt Flags Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CNT5 R/W-0 Bit 1 CNT4 R/W-0 Bit 0 CNT3 R/W-0 NOTE: "1" means interrupt request, "0" means non-interrupt Bit 0 (CNT3) : Counter3 timer overflow interrupt flag. Set when counter3 timer overflows. Bit 1 (CNT4) : Counter4 timer overflow interrupt flag. Set when counter4 timer overflows. Bit 2 (CNT5) : Counter5 timer overflow interrupt flag. Set when counter5 timer overflows. This specification is subject to change without further notice. 11.28.2004 (V1.23) 19 of 50 ePVP6810 VFD Controller 7.2.15 RE (Interrupt Flags, Wake-up) a) PAGE 0 (Interrupt Flags, Wake-up Control Bits) Bit 7 R/W-0 Bit 6 R/W-0 Bit 5 ADI R/W-0 Bit 4 R/W-0 Bit 3 /WUPC3 R/W-0 Bit 2 /WUPC2 R/W-0 Bit 1 /WUPC1 R/W-0 Bit 0 /WUPC0 R/W-0 Bit 0 (/WUPC0) : PORTC0 wake-up control, 0/1 disable/enable PC0 pin wake-up function Bit 1 (/WUPC1) : PORTC1 wake-up control, 0/1 disable/enable PC1 pin wake-up function Bit 2 (/WUPC2) : PORTC2 wake-up control, 0/1 disable/enable PC2 pin wake-up function Bit 3 (/WUPC3) : PORTC3 wake-up control, 0/1 disable/enable PC3 pin wake-up function Bit 4(-) : Not used Bit 5 (ADI) Bit 6 (-) Bit 7(-) : ADC interrupt flag after sampling : Not used : Not used 7.2.16 RF (Interrupt Flags) a) PAGE 0 (Interrupt Status Register) Bit 7 INT4 R/W-0 Bit 6 INT3 R/W-0 Bit 5 INT2 R/W-0 Bit 4 INT1 R/W-0 Bit 3 IR R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0 NOTE: "1" means interrupt request, "0" means non-interrupt Bit 0 (TCIF) Bit 1 (CNT1) Bit 2 (CNT2) Bit 3 (IR) Bit 4 (INT1) Bit 5(INT2) Bit 6 : (INT3) Bit 7(INT4) : TCC timer overflow interrupt flag, Set when TCC timer overflows. : Counter1 timer overflow interrupt flag. Set when Counter1 timer overflows. : Counter2 timer overflow interrupt flag. Set when Counter2 timer overflows. : External INT pin interrupt flag. If PORT90 contains a falling /rising edge (controlled by CONT register) trigger signal, CPU will set this bit. : External INT1 pin interrupt flag, If PORT91 contains a falling edge trigger signal, CPU will set this bit. : External INT2 pin interrupt flag. If PORT92 has a falling edge trigger signal, CPU will set this bit. : External INT3 pin interrupt flag. If PORT93 has a falling edge trigger signal, CPU will set this bit. : External IR interrupt flag. If PORT94 has a falling edge trigger signal, CPU will set this bit. 20 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller Trigger edge is as shown below: Signal TCC COUNTER1 COUNTER2 COUNTER3 COUNTER4 COUNTER5 IR INT1 INT2 INT3 INT4 Trigger Time out Time out Time out Time out Time out Time out Falling Rising edge Falling edge Falling edge Falling edge Falling edge 7.2.17 R10~R3F (General Purpose Registers) R10 ~ R1F, R20 ~ R3F (Banks 0 ~ 3) : all are general purpose registers. 7.3 Special Purpose Registers 7.3.1 A (Accumulator) Internal data transfer, or instruction operand holding. It is not an addressable register. 7.3.2 CONT (Control Register) CONT register is readable (CONTR) and writable (CONTW). Bit 7 P90EG Bit 6 INT Bit 5 TS Bit 4 RETBK Bit 3 PAB Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 This specification is subject to change without further notice. 11.28.2004 (V1.23) 21 of 50 ePVP6810 VFD Controller Bit 3 (PAB) : Prescaler assignment bit 0/1 TCC/WDT When in WDT mode (Bit 3 = 1), the prescaler is cleared by the WDTC and SLEP instructions. Likewise, when in TCC mode (Bit 3 = 0), the prescaler will can NOT be cleared by SLEP instructions. An 8-bit counter is provided as prescaler for the TCC or WDT. The prescaler is available for the TCC only or for the WDT only at a given time. An 8 bit counter is made available for TCC or WDT as determined by the status of Bit 3 (PAB) of the CONT register. Both TCC and prescaler are cleared each time a write to TCC instruction is executed. (See the table above for the prescaler ratio under CONT register and Fig.6 below for the TCC/WDT block diagram.) Bit 4 (RETBK) : Return value backup control for interrupt routine 0/1 disable/enable When this bit is set to 1, the CPU will store ACC, R3 status, and R5 PAGE 1 automatically after an interrupt is triggered. It will be restored after instruction RETI. When this bit is set to 0, you need to store ACC, R3, and R5 PAGE 1 in you program. Bit 5 (TS) : TCC signal source 0 internal instruction cycle clock timing = ( 2 / system clock) * prescaler* (256 – count vaule) 1 16.384kHz timing = ( 1 /16.384k) * prescaler * (256 – count vaule) Bit 6 (INT) : INT enable flag 0 1 interrupt masked by DISI or hardware interrupt interrupt enabled by ENI/RETI instructions Bit 7 (P90EG) : Interrupt edge type of P90 0 1 P90 interruption source is a rising edge signal. P90 interruption source is a falling edge signal. 16.38KHz Fig. 6 TCC & WDT Block Diagram 22 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7.3.3 IOC 5 (PORT5 Switches) a) Page 1 Bit 7 P57S R/W-0 Bit 6 P56S R/W-0 Bit 5 P55S R/W-0 Bit 4 P54S R/W-0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 4 ~ Bit 7 (P54S~P57S) : Port5 I/O direction control register 0 set the relative I/O pin as output HV 1 set the relative I/O pin into high impedance 7.3.4 IOC 8 a) PAGE 1 (Clock Source and Prescaler for COUNTER1 and COUNTER2) Bit 7 CNT2S R/W-0 Bit 6 Bit 5 Bit 4 Bit 3 CNT1S R/W-0 Bit 2 Bit 1 Bit 0 C2_PSC2 C2_PSC1 C2_PSC0 R/W-0 R/W-0 R/W-0 C1_PSC2 C1_PSC1 C1_PSC0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio C1_PSC2 C1_PSC1 C1_PSC0 COUNTER1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 3 (CNT1S) : COUNTER1 clock source 0 16.384kHz timing = ( 1 /16.384k) * prescaler * (256 – count vaule) 1 system clock timing = ( 2 / system clock) * prescaler* (256 – count vaule) Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio C2_PSC2 C2_PSC1 C2_PSC0 COUNTER2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 11.28.2004 (V1.23) 23 of 50 This specification is subject to change without further notice. ePVP6810 VFD Controller Bit 7 (CNT2S) : COUNTER2 clock source 0 16.384kHz timing = ( 1 /16.384k) * prescaler * (256 – count vaule) 1 system clock timing = ( 2 / system clock) * prescaler* (256 – count vaule) 7.3.5 Bit 7 IOC97 R/W-1 IOC9 (PORT9 I/O Control) Bit 6 IOC96 R/W-1 Bit 5 IOC95 R/W-1 Bit 4 IOC94 R/W-1 Bit 3 IOC93 R/W-1 Bit 2 IOC92 R/W-1 Bit 1 IOC91 R/W-1 Bit 0 IOC90 R/W-1 a) PAGE 0 (PORT9 I/O Control Register) Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9 (0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance b) PAGE 1 ( Clock Source and Prescaler for COUNTER3 and COUNTER4) Bit 7 CNT4S R/W-0 Bit 6 Bit 5 Bit 4 Bit 3 CNT3S R/W-0 Bit 2 Bit 1 Bit 0 C4_PSC2 C4_PSC1 C4_PSC0 R/W-0 R/W-0 R/W-0 C3_PSC2 C3_PSC1 C3_PSC0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C3_PSC0 ~ C3_PSC2) : COUNTER3 prescaler ratio C3_PSC2 C3_PSC1 C3_PSC0 COUNTER3 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 3 (CNT3S) : COUNTER3 clock source 0 16.384kHz timing = ( 1 /16.384k) * prescaler * (256 – count vaule) 1 system clock timing = ( 2 / system clock) * prescaler* (256 – count vaule) Bit 4 ~ Bit 6 (C4_PSC0 ~ C4_PSC2) : COUNTER4 prescaler ratio C4_PSC2 C4_PSC1 C4_PSC0 COUNTER4 1:2 1:4 1:8 1:16 1:32 This specification is subject to change without further notice. 0 0 0 0 1 24 of 50 11.28.2004 (V123) 0 0 1 1 0 0 1 0 1 0 ePVP6810 VFD Controller 1 1 1 0 1 1 1 0 1 1:64 1:128 1:256 Bit 7 (CNT4S) : COUNTER4 clock source 0 16.384kHz timing = ( 1 /16.384k) * prescaler * (256 – count vaule) 1 system clock timing = ( 2 / system clock) * prescaler* (256 – count vaule) 7.3.6 IOCA a) PAGE 1 (Clock Source and Prescaler for COUNTER5 ) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CNT5S R/W-0 Bit 2 Bit 1 Bit 0 C5_PSC2 C5_PSC1 C5_PSC0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C5_PSC0 ~ C5_PSC2) : COUNTER5 prescaler ratio C5_PSC2 C5_PSC1 C5_PSC0 COUNTER4 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 3 (CNT5S) : COUNTER5 clock source 0/1 16.384kHz/system clock 7.3.7 IOCB (PORTB I/O Control, PORTB Switch) a) PAGE 0 (PORTB I/O Control Register) Bit 7 R-1 Bit 6 IOCB6 R/W-1 Bit 5 IOCB5 R/W-1 Bit 4 IOCB4 R/W-1 Bit 3 IOCB3 R/W-1 Bit 2 IOCB2 R/W-1 Bit 1 IOCB1 R/W-1 Bit 0 IOCB0 R/W-1 Bit 0 ~ Bit 6 (IOCB0 ~ IOCB 6) : PORTB (0~6) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance b) PAGE 1 (PORTB Switches) Bit 7 Bit 6 PB6S R/W-0 Bit 5 PB5S R/W-0 Bit 4 PB4S R/W-0 Bit 3 PB3S R/W-0 Bit 2 PB2S R/W-0 Bit 1 PB1S R/W-0 Bit 0 PB0S R/W-0 This specification is subject to change without further notice. 11.28.2004 (V1.23) 25 of 50 ePVP6810 VFD Controller Bit 0 (PB0S) : Select between AD Voltage Reference pin or I/O PORTB0 pin 0 1 PB0 (I/O PORTB0) pin is selected and ADC reference voltage sourced from internal VDD VREF (ADC external reference voltage input) pin is selected Bit 1 (PB1S) : Select between normal I/O PORTB1 pin or ADC Channel 1 input AD1 pin 0 1 PB1 (I/O PORTB1) pin is selected AD1 (ADC Channel 1 input) pin is selected Bit 2 (PB2S) : Select between normal I/O PORTB2 pin or ADC Channel 2 input AD2 pin 0 PB2 (I/O PORTB2) pin is selected 1 AD2 (ADC Channel 2 input) pin is selected Bit 3 (PB3S) : Select between normal I/O PORTB3 pin or ADC Channel 3 input AD3 pin 0 PB3 (I/O PORTB3) pin is selected 1 AD3 (ADC Channel 3 input) pin is selected Bit 4 (PB4S) : Select between normal I/O PORTB4 pin or ADC Channel 4 input AD4 pin 0 PB4 (I/O PORTB4) pin is selected 1 AD4 (ADC Channel 4 input) pin is selected Bit 5 (PB5S) Select between normal I/O PORTB5 pin or ADC Channel 5 input AD5 pin 0 PB5 (I/O PORTB5) pin is selected 1 AD5 (ADC Channel 5 input) pin is selected Bit 6 (PB6S) : Select between normal I/O PORTB5 pin or ADC Channel 6 input AD6 pin 0 PB6 (I/O PORTB6) pin is selected 1 AD6 (ADC Channel 6 input) pin is selected 7.3.8 IOCC (PORTC I/O Control) a) PAGE 0 (PORTC I/O Control Register) Bit 7 R/W-1 Bit 6 R/W-1 Bit 5 R/W-1 Bit 4 R/W-1 Bit 3 IOCC3 R/W-1 Bit 2 IOCC2 R/W-1 Bit 1 IOCC1 R/W-1 Bit 0 IOCC0 R/W-1 Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance b) PAGE 1 (PORTC Switches) Bit 7 PC7S R/W-1 Bit 6 PC6S R/W-1 Bit 5 PC5S R/W-1 Bit 4 PC4S R/W-1 Bit 3 Bit 2 Bit 1 Bit 0 - 7.3.9 IOCD (Interrupt Mask, Prescaler of CN3 ~ CN5) a) PAGE 0 (Interrupt Mask) 26 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 CNT5 R/W-0 Bit 1 CNT4 R/W-0 Bit 0 CNT3 R/W-0 Bit 0 ~ 3 : Interrupt enable bit 0 disable interrupt 1 enable interrupt 7.3.10 IOCE (Interrupt Mask) a) PAGE 0 (Interrupt Mask) Bit 7 Bit 6 Bit 5 ADI R/W-0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Bit 4 (STB) : Not used Bit 5 (ADI) : ADC interrupt flag after a sampling 0/1 disable/enable interrupt Bit 6 (RBF) : Not used 7.3.11 IOCF (Interrupt Mask ) a) PAGE 0 (Interrupt Mask Register) Bit 7 INT4 R/W-0 Bit 6 INT3 R/W-0 Bit 5 INT2 R/W-0 Bit 4 INT1 R/W-0 Bit 3 IR R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0 Bit 0 ~ 7: Interrupt enable bit 0 disable interrupt 1 enable interrupt The status after interrupt and the interrupt source lists are as shown in the table below. Interrupt Signal IDLE Mode RA(7,6)=(1,0) + SLEP TCC time out IOCF bit0=1 And "ENI" 1) Wake-up 2) Interrupt (jump to Address 8 on Page0) 3) After RETI instruction, jump to SLEP Next instruction GREEN Mode RA(7,6)=(x,0) no SLEP Interrupt (jump to Address 8 on Page0) NORMAL Mode RA(7,6)=(x,1) no SLEP Interrupt (jump to Address 8 on Page0) 1) Wake-up COUNTER1 time out 2) Interrupt (jump to Address 8 on Page0) IOCF bit1=1 3) After RETI instruction, jump to And "ENI" SLEP Next instruction 1) Wake-up COUNTER2 time out 2) Interrupt (jump to Address 8 on IOCF bit2=2 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) This specification is subject to change without further notice. 11.28.2004 (V1.23) 27 of 50 ePVP6810 VFD Controller 1) Wake-up COUNTER3 time out 2) Interrupt (jump to Address 8 on IOCD bit0=1 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) 1) Wake-up COUNTER4 time out 2) Interrupt (jump to Address 8 on IOCD bit1=1 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) 1) Wake-up COUNTER5 time out 2) Interrupt (jump to Address 8 on IOCD bit2=1 Page0) And "ENI" INT1~4 3) After RETI instruction, jump to SLEP Next instruction 1) Wake-up Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) IOCF bit4=1 or IOCF 2)Interrupt (jump to Address 8 on bit5=1 IOCF bit6 = 1 Page0) or IOCF bit7= 1 3) after RETI instruction, jump to And “ENI SLEP Next instruction 1) Wake-up IR IOCF bit3= 1 And “ENI ADI IOCE bit5 = 1 And “ENI No function 2) Interrupt (jump to Address 8 on Page0) 3) After RETI instruction, jump to SLEP Next instruction Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) NOTES: 1. PORT90 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit7). 2. PORT9 (1~4) interrupt functions are controlled by IOCF Bits 4, 5, 6, & 7). They are falling edge triggers. 7.4 Application notes 1、Call-table instruction:： Because the call-table instruction can only change the Program Counter's bit7 ~ bit0 at each time, only 256 addresses can be searched once. But each program page contains 1024 addresses, if call each 256 addresses as a zone, Then each page constitutes by four zones. When a table overlaps two zones, a bug would occur during address searching. So the member of program must examine the .LST file at any time, the .LST file will jot down the information that Assembler generated, for example source code, the coding of instruction , instruction address, error message etc. 2、Operation requirement for the CPU： The system frequency must adds a latency time ( 14.33 MHz about 250 ms ；17.91 MHz about 450 ms.). After RA register was setting, it will offer the stable system frequency for the operation. 28 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 3、The register initial sets to suggest The IOC page 0 & page 1 0X0C register initial sets suggestion as follows 0x0C register value = 0B0000xxxx The R page 0 0X0C register initial sets suggestion as follows 0x0C register value =0B0000xxxx 7.5 I/O Port The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.7. PCRD Q P R C L D CLK PCWR Q PORT Q P R C L D CLK PDWR IOD Q PDRD 0 1 M U X Fig. 7 The Circuit of I/O Port and I/O Control Register 7.6 RESET A RESET can be caused by any of the following: 1. Power on reset 2. WDT timeout (if enabled and in GREEN or NORMAL mode) 3. /RESET pin pull low Once a RESET occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". W hen power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler counter are cleared. The Watchdog timer is disabled. The CONT register is set to all "1" This specification is subject to change without further notice. 11.28.2004 (V1.23) 29 of 50 ePVP6810 VFD Controller The other registers’ (Bit 7 ~ Bit 0) default values are as follows. Address 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF R Register PAGE 0 00xxxxxx 0000xxxx 00000000 00000000 00000000 00000000 00011xx0 00000000 1011xxxx xxxxx000 X0000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx 00000000 00000000 xxxx0000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx x1111111 1111xxxx xxxxx000 x000xxxx 00000000 11111111 00000000 00000000 00000000 x0000000 1111xxxx R Register PAGE 1 R Register PAGE 2 R Register IOC Register IOC Register PAGE 3 PAGE 0 PAGE 1 7.7 Wake Up The controller features two types of sleep mode for power saving: 7.7.1 SLEEP Mode, RA(6 ;7) = 0 + "SLEP" Instruction Under this mode, the controller turns off all the CPU and crystal. However, other circuits with power control like key tone control or PLL control (with register enabled), has to be turned off through software. 7.7.2 IDLE mode, RA(6 ;7) = 1 + "SLEP" Instruction. W ith this mode, the controller only turns the CPU off. The crystal remains running. 7.7.3 Wake-up from SLEEP Mode 1. WDT time out 2. External interrupt 3. /RESET pull low Any of these cases will reset the controller and run the program from address zero. The status is just like the power-on-reset condition. Be sure to enable circuit after cases 1 or 2 occurs. 30 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 7.7.4 Wake-up from IDLE Mode 1. WDT time out 2. External interrupt 3. Internal interrupt like counters All these cases requires you to enable the circuit before entering IDLE mode. All the registers values are preserved when "SLEP" instruction is executed and restored after wake-up. During execution of case 2 or 3, controller will wake up and jump to address 0x08 for interruption sub-routine. After performing the sub-routine ("RETI" instruction), the program will jump to the next instruction following the "SLEP" instruction. 7.8 Interrupts RD, RE, and RF are the interrupt status registers which record the interrupt request in flag bit. IOCD, IOCE, & IOCF are their interrupt mask registers respectively. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in their respective (RD, RE, and RF) registers. The interrupt flag bit must be cleared in the software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. 7.9 Instruction Set The Instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O register can be treated as a general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit located in the Register "R,” and affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. Instruction Binary 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr HEX 0000 0001 0002 0003 0004 000r Mnemonic NOP DAA CONTW SLEP WDTC IOW R Operation No Operation Decimal Adjust A A → CONT 0 → W DT, Stop oscillator 0 → W DT A → IOCR Status Affected None C None T,P T,P None Instruction Cycle 1 1 1 1 1 1 This specification is subject to change without further notice. 11.28.2004 (V1.23) 31 of 50 ePVP6810 VFD Controller 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R Enable Interrupt Disable Interrupt [Top of Stack] → PC [Top of Stack] → PC Enable Interrupt CONT → A IOCR → A A→R 0→A 0→R R-A → A R-A → R R-1 → A R-1 → R A∨R→A A∨R→R A&R→A A&R→R A⊕R→A A⊕R→R A+R→A A+R→R R→A R→R /R → A /R → R R+1 → A R+1 → R R-1 → A, skip if zero R-1 → R, skip if zero R(n) → A(n-1) R(0) → C, C → A(7) R(n) → R(n-1) R(0) → C, C → R(7) R(n) → A(n+1) R(7) → C, C → A(0) R(n) → R(n+1) R(7) → C, C → R(0) R(0-3) → A(4-7) R(4-7) → A(0-3) None None None None None None 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip 1 1 1 1 1 R2+A → R2 bits 9,10 do not clear Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None 32 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1110 100k kkkk 1 1111 kkkk kkkk 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k R(0-3) ↔ R(4-7) R+1 → A, skip if zero R+1 → R, skip if zero 0 → R(b) 1 → R(b) if R(b)=0, skip if R(b)=1, skip PC+1 → [SP] (Page, k) → PC (Page, k) → PC k→A A∨k→A A&k→A A⊕k→A k → A, [Top of Stack] → PC k-A → A PC+1 → [SP] 001H → PC K->R5(4:0) k+A → A None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1 This specification is subject to change without further notice. 11.28.2004 (V1.23) 33 of 50 ePVP6810 VFD Controller 8 Segment Data Buffers The ePVP6810 chip provides a total of 128 bytes data RAM. On the other hand, display Segment Data Buffers can be stored either in the data RAM of 128 bytes sizes (00h~40h) or in the common registers of Bank 2 and Bank 3 (20h~3Fh). These buffers store display RAM. The display RAM stores the data transmitted from an external device to the ePVP6810 through the serial interface and is assigned addresses as follows, in units of 8 bits: b0 b3 b4 b7 X X HL Lower 4 bits X X HU Higher 4 bits c) Display Memory Addresses: Seg1 Seg4 Seg8 Seg9 00 HU 02HU 04 HU 06 HU 08 HU 0A HU 0C HU 15 HU 0E HU 10 HU 12HU 14 HU 01 HL 03 HL 05 HL 07 HL 09 HL 0BHL 0D HL 16 HL 0F HL 11 HL 13 HL 15 HL 01 HU 03 HU 05 HU 07 HU 09 HU 0BHU 0D HU 16 HU 0F HU 11 HU 13 HU 15 HU DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 DIG10 DIG11 DIG12 00 HL 02 HL 04 HL 06 HL 08 HL 0A HL 0C HL 15 HL 0E HL 10 HL 12 HL 14 HL 34 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller b) Key Scanning Data Buffers: Fig. 8 6 x 4 Configuration Key Matrix The key matrix is of 6 x 4 configuration is as shown in the above figure. The data of each key is stored as illustrated below, and is read by a read command, starting from the least significant bit. KEY1….KEY4 SEG1/KS1 SEG3/KS3 SEG5/KS5 b0 -- -- b3 KEY1….KEY4 SEG2/KS2 SEG4/KS4 SEG6/KS6 b4 -- -- b7 W hen the most significant bit of data (SEG6, b7) has been read, the least significant bit of the next data (SEG1, b0) is read. Fig. 9 Display Mode Setting Command Selection This specification is subject to change without further notice. 11.28.2004 (V1.23) 35 of 50 ePVP6810 VFD Controller 9 Crystal OSC 9.1 General Description This oscillator is designed for the ePVP6810 chip as clock source. 9.2 Features RC oscillator: 32.768K Hz Operating voltage: 2.2~5.5V. Operating temperature: -20 C ~ 70 C o o 9.3 Block Diagram OSCI 27pf 27pf OSCO VSS Fig. 13 Crystal OSC Block Diagram 9.4 Pin Description Name XIN XOUT VDD VSS I/O Type I O Description Crystal oscillator connection pin Crystal oscillator output pin Power supply (+) pin Power supply (–) pin Remarks 9.5 Electrical (Condition : VDD = 4.5 to 5.5V, Ta = -20°C to 70°C ) Parameters Starting oscillation voltage Stable time Current consumption Duty cycle Frequency/Voltage deviation Frequency/Temperature deviation Frequency vs. Process deviation 36 of 50 11.28.2004 (V123) Sym. Vs Ts Idd ∂f/∂V ∆f Min. 45 - Typ. 2.0 5 2 50 1 1 ±6 Max. 3.2 10 3 55 1.5 2 ±10 Unit V clk mA % % % % Conditions Vdd = 5.0V Vdd = 5.0V This specification is subject to change without further notice. ePVP6810 VFD Controller 10 Absolute Operation Maximum Ratings Absolute maximum ratings (Ta = 25°C, Vss = 0 V) Parameter Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage LED driver output current VFD driver output current Operating ambient temperature Storage temperature Symbol VDD VEE VI VO IO1 IO2 Topt Tstg -0.5 to + 6 VDD +0.5 to VDD - 45 -0.5 to VDD +0.5 VEE -0.5 to VDD +0.5 +25 -40 (Grid) -15 (Segment) -40 to +85 -65 to +150 °C °C Ratings Unit V V V V mA mA 11 DC Electrical Characteristic (Ta = -20 to +70°C, VDD = 4.5 to 5.5V, Vss = 0V, VEE = VDD - 45V) Parameter Digital Input Voltage High Digital Input Voltage Low Schmitt Trigger Negative Going Threshold Voltage Schmitt Trigger Positive Going Threshold Voltage Input Leakage Current Pull Up Resister Digital Output Voltage High Digital Output Voltage Low Digital Output High Current Digital Output Low Current Digital Output High Current Digital Output Low Current HV Output Current Symbol VIH IOL VTVT+ IIN RPU VOH VOL IOH1 IOL1 IOH2 IOL2 IOH1 Min. 0.8VDD VSS 1.5 2.9 50 0.8VDD VSS -2 2 -15 15 -6 Typ. 1.8 3.2 75 -4 4 -18 18 -4 Max. VDD 0.2VDD 2.1 GPIOC, GPO9, /RESET,GPIOB 3.5 ±1 100 VDD 0.2VDD -5 5 -25 25 -3 V uA KΩ V V mA mA mA mA mA VOH=2.4V, GPIOB, GPIOC VOL=0.4V, GPIOB, GPIOC VOH=2.4V / GPIO9 VOL=0.4V / GPIO9 Vo = VDD –2V,(VDD=5V) SEG1/KS1 to SEG6/KS6 Vo = VDD –2V,(VDD=5V) GR1 to GR9, GR10/SG9, GR12/SG7 Vo = VDD –45V, driver off Driver output (VEE= -25V) 11.28.2004 (V1.23) 37 of 50 Unit V V GPIOB Test conditions GPIOB, VIN = VDD or VSS GPIOC, GPO9 and /RESET @ VDD=5V GPIOB, GPIOC HV Output Current HV leakage current HV Output pull-down resistor IOH2 IHVLEAK RL -15 5 40 -13 8 80 -11 10 120 mA uA KΩ This specification is subject to change without further notice. ePVP6810 VFD Controller Power down current (SLEEP mode) Low clock current (GREEN mode) Crystal oscillation operating mode ISB1 - 1.5 µA All input and I/O pin at VDD, output pin floating, WDT disabled VDD =3V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =5V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =3V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =5V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating /RESET=High, CLK=3.582MHz, all analog circuits disabled, output pin floating 30 ISB2 65 60 µA 90 µA Low clock current (IDLE mode) Crystal oscillation operating mode 30 ISB3 45 45 µA 60 µA Operating supply current (Normal mode) Crystal oscillation operating mode ICC 1.3 2 mA 12 AC Electrical Characteristic 11.1 CPU Instruction Timing (Ta = -20°C ~ 70°C, VDD=5V, VSS=0V) Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period Symbol Dclk Tins Tdrh Ttcc Twdt Note 1 Ta = 25°C (Tins+20)/N 16 32.768kHz 3.582MHz Condition Min 45 Typ 50 60 550 16 Max 55 Unit % us ns ms ns ms NOTE: N= selected prescaler ratio 38 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 12.2 AC Timing Characteristic (VDD=5V, Ta=+25°C) Description Oscillator timing characteristic OSC start up 32.768kHz 3.579MHz PLL Tosc 400 5 1500 10 ms us Symbol Min Typ Max Unit 12.3 ePVP6810 Operating Voltage VS main clock (X Axis Min VDD ; Y Axis Main CLK) MHz 17.91 14.33 10.74 7.16 3.58 1.79 2.2 3.0 3.3 4.0 5 5.5 V Fig. 14 Operation Voltage XY Axis This specification is subject to change without further notice. 11.28.2004 (V1.23) 39 of 50 ePVP6810 VFD Controller 12.4 AC Timing Diagrams Fig. 15a A/C Test Input/Output Waveform Fig. 15b RESET Timing Diagram ins Fig. 15c TCC Input Timing Diagram 40 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 13 Key & Switch Scanning and Display Timing The key & switch scanning and display timing diagram is given below. One cycle of key & switch scanning consists of 2 frames. The data of the 4 x 4 matrix is stored in the RAM. 31.25 us 470 us 500 us GRID 1 output 1/16 4/16 6/16 8/16 10/16 12/16 14/16 16/16 GRID 2 output SEG 1 output SEG 2 output SEG 3 output DISP ≒ 500us Key & Switch scan data GRID 1 GRID 1 output GRID 2 output GRID 3 output GRID n output SEG1 output SEG2 output SEG3 output GRID 2 GRID 3 GRID n DIG1 1/16 4/16 10/16 2/16 14/16 2/16 Fig. 16 Key & Switch Scanning and Display Timing Diagram This specification is subject to change without further notice. 11.28.2004 (V1.23) 41 of 50 ePVP6810 VFD Controller 14 Switching Characteristic Waveform f OSC OSC 50 % Fig. 19a Switching Characteristic Waveform 14.1 Switching Characteristics (Ta = - 20 to + 70°C, VDD = 4.5 to 5.5V, VEE = VDD - 45V) Parameter Oscillation frequency Propagation delay time Symbol tOSC tPLZ tPZL tTZH1 Rise time tTZH2 Fall time tTHZ 100 110 0.5 120 µs µs Min. Typ. 32.768 Max. 300 100 2 Unit KHz ns ns us CL = 100pF VEE =-25V CLK→DOUT CL = 15pF, RL = 10KΩ Test Conditions - SEG1/KS1 to SEG4/KS4, GR1 to GR9 GR10/SG9 to GR12/SG7 CL = 100pF, VEE =-25V ,SEGn, GRIDn 42 of 50 11.28.2004 (V123) This specification is subject to change without further notice. ePVP6810 VFD Controller 15 .2、Application circuit OSCI OSCO CRYSTAL1 32.768KHz C6 27pf C5 27pf VSS 44 43 42 41 40 39 38 37 36 35 34 OSCI C4 0.01uf VSS VDD R1 /RESET 470k C3 0.1uf OSCO VSS VDD 0.1uf C1 1 2 3 4 5 6 7 8 9 10 11 VSS 12 13 14 15 16 17 18 19 20 21 22 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10/SG9 GR11/SG8 GR12/SG7 OSCO VSS GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 VDD GR1 OSCI PLLC GPIOC3 GPIOC2 GPIOC1 GPIOC0 GPIO97 GPIO96 GPIO95 GPIO94 GPIO93 VSS 33 32 31 30 29 28 27 26 25 24 23 ePV6810 LQFP44 GPIO92 GPIO91 GPIO90 /RESET VEE SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 /RESET VEE C2 0.1uf VSS This specification is subject to change without further notice. 11.28.2004 (V1.23) 43 of 50 ePVP6810 VFD Controller 15 .2、Package Information (1) Package Type: Plastic LQFP-44 M i n N o r m a l M a x c Symbal A A1 A2 b c E1 E L L1 e θ 0.050 1.350 0.300 0.090 1.400 0.370 1.600 0.150 1.450 0.450 0.200 12.00 BASIC 10.00 BASIC 0.450 0.600 0.750 1 . 0 ( B A S I C ) 0 0.8(BASIC) 3.5 7 44 of 50 11.28.2004 (V123) This specification is subject to change without further notice.