HM9270D

HM 9270C/D DTMF RECEIVER General Description The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface. Features • • • • • • • • Complete receiver in an 18-pin package. Excellent performance. CMOS, single 5 volt operation. Minimum board area. Central office quality. Low power consumption. Power-Down mode (HM9270D only). Inhibit-mode (HM9270D only). Pin Configurations HM9270C IN+ IN GS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE IN+ IN GS HM9270D 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE VREF IC* IC* OSC1 OSC2 VSS VREF INH PWDN OSC1 OSC2 VSS * Connect to VSS -1- HM 9270C/D DTMF RECEIVER Block Diagram (Figure 1) INH HIGH GROUP FILTER IN+ IN DIGITAL ZERO CROSSING DETECTORS DETECTION CODE CONVERTER AND Q1 Q2 Q3 Q4 + - DIAL TONE FILTER LOW GROUP FILTER ALGORITHM LATCH GS CHIP CHIP CHIP CHIP CLOCKS POWER BIAS REF OSC2 BIAS CIRCUIT + STEERING LOGIC OSC1 VDD V SS PWDN VREF St/ GT ESt StD TOE Pin Description Pin 1 2 3 Sym. IN+ INGS Function Non-Inverting input Connections to the front-end differential amplifier. Invering Input Gain select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Reference voltage output,nominally VDD/2. May be used to bias the inputs at midrail (see application diagram). Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor. (HM9270D only). Power down (input). Active high power down the device and inhibit the oscillator internal built-in pull down resistor. (HM9270D only). Clock Input Output Clock 3.579545 MHz crystal connected between these pins completes internal oscillator. 4 VREF INH 5 6 PWDN 7 8 9 10 OSC1 OSC2 VSS TOE Negative power supply, normally connected to 0V. 3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up. -2- HM 9270C/D DTMF RECEIVER Pin 11 12 13 14 15 Sym. Q1 Q2 Q3 Q4 StD Function 3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see code table). Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St causes the device to register the detected tone-pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St (see truth table). Positive power supply, +5Volts. 16 ESt 17 St/GT 18 VDD Absolute Maximum Ratings (Notes 1, 2 and 3) Parameters Min. Max. Units Power Supply Voltage, VDD - VSS 6 V Voltage on any pin VSS - 0.3 VDD+ 0.3 V Current at any pin 10 mA o Operating temperature -40 +85 C o Storage temperature -65 +150 C Package power dissipation 500 mW Note 1. Absolute maximum ratings are those values beyond which damage to the device may occur. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Power dissipation temperature derating: -12 mV/oC from 65oC to 85oC DC Electrical Characteristics Parameter Description SUPPLY: VDD Icc Po IS INPUTS: VIL VIH IIH/IIL Iso RIN VTSt Operating Supply Voltage Operating Supply Current Power Consumption Standby Current Test Conditions Min. Typ. Max. Units 4.75 5.25 7 35 100 V mA mW µA f=3.579MHz; VDD=5V PWDN pin = VDD - 3.0 15 - Low Level Input Voltage High Level Input Voltage Input Leakage Current Pull Up (Source) Current Input Signal Impedance Inputs 1,2 Steering Threshold Voltage 1.5 3.5 VIN=Vss or VDD TOE (Pin 10)=OV @ 1kHz 0.1 7.5 10 2.35 -315 V V uA uA MΩ V HM 9270C/D DTMF RECEIVER Parameter OUTPUTS: VOL VOH IOL IOH VREF ROR Description Test Conditions No Load No Load VOUT=0.4V VOUT=4.6V No Load Min. Typ. 0.03 4.97 2.5 0.8 Max. Units V V mA mA V KΩ Low Level Output Voltage High Level Output Voltage Output Low (Sink) Current Output High (Source) Current Output Voltage VREF Output Resistance 1.0 0.4 2.4 2.7 10 Operating Characteristics Gain Setting Amplifier Parameter IIN RIN VOS PSRR CMRR AVOL fC VO CL RL VCM Description Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection DC Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Tolerable capacitive load(GS) Tolerable resistive load(GS) Common Mode Range Test Conditions VSS < VIN < VDD Min. Typ. Max. ±100 10 ±25 60 60 65 1.5 4.5 100 50 3.0 Units nA MΩ mV dB dB dB MHz VPP pF KΩ VPP 1kHz -3.0V tGTA) FIGURE 8. GUARD TIME ADJUSTMENT -8- HM 9270C/D DTMF RECEIVER Input Configuration The input arrangement of the HM9270C/D provides a differential-input operational amplifier as well as a bias source (VREF ) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Fig. 2 with the op-amp connected for unity gain and VREF biasing the input at 1/2V DD. Fig. 9 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. C1 R1 + C2 R4 GS HM9270C/D R5 R3 R2 VREF FIGURE 9. DIFFERENTIAL INPUT CONFIGURATION Power - down and inhibit mode A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output code will remain the same as the previous detected code (see table 1). fLow 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Fhigh Key 1209 1 1336 2 1477 3 1209 4 1336 5 1477 6 1209 7 1336 8 1477 9 1336 0 1209 * 1477 # 1633 A 1633 B 1633 C 1633 D ANY TOE Q4 H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H H L L Z Q3 L L L H H H H L L L L H H H H L Z Q2 L H H L L H H L L H H L L H H L Z Q1 H L H L H L H L H L H L H L H L Z fLow 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Fhigh Key 1209 1 1336 2 1477 3 1209 4 1336 5 1477 6 1209 7 1336 8 1477 9 1336 0 1209 * 1477 # 1633 A 1633 B 1633 C 1633 D ANY TOE Q4 Q3 Q2 Q1 H L L L H H L L H L H L L H H H L H L L H L H L H H L H H L H L H H H H H L L L H H L L H H H L H L H H L H H H H H L L H H PREVIOUS DATA H H L Z Z Z Z Table 1: Truth table INH =VSS (Z: high impedance) INH=VDD -9- HM 9270C/D DTMF RECEIVER SPECIAL PACKAGE PIN CONFIGURATIONS HM9270DM IN+ INGS VREF INH PWDN OSC1 OSC2 VSS NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT EST StD Q4 Q3 Q2 Q1 TOE NC - 10 -