EM6161FS8AW-70LF

merging Memory & Logic Solutions Inc. Document Title 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM EM611FV16 Series Low Power, 64Kx16 SRAM Revision History Revision No. 0.0 0.1 History Initial Draft 2’nd Draft Add Pb-free part number Draft Date May 9 , 2003 February 13 , 2004 Remark Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 merging Memory & Logic Solutions Inc. FEATURES • • • • • • Process Technology : 0.18µ m Full CMOS Organization : 64K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 48-FPBGA 6.0x7.0 EM611FV16 Series Low Power, 64Kx16 SRAM GENERAL DESCRIPTION The EM611FV16 families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family EM611FV16 Operating Temperature Industrial (-40 ~ 85oC) Vcc Range Speed Standby (I SB1 , Typ.) 0.5 µA2) Operating (I CC1.Max.) 3 mA PKG Type 2.7V~3.6V 551) /70ns 48-FPBGA 1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25 oC and not 100% tested. PIN DESCRIPTION 1 A B C D E F G H 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit LB I/O 9 OE UB A0 A3 A5 DNU A1 A4 A6 A7 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11 DNU I/O1 I/O3 VCC V SS I/O7 I/O8 DNU A A11 10 A 12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Data Cont Data Cont VC C R ow S elec t VSS Memory Array 1024 x 1024 I/O10 I/O11 V SS VC C I/O12 I/O13 DNU DNU A14 A12 A9 A15 A13 A10 I/O1 ~ I/O8 I/O9 ~ I/O16 I/O Circuit Column Select I/O15 I/O14 I/O16 DNU DNU A8 48-FPBGA : Top view (ball down) W E O E UB Control Logic N ame CS OE WE A 0 ~A15 Function C hip select input O utput Enable input W rite Enable input A ddress Inputs Name Vcc Vss UB LB DNU Function Power Supply Ground U pper Byte (I/O 9~16) L ower Byte (I/O 1~8 ) Do Not Use LB CS I/O1 ~I/O16 D ata Inputs/outputs 2 merging Memory & Logic Solutions Inc. ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature EM611FV16 Series Low Power, 64Kx16 SRAM Symbol VIN , VOUT VCC PD TA Ratings -0.2 to Vcc+0.3(Max. 4.0V) -0.2 to 4.0V 1.0 -40 to 85 Unit V V W oC * Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS H X L L L L L L L L OE X X H H L L L X X X WE X X H H H H H L L L LB X H L X L H L L H L UB X H X L H L L H L L I/O 1-8 High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O9-16 High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Active Active Active Active Active Active Active Active Note: X means don’t care. (Must be low or high state) 3 merging Memory & Logic Solutions Inc. RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. EM611FV16 Series Low Power, 64Kx16 SRAM Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 3) Typ 3.3 0 - Max 3.6 0 VCC + 0 .22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol C IN CIO Test Condition VIN=0V VIO =0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol I LI ILO I CC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB VIN =VSS to VCC CS=VIH or OE=VIH or WE =VIL, LB=UB=VIH , VIO=VSS to VCC I IO=0mA, CS =VIL, VIN =VIH or V IL Cycle time=1µs, 100% duty, IIO =0mA, CS