EM621FS16GT-70LF

EM641FT8 Document Title 512K x8 bit Low Power Full CMOS Static RAM Low Power, 512Kx8 SRAM Revision History Revision No. 0.0 0.1 History Initial Draft 0.1 Revision IDR Current from 1.5uA to 7uA tOE from 25nsec to 30nsec with 55ns part Draft Date Nov. 20, 2007 Dec. 5, 2007 Remark Preliminary 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM641FT8 512K x8 Bit Low Power CMOS Static RAM FEATURES - Very high speed : 45ns - Process Technology : 0.15um Full CMOS - Organization : 512K x8 - Power Supply Voltage => EM641FT8V : 4.5V~5.5V - Low Data Retention Voltage :1.5V (MIN) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns - KGD based on SOP package structure Low Power, 512Kx8 SRAM GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms - Typical Pad Size : 76.0um x 80.0um - Wafer diameter : 8 inch FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VCC VSS Row Select Memory Array 512K x 8 I/O0 ~ I/O7 Data Cont I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 WE OE CS Control Logic Name CS OE WE A0~A18 I/O0~I/O7 Function Chip select input Output Enable input Write Enable input Address Inputs Data Inputs/Outputs Name VCC VSS Function Power Supply Ground 2 EM641FT8 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to VSS Voltage on Vcc supply relative to VSS Power Dissipation Operating Temperature Low Power, 512Kx8 SRAM Symbol VIN, VOUT VCC PD TA Minimum -0.5 to 6.0V -0.5 to 6.0V 1.0 -40 to 85 Unit V V W o C Note : Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS H L L L OE X L X H WE X H L H I/O0-7 High-Z Data Out Data In High-Z Mode Deselected/ Power down Read Write Selected, Output Disabled Power Stand by Active Active Active Note : X means don’t care. (Must be low or high state) 3 EM641FT8 RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage Symbol VCC 2) Low Power, 512Kx8 SRAM Min 4.5 0 2.2 -0.54) Typ 0 - Max 5.5 0 VCC + 0.53) 0.6 Unit V V V V VSS VIH VIL Notes : 1. TA= -40 to 85oC, otherwise specified 2. Overshoot: VCC +1.0 V in case of pulse width < 20ns 3. Undershoot: -1.0 V in case of pulse width < 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance Note : Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC ELECTRICAL CHARACTERISTICS (TA = -40oC to +85oC) Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VIO=VSS to VCC IIO=0mA, CS=VIL, VIN=VIH or VIL Cycle time=1µs, 100% duty, IIO=0mA, CSVCC-0.2V Other inputs = 0~VCC (Typ. condition : VCC=5V @ 25oC) (Max. condition : VCC=5.5V @ 85oC) 45ns 55ns 70ns Test Conditions Min -1 -1 2.4 - Typ - Max 1 1 5 7 65 55 45 0.4 1 Unit uA uA mA mA ICC2 VOL VOH ISB mA Output low voltage Output high voltage Standby Current (TTL) V V mA Standby Current (CMOS) ISB1 LF - 1.51) 20 uA NOTES : 1.Typical values are measured at Vcc=5V, TA=25oC and not 100% tested. 4 EM641FT8 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0V to VCC Input Rise and Fall Time : 1V/ns Input and Output reference Voltage : 0.5VCC Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) Notes : 1. Including scope and Jig capacitance 2. R1 = 1800 ohm, R2 = 990 ohm 3. VTM = VCC 4. CL = 5pF + 1 TTL (measurement with tLZ, tOLZ, tHZ, tOHZ, tWHZ) Low Power, 512Kx8 SRAM VTM3) R12) Output CL1) R22) READ CYCLE (Vcc = 4.5V to 5.5V, GND = 0V, TA = -40oC to +85oC) Parameter Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH 45ns Min 45 10 5 0 0 10 Max 45 45 25 20 15 Min 55 10 5 0 0 10 55ns Max 55 55 30 20 20 Min 70 10 5 0 0 10 70ns Max 70 70 35 25 25 - Unit ns ns ns ns ns ns ns ns ns WRITE CYCLE (Vcc = 4.5V to 5.5V, GND = 0V, TA = -40oC to +85oC) Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End of write to output low-Z Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 45ns Min 45 45 0 45 35 0 0 25 0 5 Max 15 Min 55 45 0 45 40 0 0 25 0 5 55ns Max 20 Min 70 60 0 60 50 0 0 30 0 5 70ns Max 20 Unit ns ns ns ns ns ns ns ns - ns ns 5 EM641FT8 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Transition Controlled) Low Power, 512Kx8 SRAM tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (OE Controlled) tRC Address tAA CS tOE OE tOLZ Data Out High-Z tLZ Data Valid tCO tOH tHZ tOHZ High-Z NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 EM641FT8 TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled, OE High During WRITE) tWC Address tCW2) CS tAW tWP1) WE tAS3) OE Data in High-Z tOHZ tDW Data Valid Low Power, 512Kx8 SRAM tWR4) tDH High-Z tOW Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS3) CS tAW tWP1) WE tDW Data in High-Z Data Valid tCW2) tWR4) tDH Data out High-Z 7 EM641FT8 TIMING WAVEFORM OF WRITE CYCLE(3) (WE Controlled, OE LOW) Low Power, 512Kx8 SRAM tWC Address tCW2) CS tAW tAS3) WE tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tWR4) tWP1) tDH High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 8 EM641FT8 DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time         Low Power, 512Kx8 SRAM Symbol VDR IDR tSDR tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min 1.5 0 tRC Typ2) 1 - Max 7 - Unit V µA ns NOTES 1. See the ISB1 measurement condition of data sheet page 4. 2. Typical value is measured at TA=25oC and not 100% tested. DATA RETENTION WAVE FORM tSDR Vcc 5V Data Retention Mode tRDR 2.2V ¡ VDR CS GND VDR 1.5V CS > Vcc-0.2V 9 EM641FT8 SRAM PART CODING SYSTEM Low Power, 512Kx8 SRAM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage 1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 11. Power 10. Speed 9. Package 8. Generation 7. Organization 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------F ----------------------G ---------------------1st generation 2nd generation 3rd generation 4th generation 5th generation 6th generation 7th generation 8th generation 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V --------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 10