EM621FV16AW55L

merging Memory & Logic Solutions Inc. Document Title 128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM EM610FV8 Series Low Power, 128Kx8 SRAM Revision History Revision No. 0.0 0.1 History Initial Draft 2’nd Draft Add Pb-free part number Draft Date December 2 , 2003 February 13 , 2004 Remark Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 merging Memory & Logic Solutions Inc. FEATURES • • • • • • Process Technology : 0.18µ m Full CMOS Organization :128K x 8 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min) Three state output and TTL Compatible Package Type : 36-FPBGA 6.0x7.0 EM610FV8 Series Low Power, 128Kx8 SRAM GENERAL DESCRIPTION The EM610FV8 families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family EM610FV8 Operating Temperature Industrial (-40 ~ 85o C) Vcc Range Speed Standby (ISB1 , Typ) 0.5 µA2) Operating (I CC1.Max) 3 mA PKG Type 36FPBGA 2.7V~3.6V 551) / 70ns 1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25 oC and not 100% tested. PIN DESCRIPTION 1 A B C D E F G H 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A0 I/O 5 I/O 6 V SS VC C I/O 7 I/O 8 A9 A1 A2 CS2 WE DNU A3 A4 A5 A6 A7 A8 I/O1 I/O2 VCC V SS R ow S elec t A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Data Cont VC C VSS Memory Array 1024 x 1024 I/O1 ~ I/O8 I/O Circuit Column Select DNU DNU OE A10 CS1 A11 A16 A12 A15 A13 I/O3 I/O4 A14 A A A12 A1 A A A 10 11 3 14 15 16 36-FPBGA : Top view (ball down) W E O E CS 1 Control Logic N ame CS 1 ,CS 2 OE A 0 ~A16 I/O1 ~I/O 8 Function Chip select inputs O utput Enable input A ddress Inputs D ata Inputs/outputs Name WE Vcc Vss DNU Function Write Enable input Power Supply Ground Do Not Use CS 2 2 merging Memory & Logic Solutions Inc. ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature EM610FV8 Series Low Power, 128Kx8 SRAM Symbol VIN , VOUT VCC PD TA Ratings -0.2 to Vcc+0.3 (Max. 4.0V) -0.2 to 4.0V 1.0 -40 to 85 Unit V V W oC * Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS 1 H X L L L CS 2 X L H H H OE X X H L X WE X X H H L I/O High-Z High-Z High-Z Data Out Data In Mode Deselected Deselected Output Disabled Read Write Power Stand by Stand by Active Active Active Note: X means don’t care. (Must be low or high state) 3 merging Memory & Logic Solutions Inc. RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. EM610FV8 Series Low Power, 128Kx8 SRAM Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 3) Typ 3.3 0 - Max 3.6 0 VCC + 0.22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN C IO Test Condition VIN =0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC I CC1 Average operating current I CC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB V IN=V SS t o V CC C S 1 = VIH , CS2 =VIL o r OE=V IH o r WE =VIL , VIO= VSS t o V CC I IO=0mA, CS 1=V IL, CS 2=WE = VIH , VI N=VI H or VIL C ycle time=1 µs, 100% duty, I IO=0mA, CS 1< 0.2V, CS2 >V CC -0.2V, V IN< 0.2V or VIN >V CC-0.2V C ycle time = Min, I IO =0mA, 100% duty, CS 1=V IL, CS2 =V IH, V IN=V IL or VI H I OL = 2 .1mA I O H = - 1.0mA C S 1 = VIH , CS2 =VIL , Other inputs=V IH or V IL C S 1 >V CC-0.2V, CS 2>V C C-0.2V (CS 1 c ontrolled) or 0V