EM621FV8CW-12L

merging Memory & Logic Solutions Inc. Document Title 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM EM611FV16U Series Low Power, 64Kx16 SRAM Revision History Revision No. 0.0 0.1 History Initial Draft 2’nd Draft Add Pb-free part number Draft Date May 9 , 2003 February 13 , 2004 Remark Emerging Memory & Logic Solutions Inc. IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 merging Memory & Logic Solutions Inc. FEATURES • • • • • • Process Technology : 0.18µ m Full CMOS Organization : 64K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 44-TSOP2 EM611FV16U Series Low Power, 64Kx16 SRAM GENERAL DESCRIPTION The EM611FV16U families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family EM611FV16U Operating Temperature Industrial (-40 ~ 85oC) Vcc Range Speed Standby (I SB1 , Typ.) 0.5 µA2 ) Operating (I CC1.Max.) 3 mA PKG Type 2.7V~3.6V 551) /70ns 44 TSOP2 1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25 oC and not 100% tested. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Data Cont Data Cont Pre-charge Circuit VC C R ow S elec t VSS Memory Array 1024 x 1024 44 - TSOP2 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O1 ~ I/O8 I/O9 ~ I/O16 I/O Circuit Column Select A A11 10 A 12 A13 A14 A15 W E O E UB Control Logic Name CS OE WE A 0 ~A15 Function C hip select input O utput Enable input W rite Enable input A ddress Inputs Name Vcc Vss UB LB NC Function Power Supply Ground U pper Byte (I/O 9~16) L ower Byte (I/O 1~8 ) No Connection LB CS I/O1 ~I/O16 D ata Inputs/outputs 2 merging Memory & Logic Solutions Inc. ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature EM611FV16U Series Low Power, 64Kx16 SRAM Symbol VIN , VOUT VCC PD TA Ratings -0.2 to Vcc+0.3(Max. 4.0V) -0.2 to 4.0V 1.0 -40 to 85 Unit V V W oC * Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS H L L L L L L L L OE X H X L L L X X X WE X H X H H H L L L LB X X H L H L L H L UB X X H H L L H L L I/O 1-8 High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O9-16 High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Active Active Active Active Active Active Active Active Note: X means don’t care. (Must be low or high state) 3 merging Memory & Logic Solutions Inc. RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. EM611FV16U Series Low Power, 64Kx16 SRAM Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 3) Typ 3.3 0 - Max 3.6 0 VCC + 0 .22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol C IN CIO Test Condition VIN=0V VIO =0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI I LO ICC I CC1 Average operating current I CC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH I SB VIN =VS S to VCC CS=VIH or OE =VIH or WE=VIL, VIO=VSS to V CC IIO=0mA, CS=VIL, VIN =VIH or VIL Cycle time=1µs, 100% duty, I IO=0mA, CSVCC -0.2V Other inputs=0~VCC Standby Current (CMOS) ISB1 (Typ. condition : VCC =3.3V @ 25o C) (Max. condition : VCC =3.6V @ 85 C) NOTES o Test Conditions Min -1 -1 55ns 70ns 2.4 LL LF Typ - Max 1 1 3 3 26 20 0.4 0.3 Unit µA µA mA mA mA V V mA - 0.51 ) 5 µA 1. Typical values are measured at Vcc=3.3V, T A= 25o C and not 100% tested. 4 merging Memory & Logic Solutions Inc. AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R1 =3070Ω, R 2 =3150Ω 3. VTM=2.8V EM611FV16U Series Low Power, 64Kx16 SRAM VTM 3) R12) CL1) R22) READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40oC to +85oC) Parameter Read cycle time Address access time Chip select to output Output enable to valid output UB, LB acess time Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tco tO E tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH 55ns Min 55 Max 55 55 25 30 10 5 5 0 0 0 10 20 20 20 10 5 5 0 0 0 10 Min 70 - 70ns Max 70 70 35 35 25 25 25 - Unit ns ns ns ns ns ns ns ns ns ns ns ns WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tWC tCW tAs tAW tBW tWP tWR tWHZ tDW tDH tOW 55ns Min 55 45 0 45 45 40 0 0 25 0 5 Max 25 Min 70 60 0 60 60 50 0 0 30 0 5 70ns Max 30 Unit ns ns ns ns ns ns ns ns ns ns ns 5 merging Memory & Logic Solutions Inc. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). EM611FV16U Series Low Power, 64Kx16 SRAM (Address Controlled, CS=OE=V IL, WE=V IH, U B o r/and LB= VIL) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) ( WE = VIH) tRC Address tAA CS tCO tB A UB ,LB tO E OE tOLZ Data Out High-Z Data Valid tOH tHZ tBHZ tOHZ tBLZ tLZ NOTES (READ CYCLE) 1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device interconnection. 6 merging Memory & Logic Solutions Inc. TIMING WAVEFORM OF WRITE CYCLE(1) (WE C ONTROLLED) tWC Address tCW (2) CS tAW tBW UB ,LB tWP (1) WE tAS(3) Data in High-Z tDW EM611FV16U Series Low Power, 64Kx16 SRAM tWR (4) tDH High-Z tOW Data Valid tWHZ Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS C ONTROLLED) tWC Address tAS(3) CS tAW tBW UB ,LB tWP (1) WE tDW Data in Data Valid tCW (2) tWR (4) tDH Data out High-Z High-Z 7 merging Memory & Logic Solutions Inc. EM611FV16U Series Low Power, 64Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB C ONTROLLED) tWC Address tCW(2) CS tA W tB W UB ,LB tA S(3) WE tDW Data in Data out High-Z Data Valid tW R(4) tW P(1) tDH High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP ) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS going low to end of write. 3. t A S is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. 8 merging Memory & Logic Solutions Inc. DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES EM611FV16U Series Low Power, 64Kx16 SRAM Symbol VDR I DR tSDR tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) Min 1.5 0 Typ2) 0.25 - Max 3.6 - Unit V µA VCC =1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form ns t RC - 1. See the IS B 1 measurement condition of datasheet page 4. 2.Typical values are measured at TA= 25o C and not 100% tested. DATA RETENTION WAVE FORM tSDR Vcc 2.7V Data Retention Mode tRDR 2.2V VDR CS > V cc-0.2V CS GND 9 merging Memory & Logic Solutions Inc. EM611FV16U Series Low Power, 64Kx16 SRAM Unit: millimeters PACKAGE DIMENSION 10 merging Memory & Logic Solutions Inc. MEMORY FUNCTION GUIDE EM611FV16U Series Low Power, 64Kx16 SRAM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage 1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Option 0 ----------------------- Dual CS 1 ----------------------- Single CS 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------ 5.0V V ------------------------- 2.7V~3.6V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 11 11. Power 10. Speed 9. Packages 8. Version 7. Orgainzation 8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision E ----------------------- Fifth revision F ----------------------- Sixth revision 9. Package Blank ---------------------- FPBGA S ---------------------------- 32 sTSOP1 T ---------------------------- 32 TSOP1 U ---------------------------- 44 TSOP2 W ---------------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free) L ---------------------- Low Power S ---------------------- Standard Power