RMP116MFAW-70E

Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM Document Title 1M x 16 bit Pseudo SRAM ( EMP116MFAW Series ) Specification Revision History Revision No. 0.0 History Initial Draft Draft Date Oct. 24 , 2005 Remark Preliminary 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-717 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.      Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM 1Mb x16 Pseudo Static RAM Specification GENERAL DESCRIPTION The EMP116MFAW series is 16,777,216 bits of Pseudo SRAM which uses DRAM type memory cells, but this device has refresh-free operation and extreme low power consumption technology. Furthermore the interface is compatible to a low power Asynchronous type SRAM. The EMP116MFAW is organized as 1,048,576 Words x 16 bit. FEATURES - Organization :1M x16 - Power Supply Voltage : 2.7 ~ 3.3V - Separated I/O power(VccQ) & Core power(Vcc) - Three state outputs - Byte read/write control by UB# /LB# - Support Direct Deep Power Down control by ZZ# and Auto-TCSR for power saving PRODUCT FAMILY Part Number Operating Temp. Power Supply Speed (tRC) Power Dissipation (ISB1, Max.) Standby (ICC2, Max.) Operating RMP116MFAW-70E -25oC to 85oC 2.7V to 3.3V 70ns 100uA 25mA FUNCTION BLOCK DIAGRAM ZZ# CS# UB# LB# WE# OE# Self-Refresh CONTROL CONTROL LOGIC COLUMN SELECT ROW SELECT A0~A19 ADDRESS DECODER Memory Array 1M X 16 DQ0~ DQ15 Din/Dout BUFFER I/O CIRCUIT ¡¡¡¡ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM 1Mb x16 Pseudo Static RAM GENERAL WAFER SPECIFICATIONS - Process Technology : 0.125um CMOS Deep trench process - 3 Metal layers including local inter-connection - Wafer thickness : 725 +/- 25um - Wafer Diameter : 8-inch PAD DESCRIPTION Name CS# OE# WE# ZZ# Function Chip select inputs Output enable input Write enable input Low Power Control Name LB# UB# VCC VCCQ Function Lower byte (DQ0~7) Upper byte (DQ8~15) Power supply I/O Power supply DQ0-15 Data In-out A0-19 Address inputs VSS(Q) Ground NC No connection ¢¢¢¢ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM ABSOLUTE MAXIMUM RATINGS 1) Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC, VCCQ PD TSTG TA Ratings -0.2 to VCCQ+0.3V -0.22) to 3.6V 1.0 -65 to 150 -25 to 85 Unit V V W o o C C 1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION CS# H X X L L L L L L L L ZZ# H L H H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L DQ0~7 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Deep Power Down Stand by Active Active Active Active Active Active Active Active Note: X means don’t care. (Must be low or high state) ££££ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VCCQ VSS, VSSQ VIH VIL Min 2.7 2.7 0 0.8 * VCCQ -0.23) Typ 3.0 3.0 0 - Max 3.3 3.3 0 VCCQ + 0.22) 0.2 * VCCQ Unit V V V V V TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH Test Conditions VIN=VSS to VCCQ , VCC=VCCmax CS#=VIH , ZZ#=VIH , OE#=VIH or WE#=VIL , VIO=VSS to VCCQ , VCC=VCCmax Cycle time=1µs, 100% duty, IIO=0mA, CS#VCCQ-0.2V, Other inputs = 0 ~ VCCQ Min -1 -1 0.8*VCCQ Typ - Max 1 1 3 25 0.2*VCCQ Unit uA uA mA mA V V 150 120 100 Standard Reduced Low Power Standby Current (CMOS) ISB (Typ. condition : VCC=3.0V @ 25oC) (Max. condition : VCC=3.3V @ 85oC) uA 1. Maximum Icc specifications are tested with VCC = VCCmax. ¤¤¤¤ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance 1) Dout CL1) AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC) Parameter List Read Cycle Time Address access time Chip enable to data output Output enable to valid output UB#, LB# enable to data output Read Chip enable to low-Z output UB#, LB# enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB#, LB# disable to high-Z output Output disable to high-Z output Output hold from Address change Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write UB#, LB# valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Speed Min 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 Max 1k 70 70 25 70 15 15 15 1k 15 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ¥¥¥¥ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM TIMING DIAGRAMS READ CYCLE (1) (Address controlled, CS#=OE#=VIL, ZZ#=WE#=VIH, UB# or/and LB#=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid READ CYCLE (2) (ZZ#=WE#=VIH) tRC Address tAA CS# LB#, UB# OE# Data Out High-Z tCO tBA tOE tOH tHZ tBHZ tOHZ Data Vaild tOLZ tLZ tBLZ NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 1us. ¦¦¦¦ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM WRITE CYCLE (1) (WE# controlled, ZZ#=VIH) Address CS# LB#,UB# WE# tAS Data In Data Out High-Z tWC tAW tCW tBW tWP tDW Data Valid tWR tDH tWHZ Data Undefined tOW WRITE CYCLE (2) (CS# controlled, ZZ#=VIH) Address tAS tWC tCW tAW tWR CS# LB#,UB# WE# tBW tWP tDW tDH Data In Data Out High-Z Data Valid §§§§ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM WRITE CYCLE (3) (UB#,LB# controlled, ZZ#=VIH) tWC Address tCW CS# tAW LB#,UB# WE# tAS tBW tWP tDW Data In Data Out High-Z tWR tDH Data Valid NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS#, low WE# and low UB# or LB#. A write begins at the last transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from CS# going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS# or WE# going high. 5. Do not Access device with cycle timing shorter than tWC for continuous periods > 1us. ¨¨¨¨ Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM LOW POWER MODES Deep Power Down Mode Entry/Exit CS# tZZCS ZZ# tZZP ~~ ~~ tCSZZ ~ ~ tR Normal operation Deep Power Down Entry NOTES ( DEEP POWER DOWN ) During Deep Power Down mode, all referesh related activity are disabled. Deep Power Down Exit Parameter tZZCS tCSZZ tR tZZP Description ZZ# low to CS# low CS# high to ZZ# high Operation Recovery Time ZZ# pulse width Min 0 0 200 20 Max - Unit ns ns us ns Low Power Mode Characteristics Parameter Deep Power Down Current Symbol IZZ Test Conditions ZZ# < 0.2V, Other inputs = 0 ~ VCCQ (Max. condition : VCC=3.3V @ 85oC) Min - Typ - Max 10 Unit uA ©©©©      Rev 0.0 Preliminary EMP116MFAW Series 1Mx16 Pseudo Static RAM TIMING WAVEFORM OF POWER UP 200us VCC(Min.) VCC CS# Power Up Mode Normal Operation NOTE ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS# high. Then you get into the normal operation.           Rev 0.0