RMS132AF-10E

RMS132AW Advance Information 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These RMS132AW are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are and output voltage levels are compatible with LVCMOS. referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input Features JEDEC standard 3.0V/3.3V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. • Programmable CAS Latency : 2,3 clocks. • Programmable Driver Strength Control - Full Strength or 1/2, 1/4 of Full Strength • Deep Power Down Mode. • All inputs and outputs referenced to the positive edge of the system clock. • Data mask function by DQM. • Internal dual banks operation. • Burst Read Single Write operation. • Special Function Support. - PASR(Partial Array Self Refresh) - Auto TCSR(Temperature Compensated Self Refresh) • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge. Table1: Ordering Information Part No. RMS132AW-75E Clock Freq. 133 MHz Temperature -25°C to 85°C VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V Interface LVCMOS Package Wafer Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-717 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 1 RMS132AW Advance Information Figure1: Bond Pad Layout (TOP View) • • • • • Deep Trench Process 3 Metal Layers including Local Inter-connection Top Metal : Al-Cu Typical Pad Size : 70um X 70um Wafer Diameter : 8 inch (2332.4, 5826.8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 X 70um 70um Pad 52 103.5um 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 75um Pad 53 Y 217um (0,0) The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 2 RMS132AW Advance Information Table3: Pin Descriptions Pin CLK Pin Name System Clock Descriptions The system clock input. All other inputs are registered to the SDRAM on the rising edge CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Enable or disable all inputs except CLK, CKE and DQM. Selects bank to be activated during RAS activity. Selects bank to be read/written during CAS activity. Row Address Column Address Auto Precharge : RA0~RA10 : CA0~CA7 : A10 CKE /CS BA Clock Enable Chip Select Bank Address A0~A10 Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection /RAS, /CAS, /WE RAS, CAS and WE define the operation. Refer function truth table for details. Controls output buffers in read mode and masks input data in write mode. Multiplexed data input/output pin. Power supply for internal circuits and input buffers. Power supply for output buffers. No connection. DQM0~DQM3 DQ0~DQ31 VDD/VSS VDDQ/VSSQ NC The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 3 RMS132AW Advance Information Figure2: Functional Block Diagram EXTENDED MODE REGISTER CLOCK GENERATOR TCSR PASR CLK CKE ADDRESS ROW MODE REGISTER ADDRESS BUFFER & REFRESH COUNTER BANK B BANK A ROW DECODER ROW DECODER SENSE AMPLIFIER /CS /RAS /CAS /WE COLUMN DECODER COLUMN ADDRESS BUFFER & BURST COUNTER DATA CONTROL CIRCUIT The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. COMMAND DECODER CONTROL LOGIC & LATCH CIRCUIT DQM LATCH CIRCUIT INPUT & OUTPUT BUFFER DQ 4 RMS132AW Advance Information Figure3: Simplified State Diagram EXTENDED MODE REGISTER SET EM RS SELF REFRESH LF SE LF SE I EX T MODE REGISTER SET MRS IDLE CK E D DP IT EX REF CBR REFRESH CK E ↓ ACT DEEP POWER DOWN D DP POWER DOWN ROW ACTIVE T BS CKE ↓ CKE BS T ACTIVE POWER DOWN RG HA EC PR H IT TO EW AU IT WR PRE W AU RIT TO E PR WIT EC H HA RG E WRITE READ WRITE SUSPEND CKE ↓ WRITE CKE READ WRITE CKE ↓ READ CKE E READ SUSPEND WRITE A SUSPEND CKE ↓ WRITE A atio n) CKE ↓ READ A CKE E PR READ A SUSPEND CKE POWER ON PRECHARGE PRECHARGE PR E(P rec h arg e The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. e arg ech (Pr n) atio min ter ter min Automatic Sequence Manual Input 5 RMS132AW Advance Information Figure4: Mode Register Definition BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 0 10 0 9 WB 0 8 0 7 6 5 4 BT 3 2 1 0 Mode Register (Mx) CAS Latency Burst Length M9 0 1 Write Burst Mode Burst Read and Burst Write Burst Read and Single Write M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved M3 0 1 Burst Type Sequential Interleave M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved Note: M11(BA) must be set to “0” to select Mode Register (vs. the Extended Mode Register) Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4: Burst Definition Burst Length 2 0 4 0 1 1 0 0 0 8 0 1 1 1 1 Full Page 0 0 1 1 0 0 1 1 n=A0-7 (Location 0-256) Starting Column Order of Access Within a Burst Address Sequential Interleaved A2 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1. Cn+2, Cn+3, Cn+4… …Cn-1, Cn... Not Supported 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Note : 1. For full-page accesses: y = 256 2. For a burst length of two, A1-A7 select the blockof-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 select the blockof-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 6 RMS132AW Advance Information Figure5: Extended Mode Register BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 1 10 0 0 9 0 8 0 7 6 DS 5 4 TCSR 3 2 1 PASR 0 Extended Mode Register (Ex) E6 0 0 1 1 E5 0 1 0 1 Driver Strength Full Strength 1/2 Strength 1/4 Strength Reserved E4 0 0 1 1 E2 0 0 0 0 1 1 1 1 E3 0 1 0 1 E1 0 0 1 1 0 0 1 1 Maximum Case Temp. 85° 70° 45° Auto E0 0 1 0 1 0 1 0 1 All Banks One Bank (BA=0) Reserved Reserved Reserved Half of One Bank (BA=0, Row Address MSB=0) Quarter of One Bank (BA=0, Row Address 2 MSB=0) Reserved Self Refresh Coverage Note: E11(BA) must be set to “1” to select Extend Mode Register (vs. the base Mode Register) The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 7 RMS132AW Advance Information Functional Description In general, this 32Mb SDRAM (512K x 32Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32-bits Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA select the bank, A0-A10 select the row). The address bits (BA select the bank, A0-A7 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation. Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Extended Mode Register The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (BA=1) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M7 through M10 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 8 RMS132AW Advance Information Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA selects the bank, and the value on the A0-A10 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 9 RMS132AW Advance Information CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure6: CAS Latency T0 CLK T1 T2 T3 COMMAND READ NOP tLZ NOP tOH Dout DQ tAC CAS Latency=2 T0 CLK T1 T2 T3 T4 COMMAND READ NOP NOP tLZ NOP tOH Dout DQ tAC CAS Latency=3 DON’T CARE UNDEFINED Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 10 RMS132AW Advance Information Table5: Command Truth Table Function Command Inhinit (NOP) No Operation (NOP) Mode Register Set Extended Mode Register Set Active (select bank and activate row) Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge Selected Bank Burst Stop Auto Refresh Self Refresh Entry Self Refresh Exit CKEn-1 H H H H H H H H H H H H H H L CKEn X X X X X X X X X X X H H L H /CS H L L L L L L L L L L L L L H L H L H L H L /RAS X H L L L H H H H L L H L L X H X H X H X V X L H X H L /CAS X H L L H L L L L H H H L L X H X H X H X V /WE X H L L H H H L L L L L H H X H X H X H X V DQM X X X X X L/H L/H L/H L/H X X X X X X ADDR X X OP CODE OP CODE Bank/Row Bank/Col Bank/Col Bank/Col Bank/Col X Bank X X X X 3 3 2 L H L H H L 5 5 5 5 4 4 A10 Note Precharge Power Down Entry H L X X Precharge Down Exit L H X X Clock Suspend Entry Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit Note : H L H L L H L H X X X X X X X X 6 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. H: High Level, L: Low Level, X: Don't Care, V: Valid 2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK. 6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is assigned to the Deep Power Down function. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 11 RMS132AW Advance Information Table6: Function Truth Table Current State Command /CS L L L L L L L H L L L L Row Active L L L H L L L L Read L L L H /RAS L L L L H H H X L L L L H H H X L L L L H H H X /CAS L L H H L L H X L L H H L L H X L L H H L L H X /WE L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA A0-A10 OP CODE X X Row Add. Col Add./ A10 Col Add./ A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/Write AP Read/Read AP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/Read AP No Operation Device Deselect Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the Specified Bank and Row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : Optional AP(A10=H) Start Read : Optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst : Start the Precharge ILLEGAL Termination Burst : Start Write(AP) Terimination Burst : Start Read(AP) Continue the Burst Continue the Burst Note 14 5 Idle 4 4 3 3 13,14 13 7 4 6 6 13,14 13 4 8,9 8 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 12 RMS132AW Advance Information Table6: Function Truth Table Current State Command /CS L L L L Write L L L H L L Read with Auto Precharge L L L L L H L L Write with Auto Precharge L L L L L H /RAS L L L L H H H X L L L L H H H X L L L L H H H X /CAS L L H H L L H X L L H H L L H X L L H H L L H X /WE L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA A0-A10 OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Action ILLEGAL ILLEGAL Termination Burst : Start the Precharge ILLEGAL Termination Burst : Start Write(AP) Terimination Burst : Start READ(AP) Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 13,14 13 4,12 4,12 12 12 13,14 13 4,12 4,12 12 12 Note 13,14 13 10 4 8 8,9 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 13 RMS132AW Advance Information Table6: Function Truth Table Current State Command /CS L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L H /RAS L L L L H H H X L L L L H H H X L L L L H H H X /CAS L L H H L L H X L L H H L L H X L L H H L L H X /WE L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA A0-A10 OP CODE X X Row Add. Col Add./ A10 Col Add./ A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/Write AP Read/Read AP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/Read AP No Operation Device Deselect Action ILLEGAL ILLEGAL No Operation : Bank(s) Idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation : Bank(s) Idle after tRP No Operation : Bank(s) Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : ROw Active after tRCD No Operation : ROw Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write : Optional AP(A10=H) Start Write : Optional AP(A10=H) No Operation : Row Active after tDPL No Operation : Row Active after tDPL 9 13,14 13 4,13 4,12 13,14 13 4,12 4,11,12 4,12 4,12 4,12 4,12 4,12 Note 13,14 13 The specifications of this device are subject to change without notice. For latest documentation see http://www.emsli.com. 14 RMS132AW Advance Information Table6: Function Truth Table Current State Command /CS L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L Mode Register Accessing L L L L H /RAS L L L L H H H X L L L L H H H X L L L L H H H X /CAS L L H H L L H X L L H H L L H X L L H H L L H X /WE L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA A0-A10 OP CODE X X Row Add. Col Add./ A10 Col Add./ A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X OP CODE X X Row Add. Col Add./A10 Col Add./A10 X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/Write AP Read/Read AP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/Read AP No Operation Device Deselect Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Precharge after tDPL No Operation : Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Idle after tRC No Operation : Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Idle after 2 Clock Cycle No Operation : Idle after 2 Clock Cycle 13,14 13 13 13 13 13 13,14 13 13 13 13 13 Note 13,14 13 4,13 4,12 4,12 4,9,12 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 15 RMS132AW Advance Information Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 16 RMS132AW Advance Information Table7: CKE Truth Table Current State CKE Prev Cycle H L L L L L L H L Power Down L H L Current Cycle X H H H H H L X H /CS X H L L L L X X H L /RAS X X H H H L X X X H L X X L H Deep Power Down L L H H H H All Banks Idle H H H H H H L H Any State other than listed above H L L L X H L H H H H H L L L L L X H L H L X X X X H L L L L H L L L L X X X X X X X X X X H L L L X H L L L X X X X X Command /CAS X X H H L X X X X H X L X X X X X X X H L L X X H L L X X X X X /WE X X H L X X X X X H X X L X X X X X X X H L X X X H L X X X X X X X X X X X X OP CODE X X X X X Entry Self Refresh Mode Register Set Power Down Refer to Operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 5 X X OP CODE Auto Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table 5 4 4 4 5 BA X X X X X X X X X X X X X X X X X A0-A10 X X X X X X X X X X X X X X X X X Maintain Power Down Mode INVALID Deep Power Down Mode Set Maintain Deep Power Down Mode Refer to the Idle State section of the Current State Truth Table 4 4 4 2 6 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode Exit, All Banks Idle ILLEGAL 3 2 3 Action Note 2 3 3 3 3 3 Self Refresh The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 17 RMS132AW Advance Information Note : 1. H: Logic High, L: Logic Low, X: Don't care 2. For the given current state CKE must be low in the previous cycle. 3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 4. The address inputs depend on the command that is issued. 5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 100usec. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 18 RMS132AW Advance Information Table8: Absolute Maximum Rating Parameter Ambient Temperature (Industrial) Ambient Temperature (Commercial) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Note : Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD Rating -25 ~ 85 0 ~ 70 -55 ~ 150 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 Unit °C °C V V mA W Table9: Capacitance (TA=25 °C, f=1MHz, VDD=3.0V or 3.3V) Parameter Input Capacitance Pin CLK A0~A10, BA, CKE, /CS, /RAS, /CAS, /WE, DQM0~DQM3 DQ0~DQ31 Symbol CI1 CI2 CIO Min 2 2 3 Max 4 4 5 Unit pF pF pF Data Input/Output Capacitance Table10: DC Operating Condition (Voltage referenced to VSS=0V, TA= -25 ~ 85 °C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Note : 1. VDDQ must not exceed the level of VDD 2. VIH(max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns. 3. VIL(min) = -2.0V AC. The overshoot voltage duration is ≤ 3ns. 4. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. DOUT is disabled, 0V ≤ VOUT ≤ VDDQ. Symbol VDD VDDQ VIH VIL VOH VOL ILI ILO Min 2.7 2.7 2.2 -0.3 2.4 -1 -1.5 Typ 3.0 3.0 0 - Max 3.6 3.6 VDDQ+0.3 0.5 0.4 1 1.5 Unit V V V V V V uA uA Note 1 2 3 IOH= -0.1mA IOL= +0.1mA 4 5 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 19 RMS132AW Advance Information Table11: AC Operating Condition (TA= -25 ~ 85 °C, VDD = 3.0V or 3.3V ± 0.3V, VSS=0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL VTRIP tR / tF VOUTREF CL Typ 2.4 / 0.4 0.5 x VDDQ 1/1 0.5 x VDDQ 30 Unit V V ns V pF VDDQ 1200Ω Output 870Ω 30pF Output Z0=50Ω VTT=0.5 x VDDQ 50Ω 30pF DC Output Load Circuit AC Output Load Circuit The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 20 RMS132AW Advance Information Table12: DC Characteristic (DC operating conditions unless otherwise noted) Parameter Operating Current Precharge Standby Current in Power Down Mode Sym ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 Test Condition Burst Length=1, One Bank Active, tRC ≥ tRC(min) IOL = 0 mA CKE ≤ VIL(max), tCK = 10ns CKE & CLK ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2 clks. CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Input signals are stable. CKE ≤ VIL(max), tCK = 10ns CKE & CLK ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2 clks. CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Input signals are stable. tCK>tCK(min), IOL = 0 mA, Page Burst All Banks Activated, tCCD = 1 clk tRC ≥ tRFC(min), All Banks Active Speed -60 -75 45 80 80 6 -10 Unit mA Note 1 uA Precharge Standby Current in Non Power Down Mode mA 1 0.5 0.5 15 mA 6 80 75 40 70 mA mA 1 2 Active Standby Current in Power Down Mode mA Active Standby Current in Non Power Down Mode Burst Mode Operating Current Auto Refresh Current (4K Cycle) PASR Self Refresh Current 2 Banks TCSR 45~85°C -25~45°C 45~85°C -25~45°C 80~100 ICC6 CKE ≤ 0.2V 60~80 70~90 50~70 ICC7 10 uA uA 1 Bank Deep Power Down Mode Current Note : 1. Measured with outputs open. 2. Refresh period is 64ms. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 21 RMS132AW Advance Information Table13: AC Characteristic (AC operation conditions unless otherwise noted) Parameter CLK Cycle Time Access time from CLK (pos. edge) CLK High-Level Width CLK Low-Level Width CKE Setup Time CKE Hold Time /CS, /RAS, /CAS, /WE, DQM Setup Time /CS, /RAS, /CAS, /WE, DQM Hold Time Address Setup Time Address Hold Time Data-In Setup Time Data-In Hold Time Data-Out High-Impedance Time from CLK (pos.edge) Data-Out Low-Impedance Time Data-Out Hold Time (load) Data-Out Hold Time (no load) ACTIVE to PRECHARGE command PRECHARGE command period ACTIVE bank a to ACTIVE bank a command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay READ/WRITE command to READ/WRITE command WRITE command to input data delay Data-in to PRECHARGE command Data-in to ACTIVE command DQM to data high-impedance during READs DQM to data mask during WRITEs LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode Refresh period (4,096 rows) AUTO REFRESH period Exit SELF REFRESH to ACTIVE command Transition time CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 Sym tCK3 tCK2 tAC3 tAC2 tCH tCL tCKS tCKH tCMS tCMH tAS tAH tDS tDH tHZ3 tHZ2 tLZ tOH tOHN tRAS tRP tRC tRRD tRCD tCCD tDWD tDPL tDAL tDQZ tDQM tMRD tROH3 tROH2 tBDL tCDL tCKED tPED tREF tRFC tXSR tT Min 6.0 10 -60 Max 1000 5.5 8 Min 7.5 10 -75 Max 1000 6 8 Min 10 10 -10 Max 1000 8 8 Unit Note 1 2 3 3 2.5 2.5 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 5.5 8 1.0 2.5 1.8 42 18 60 12 18 1 0 12 30 2 0 2 3 2 1 1 1 1 64 66 66 0.5 1.2 100K 2.5 2.5 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 6 8 1.0 2.5 1.8 45 22.5 67.5 15 22.5 1 0 15 37.5 2 0 2 3 2 1 1 1 1 64 67.5 67.5 0.5 1.2 100K 2.5 2.5 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 8 8 1.0 2.5 1.8 40 24 64 20 20 1 0 20 40 2 0 2 3 2 1 1 1 CLK 1 64 70 70 0.5 1.2 ns ms CLK ns CLK 100K ns 4 5 6 6 7 7 6 6 8 6 6 6 9 9 5 5 The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 22 RMS132AW Advance Information Note : 1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to reduce the data rate. 2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. 3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 5. Parameter guaranteed by design. A. Target values listed with alternative values in parentheses. B. tRFC must be less than or equal to tRC+1CLK tXSR must be less than or equal to tRC+1CLK 6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate 8. JEDEC and PC100 specify three clocks. 9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate. 10. A new command can be given tRC after self refresh exit. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 23 RMS132AW Advance Information Special Operation for Low Power Consumption Temperature Compensated Self Refresh Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Setting M4 and M3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. Partial Array Self Refresh For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One Bank;bank 0. WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost. Deep Power Down Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 24 RMS132AW Advance Information Figure7: Deep Power Down Mode Entry CLK CKE /CS /RAS tRP Precharge if needed Deep Power Down Entry Figure8: Deep Power Down Mode Exit CLK CKE /CS /RAS /CAS /WE 100 µ s Deep Power Down Exit tRP Auto Refresh Auto Refresh tRFC Mode Register Set New Command Extended Mode Register Set All Banks Precharge The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 25 RMS132AW Advance Information Ordering Information EMLSI MEMORY PRODUCT FAMILY S : SDRAM R M XX XXXX X X X X XX– XX X TEMP E : Extended (-25’C ~ +85’C) SPEED 6 : 6ns 75 : 7.5ns 10 : 10ns CONFIGURATION / DENSITY 132 : 1Mx32, 32M bits POWER SUPPLY BLANK : VDD=3.3V & VDDQ=3.3V PACKAGE MATERIAL Blank : Normal MODE BLANK : DRAM PACKAGE TYPE F : FBGA W : Wafer VERSION A : 1st Ver. Revision History Revision A Date January 12th, 2006 Initial ADVANCE Release Change Description © 2004 EMLSI All rights reserved. EMLSI reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. EMLSI does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. EMLSI makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does EMLSI assume any liability arising out of the application or use of any product or circuit described herein. EMLSI does not authorize use of its products as critical components in any application in which the failure of the EMLSI product may be expected to result in significant injury or death, including life support systems and critical medical instrument. The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 26