Intel® Stratix® 10 Device Datasheet
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Contents
Contents
Intel® Stratix® 10 Device Datasheet.......................................................................................................................................... 3
Electrical Characteristics...................................................................................................................................................... 4
Operating Conditions.................................................................................................................................................. 4
Switching Characteristics....................................................................................................................................................29
Core Performance Specifications.................................................................................................................................29
Periphery Performance Specifications.......................................................................................................................... 37
L-Tile Transceiver Performance Specifications............................................................................................................... 48
H-Tile Transceiver Performance Specifications.............................................................................................................. 57
E-Tile Transceiver Performance Specifications...............................................................................................................66
P-Tile Transceiver Performance Specifications............................................................................................................... 69
HPS Performance Specifications................................................................................................................................. 75
Configuration Specifications.............................................................................................................................................. 105
General Configuration Timing Specifications............................................................................................................... 105
POR Specifications..................................................................................................................................................105
External Configuration Clock Source Requirements......................................................................................................106
JTAG Configuration Timing.......................................................................................................................................106
AS Configuration Timing.......................................................................................................................................... 107
Avalon®-ST Configuration Timing..............................................................................................................................109
Configuration Bit Stream Sizes................................................................................................................................. 112
I/O Timing......................................................................................................................................................................112
Programmable IOE Delay..................................................................................................................................................113
Glossary.........................................................................................................................................................................113
Document Revision History for the Intel Stratix 10 Device Datasheet...................................................................................... 118
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Intel® Stratix® 10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for
Intel® Stratix® 10 devices.
Table 1.
Intel Stratix 10 Device Grades and Speed Grades Supported
Device Grade
Speed Grade Supported
Extended
•
•
•
•
•
–E1V (fastest)
–E2V
–E2L
–E3V
–E3X
Industrial
•
•
•
•
•
–I1V
–I2V
–I2L
–I3V
–I3X
Commercial
•
–C2L
The suffix after the speed grade denotes the power options offered in Intel Stratix 10 devices.
•
V—SmartVID with standard static power. For “V” suffix devices, both VCC and VCCP must share the same SmartVID
regulator. VCCL_HPS can share the same SmartVID regulator or can use a separate fixed voltage regulator.
•
L—0.85 V fixed voltage with low static power
•
X—0.85 V fixed voltage with lowest static power
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks
of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel
assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
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Table 2.
Datasheet Status for Intel Stratix 10 Devices
Variant
Datasheet Status
Intel Stratix 10 GX
Final (Preliminary for 1SG040HF35 device only)
Intel Stratix 10 SX
Final (Preliminary for 1SX040HF35 device only)
Intel Stratix 10 TX
Final
Intel Stratix 10 MX
Final
Intel Stratix 10 DX
Final
(1)
Note:
The specifications for 1SG065 and 1SX065 devices will be available in the Intel Stratix 10 Device Datasheet in a future
release.
Note:
The following tables are still preliminary:
•
H-Tile Transmitter Specifications
•
General Configuration Timing Specifications for Intel Stratix 10 Devices
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel Stratix 10 devices.
Operating Conditions
Intel Stratix 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel Stratix 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel Stratix 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
(1)
Specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
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Caution:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 3.
Absolute Maximum Ratings for Intel Stratix 10 Devices
Symbol
Description
Condition
Minimum
Maximum
Unit
VCC
Core voltage power supply
—
–0.50
1.26
V
VCCP
Periphery circuitry and transceiver fabric interface power supply
—
–0.50
1.26
V
VCCERAM
Embedded memory and digital transceiver power supply
—
–0.50
1.24
V
VCCPT
Power supply for programmable regulator and I/O pre-driver
—
–0.50
2.46
V
VCCBAT
Battery back-up power supply for design security volatile key register
—
–0.50
2.46
V
VCCIO_SDM
Configuration pins power supply
—
–0.50
2.19
V
VCCIO
I/O buffers power supply (except for 1SG040HF35 and 1SX040HF35
banks 3C and 3D)
3 V I/O
–0.50
4.10
V
–0.50
2.19
V
LVDS I/O
(2)
VCCIO3C
I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices
bank 3C only
—
–0.50
3.63
V
VCCIO3D
I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices
bank 3D only
—
–0.50
1.98
V
VCCA_PLL
Phase-locked loop (PLL) analog power supply
—
–0.50
2.46
V
VCCPLLDIG_SDM
Secure Device Manager (SDM) block PLL digital power supply
—
–0.50
1.21
V
VCCPLL_SDM
SDM block PLL analog power supply
—
–0.50
2.19
V
VCCFUSEWR_SDM
Fuse block writing power supply
—
–0.50
3.19
V
VCCADC
ADC voltage sensor power supply
—
–0.50
2.19
V
VCCIO_UIB
Power supply for the Universal Interface Bus between the core and
embedded HBM2 memory
—
–0.30
1.50
V
VCCM_WORD
Power supply for the embedded HBM2 memory
—
–0.30
3.00
V
VCCT_GXB
Transmitter analog power supply
—
–0.50
1.47
V
continued...
(2)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Symbol
Description
Condition
Minimum
Maximum
Unit
VCCR_GXB
Receiver analog power supply
—
–0.50
1.47
V
VCCH_GXB
Transmitter output buffer power supply
—
–0.50
2.46
V
VCCRT_GXE
E-tile transceiver power supply
—
–0.50
1.21
V
VCCRTPLL_GXE
E-tile transceiver PLL power supply
—
–0.50
1.21
V
VCCH_GXE
E-tile transceiver analog power supply
—
–0.50
1.47
V
VCCCLK_GXE
E-tile transceiver LVPECL REFCLK power supply
—
–0.50
3.41
V
VCCRT_GXP
P-tile transceiver power supply
—
–0.50
1.21
V
VCCFUSE_GXP
P-tile transceiver eFuse power supply
—
–0.50
1.21
V
VCCH_GXP
P-tile transceiver analog power supply
—
–0.50
2.46
V
VCCCLK_GXP
P-tile transceiver I/O buffer power supply
—
–0.50
2.46
V
VCCL_HPS
HPS core voltage and periphery circuitry power supply
—
–0.50
1.30
V
VCCIO_HPS
HPS I/O buffers power supply
–0.50
2.19
V
VCCPLL_HPS
HPS PLL power supply
—
–0.50
2.46
V
VI
DC input voltage
3.3 V I/O
–0.30
VCCIO + 0.33
V
3 V I/O
–0.30
VCCIO + 0.65
V
LVDS I/O
–0.30
VCCIO + 0.3
V
15
mA
IOUT
DC output current per pin
LVDS I/O
—
(2)
–15
(3)(4)(5)(6)
(7)
continued...
(3)
The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down
conditions is 10 mA.
(4)
Total current per LVDS I/O bank must not exceed 100 mA.
(5)
Voltage level must not exceed 1.89 V.
(6)
Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.
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Symbol
TJ
TSTG
Description
Condition
Minimum
Maximum
Unit
Absolute junction temperature for Intel Stratix 10 MX, NX, and DX
2100 devices
—
–55
120
°C
Absolute junction temperature for Intel Stratix 10 GX 10M device
—
0
125
°C
Absolute junction temperature for all other Intel Stratix 10 devices
—
–55
125
°C
Storage temperature (no bias) for Intel Stratix 10 MX, NX, and DX
2100 devices
—
–55
120
°C
Storage temperature (no bias) for Intel Stratix 10 GX 10M device
—
0
125
°C
Storage temperature (no bias) for all other Intel Stratix 10 devices
—
–55
150
°C
Related Information
•
AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices
Provides the power sequencing requirements for Intel Stratix 10 devices.
•
Power Sequencing Considerations for Intel Stratix 10 Devices, Intel Stratix 10 Power Management User Guide
Provides the power sequencing requirements for Intel Stratix 10 devices.
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –1.1 V for input
currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal
is equivalent to 100% duty cycle.
For example, when using VCCIO = 1.8 V, a signal that overshoots to 2.44 V for LVDS I/O can only be at 2.44 V for ~6% over
the lifetime of the device.
(7)
Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power
sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel Cyclone® 10 GX, Intel Arria®
10, and Intel Stratix 10 Devices and Intel Stratix 10 Power Management User Guide.
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Table 4.
Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices (for LVDS I/O)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol
Vi (AC)
Table 5.
Description
AC input voltage
LVDS I/O (V)
(8)
Overshoot Duration as % at TJ = 100°C
Unit
VCCIO + 0.30
100
%
VCCIO + 0.35
60
%
VCCIO + 0.40
30
%
VCCIO + 0.45
20
%
VCCIO + 0.50
10
%
VCCIO + 0.55
6
%
> VCCIO + 0.55
No overshoot allowed
—
Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices (for 3 V I/O)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol
Vi (AC)
(8)
Description
AC input voltage
Overshoot Duration as % at TJ = 100°C
Unit
VCCIO + 0.65
100
%
VCCIO + 0.70
42
%
VCCIO + 0.75
18
%
VCCIO + 0.80
9
%
VCCIO + 0.85
4
%
> VCCIO + 0.85
No overshoot allowed
—
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Table 6.
Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices (for 3.3 V I/O)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol
Vi (AC)
Description
AC input voltage
3.3 V I/O (V)
Overshoot Duration as % at TJ = 100°C
Unit
VCCIO + 0.33
100
%
VCCIO + 0.41
60
%
VCCIO + 0.47
40
%
VCCIO + 0.69
10
%
VCCIO + 0.95
2
%
> VCCIO + 0.95
No overshoot allowed
—
For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period.
Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on
with 100% I/O toggle rate and 50% duty cycle signal.
Figure 1.
Intel Stratix 10 Devices Overshoot Duration
2.45 V
2.44V
1.8 V
DT
T
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel Stratix 10 devices.
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Recommended Operating Conditions
Table 7.
Recommended Operating Conditions for Intel Stratix 10 Devices
This table lists the steady-state voltage values expected for Intel Stratix 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol
VCC
Description
Core voltage power supply for Intel Stratix 10
GX 10M device
Core voltage power supply for all other Intel
Stratix 10 devices
VCCP
Periphery circuitry and transceiver fabric
interface power supply for Intel Stratix 10 GX
10M device
Periphery circuitry and transceiver fabric
interface power supply for all other Intel Stratix
10 devices
Condition
Minimum
(9)
Typical
Maximum
(9)
Unit
–E2L, –C2L
0.85
0.88
0.91
V
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V (10)
(Typical) – 30
mV
0.8 – 0.94
(Typical) + 30
mV
V
–E2L, –I2L, –E3X, –I3X
0.82
0.85
0.88
V
–E2L, –C2L
0.85
0.88
0.91
V
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V (10)
(Typical) – 30
mV
0.8 – 0.94
(Typical) + 30
mV
V
–E2L, –I2L, –E3X, –I3X
0.82
0.85
0.88
V
1.8 V
1.71
1.8
1.89
V
VCCIO_SDM
Configuration pins power supply
VCCPLLDIG_SDM
Secure Device Manager (SDM) block PLL digital
power supply
—
0.87
0.9
0.93
V
VCCPLL_SDM
SDM block PLL analog power supply
—
1.71
1.8
1.89
V
VCCFUSEWR_SDM
Fuse block writing power supply
—
2.35
2.4
2.45
V
VCCADC
ADC voltage sensor power supply
—
1.71
1.8
1.89
V
VCCERAM
Embedded memory and digital transceiver
power supply
0.9 V
0.87
0.9
0.93
V
continued...
(9)
(10)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power
distribution network design.
The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel Stratix 10 SmartVID devices is mandatory for VCC
and VCCP. The PMBus voltage regulator and Intel Stratix 10 SmartVID devices are connected via PMBus.
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Symbol
VCCBAT
(11)
Description
Battery back-up power supply (For design
security volatile key register)
Condition
Minimum
(9)
Typical
Maximum
(9)
Unit
—
1.2
—
1.8
V
VCCPT
Power supply for programmable regulator and
I/O pre-driver
1.8 V
1.71
1.8
1.89
V
VCCIO
I/O buffers power supply for LVDS I/O (except
for 1SG040HF35 and 1SX040HF35 banks 3C
and 3D)
1.8 V
1.71
1.8
1.89
V
1.5 V
1.425
1.5
1.575
V
1.35 V
1.283
1.35
1.45
V
1.25 V
1.19
1.25
1.31
V
1.2 V
1.14
1.2
1.26
V
3.0 V
2.85
3
3.15
V
2.5 V
2.375
2.5
2.625
V
1.8 V
1.71
1.8
1.89
V
1.5 V
1.425
1.5
1.575
V
VCCIO3V
I/O buffers power supply for 3 V I/O
1.2 V
1.14
1.2
1.26
V
I/O buffers power supply for 1SG040HF35 and
1SX040HF35 devices bank 3C only
3.3 V
3.135
3.3
3.465
V
3.0 V
2.85
3
3.15
V
VCCIO3D
I/O buffers power supply for 1SG040HF35 and
1SX040HF35 devices bank 3D only
1.8 V
1.71
1.8
1.89
V
VCCIO_UIB
Power supply for the Universal Interface Bus
between the core and embedded HBM2
memory
1.2 V
1.17
1.2
1.23
V
VCCM_WORD
Power supply for the embedded HBM2 memory
—
2.4
2.5
2.6
VCCIO3C
V
continued...
(9)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power
distribution network design.
(11)
Intel recommends connecting VCCBAT to a 1.8 V power supply if you do not use the design security feature in Intel Stratix 10 devices.
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Symbol
VCCA_PLL
VI
VO
(12)(13)
Description
PLL analog voltage regulator power supply
DC input voltage
Operating junction temperature for Intel Stratix
10 GX 10M device
Minimum
(9)
Typical
Maximum
(9)
Unit
—
1.71
1.8
1.89
V
3.3 V I/O
–0.3
—
VCCIO + 0.33
V
3 V I/O
–0.3
—
VCCIO + 0.65
V
LVDS I/O
–0.3
—
VCCIO + 0.3
V
—
0
—
VCCIO
V
0
—
Commercial
25
—
85
Extended
25
—
100
Output voltage
Operating junction temperature for Intel Stratix
10 MX, NX, and DX 2100 devices
TJ
Condition
Extended
(14)
100
(15)
°C
°C
°C
continued...
(9)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power
distribution network design.
(12)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
(13)
This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the
maximum value.
(14)
Intel Stratix 10 MX, NX, and DX 2100 devices are generally offered in Extended temperature range only. If Industrial temperature
range is required, note that you can configure these devices at less than 0°C, but the HBM2 interface will be held in reset and will not
be calibrated until TJ reaches 0°C. Contact your Intel sales representative for the availability of Intel Stratix 10 MX, NX, and DX 2100
Industrial temperature range devices.
(15)
Recommended maximum operating temperature for HBM2 is 95°C.
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Symbol
Description
Operating junction temperature for all other
Intel Stratix 10 devices
tRAMP
(17)(18)(19)
Power supply ramp time
Condition
Extended
Industrial
Standard POR
Minimum
(9)
0
-20 (–40)
200 μs
(16)
Typical
Maximum
(9)
Unit
—
100
°C
—
100
°C
—
100 ms
—
Related Information
My-Intel.com
(9)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power
distribution network design.
(16)
E-tile supports an operating temperature range of –40°C to 100°C. However, the E-tile transceivers may experience a higher error
rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended
operating temperature range for E-tile protocol-compliant transceiver links is –20°C to 100°C. The environmental temperature ramp
rate for the device is limited to 2°C per minute, otherwise, the device would not be compliant and may lead to link activity failure.
(17)
tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
(18)
To support AS fast mode, all power supplies to the Intel Stratix 10 device must be fully ramped-up within 10 ms to the recommended
operating conditions.
(19)
To support AS normal mode, VCCIO_SDM of the Intel Stratix 10 device must be fully ramped-up within 10 ms to the recommended
operating condition.
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Transceiver Power Supply Operating Conditions
Table 8.
Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Non-Bonded
Configuration
Symbol
VCCT_GXB[L,R] and
VCCR_GXB[L,R]
Description
Chip-to-chip
Backplane
VCCH_GXB[L,R]
(20)
(24)
Transceiver high voltage
power
Datarate
Minimum
Typical
1.0 Gbps to 26.6 Gbps
1.1
1.12
1.0 Gbps to 17.4
Gbps (21) (22)
1.0
1.03
1.0 Gbps to 12.5
Gbps (21)
1.0
1.03
—
1.71
(21) (22)
(26)
Maximum
Unit
1.14
V
(23)
1.06
V
(25), (23)
1.06
V
1.89
V
1.8
(20)
Chip-to-chip refers to transceiver links that are short reach and do not require advanced equalization such as decision feedback
equalization (DFE).
(21)
Stratix 10 transceivers can support data rates below 1.0 Gbps through over sampling.
(22)
Bonded channels operating at datarates above 16.0 Gbps require 1.12 V ±20 mV at the pin. For channels that are placed on the
same tile as the channels that require 1.12 V ±20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ±20 mV.
(23)
For a 1.03-V typical voltage, the maximum/minimum should be ± 30 mV; hence, VMAX = 1.06 V. However, when these channels share
the power supply with channels requiring a 1.12-V typical voltage, these channels should increase typical voltage to 1.12 V, with a
maximum/minimum ± 20 mV; hence VMAX = 1.14 V.
(24)
Backplane applications refer to ones which require advanced equalization, such as DFE enabled, to compensate for channel loss.
(25)
Refer to the Intel Quartus® Prime Pro Edition software for the typical nominal value.
(26)
In an optical transfer network (OTN) application, the minimum VCCH voltage specification at the package pin is 1.77 V.
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Table 9.
Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Bonded
Configuration
Symbol
VCCT_GXB[L,R] and
VCCR_GXB[L,R]
Description
Chip-to-chip
Datarate
(20)
1.0 Gbps to 16.0 Gbps
Minimum
(21)
> 16.0 Gbps to 17.4 Gbps
(21)
(22)
Backplane
VCCH_GXB[L,R]
Table 10.
(21)
—
1.0
1.03
1.1
1.12
1.0
1.03
1.71
(26)
(25), (23)
1.8
Maximum
Unit
1.06
V
1.14
V
1.06
V
1.89
V
Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices in a NonBonded Configuration
VCCT_GXB[L,R] and
VCCR_GXB[L,R]
VCCH_GXB[L,R]
Description
(20)and
Chip-to-chip
Backplane (24)
Transceiver high
voltage power
Datarate
Minimum
Typical
1.0 Gbps to 28.3 Gbps
(GXT) (21)
1.1
1.12
1.0 Gbps to 17.4 Gbps
(GX) (21)
1.0
1.03
—
1.71
(26)
(23)
1.8
Maximum
Unit
1.14
V
1.06
V
1.89
V
Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices in a Bonded
Configuration
Symbol
Description
(20)
VCCT_GXB[L,R] and
VCCR_GXB[L,R]
Chip-to-chip
Backplane (24)
VCCH_GXB[L,R]
Transceiver high
voltage power
Note:
1.0 Gbps to 12.5 Gbps
Transceiver high
voltage power
Symbol
Table 11.
(24)
Typical
(23)
and
Datarate
1.0 Gbps to 16.0 Gbps
Minimum
(21)
Typical
1.0
1.03
> 16.0 Gbps to 17.4
Gbps (21)
1.1
—
1.71
(26)
(23)
Maximum
Unit
1.06
V
1.12
1.14
V
1.8
1.89
V
Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-tile basis to
minimize power consumption. Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines and the Intel Quartus
Prime pin report for information about pinning out the package to minimize power consumption for your specific design.
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Table 12.
Transceiver Power Supply Operating Conditions for Intel Stratix 10 TX/MX E-Tile Devices
Symbol
VCCRT_GXE
(28)
VCCRTPLL_GXE
(28)
(27)
Description
Minimum
Typical
Transceiver power
supply
0.87
0.9
Transceiver PLL power
supply
0.87
Maximum
(27)
Unit
Noise Mask (at ball
grid array (BGA))
0.93
V
20 mVpp (100 kHz to
400 kHz)
3 mVpp (3 MHz to 500
MHz)
10 mVpp at 1 GHz
0.9
0.93
V
6 mVpp at 100 kHz
1 mVpp (600 kHz to
10 MHz)
10 mVpp at 1 GHz
VCCH_GXE
Analog power supply
1.067
1.1
1.133
V
10 mVpp (800 kHz to
500 MHz
VCCCLK_GXE
LVPECL REFCLK power
supply
2.375
2.5
2.625
V
—
(27)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
(28)
The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV.
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Table 13.
Transceiver Power Supply Operating Conditions for Intel Stratix 10 DX P-Tile Devices
The specifications below should be met at the board level via direct connection to the package power balls. Place the voltage rail (VR) sense point in the FPGA
pinfield as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.
Symbol
Description
Minimum
Typical
Maximum
Unit
0.87
0.90
0.93
V
P-tile eFuse power
supply
0.87
0.90
0.93
V
P-tile I/O buffer power
supply
1.75
1.80
1.85
V
High voltage power for
Transceiver
1.75
1.80
1.85
V
VCCRT_GXP(29)
Transceiver power
supply
VCCFUSE_GXP(29)
VCCCLK_GXP(31)
VCCH_GXP(31)
(32)
(32)
Data Rate
Up to 16 Gbps(30)
Related Information
Intel Stratix 10 Device Family Pin Connection Guidelines
(29)
The recommended DC setpoint is 0.5% of the typical value, the recommended VR ripple and AC transient sum up to 2.5% of the
typical value.
(30)
The data rate includes Intel PCIe* Gen1 through Gen4 protocols and Intel UPI protocol at 9.6 Gbps, 10.4 Gbps, and 11.2 Gbps in
future releases.
(31)
The recommended DC setpoint is 0.5% of the typical value, the recommended VR ripple is 0.5% of the typical value, and the
recommended AC transient is 2% of the typical value.
(32)
Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.
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HPS Power Supply Operating Conditions
Table 14.
HPS Power Supply Operating Conditions for Intel Stratix 10 Devices
This table lists the steady-state voltage and current values expected for Intel Stratix 10 system-on-a-chip (SoC) devices with Arm*-based hard processor system
(HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Intel Stratix 10 Devices table for the
steady-state voltage values expected from the FPGA portion of the Intel Stratix 10 SoC devices.
Symbol
VCCL_HPS
Description
Condition
Minimum
Typical
Maximum
Unit
HPS core voltage and periphery circuitry power
supply
–E2L, –I2L, –E3X, –I3X
0.87
0.9
0.93
V
0.91
0.94
0.97
V
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
0.87
0.9
0.93
V
0.91
0.94
0.97
V
0.87
0.9
0.93
V
0.91
0.94
0.97
V
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
0.87
0.9
0.93
V
0.91
0.94
0.97
V
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V (33)
VCCPLLDIG_HPS
HPS PLL digital power supply
–E2L, –I2L, –E3X, –I3X
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V (33)
VCCPLL_HPS
HPS PLL analog power supply
1.8 V
1.71
1.8
1.89
V
VCCIO_HPS
HPS I/O buffers power supply
1.8 V
1.71
1.8
1.89
V
Related Information
(33)
•
Recommended Operating Conditions on page 10
Provides the steady-state voltage values for the FPGA portion of the device.
•
HPS Clock Performance on page 75
When using the V suffix devices, the use of Power Management Bus (PMBus) voltage regulator dedicated to Intel Stratix 10 SmartVID
devices is mandatory for VCC and VCCP. The PMBus voltage regulator and Intel Stratix 10 SmartVID devices are connected via PMBus.
VCCL_HPS and VCCPLLDIG_HPS may be connected to the PMBus voltage regulator or a fixed voltage.
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DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Intel FPGA Power and Thermal Calculator (PTC) and the Intel
Quartus Prime Power Analyzer feature.
Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude
estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Table 15.
I/O Pin Leakage Current for Intel Stratix 10 Devices
Symbol
Description
Condition
Min
Max
Unit
II
Input pin leakage
VI = 0 V to VCCIOMAX
–80
80
µA
II_3.3VIO
Input pin leakage for 3.3 V I/O pin
VI = 0 V to VCCIOMAX
–2
2
µA
IOZ
Tri-stated I/O pin leakage
VO = 0 V to VCCIOMAX
–80
80
µA
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.
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Table 16.
Bus Hold Parameters for Intel Stratix 10 Devices
Parameter
Symbol
Condition
VCCIO (V)
1.2
1.5
Unit
1.8
2.5
3.0
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold, low,
sustaining
current
ISUSL
VIN > VIL
(max)
8
—
12
—
30
—
60
—
70
—
µA
Bus-hold, high,
sustaining
current
ISUSH
VIN < VIH
(min)
–8
—
–12
—
–30
—
–60
—
–70
—
µA
Bus-hold, low,
overdrive current
IODL
0 V < VIN <
VCCIO
—
125
—
175
—
200
—
300
—
500
µA
Bus-hold, high,
overdrive current
IODH
0 V < VIN <
VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
µA
Bus-hold trip
point
VTRIP
—
0.3
0.9
0.38
1.13
0.68
1.07
0.7
1.7
0.8
2
V
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to
the calibration block.
Table 17.
OCT Calibration Accuracy Specifications for Intel Stratix 10 Devices
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Description
Symbol
Condition (V)
Calibration Accuracy
Unit
–E1, –I1
–E2, –I2
–E3, –I3
34-Ω, 48-Ω, 60-Ω, 80-Ω,
120-Ω, and 240-Ω RS
Internal series termination with calibration
(34-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and
240-Ω setting)
VCCIO = 1.2
±15
±15
±15
%
34-Ω and 40-Ω RS
Internal series termination with calibration
(34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35, 1.25, 1.2
±15
±15
±15
%
25-Ω and 50-Ω RS
Internal series termination with calibration
(25-Ω and 50-Ω setting)
VCCIO = 1.8, 1.5, 1.2
±15
±15
±15
%
continued...
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Symbol
Description
Condition (V)
Calibration Accuracy
Unit
–E1, –I1
–E2, –I2
–E3, –I3
±15
±15
±15
%
34-Ω, 40-Ω, 48-Ω, 60-Ω,
80-Ω, 120-Ω, and 240-Ω RT
Internal parallel termination with
calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80Ω, 120-Ω, and 240-Ω setting)
POD12 I/O standard,
VCCIO = 1.2
48-Ω, 50-Ω, 60-Ω, and
120-Ω RT
Internal parallel termination with
calibration (48-Ω, 50-Ω, 60-Ω, and 120-Ω
setting)
VCCIO = 1.5, 1.2
–10 to +60
–10 to +60
–10 to +60
%
48-Ω, 60-Ω, and 120-Ω RT
Internal parallel termination with
calibration (48-Ω, 60-Ω, and 120-Ω
setting)
VCCIO = 1.25
–10 to +70
–10 to +70
–10 to +70
%
48-Ω, 60-Ω, and 120-Ω RT
Internal parallel termination with
calibration (48-Ω, 60-Ω, and 120-Ω
setting)
VCCIO = 1.35
–10 to +65
–10 to +65
–10 to +65
%
50-Ω RT
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8
–10 to +50
–10 to +50
–10 to +50
%
OCT Without Calibration Resistance Tolerance Specifications
Table 18.
OCT Without Calibration Resistance Tolerance Specifications for Intel Stratix 10 Devices
This table lists the Intel Stratix 10 OCT without calibration resistance tolerance to PVT changes.
Symbol
Description
I/O Buffer
Type
Condition (V)
Resistance Tolerance
Unit
–E1, –I1
–E2, –I2
–E3, –I3
25-Ω and 50-Ω RS
Internal series termination without
calibration
(25-Ω and 50-Ω setting)
3 V I/O
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2
–40 to +30
±40
±40
%
25-Ω and 50-Ω RS
Internal series termination without
calibration
(25-Ω and 50-Ω setting)
LVDS I/O
VCCIO = 1.8, 1.5, 1.2
–20 to +35
–20 to +35
–20 to +35
%
continued...
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Symbol
Description
I/O Buffer
Type
Condition (V)
Resistance Tolerance
Unit
–E1, –I1
–E2, –I2
–E3, –I3
34-Ω and 40-Ω RS
Internal series termination without
calibration
(34-Ω and 40-Ω setting)
LVDS I/O
VCCIO = 1.5, 1.35, 1.25,
1.2
–20 to +35
–20 to +35
–20 to +35
%
48-Ω, 60-Ω, 80-Ω, and
240-Ω RS
Internal series termination without
calibration
(48-Ω, 60-Ω, 80-Ω, and 240-Ω
setting)
LVDS I/O
VCCIO = 1.2
–20 to +35
–20 to +35
–20 to +35
%
100-Ω RD
Internal differential termination (100Ω setting)
LVDS I/O
VCCIO = 1.8
±25
±35
±40
%
Pin Capacitance
Table 19.
Pin Capacitance for Intel Stratix 10 Devices
Symbol
Description
Maximum
Unit
CIO_COLUMN
Input capacitance on column I/O pins
3.5
pF
CIO_3.3VIO
Input/output capacitance of I/O pins
5
pF
COUTFB
Input capacitance on dual-purpose clock output/feedback pins
3.5
pF
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the
configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options. The internal weak pulldown feature is only supported in selected HPS and SDM I/O. The typical value for this internal weak pull-down resistor is
approximately 25 kΩ.
Table 20.
Internal Weak Pull-Up Resistor Values for Intel Stratix 10 Devices
Symbol
RPU
Description
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
Condition (V)
Nominal Value
Resistance
Tolerance
Unit
VCCIO = 3.0 ±5%
25
±25%
kΩ
VCCIO = 2.5 ±5%
25
±25%
kΩ
VCCIO = 1.8 ±5%
25
±25%
kΩ
continued...
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Symbol
Description
Condition (V)
Nominal Value
Resistance
Tolerance
Unit
VCCIO = 1.5 ±5%
25
±25%
kΩ
VCCIO = 1.35 ±5%
25
±25%
kΩ
VCCIO = 1.25 ±5%
25
±25%
kΩ
VCCIO = 1.2 ±5%
25
±25%
kΩ
Related Information
•
Intel Stratix 10 Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
•
Intel Stratix 10 Configuration Pins, Intel Stratix 10 Configuration User Guide
Provides more information about the SDM I/O pins weak pull-up and weak pull-down features.
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH
and IOL) for various I/O standards supported by Intel Stratix 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Related Information
Recommended Operating Conditions on page 10
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Single-Ended I/O Standards Specifications
Table 21.
Single-Ended I/O Standards Specifications for Intel Stratix 10 Devices
I/O Standard
VCCIO (V)
VIL(V)
VIH(V)
VOL (V)
VOH (V)
IOL (34)
(mA)
IOH (34)
(mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.3 V LVTTL, 3.3
V LVCMOS (35)
3.135
3.3
3.465
–0.3
0.8
2
3.6
0.4
2.4
4
–4
3.0 V LVTTL, 3.0
V LVCMOS (35)
2.85
3
3.15
–0.3
0.8
2
3.6
0.4
2.4
4
–4
3.0 V LVTTL
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
3.0 V LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
2.5 V
2.375
2.5
2.625
–0.3
0.7
1.7
3.3
0.4
2
1
–1
1.8 V
1.71
1.8
1.89
-0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.45
VCCIO – 0.45
2
–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
Schmitt Trigger
Input
1.71
1.8
1.89
—
0.35 × VCCIO
0.65 × VCCIO
—
—
—
—
—
(34)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 1.8- V
LVCMOS specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet
the IOL and IOH specifications in the datasheet.
(35)
Specifications for 3.3 V LVTTL, 3.3 V LVCMOS, 3.0 V LVTTL, and 3.0 V LVCMOS I/O standards supported in 1SG040HF35 or
1SX040HF35 devices I/O bank 3C only.
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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 22.
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Stratix 10 Devices
I/O Standard
VCCIO (V)
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF - 0.04
VREF
VREF + 0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-135
1.283
1.35
1.45
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-125
1.19
1.25
1.31
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-12
1.14
1.2
1.26
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 × VCCIO
0.5 × VCCIO
0.53 × VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
—
—
—
POD12
1.14
1.2
1.26
—
Internally
calibrated
—
—
VCCIO
—
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Table 23.
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Stratix 10 Devices
I/O Standard
VIL(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
IOL (36) IOH (36)
(mA)
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
SSTL-18 Class I
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18 Class
II
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO –0.28
13.4
–13.4
SSTL-15 Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
8
–8
SSTL-15 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
16
–16
SSTL-135
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.16
VREF + 0.16
0.2 × VCCIO
0.8 × VCCIO
—
—
SSTL-125
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.15
VREF + 0.15
0.2 × VCCIO
0.8 × VCCIO
—
—
SSTL-12
—
VREF – 0.10
VREF + 0.10
—
VREF – 0.15
VREF + 0.15
0.2 × VCCIO
0.8 × VCCIO
—
—
HSTL-18 Class I
—
VREF –0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-18 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-15 Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-15 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –0.4
16
–16
HSTL-12 Class I
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
8
–8
HSTL-12 Class
II
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
16
–16
—
VREF – 0.13
VREF + 0.13
—
VREF – 0.22
VREF + 0.22
0.1 × VCCIO
0.9 × VCCIO
—
—
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
—
—
—
—
HSUL-12
POD12
(36)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI
specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL
and IOH specifications in the datasheet.
Intel® Stratix® 10 Device Datasheet
26
VIH(DC) (V)
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Differential SSTL I/O Standards Specifications
Table 24.
Differential SSTL I/O Standards Specifications for Intel Stratix 10 Devices
I/O Standard
VCCIO (V)
VSWING(DC) (V)
VSWING(AC) (V)
VIX(AC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
SSTL-18 Class
I, II
1.71
1.8
1.89
0.25
VCCIO + 0.6
0.5
VCCIO + 0.6
VCCIO/2 – 0.175
—
VCCIO/2 +
0.175
SSTL-15 Class
I, II
1.425
1.5
1.575
0.2
(37)
2(VIH(AC) –
VREF)
2(VREF –
VIL(AC))
VCCIO/2 – 0.15
—
VCCIO/2 + 0.15
SSTL-135
1.283
1.35
1.45
0.18
(37)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VCCIO/2 – 0.15
—
VCCIO/2 + 0.15
SSTL-125
1.19
1.25
1.31
0.18
(37)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VCCIO/2 – 0.15
—
VCCIO/2 + 0.15
SSTL-12
1.14
1.2
1.26
0.16
(37)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VREF – 0.15
VCCIO/2
VREF + 0.15
Differential HSTL and HSUL I/O Standards Specifications
Table 25.
Differential HSTL and HSUL I/O Standards Specifications for Intel Stratix 10 Devices
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VDIF(AC) (V)
VX(AC) (V)
VCM(DC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
HSTL-18 Class
I, II
1.71
1.8
1.89
0.2
—
0.4
—
0.78
—
1.12
0.78
—
1.12
HSTL-15 Class
I, II
1.425
1.5
1.575
0.2
—
0.4
—
0.68
—
0.9
0.68
—
0.9
HSTL-12 Class
I, II
1.14
1.2
1.26
0.16
VCCIO +
0.3
0.3
VCCIO +
0.48
—
0.5 ×
VCCIO
—
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
HSUL-12
1.14
1.2
1.3
2(VIH(DC) –
VREF)
2(VREF –
VIH(DC))
2(VIH(AC) –
VREF)
2(VREF –
VIH(AC))
0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
(37)
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended
limits (VIH(DC) and VIL(DC)).
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Differential I/O Standards Specifications
Table 26.
Differential I/O Standards Specifications for Intel Stratix 10 Devices
I/O Standard
LVDS
RSDS
(41)
(42)
Mini-LVDS
LVPECL
(43)
(44)
VCCIO (V)
VID (mV)
(38)
VICM(DC) (V)
VOD (V)
(39) (40)
VOCM (V)
(39)
Min
Typ
Max
Min
Max
Min
Condition
Max
Min
Typ
Max
Min
Typ
Max
1.71
1.8
1.89
100
—
0.05
Data rate
≤700 Mbps
1.65
0.247
—
0.6
1.125
1.25
1.375
1
Data rate
>700 Mbps
1.6
1.71
1.8
1.89
100
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.4
1.71
1.8
1.89
200
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.4
1.71
1.8
1.89
300
—
0.6
Data rate
≤700 Mbps
1.7
—
—
—
—
—
—
1
Data rate
>700 Mbps
1.6
(38)
The minimum VID value is applicable over the entire common mode range, VCM.
(39)
RL range: 90 ≤ RL ≤ 110 Ω.
(40)
The specification is only applicable to default VOD setting. Intel recommends performing IBIS or HSPICE simulation to estimate the
buffer's electrical performance when non-default VOD setting is used.
(41)
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700
Mbps and 0.05 V to 1.65 V for data rates below 700 Mbps.
(42)
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.
(43)
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.
(44)
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above
700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.
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Switching Characteristics
This section provides the performance characteristics of Intel Stratix 10 core and periphery blocks.
Core Performance Specifications
Clock Tree Specifications
Table 27.
Clock Tree Performance for Intel Stratix 10 Devices
Parameter
Performance
Programmable clock routing
Unit
–E1V, –I1V
–E2V, –E2L, –I2V, –I2L, –
C2L
–E3V, –E3X, –I3V, –I3X
1,000
900
780
MHz
PLL Specifications
Fractional PLL Specifications
Table 28.
Fractional PLL Specifications for Intel Stratix 10 Devices
These specifications are applicable when fPLL is used in core mode.
Symbol
Parameter
Condition
Min
Typ
Max
800
(45)
Unit
fIN
Input clock frequency
—
29
—
MHz
fINPFD
Input clock frequency to the phase
frequency detector (PFD)
—
29
—
700
MHz
fVCO
PLL voltage-controlled oscillator (VCO)
operating range for core applications
—
6
—
14.025
GHz
tEINDUTY
Input clock duty cycle
—
40
—
60
%
fOUT
Output frequency for internal clock
—
—
—
1
GHz
continued...
(45)
This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
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Symbol
fDYCONFIGCLK
Parameter
Dynamic configuration clock for
Condition
Min
Typ
Max
Unit
—
—
—
125
MHz
reconfig_clk
tLOCK
Time required to lock from end-of-device
configuration
—
—
—
1
ms
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-postscale counters/delays)
—
—
—
1
ms
fCLBW
PLL closed-loop bandwidth
—
0.3
—
4
MHz
FREF ≥ 100 MHz
—
—
0.13
UI (p-p)
FREF < 100 MHz
—
—
±650
ps (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
—
—
32
—
bit
tINCCJ
(46), (47)
tOUTPJ
(48)
tOUTCCJ
dKBIT
(48)
Input clock cycle-to-cycle jitter
Period jitter for clock output
Cycle-to-cycle jitter for clock output
Bit number of Delta Sigma Modulator (DSM)
Related Information
Memory Output Clock Jitter Specifications on page 45
Provides more information about the external memory interface clock output jitter specifications.
(46)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with
jitter < 120 ps.
(47)
FREF is fIN/N, specification applies when N = 1.
(48)
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory
Output Clock Jitter Specifications for Intel Stratix 10 Devices table.
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I/O PLL Specifications
Table 29.
I/O PLL Specifications for Intel Stratix 10 Devices
Symbol
fIN
Parameter
Input clock frequency
fINPFD
Input clock frequency to the PFD
fVCO
PLL VCO operating range
Condition
Min
Typ
–1 speed grade
10
—
1,100
Max
–2 speed grade
10
—
900
(49)
MHz
–3 speed grade
10
—
750
(49)
MHz
—
10
—
325
MHz
–1 speed grade
600
—
1,600
MHz
–2 speed grade
600
—
1,434
MHz
–3 speed grade
600
—
1,280
(49)
(50)
Unit
MHz
MHz
fCLBW
PLL closed-loop bandwidth
—
0.5
—
10
MHz
tEINDUTY
Input clock or external feedback clock input
duty cycle
—
40
—
60
%
fOUT
Output frequency for internal clock (C counter)
–1 speed grade
—
—
1,100
MHz
–2 speed grade
—
—
900
MHz
–3 speed grade
—
—
750
MHz
–1 speed grade
—
—
800
MHz
–2 speed grade
—
—
720
MHz
–3 speed grade
—
—
650
fOUT_EXT
Output frequency for external clock output
MHz
continued...
(49)
This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
(50)
This specification is only applicable when the I/O PLL is instantiated with the IOPLL Intel FPGA IP core. For I/O PLL instantiated with
LVDS SERDES Intel FPGA IP core, PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core, External Memory Interfaces Intel
Stratix 10 FPGA IP core, and High Bandwidth Memory (HBM-2) Interface Intel FPGA IP core, the maximum fVCO is 1,250 MHz.
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
tOUTDUTY
Duty cycle for dedicated external clock output
(when set to 50%)
—
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
—
5
ns
fDYCONFIGCLK
Dynamic configuration clock for mgmt_clk and
—
—
—
200
MHz
scanclk
tLOCK
Time required to lock from end-of-device
configuration or deassertion of areset
—
—
—
1
ms
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-post-scale
counters/delays)
—
—
—
1
ms
tPLL_PSERR
Accuracy of PLL phase shift
—
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
—
10
—
—
ns
FREF ≥ 100 MHz
—
—
0.15
UI (p-p)
FREF < 100 MHz
—
—
±750
ps (p-p)
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
tINCCJ
(51)(52)
tOUTPJ_DC
Period jitter for dedicated clock output
tOUTCCJ_DC
tOUTPJ_IO
Input clock cycle-to-cycle jitter
(53)
Cycle-to-cycle jitter for dedicated clock output
Period jitter for clock output on the regular I/O
mUI (p-p)
continued...
(51)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with
jitter < 120 ps.
(52)
FREF is fIN/N, specification applies when N = 1.
(53)
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory
Output Clock Jitter Specifications for Intel Stratix 10 Devices table.
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Symbol
tOUTCCJ_IO
(53)
tCASC_OUTPJ_DC
Parameter
Condition
Min
Typ
Max
Unit
Cycle-to-cycle jitter for clock output on the
regular I/O
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
Period jitter for dedicated clock output in
cascaded PLLs through dedicated cascade path
and core clock fabric
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
Related Information
Memory Output Clock Jitter Specifications on page 45
Provides more information about the external memory interface clock output jitter specifications.
DSP Block Specifications
Table 30.
DSP Block Performance Specifications for Intel Stratix 10 Devices
Mode
Performance
Unit
–E1V, –I1V
–E2V, –E2L, –I2V, –
I2L, –C2L
–E3V, –E3X, –I3V, –
I3X
1,000
771
667
MHz
1,000
771
667
MHz
1,000
771
667
MHz
1,000
771
667
MHz
Fixed-point 18 × 19 systolic mode
1,000
771
667
MHz
Complex 18 × 19 multiplication mode
1,000
771
667
MHz
Floating point multiplication mode
750
579
500
MHz
Floating point adder or subtract mode
750
579
500
Fixed-point 18 × 19 multiplication mode
Fixed-point 27 × 27 multiplication mode
(54)
Fixed-point 18 × 18 multiplier adder mode
(54)
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode
(54)
MHz
continued...
(54)
When chainin or chainout is enabled, the performance specifications for the following speed grades are as follows:
• –E1V and –I1V: 750 MHz
• –E2V, –E2L, –I2V, –I2L, and –C2L: 578 MHz
• –E3V, –E3X, –I3V, and –I3X: 507 MHz
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Mode
Performance
Unit
–E1V, –I1V
–E2V, –E2L, –I2V, –
I2L, –C2L
–E3V, –E3X, –I3V, –
I3X
Floating point multiplier adder or subtract mode
750
579
500
MHz
Floating point multiplier accumulate mode
750
579
500
MHz
Floating point vector one mode
750
579
500
MHz
Floating point vector two mode
750
579
500
MHz
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block
clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Table 31.
Memory Block Performance Specifications for Intel Stratix 10 Devices
Memory
Mode
Performance
–E1V, –I1V
MLAB
Unit
Single port, all supported widths (×16/×32)
1,000
782
667
MHz
Simple dual-port, all supported widths (×16/×32)
1,000
782
667
MHz
550
450
400
MHz
ROM, all supported width (×16/×32)
1,000
782
667
MHz
Single-port, all supported widths
1,000
782
667
MHz
Simple dual-port, all supported widths
1,000
782
667
MHz
Simple dual-port, coherent read enabled
1,000
782
667
MHz
Simple dual-port with the read-during-write option set to
Old Data, all supported widths
800
640
560
MHz
Simple dual-port with ECC enabled, 512 × 32
600
480
420
Simple dual-port with read-during-write option
M20K Block
–E2V, –E2L, –I2V, – –E3V, –E3X, –I3V, –
I2L, –C2L
I3X
MHz
continued...
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Memory
Mode
Performance
–E1V, –I1V
eSRAM
Unit
Simple dual-port with ECC, optional pipeline registers
enabled, and fast write mode, 512 × 32
1,000
782
667
MHz
Simple dual-port with ECC and optional pipeline registers
enabled, with the read-during-write option set to Old
Data, 512 × 32
1,000
750
667
MHz
True dual port, all supported widths
600
500
420
MHz
Simple quad-port, all supported widths
600
480
420
MHz
ROM (single port), all supported widths
1,000
782
667
MHz
600
500
420
MHz
200–750
200–640
200–500
MHz
ROM (dual port), all supported widths
(55)(56)
–E2V, –E2L, –I2V, – –E3V, –E3X, –I3V, –
I2L, –C2L
I3X
Simple dual-port
Direct Interface Bus (DIB) Specifications
Table 32.
DIB Specifications for Intel Stratix 10 GX 10M Device
Mode
Maximum DIB Clock (MHz)
DIB-DIB Latency (ns)
—
2.5
ASYNC mode (1:1, 2:1, 4:1 TDM)
400
—
SYNC mode (1:1, 2:1, 4:1 TDM)
400
—
BYPASS mode (1:1)
Related Information
Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP User Guide
Provides more information about DIB.
(55)
The input clock source for eSRAM must not exceed 20 ps peak-to-peak, or 1.42 ps RMS at 1e–12 BER or 1.22 ps at 1e–16 BER.
(56)
For speed grade –3 devices, the following clock frequency ranges are not supported:
• 466.51 MHz – 499.99 MHz
• 233.26 MHz – 249.99 MHz
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Internal Temperature Sensing Diode Specifications
Table 33.
Internal Temperature Sensing Diode Specifications for Intel Stratix 10 Devices
Temperature Range
–40 to 125 °C
(57)
Accuracy
Offset Calibrated Option
Sampling Rate
Conversion Time
±5 °C
No
1 KSPS
< 1 ms
External Temperature Sensing Diode Specifications
Table 34.
External Temperature Sensing Diode Specifications for Intel Stratix 10 Devices
•
The typical value is at 25°C.
•
The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation. The characteristics can also apply to
two-currents temperature sensing chip implementation, except for the ideality factor for L-Tile and H-Tile.
•
Absolute accuracy is dependent on third-party external diode ADC and integration specifics.
Description
Min
Typ
Max
Unit
10
—
170
μA
Vbias, voltage across diode (core fabric, L-Tile, and H-Tile TSD)
0.35
—
0.9
V
Vbias, voltage across diode (E-Tile TSD)
0.56
—
0.82
V
Vbias, voltage across diode (P-Tile TSD)
0.56
—
0.87
V
Series resistance (core fabric TSD)
—
—
< 11
Ω
Series resistance (L-Tile and H-Tile TSD)
—
—
< 17
Ω
Series resistance (E-Tile TSD)
—
—
2000
—
—
Cycles
OCTUSRCLK
Clock required by OCT calibration blocks
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal transitions
in a bidirectional I/O buffer to dynamically switch between RS OCT and
RT OCT
—
8
—
Full-rate cycle
Figure 6.
Timing Diagram for on oe and dyn_term_ctrl Signals
RX
Tristate
Tristate
TX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
L-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices
Table 45.
Intel Stratix 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance
Symbol/Description
Transceiver Speed Grade
-1
Chip-to-chip
N/A
-2
26.6 Gbps
-3
17.4 Gbps
continued...
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Symbol/Description
Transceiver Speed Grade
-1
-2
8 channels per tile
Backplane
N/A
-3
(75)
12.5 Gbps
12.5 Gbps
Note:
Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and
non-bonded transceiver channels in Intel Stratix 10 L-Tile devices.
Table 46.
L-Tile ATX PLL Performance
Symbol/Description
Condition
Supported Output Frequency
tLOCK
(76)
tARESET
(78)
Note:
Required Reset Time
(77)
Maximum Frequency
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Unit
13.3
8.7
GHz
Minimum Frequency
500
MHz
Maximum Frequency
1
ms
25
Avalon Clock Cycles
—
TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI,
and DCD = 0.05 UI.
(75)
Refer to AN-778: Intel Stratix 10 Transceiver Usage for more details on channel selection requirements.
(76)
This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
(77)
You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL
pll_powerdown register.
(78)
You must assert pll_powerdown for a minimum of 25 cycles are required if you are using a 250-MHz AVMM clock.
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Table 47.
L-Tile fPLL Performance
Symbol/Description
Condition
Mode
Maximum datarate
(77)
(78)
12.5
Unit
Gbps
14.025
4.6
Transceiver - General
6
Transceiver - OTN, SDI Cascade
7
—
Gbps
1
ms
25
Avalon Clock Cycles
L-Tile CMU PLL Performance
Symbol/Description
Condition
Supported Output Frequency (VCO
frequency based)
tLOCK
Transceiver - General
Maximum Frequency
tARESET Required Reset Time
Table 48.
12.5
Transceiver - HDMI
Minimum datarate
(76)
Transceiver - HDMI
Transceiver - OTN, SDI Cascade
Supported Output Frequency
(VCO frequency based)
tLOCK
All Transceiver Speed Grades
(76)
tARESET Required Reset Time
(77) (78)
All Transceiver Speed Grades
Unit
Maximum Frequency
5.15625
GHz
Minimum Frequency
2.3
GHz
Maximum Frequency
1
ms
25
Avalon Clock Cycles
—
Related Information
AN-778: Intel Stratix 10 Transceiver Usage
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Transceiver Specifications for Intel Stratix 10 GX/SX L-Tile Devices
Table 49.
L-Tile Reference Clock Specifications
Symbol/Description
Condition
All Transceiver Speed Grades
Min
Supported I/O Standards
Dedicated reference clock pin
Typ
Unit
Max
CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency
(CMU PLL)
50
—
800
MHz
Input Reference Clock Frequency
(ATX PLL)
100
—
800
MHz
—
800
MHz
Input Reference Clock Frequency
(fPLL)
50
(79)
Rise time
20% to 80%
—
—
350
ps
Fall time
80% to 20%
—
—
350
ps
Duty cycle
—
45
—
55
%
Spread-spectrum modulating clock frequency
PCIe
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –0.5
—
%
On-chip termination resistors
—
—
100
—
Ω
Absolute VMAX
Dedicated reference clock pin
—
—
1.6
V
RX reference clock pin
—
—
1.2
V
Absolute VMIN
—
–0.4
—
—
V
Peak-to-peak differential input voltage
—
200
—
1600
mV
VICM (AC coupled)
VCCR_GXB =1.03 V
—
0
—
V
VICM (DC coupled)
HCSL I/O standard for PCIe
reference clock
250
—
550
mV
continued...
(79)
The fMIN is 25 MHz when the fPLL is used for the HDMI protocol.
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Symbol/Description
Condition
Transmitter REFCLK Phase Noise (800 MHz)
(80)
All Transceiver Speed Grades
Unit
Min
Typ
Max
100 Hz
—
—
–70
dBc/Hz
1 kHz
—
—
–90
dBc/Hz
10 kHz
—
—
–100
dBc/Hz
100 kHz
—
—
–110
dBc/Hz
≥ 1 MHz
—
—
–120
dBc/Hz
2.0 k ±1%
—
2.0 k ±1%
Ω
RREF
—
TSSC-MAX-PERIOD-SLEW
Max spread spectrum clocking
(SSC) df/dt
0.75
Note:
When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk
Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base
Specification Revision 3.0.
Table 50.
L-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network
Maximum Performance
(81)
Channel Span
Unit
ATX
fPLL
CMU
x1
17.4
12.5
10.3125
6 channels
Gbps
x6
17.4
12.5
N/A
6 channels
Gbps
12.5
N/A
2 banks up and 1 bank
down (total 24 channels)
or
Gbps
x24
17.4
(85)
continued...
(80)
To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise
at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).
(81)
The maximum data rate depends on speed grade.
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Clock Network
Maximum Performance
ATX
(81)
Channel Span
fPLL
Unit
CMU
2 banks down and 1 bank
up (total 24 channels)
GXT clock lines
26.6
N/A
N/A
4 GXT channels within the
same transceiver bank and
2 from the bank above or
2 from the bank below.
Gbps
(82)
Table 51.
L-Tile Receiver Specifications
Symbol/Description
Transceiver Speed Grade 3
Condition
Min
Typ
Unit
Max
Supported I/O Standards
—
High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute VMAX for a
receiver pin (83)
—
—
—
1.2
V
Absolute VMIN for a
receiver pin (83) (84)
—
-0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p)
VCCR_GXB = 1.03 V
—
—
2.0
V
Differential on-chip
termination resistors
85-Ω setting
—
85 ± 20%
—
Ω
(85)
continued...
(81)
The maximum data rate depends on speed grade.
(82)
If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above.
If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.
(83)
The device cannot tolerate prolonged operation at this absolute maximum.
(84)
A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.
(85)
Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For a given L-Tile, if there are channels
that need the higher power supply, tie all the channels on that side to the higher power supply.
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Symbol/Description
VICM (AC coupled)
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
100-Ω setting
—
100 ± 20%
—
Ω
VCCR_GXB = 1.03 V
—
700
—
mV
VCCR_GXB = 1.12 V
—
750
—
mV
(86)
—
—
—
1
ms
(87)
—
4
—
—
µs
tLTR
tLTD
tLTD_manual(88)
—
4
—
—
µs
tLTR_LTD_manual(89)
—
15
—
—
µs
Run Length
—
—
—
200
UI
-300
—
300
ppm
-1000
—
1000
ppm
CDR ppm tolerance
PCIe-only
All other protocols
(86)
tLTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset, or after the
CDR's calibration is complete.
(87)
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(88)
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high
when the CDR is functioning in the manual mode.
(89)
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes
high when the CDR is functioning in the manual mode.
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Table 52.
L-Tile Transmitter Specifications
Symbol/Description
Supported I/O Standards
Differential on-chip
termination resistors
VOCM (AC coupled)
Rise time
Fall time
(91)
(91)
Intra-differential pair skew
Table 53.
Condition
Transceiver Speed Grade 2 and 3
Min
—
Typ
High Speed Differential I/O
Unit
Max
(90)
—
85-Ω setting
—
85 ± 20%
—
Ω
100-Ω setting
—
100 ± 20%
—
Ω
VCCT_GXB = 1.03 V
—
515
—
mV
20% to 80%
20
—
130
ps
80% to 20%
20
—
130
ps
TX VCM = 0.5 V and slew
rate of 15 ps
—
—
15
(92)
ps
L-Tile Typical Transmitter VOD Settings
Symbol
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB
VOD Setting
(93)
VOD/VCCT_GXB Ratio
31
1.00
30
0.97
29
0.93
28
0.90
27
0.87
26
0.83
continued...
(90)
High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Stratix 10 L-/H-Tile transceivers.
(91)
The Intel Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional
mode.
(92)
This specification pertains to Hyper Memory Cube.
(93)
Intel recommends a VOD ranging from 31 to 17.
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Symbol
Table 54.
VOD Setting
(93)
VOD/VCCT_GXB Ratio
25
0.80
24
0.77
23
0.73
22
0.70
21
0.67
20
0.63
19
0.60
18
0.57
17
0.53
16
0.50
15
0.47
14
0.43
13
0.40
12
0.37
L-Tile Transmitter Channel-to-channel Skew Specifications
Mode
Channel Span
x6 Clock
Up to 6 channels in one bank
x24 Clock
Up to 24 channels in one tile
Maximum Skew
Unit
61
ps
500
(94)
(93)
Intel recommends a VOD ranging from 31 to 17.
(94)
500 ps is not supported for all configurations and depends upon the Master CGB placement.
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Table 55.
Transceiver Clocks Specifications for Intel Stratix 10 L-Tile Devices
Clock
Value
Unit
reconfig_clk
≤ 150
MHz
fixed_clk for the RX detect circuit
250 ± 20%
MHz
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
Related Information
•
External Configuration Clock Source Requirements on page 106
•
PLLs and Clock Networks
H-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices
Table 56.
Intel Stratix 10 GX/SX/MX/TX H-Tile Transmitter and Receiver Datarate Performance
Symbol
Description
Transceiver Speed Grade
-1
GX channels
Chip-to-chip and Backplane
GXT channels
Note:
(95)
-2
Chip-to-chip and Backplane
-3
17.4 Gbps
28.3 Gbps
(95)
26.6 Gbps
N/A
Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and
non-bonded transceiver channels in Intel Stratix 10 H-Tile devices.
Only four GXT channels per bank are supported for backplane applications operating at 28.3 Gbps.
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Table 57.
H-Tile ATX PLL Performance
Symbol/Description
Supported Output
Frequency
tLOCK
(96)
tARESET
(97)
Condition
Transceiver Speed Grade Transceiver Speed Grade Transceiver Speed Grade
1
2
3
Maximum Frequency
14.15
13.3
8.7
Unit
GHz
Minimum Frequency
500
MHz
Maximum Frequency
1
ms
25
Avalon Clock Cycles
—
Note:
TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI,
and DCD = 0.05 UI.
Table 58.
H-Tile Fractional PLL Performance
Symbol/Description
Condition
Maximum datarate
tARESET
(97)
Transceiver - HDMI
12.5
Transceiver - General
12.5
Transceiver - HDMI
Minimum datarate
tLOCK
All Transceiver Speed Grades
Transceiver - OTN, SDI Cascade
Supported Output Frequency
(VCO frequency based)
(96)
Mode
4.6
6
Transceiver - OTN, SDI Cascade
7
—
Gbps
14.025
Transceiver - General
Maximum Frequency
Unit
Gbps
1
ms
25
Avalon Clock Cycles
(96)
This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
(97)
You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL
pll_powerdown register.
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Table 59.
H-Tile CMU PLL Performance
Symbol/Description
Supported Output Frequency
tLOCK
(96)
tARESET
(97)
Condition
All Transceiver Speed Grades
Unit
Maximum Frequency
5.15625
GHz
Minimum Frequency
2.450
GHz
Maximum Frequency
1
ms
25
Avalon Clock Cycles
—
Transceiver Specifications for Intel Stratix 10 GX/SX H-Tile Devices
Table 60.
H-Tile Reference Clock Specifications
Symbol/Description
Supported I/O Standards
Condition
Min
Dedicated reference clock pin
Typ
Max
Unit
CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)
50
—
800
MHz
Input Reference Clock Frequency (ATX PLL)
100
—
800
MHz
(98)/50
—
800
MHz
Input Reference Clock Frequency (fPLL PLL)
25
Rise time
20% to 80%
—
—
350
ps
Fall time
80% to 20%
—
—
350
ps
Duty cycle
—
45
—
55
%
Spread-spectrum modulating clock frequency
PCIe
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –0.5
—
%
On-chip termination resistors
—
—
100
—
Ω
Absolute VMAX
Dedicated reference clock pin
—
—
1.6
V
RX reference clock pin
—
—
1.2
V
–0.4
—
—
Absolute VMIN
—
V
continued...
(98)
The 25 MHz is only available when HDMI is selected for fPLL protocol mode.
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Symbol/Description
Condition
Typ
Max
Unit
200
—
1600
mV
Peak-to-peak differential input voltage
—
VICM (AC coupled)
VCCR_GXB =1.03 V
—
0
—
V
VCCR_GXB = 1.12 V
—
0
—
V
250
—
550
mV
100 Hz
—
—
–70
dBc/Hz
1 kHz
—
—
–90
dBc/Hz
10 kHz
—
—
–100
dBc/Hz
100 kHz
—
—
–110
dBc/Hz
≥ 1 MHz
—
—
–120
dBc/Hz
RREF
—
—
2.0 k ±1%
—
Ω
TSSC-MAX-PERIOD-SLEW
Max SSC df/dt
VICM (DC coupled)
Transmitter REFCLK Phase Noise (800 MHz)
Note:
(99)
(100)
HCSL I/O standard for PCIe
reference clock
(99) (100)
0.75
When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk
Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base
Specification Revision 3.0.
To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise
at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).
A phase noise (PN) mask overrides the REFCLK noise.
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Table 61.
H-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network
Maximum Performance
(101)
Channel Span
Unit
ATX
fPLL
CMU
x1
17.4
12.5
10.3125
6 channels
Gbps
x6
17.4
12.5
N/A
6 channels
Gbps
12.5
N/A
2 banks up and 1 bank
down (total 24 channels)
or
2 banks down and 1 bank
up (total 24 channels)
Gbps
N/A
N/A
4 GXT channels within the
same transceiver bank and
2 from the bank above or
2 from the bank below.
Gbps
x24
17.4
GXT clock lines
(105)
28.3
(102)
Table 62.
H-Tile Receiver Specifications
Symbol/Description
Condition
All Transceiver Speed Grades
Min
Typ
Unit
Max
Supported I/O Standards
—
High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute VMAX for a
receiver pin (103)
—
—
—
1.2
V
Absolute VMIN for a
receiver pin (104)
—
-0.4
—
—
V
continued...
(101)
The maximum data rate depends on speed grade.
(102)
If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above.
If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.
(103)
The device cannot tolerate prolonged operation at this absolute maximum.
(104)
A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.
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Symbol/Description
All Transceiver Speed Grades
Condition
Min
Typ
Max
Unit
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before device
configuration
—
—
—
2.0
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration
VCCR_GXB = 1.03 V, 1.12 V
(105), (106)
—
—
2.0
V
85-Ω setting
—
85 ± 20%
—
Ω
Differential on-chip
termination resistors
VICM (AC coupled)
tLTR
(107)
tLTD
(108)
tLTD_manual
(109)
tLTR_LTD_manual
(110)
100-Ω setting
—
100 ± 20%
—
Ω
VCCR_GXB = 1.03 V
(106)
—
700
—
mV
VCCR_GXB = 1.12 V
(106)
—
750
—
mV
—
—
—
1
ms
—
4
—
—
µs
—
4
—
—
µs
—
15
—
—
µs
continued...
(105)
Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
H-Tile as the channels that required 1.12 V ± 20 mV, VCCR_GXB = 1.12 V ± 20 mV.
(106)
For GXT channels, VCCR_GXB must be 1.12 V. For GX channels, VCCR_GXB must be 1.03 V. VCCR_GXB must be 1.12 V for the transceiver
on the same H-Tile when using GX and GXT channels together.
(107)
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset or after CDR
calibration is completed.
(108)
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(109)
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high
when the CDR is functioning in the manual mode.
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Symbol/Description
Run Length
—
PCIe-only
CDR ppm tolerance
Table 63.
All Transceiver Speed Grades
Condition
All other protocols
Unit
Min
Typ
Max
—
—
200
UI
-300
—
300
ppm
-1000
—
1000
ppm
H-Tile Transmitter Specifications
The data in this table is preliminary.
Symbol/Description
Supported I/O Standards
Differential on-chip
termination resistors
VOCM (AC coupled)
VOCM (AC coupled)
VOCM (DC coupled)
(113)
VOCM (DC coupled)
(113)
Transceiver Speed Grade 3
Condition
Min
—
Typ
High Speed Differential I/O
85-Ω setting
100-Ω setting
Unit
Max
(111)
—
—
85 ± 20%
—
Ω
—
100 ± 20%
—
Ω
VCCT_GXB = 1.03 V
(112)
—
515
—
mV
VCCT_GXB = 1.12 V
(112)
—
560
—
mV
VCCT_GXB = 1.03 V
(112)
—
515
—
mV
VCCT_GXB = 1.12 V
(112)
—
560
—
mV
continued...
(110)
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes
high when the CDR is functioning in the manual mode.
(111)
High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Stratix 10 transceivers.
(112)
For GXT channels, VCCT_GXB must be 1.12 V. For GX channels, VCCT_GXB must be 1.03 V. VCCT_GXB must be 1.12 V when using GX and
GXT channels together within the same H-Tile.
(113)
DC coupling specifications are pending silicon characterization.
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Symbol/Description
Rise time
Fall time
(114)
(114)
Intra-differential pair skew
Table 64.
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
20% to 80%
20
—
130
ps
80% to 20%
20
—
130
ps
TX VCM = 0.5 V and slew
rate of 15 ps
—
—
15
(115)
ps
H-Tile Typical Transmitter VOD Settings
Symbol
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB
VOD Setting
(116)
VOD/VCCT_GXB Ratio
31
1.00
30
0.97
29
0.93
28
0.90
27
0.87
26
0.83
25
0.80
24
0.77
23
0.73
22
0.70
21
0.67
20
0.63
continued...
(114)
The Intel Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional
mode.
(115)
This specification pertains to Hyper Memory Cube.
(116)
Intel recommends a VOD ranging from 31 to 17.
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Symbol
Table 65.
VOD Setting
VOD/VCCT_GXB Ratio
19
0.60
18
0.57
17
0.53
16
0.50
15
0.47
14
0.43
13
0.40
12
0.37
H-Tile Transmitter Channel-to-channel Skew Specifications
Mode
Channel Span
x6 Clock
Up to 6 channels in one bank
x24 Clock
Table 66.
(116)
Up to 24 channels in one bank
Maximum Skew
Unit
61
ps
500
(117)
ps
Transceiver Clocks Specifications for Intel Stratix 10 GX/SX H-Tile Devices
Clock
Value
Unit
reconfig_clk
≤ 150
MHz
fixed_clk for the RX detect circuit
250 ± 20%
MHz
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
Related Information
•
External Configuration Clock Source Requirements on page 106
•
PLLs and Clock Networks
(116)
Intel recommends a VOD ranging from 31 to 17.
(117)
500 ps is not supported for all configurations and depends upon the Master CGB placement.
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E-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 E-Tile Devices
Table 67.
E-Tile Transmitter and Receiver Data Rate Performance Specifications
Symbol/Description
Supported data rate
Condition
(118)
Transceiver Speed Grade
NRZ
PAM4
-1
-2
-3
28.9 Gbps
28.3 Gbps
17.4 Gbps
56 Gbps
32 Gbps
57.8 Gbps
(119)
Transceiver Reference Clock Specifications
Table 68.
E-Tile Reference Clock LVPECL DC Electrical Characteristics
Symbol
Refclk Parameter
Minimum
Typical
Maximum
Unit
VTT
Termination Voltage (2.5V
compliant)
0.4
0.5
0.6
V
VTT
Termination Voltage (3.3V
compliant)
1.04
1.3
1.56
V
RTT
Termination Resistor
40
50
60
Ohm
VDIFF
Differential Voltage
0.4
0.8
1.2
V
VCM
Input Common Mode
Voltage (2.5V compliant,
no internal termination
resistor)
VDIFF/2
VCCCLK_GXE-VDIFF/2
V
continued...
(118)
The supported data rate is for chip-to-chip and backplane links.
(119)
Two channels are combined to support up to 57.8 Gbps.
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Table 69.
Symbol
Refclk Parameter
Minimum
Typical
Maximum
Unit
VCM
Input Common Mode
Voltage (2.5V compliant,
internal termination
resistor)
VCCCLK_GXE - 1.6
VCCCLK_GXE - 1.3
VCCCLK_GXE - 1.0
V
VCM
Input Common Mode
Voltage (3.3V compliant,
no internal termination
resistor)
VDIFF/2
VCCCLK_GXE-VDIFF/2
V
VCM
Input Common Mode
Voltage (3.3V compliant,
internal termination
resistor)
1.4
2
2.6
V
E-Tile Reference Clock Electrical & Jitter Requirements
Parameter
Condition
Minimum
Typical
Maximum
Unit
Frequency
-
125
156.25
700
MHz
Frequency Tolerance
-
-100
100
PPM
Clock Duty Cycle
-
45
55
%
Rise & Fall Times
20% - 80%
40
Phase Jitter
12 KHz - 20 MHz
Phase Noise
(120)
(120)
50
300
ps
0.5
ps rms
10 KHz
-130
dBc/Hz
100 KHz
-138
dBc/Hz
500 KHz
-138
dBc/Hz
3 MHz
-140
dBc/Hz
10 MHz
-144
dBc/Hz
20 MHz
-146
dBc/Hz
0.375
The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of
156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) =
REFCLK phase noise at 156.25 MHz + 20*log10(f/156.25)
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Transmitter Specifications for Intel Stratix 10 E-Tile Devices
Table 70.
E-Tile Transmitter Specifications
Symbol/Description
Transmitter differential
output voltage peak-topeak
Condition
Minimum
No precursor/postcursor
de-emphasis
Transmitter common mode
voltage
Typical
Maximum
Unit
0.965
V
VCCRT_GXE/2
V
Receiver Specifications for Intel Stratix 10 E-Tile Devices
Table 71.
E-Tile Receiver Specifications
Symbol/Description
Condition
Minimum
Typical
Maximum
Supported I/O Standards
—
Absolute VMAX for a
receiver pin(122)
NRZ
—
VCCH_GXE + 0.3
—
V
PAM4
—
VCCH_GXE
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before/after
device configuration(122)
—
VCM (AC coupled)(121)
NRZ
(122)
LVPECL
Unit
—
1.2
GND
—
V
VCCH_GXE
V
continued...
(121)
These values use internal AC-coupling. External AC-coupling capacitors are required when the RX input common mode voltage is
beyond the range mentioned in this table (for PAM4 or NRZ). When using external AC-coupling capacitors, the RX termination is set
to VCCH_GXE. When using internal AC-coupling capacitors, set the RX termination floating. The external AC-coupling capacitor has a
typical value of at least 100 nF.
(122)
To support Hot Swap with E-tile, ensure the following:
• RX inputs have external AC coupling capacitors of at least 100 nF.
• The absolute voltage applied to the RX+ and RX- pins should not exceed ±300 mV (for a total of 600 mV p-p) (single ended).
• The total differential voltage (combination of RX+/RX-) should not exceed 1,200 mV.
• The transceiver termination selection must be external AC coupling (during mission mode).
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Symbol/Description
Condition
PAM4
Typical
Maximum
Unit
GND + 0.3
—
VCCH_GXE – 0.3
V
symbols
—
—
—
100(124)
DC input impedance
—
40
—
60
Ω
DC differential input
impedance
—
80
100
120
Ω
Powered down DC input
impedance
Receiver pin impedance
when the receiver
termination is powered
down
100k
—
—
Ω
Differential termination
From DC to 100 MHz
80
100
120
Ω
PPM tolerance
Allowed frequency
mismatch between
REFCLK and RX data
—
—
750
ppm
Receiver run
length(123)
Minimum
P-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 DX P-Tile Devices
Table 72.
P-Tile Transmitter and Receiver Data Rate Performance
For specification status, see the Data Sheet Status table
Symbol/Description
Supported data
rate(125)
Condition
PCIe
Gen 1
Gen 2
Gen 3
Gen 4
Unit
2.5
5
8
16
Gbps
(123)
No additional transition density requirements apply.
(124)
The incoming data must be statistically DC-balanced.
(125)
Intel Ultra Path Interconnect (Intel UPI) supports chip-to-chip and low-loss cable up to 10.4 Gbps.
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Table 73.
P-Tile PLLA Performance
For specification status, see the Data Sheet Status table
Symbol/Description
VCO frequency
Condition
PCIe
Intel UPI
(126)
Min
Typ
Max
Unit
—
5
—
GHz
—
5.2
—
GHz
PLL bandwidth
(BWTX_PKG_PLL1)(127)
PCIe 2.5 GT/s
1.5
—
22
MHz
PCIe 5.0 GT/s
8
—
16
MHz
PLL bandwidth
(BWTX_PKG_PLL2)(127)
PCIe 5.0 GT/s
5
—
16
MHz
PLL peaking (PKGTX_PLL1)
PCIe 2.5 GT/s
—
—
3
dB
PCIe 5.0 GT/s
—
—
3
dB
PCIe 5.0 GT/s
1
—
—
dB
PLL peaking
(PKGTX_PLL2)(127)
Table 74.
P-Tile PLLB Performance
For specification status, see the Data Sheet Status table. PLLB is not used for the UPI mode.
Symbol/Description
Condition
Min
Typ
Max
Unit
VCO frequency
PCIe
—
8
—
GHz
PLL bandwidth (BWTXPKG_PLL1)(128)
PCIe 8.0 GT/s
2
—
4
MHz
PCIe 16.0 GT/s
2
—
4
MHz
continued...
(126)
The maximum VCO frequency supported now for PLLA in Intel UPI mode is 5.2 GHz. This will increase to 5.6 GHz in future for Intel
UPI mode operating at 11.2 Gbps.
(127)
The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.
(128)
The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.
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Symbol/Description
PLL bandwidth (BWTXPKG_PLL2)(128)
PLL peaking (PKGTXPLL1)(128)
PLL peaking (PKGTXPLL2)(128)
Condition
Min
Typ
Max
Unit
PCIe 8.0 GT/s
2
—
5
MHz
PCIe 16.0 GT/s
2
—
5
MHz
PCIe 8.0 GT/s
—
—
2
dB
PCIe 16.0 GT/s
—
—
2
dB
PCIe 8.0 GT/s
—
—
1
dB
PCIe 16.0 GT/s
—
—
1
dB
Min
Typ
Max
Unit
Transceiver Reference Clock Specifications
Table 75.
P-Tile Reference Clock Specifications
For specification status, see the Data Sheet Status table
Symbol/Description
Condition
Supported I/O standards
—
Input reference clock
frequency (129)
—
HCSL
—
99.97
100
100.03
MHz
(130)
PCIe
0.6
—
4
V/ns
rate(130)
PCIe
0.6
—
4
V/ns
Duty cycle
PCIe
40
—
60
%
Spread-spectrum
modulating clock
frequency
—
30
—
33
kHz
Spread-spectrum
downspread
—
–0.5
—
0
%
Rising edge rate
Falling edge
continued...
(129)
This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications
in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express Base Specification Revision 4.0.
(130)
Measured from -150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential
zero crossing.
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Symbol/Description
Condition
Min
Typ
Max
Unit
Absolute VMAX
—
—
—
1.15
V
Absolute VMIN
—
—
—
–0.3
V
Peak-to-peak differential
input voltage
—
300
—
1,500
mV
VICM (DC coupled)
HCSL I/O standard for
PCIe reference clock
250
—
550
mV
Cycle to cycle jitter
(TCCJITTER) (131)
PCIe
—
—
150
ps
TSSC-MAX-PERIOD-SLEW
Max SSC df/dt
—
—
1,250
ppm/us
Related Information
PCI Express Base Specification Revision 4.0
Transmitter Specification for Intel Stratix 10 DX P-Tile Devices
Table 76.
P-Tile Transmitter Specifications
For specification status, see the Data Sheet Status table. AC coupling capacitors required for PCIe links are placed on the board external to the Intel Stratix 10
device. Intel UPI links are DC coupled and don't require AC coupling capacitors.
Symbol/Description
Condition
Supported I/O standards
—
Differential on-chip
termination resistors
PCIe
Differential peak-to-peak
voltage for full swing
Min
Typ
Max
High Speed Differential I/O
Unit
—
80
—
120
Ω
PCIe 2.5 GT/s
800
—
1,100
mV
PCIe 5.0 GT/s
800
—
1,100
mV
PCIe 8.0 GT/s
800
—
1,100
mV
PCIe 16.0 GT/s
800
—
1,100
mV
continued...
(131)
For common reference clock architecture, follow the jitter limit specified in the PCI Express* Card Electromechanical Specification for
2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express Base
Specification Revision 3.0, and the Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express Base Specification Revision 4.0.
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Symbol/Description
Condition
Min
Typ
Max
Unit
250
—
—
mV
Differential peak-to-peak
voltage during EIEOS
PCIe 8.0 GT/s and 16.0
GT/s
Lane-to-lane output skew
PCIe 2.5 GT/s
—
—
2.5
ns
PCIe 5.0 GT/s
—
—
2
ns
PCIe 8.0 GT/s
—
—
1.5
ns
PCIe 16.0 GT/s
—
—
1.25
ns
—
—
5
UI
Typ
Max
Unit
Intel UPI
(132)
Receiver Specifications for Intel Stratix 10 DX P-Tile Devices
Table 77.
P-Tile Receiver Specifications
For specification status, see the Data Sheet Status table
Symbol/Description
Supported I/O Standards
Peak-to-peak differential
input voltage VID (diff p-p)
Condition
Min
—
High Speed Differential I/O
—
PCIe 2.5 GT/s
(133)
0.175
—
1.2
V
PCIe 5.0 GT/s
(133)
0.1
—
1.2
V
PCIe 8.0 GT/s
PCIe 16.0 GT/s
25
(134)
15
(134)
—
—
—
(135)
mV
—
(135)
mV
continued...
(132)
Delay of any of Intel UPI 20 data lanes relative to other data lanes.
(133)
Voltage shown for PCIe 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
(134)
For PCIe at 2.5 and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe 8.0 GT/s
and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx
package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
(135)
The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe Express Base
Specification Rev. 4.0 for the generator (TX) launch voltage value.
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Symbol/Description
Condition
Typ
Max
Unit
Differential on-chip
termination resistors
—
80
—
120
Ω
(136)
—
167.3
169
170.7
Ω
—
2.772
2.8
2.828
kΩ
RESREF
RREF
(136)
Connecting RESREF at 169 Ω calibrates PCIe channel on-chip termination to 85 Ω.
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HPS Performance Specifications
This section provides hard processor system (HPS) specifications and timing for Intel Stratix 10 devices.
HPS Clock Performance
Table 78.
Maximum HPS Clock Frequencies for Intel Stratix 10 Devices
Performance
–E1V, –I1V
–E2V, –I2V
–E3V, –I3V
–E2L, –I2L(139)
–E3X, –I3X
(139)
VCCL_HPS (V)
MPU Frequency (MHz)
SDRAM Interconnect
Frequency(137) (MHz)
L3 Interconnect Frequency
(MHz)
SmartVID
1,200
533
400
0.9
1,200
533
400
0.94
1,350
533
SmartVID
1,000
467
400
0.9
1,000
467
400
0.94
1,000
467
400
SmartVID
800
400
333
0.9
800
400
333
0.94
800
400
400
0.9
1200
467
400
0.94
1,350
467
0.9
1,200
400
0.94
1,350
400
400
400
(138)
400
400
(137)
This frequency is for the hmc_free_clk, which is half the frequency of the HPS external memory interface (EMIF).
(138)
If MPU frequency is 1,350 MHz, the L3 interconnect frequency is 385 MHz because of the clock ratios.
(139)
Note that VCCL_HPS can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.
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(138)
(138)
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Related Information
External Memory Interface Spec Estimator
Provides the specific details of the maximum allowed SDRAM operating frequency.
HPS Internal Oscillator Frequency
Table 79.
HPS Internal Oscillator Frequency for Intel Stratix 10 Devices
Description
Internal Oscillator Frequency
Intel® Stratix® 10 Device Datasheet
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Min
Typ
Max
Unit
100
200
300
MHz
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HPS PLL Specifications
HPS PLL Input Requirements
Table 80.
HPS PLL Input Requirements for Intel Stratix 10 Devices
The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for information
about assigning this pin.
Description
Min
Typ
Max
Unit
Clock input range
25
—
125
MHz
Clock input accuracy
—
—
50
PPM
Clock input duty cycle
45
50
55
%
HPS PLL Performance
Table 81.
HPS PLL Performance for Intel Stratix 10 Devices
Description
Min
Max
Unit
Main PLL VCO output
—
3000
MHz
Peripheral PLL VCO output
—
3000
MHz
h2f_user0_clk
(140)
—
500
MHz
h2f_user1_clk
(140)
—
500
MHz
(140)
The HPS PLL provides this clock to the FPGA fabric.
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HPS SPI Timing Characteristics
Table 82.
SPI Master Timing Requirements for Intel Stratix 10 Devices
You can adjust the input delay timing by programming the rx_sample_dly register.
Symbol
Tspi_ref_clk
Description
The period of the SPI internal reference clock, sourced from
Min
Typ
Max
Unit
—
—
ns
16.67
—
—
ns
2.5
l4_main_clk
Tclk
SPIM_CLK clock period
Tdutycycle
SPIM_CLK duty cycle
45
50
55
%
Tck_jitter
SPIM_CLK output jitter
—
—
2
%
Tdio
Master-out slave-in (MOSI) output skew
–3
—
2
ns
(1.5 × Tclk) – 2
—
—
ns
Tclk – 2
—
—
ns
4.5 –
(rx_sample_dly
× T spi_ref_clk) (143)
—
—
ns
1.3 +
(rx_sample_dly×
Tspi_ref_clk)
—
—
ns
Tdssfrst
Tdsslst
Tsu
Th
(141)
(141)
(142)
(142)
SPI_SS_N asserted to first SPIM_CLK edge
Last SPIM_CLK edge to SPI_SS_N deasserted
SPIM_MISO setup time with respect to SPIM_CLK capture edge
Input hold in respect to SPIM_CLK capture edge
(141)
SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
(142)
The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge
depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising
edge.
(143)
Valid values of rx_sample_dly range from 1 to 64 (units are in T
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spi_ref_clk
steps).
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Figure 7.
SPI Master Output Timing Diagram
scph* = 0
Tdssfrst
SPI_SS
Tdsslst
Tdio (max)
Tdio (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
OUT0
OUT1
OUTn
SPI_MISO
scph* = 1
SPI_SS
Tdssfrst
Tdio (max)
Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
OUT0
OUT1
OUTn
SPI_MISO
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Figure 8.
SPI Master Input Timing Diagram
scph* = 0
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
Tsu
SPI_MISO
IN0
Th
IN1
INn
scph* = 1
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
Tsu
SPI_MISO
IN0
IN1
Th
INn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Table 83.
SPI Slave Timing Requirements for Intel Stratix 10 Devices
Symbol
Tspi_ref_clk
Description
The period of the SPI internal reference clock, sourced from
Min
2.5
l4_main_clk
Typ
Max
Unit
—
—
ns
Tclk
SPIM_CLK clock period
30
—
—
ns
Tdutycycle
SPIM_CLK duty cycle
45
50
55
%
Td
Master-in slave-out (MISO) output skew
(2 × Tspi_ref_clk) +
3
—
(3 × Tspi_ref_clk) +
11
ns
Tsu
Master-out slave-in (MOSI) setup time
4
—
—
ns
Th
Master-out slave-in (MOSI) hold time
9
—
—
ns
Tsuss
SPI_SS_N asserted to first SPIM_CLK edge
Tspi_ref_clk + 4
—
—
ns
Thss
Last SPIM_CLK edge to SPI_SS_N deasserted
Tspi_ref_clk + 4
—
—
ns
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Figure 9.
SPI Slave Output Timing Diagram
scph* = 0
Td (max)
SPI_SS
Td (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
OUT0
OUT1
OUTn
SPI_MOSI
scph* = 1
Td (max)
SPI_SS
Td (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
OUT0
OUT1
OUTn
SPI_MOSI
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Figure 10.
SPI Slave Input Timing Diagram
scph* = 0
Tsuss
SPI_SS
Thss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
IN0
scph* = 1
SPI_SS
Th
Ts
IN1
INn
Tsuss
Thss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
Ts
IN0
IN1
Th
INn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Related Information
SPI Controller
For more information about the SPI controller and timing, refer to the SPI Controller chapter in the Intel Stratix 10 Hard
Processor System Technical Reference Manual
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HPS SD/MMC Timing Characteristics
Table 84.
HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Stratix 10 Devices
These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.
Symbol
Min
Typ
Max
Unit
2500
—
—
ns
SDMMC_CCLK clock period (SDR12)
40
—
—
ns
SDMMC_CCLK clock period (SDR25)
20
—
—
ns
Tdutycycle
SDMMC_CCLK duty cycle
45
50
55
%
Tsdmmc_cclk_jitter
SDMMC_CCLK output jitter
—
—
2
%
Tsdmmc_clk
Internal reference clock before division by 4
5
—
—
ns
Tsdmmc_clk ×
drvsel/2
—
3 + (Tsdmmc_clk ×
drvsel/2)
ns
6 – (Tsdmmc_clk ×
smplsel/2)
—
—
ns
0.5 + (Tsdmmc_clk ×
smplsel/2)
—
—
ns
Tsdmmc_cclk
Description
SDMMC_CCLK clock period (Identification mode)
Td
SDMMC_CMD/SDMMC_DATA[7:0] output delay
Tsu
SDMMC_CMD/SDMMC_DATA[7:0] input setup
Th
SDMMC_CMD/SDMMC_DATA[7:0] input hold
(144)
(145)
(145)
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at
1.8 V at power on.
Note:
SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC
interface.
(144)
When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz
for example, the output delay time is 7.5 to 10.5 ns.
(145)
When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200
MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.
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Figure 11.
SD/MMC Timing Diagram
SDMMC_CCLK
Td
SDMMC_CMD and SDMMC_DATA (Out)
Command/Data Out
TSU
Th
SDMMC_CMD and SDMMC_DATA (In)
Command/Data In
Related Information
SD/MMC Controller
For more information about the SD/MMC controller and timing, refer to the SD/MMC Controller chapter in the Intel Stratix
10 Hard Processor System Technical Reference Manual
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HPS USB UPLI Timing Characteristics
Table 85.
HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for
Intel Stratix 10 Devices
Min
Typ
Max
Unit
Tusb_clk
Symbol
USB_CLK clock period
—
16.667
—
ns
Td
Clock to USB_STP/USB_DATA[7:0] output delay
2
—
7
ns
Tsu
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
4
—
—
ns
Th
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
1
—
—
ns
Figure 12.
Description
USB ULPI Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
USB_DIR and USB_NXT
Note:
To PHY
From PHY
TSU
Th
The USB interface supports single data rate (SDR) timing only.
Related Information
USB 2.0 OTG Controller
For more information about the USB 2.0 OTG controller and timing, refer to the USB 2.0 OTG Controller chapter in the
Intel Stratix 10 Hard Processor System Technical Reference Manual
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HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 86.
Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tclk (1000Base-T)
TX_CLK clock period
—
8
—
ns
Tclk (100Base-T)
TX_CLK clock period
—
40
—
ns
Tclk (10Base-T)
TX_CLK clock period
—
400
—
ns
Tdutycycle (1000Base-T)
TX_CLK duty cycle
45
50
55
%
Tdutycycle(10/100Base-T)
TX_CLK duty cycle
40
50
60
%
–0.5
—
0.5
ns
Min
Typ
Max
Unit
ns
Td
(146)
TXD/TX_CTL to TX_CLK output skew
(147)
Figure 13.
RGMII TX and RMII TX Timing Diagram
TX_CLK
TX_D[3:0]
D0
D1
Td
TX_CTL
Table 87.
RGMII RX Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
Tclk (1000Base-T)
RX_CLK clock period
—
8
—
Tclk (100Base-T)
RX_CLK clock period
—
40
—
ns
continued...
(146)
Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
(147)
If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O
programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
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Symbol
Description
Min
Typ
Max
Unit
Tclk (10Base-T)
RX_CLK clock period
—
400
—
ns
Tdutycycle(1000Base-T)
RX_CLK duty cycle
45
50
55
%
Tdutycycle(10/100Base-T)
RX_CLK duty cycle
40
50
60
%
Tsu
RX_D/RX_CTL to RX_CLK setup time
1
—
—
ns
RX_CLK to RX_D/RX_CTL hold time
1
—
—
ns
Th
(148)
Figure 14.
RGMII RX and RMII RX Timing Diagram
RX_CLK
TSU
RX_D[3:0]
Th
D0
D1
RX_CTL
Table 88.
Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel Stratix 10 Devices
Symbol
Min
Typ
Max
Unit
REF_CLK clock period, sourced by HPS TX_CLK
—
20
—
ns
REF_CLK clock period, sourced by external clock source
—
20
—
ns
Tdutycycle_int
Clock duty cycle, REF_CLK sourced by TX_CLK
35
50
65
%
Tdutycycle_ext
Clock duty cycle, REF_CLK sourced by external clock source
35
50
65
%
Min
Typ
Max
Unit
2
—
10
ns
Tclk
Table 89.
RMII TX Timing Requirements for Intel Stratix 10 Devices
Symbol
Td
(148)
Description
Description
TX_CLK to TXD/TX_CTL output data delay
If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK
by 1.5-2 ns, using the HPS I/O programmable delay.
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Table 90.
RMII RX Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tsu
RX_D/RX_CTL setup time
2
—
—
ns
Th
RX_D/RX_CTL hold time
1
—
—
ns
Table 91.
Management Data Input/Output (MDIO) Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
400
—
—
ns
Tclk
MDC clock period
Td
MDC to MDIO output data delay
10
—
300
ns
Tsu
Setup time for MDIO data
10
—
—
ns
Th
Hold time for MDIO data
0
—
—
ns
Figure 15.
MDIO Timing Diagram
MDC
Td
MDIO_OUT
Dout0
Dout1
TSU
MDIO_IN
Th
Din0
Related Information
Ethernet Media Access Controller
For more information about the Ethernet MAC and timing, refer to the Ethernet Media Access Controller chapter in the
Intel Stratix 10 Hard Processor System Technical Reference Manual
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HPS I2C Timing Characteristics
HPS I2C Timing Requirements for Intel Stratix 10 Devices
Table 92.
Symbol
Tclk
TLOW
Standard Mode
(149)
(152)
TSU;DAT
THD;DAT
TVD;DAT and
TVD;ACK (156)
Unit
Max
Min
Max
10
—
2.5
—
μs
I2C clock output jitter
—
2
—
SCL high period
(150)
SCL low period
Setup time for serial data line (SDA) data to SCL
(155)
Fast Mode
Min
Serial clock (SCL) clock period
Tclk_jitter
THIGH
Description
4
—
(153)
4.7
—
2
%
0.6
(151)
—
μs
1.3
(154)
—
μs
0.25
—
0.1
—
μs
0
3.15
0
0.6
μs
Hold time for SCL to SDA data
SCL to SDA output data delay
—
3.45
(157)
—
0.9
(158)
μs
continued...
(149)
You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
(150)
The recommended minimum setting for ic_ss_scl_hcnt is 440.
(151)
The recommended minimum setting for ic_fs_scl_hcnt is 71.
(152)
You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
(153)
The recommended minimum setting for ic_ss_scl_lcnt is 500.
(154)
The recommended minimum setting for ic_fs_scl_lcnt is 141.
(155)
THD;DAT is affected by the rise and fall time.
(156)
TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
(157)
Use maximum SDA_HOLD = 240 to be within the specification.
(158)
Use maximum SDA_HOLD = 60 to be within the specification.
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Symbol
Description
TSU;STA
Setup time for a repeated start condition
THD;STA
Hold time for a repeated start condition
TSU;STO
Setup time for a stop condition
TBUF
SDA high pulse duration between STOP and START
Fast Mode
Unit
Min
Max
Min
Max
4.7
—
0.6
—
μs
4
—
0.6
—
μs
4
—
0.6
—
μs
4.7
—
1.3
—
μs
Tscl:r
(159)
SCL rise time
—
1000
20
300
ns
Tscl:f
(159)
SCL fall time
—
300
6.54
300
ns
Tsda:r
(159)
SDA rise time
—
1000
20
300
ns
Tsda:f
(159)
SDA fall time
—
300
6.54
300
ns
(159)
Rise and fall time parameters vary depending on external factors such as the characteristics of the IO driver, pull-up resistor value,
and total capacitance on the transmission line.
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Figure 16.
I2C Timing Diagram
tf
tr
tSU;DAT
70%
30%
SDA
tHD;DAT
tf
tHIGH
tr
tVD;DAT
70%
30%
SCL
tHD;STA
Tclk
tLOW
tBUF
70%
30%
SDA
tSU;STA
tHD;STA
tVD;ACK
tSU;STO
70%
30%
SCL
Related Information
I2C Controller
For more information about the I2C controller and timing, refer to the I2C Controller chapter in the Intel Stratix 10 Hard
Processor System Technical Reference Manual
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HPS NAND Timing Characteristics
Table 93.
HPS NAND ONFI 1.0 Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
TWP
(160)
Write enable pulse width
TWH
(160)
Write enable hold time
TRP
(160)
Read enable pulse width
TREH
(160)
Read enable hold time
TCLS
(160)
Command latch enable to write enable setup time
TCLH
(160)
Command latch enable to write enable hold time
TCS
(160)
Chip enable to write enable setup time
TCH
(160)
Chip enable to write enable hold time
TALS
(160)
Address latch enable to write enable setup time
TALH
(160)
Max
Unit
10
—
ns
7
—
ns
10
—
ns
7
—
ns
10
—
ns
5
—
ns
15
—
ns
5
—
ns
10
—
ns
Address latch enable to write enable hold time
5
—
ns
TDS
(160)
Data to write enable setup time
7
—
ns
TDH
(160)
Data to write enable hold time
5
—
ns
TWB
(160)
Write enable high to R/B low
—
200
ns
TCEA
Chip enable to data access time
—
100
ns
TREA
Read enable to data access time
—
40
ns
TRHZ
Read enable to data high impedance
—
200
ns
TRR
Ready to read enable low
20
—
ns
(160)
This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical
Reference Manual for more information about software-programmable timing in the NAND flash controller.
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Figure 17.
NAND Command Latch Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
IO0-7
R/B
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tDH
Command
tWB
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Figure 18.
NAND Address Latch Timing Diagram
tCLS
CLE
tCS
CE
tWP
WE
ALE
IO0-7
Intel® Stratix® 10 Device Datasheet
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tWH
tALS
tALH
tDS
tDH
Address
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Figure 19.
NAND Data Output Cycle Timing Diagram
tCLH
CLE
tCH
CE
tWP
WE
tWH
tALS
ALE
tDS
tDH
tDS
DOUT 0
IOx
Figure 20.
tWP
tWP
tDH
tDS
DOUT 1
tDH
DOUT n
NAND Data Input Cycle Timing Diagram
tCEA
CE
tRP
tRP
RE
tREH
tRR
R/B
IOx
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tRP
tREA
tRHZ
DIN 0
tREA
tRHZ
DIN 1
tREA
tRHZ
DIN n
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Figure 21.
NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
CE
tRP
RE
tREH
tRR
tREA
R/B
tREA
tRHZ
IOx
DIN 0
DIN 1
DIN n
tCEA
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Figure 22.
NAND Read Status Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tCEA
CE
WE
RE
IO0-7
tWP
tRHZ
tDS
tDH
70h
Status
tREA
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Figure 23.
NAND Read Status Enhanced Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tALH
tWP
tALS
tWH
tALH
ALE
RE
tDS
IO0-7
tREA
tDH
78h
R1
R2
R3
tRHZ
Status
Related Information
NAND Flash Controller
Refer to the NAND Flash Controller chapter in the Intel Stratix 10 Hard Processor System Technical Reference Manual for
more information about the NAND flash controller and timing, particularly software-programmable timing.
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HPS Trace Timing Characteristics
Table 94.
Trace Timing Requirements for Intel Stratix 10 Devices
To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace
interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.
Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed
possible. Refer to your trace module datasheet for termination recommendations.
Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing
relationship with the HPS programmable I/O delay.
Symbol
Description
Min
Typ
Max
Unit
6.667
—
—
ns
Tclk
Trace clock period
Tclk_jitter
Trace clock output jitter
—
—
2
%
Tdutycycle
Trace clock maximum duty cycle
45
50
55
%
Td
Tclk to D0–D15 output data delay
0
—
1.8
ns
Figure 24.
Trace Timing Diagram
Clock (DDR)
Trace Data (DDR)
Td
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HPS GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock
frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable
GPIO pulse width is 62.5 µs (at 32 kHz).
If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal
is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If
the external signal is more than two clock cycles, the external signal is not filtered.
Related Information
General-Purpose I/O Interface
For more information about the GPIO interface and timing, refer to the General-Purpose I/O Interface chapter in the Intel
Stratix 10 Hard Processor System Technical Reference Manual
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HPS JTAG Timing Characteristics
Table 95.
HPS JTAG Timing Requirements for Intel Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
41.66
—
—
ns
tJCP
TCK clock period
tJCH
TCK clock high time
20
—
—
ns
tJCL
TCK clock low time
20
—
—
ns
tJPSU (TDI)
TDI JTAG port setup time
5
—
—
ns
tJPSU (TMS)
TMS JTAG port setup time
5
—
—
ns
tJPH
JTAG port hold time
0
—
—
ns
tJPCO
JTAG port clock to output
0
—
8
ns
tJPZX
JTAG port high impedance to valid output
—
—
10
ns
tJPXZ
JTAG port valid output to high impedance
—
—
10
ns
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HPS Programmable I/O Timing Characteristics
Table 96.
HPS Programmable I/O Delay for Intel Stratix 10 Device
Programmable
Delay
Description
Min
Typ
Max
Unit
0, 2, 4, 6, 8, 10,
12, 14, 16, 18, 20,
22, 24, 26, 28, 30
No delay enabled
—
0
—
ps
1
Delay Step 1
—
120
—
ps
3
Delay Step 2
—
240
—
ps
5
Delay Step 3
—
360
—
ps
7
Delay Step 4
—
480
—
ps
9
Delay Step 5
—
600
—
ps
11
Delay Step 6
—
720
—
ps
13
Delay Step 7
—
840
—
ps
15
Delay Step 8
—
960
—
ps
17
Delay Step 9
—
1080
—
ps
19
Delay Step 10
—
1200
—
ps
21
Delay Step 11
—
1320
—
ps
23
Delay Step 12
—
1440
—
ps
25
Delay Step 13
—
1560
—
ps
27
Delay Step 14
—
1680
—
ps
29
Delay Step 15
—
1800
—
ps
31
Delay Step 16
—
1920
—
ps
You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0
through 47).
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Configuration Specifications
General Configuration Timing Specifications
Table 97.
General Configuration Timing Specifications for Intel Stratix 10 Devices
The data in this table is preliminary.
Symbol
Description
Requirement
Min
Max
20
tCF12ST1
nCONFIG high to nSTATUS high
—
tCF02ST0
nCONFIG low to nSTATUS low when device is configured
—
tST0
nSTATUS low pulse during configuration error
tCD2UM
(162)
CONF_DONE high to user mode
Unit
400
ms
(161)
ms
0.5
10
ms
—
5
ms
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR
circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device
is ready to begin configuration.
Table 98.
POR Delay Specification for Intel Stratix 10 Devices
POR Delay
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32
AS (Fast mode)
Minimum
Maximum
Unit
12
20
ms
2
6.5
ms
(161)
The duration may be up to 1000 ms if using device security feature.
(162)
This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.
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External Configuration Clock Source Requirements
Table 99.
External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements
Description
Clock input frequency
(163)
External Clock Source
Min
Typ
Powered by VCCIO_SDM
Max
25/100/125
Unit
MHz
Clock input jitter tolerance
—
—
2
%
Clock input duty cycle
45
50
55
%
JTAG Configuration Timing
Table 100.
JTAG Timing Parameters and Values for Intel Stratix 10 Devices
Symbol
Description
Unit
Minimum
Maximum
tJCP
TCK clock period
30
—
ns
tJCH
TCK clock high time
14
—
ns
tJCL
TCK clock low time
14
—
ns
tJPSU (TDI)
TDI JTAG port setup time
2
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
JTAG port clock to output
—
7
ns
tJPZX
JTAG port high impedance to valid output
—
14
ns
tJPXZ
JTAG port valid output to high impedance
—
14
ns
Note:
(163)
P-tile supports IEEE 1149.6 JTAG standard at maximum speed of 1 MHz only if you use EXTEST_PULSE/EXTEST_TRAIN AC
JTAG instruction.
The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency
on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus Prime software. Other frequencies in the
range are not supported.
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Requirement
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Figure 25.
JTAG Timing Diagram
TMS
TDI
tJCH
TCK
tJCP
tJCL
tJPZX
tJPSU
tJPH
tJPXZ
tJPCO
TDO
AS Configuration Timing
Table 101.
AS Timing Parameters for Intel Stratix 10 Devices
Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. The maximum tolerance for skew between
nCSO and AS_CLK is recommended to be less than 200 ps. The tolerance for skew between AS_CLK to AS_DATA must be within 0 ps – 400 ps.
Symbol
Minimum
Typical
Maximum
Unit
AS_CLK clock period
—
7.52
—
ns
Tdutycycle
AS_CLK duty cycle
45
50
55
%
Tdcsfrs
AS_nCSO[3:0] asserted to first AS_CLK edge
Tclk
(164)
Tdcslst
Description
Last AS_CLK edge to AS_nCSO[3:0] deasserted
4.21
(165)
5.18
(165)
—
—
7.50
8
(165)
(165)
ns
ns
continued...
(164)
AS_CLK fmax has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash
devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash
setup/hold time specifications and Intel Stratix 10 AS timing specifications in the Intel Stratix 10 Device Datasheet. For AS using
multiple serial flash devices, refer to the Intel Stratix 10 Configuration User Guide for the recommended AS_CLK frequency and
maximum board loading.
(165)
AS operating at maximum clock frequency = 133 MHz. The delay is larger when operating at AS clock frequency lower than 133 MHz.
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Symbol
Tdo
(166)
Text_delay
(169)
Tdcsb2b
Description
Minimum
Typical
Maximum
Unit
–1.5
—
1.31
ns
Total external propagation delay on AS signals
0
—
15
ns
Minimum delay of slave select deassertion between two back-to-back
transfers
1
—
—
AS_CLK
AS_DATA[3:0] output delay
(167)(168)
(166)
Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver,
transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation.
Use the following equations to do static timing analysis for flash setup/hold timing.
• To analyze flash setup time, Tsu = AS_CLK/2 – Tdo(max) + Tbd_clk – Tbd_data(max)
• To analyze flash hold time, Tho = AS_CLK/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
(167)
Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum
and maximum specification values.
Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
(168)
Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.
(169)
Text_delay specification is based on AS_CLK = 133 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to
the Intel Stratix 10 Configuration User Guide.
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Figure 26.
AS Configuration Serial Output Timing Diagram
Tdcsfrs Tdo (min)
Tdcslst
Tdo (max)
nCSO
AS_CLK
OUT0
AS_DATA
Figure 27.
OUT1
OUTn
AS Configuration Serial Input Timing Diagram
nCSO
AS_CLK
Text_delay
AS_DATA
IN0
IN1
INn
Related Information
AS_CLK, Intel Stratix 10 Configuration User Guide
Provides the supported configuration clock source and AS_CLK frequencies in Intel Stratix 10 devices.
Avalon®-ST Configuration Timing
Table 102.
Avalon®-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Stratix 10 Devices
Symbol
Description
Minimum
Maximum
Unit
tACLKH
AVST_CLK high time
3.6
—
ns
tACLKL
AVST_CLK low time
3.6
—
ns
tACLKP
AVST_CLK period
8
—
ns
continued...
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Symbol
tADSU
tADH
(170)
(170)
Description
AVST_DATA setup time before rising edge of AVST_CLK
AVST_DATA hold time after rising edge of AVST_CLK
tAVSU
AVST_VALID setup time before rising edge of AVST_CLK
tAVDH
AVST_VALID hold time after rising edge of AVST_CLK
(170)
Maximum
Unit
5.5
—
ns
0
—
ns
5.5
—
ns
0
—
ns
Data sampled by the FPGA (sink) at the next rising clock edge.
Intel® Stratix® 10 Device Datasheet
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Figure 28.
Avalon®-ST Configuration Timing Diagram
tACLKP
tACLKH
tACLKL
AVSTx8_CLK (1)
or AVST_CLK
AVST_READY (2)
tAVSU
tAVDH
tADSU
tADH
AVSTx8_VALID (3), (4)
or AVST_VALID
AVSTx8_DATA[7:0] (5), (6)
AVST_DATA[15:0]
AVST_data[31:0]]
must deassert
within 6 cycles
data0 data1 data2 data3
Notes:
1. For Avalon-ST x16 and x32, this signal is AVST_CLK. These clocks must be running throughout the configuration
(until CONF_DONE goes high).
2. AVST_READY is valid only when nSTATUS is high. AVST_READY is an asynchronous signal to AVSTx8_CLK/AVST_CLK.
3. For Avalon-ST x16 and x32, this signal is AVST_VALID.
4. The waveforms shows the interface signals with a host which uses ready latency =2. The AVSTx8_VALID signal is delayed from
AVST_READY signal by 2 clock cycles.
5. For Avalon-ST x16 and x32, this signal is AVST_DATA[15:0] and AVST_DATA[31:0] respectively.
6. Host may send up to 6 more data after AVST_READY has de-asserted.
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Configuration Bit Stream Sizes
Table 103.
Configuration Bit Stream Sizes for Intel Stratix 10 Devices
This table shows the estimated configuration bit stream sizes of the EPCQ-L serial configuration device or external flash size before design compilation. The sizes
are for compressed bit stream. The actual sizes may vary based on your design. The actual sizes may be equal or smaller than the bit stream sizes in this table.
256 Mb quad SPI flash size is adequate to store the Intel Stratix 10 periphery image.
Variant
Product Line
Compressed Configuration Bit Stream Size (Mbits)
Intel Stratix 10 GX, SX, TX, MX,
and DX
GX 400, SX 400, TX 400
79
GX 650, SX 650
127
GX 850, GX 1100, SX 850, SX 1100, TX 850, TX 1100, DX 1100
226
GX 1660, GX 2110, TX 1650, TX 2100, MX 1650, MX 2100, DX
2100
379
GX 1650, GX 2100, GX 2500, GX 2800, SX 1650, SX 2100, SX
2500, SX 2800, TX 2500, TX 2800, DX 2800
577
GX 10M
654(171)
I/O Timing
I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing
analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script.
The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the
design after you complete place-and-route.
Related Information
AN 775: I/O Timing Information Generation Guidelines
Provides the techniques to generate I/O timing information using the Intel Quartus Prime software.
(171)
Intel Stratix 10 GX 10M FPGA has two high-density Intel Stratix 10 GX FPGA core fabric die. This value is the bit stream size for one
core fabric die.
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Programmable IOE Delay
Table 104.
Programmable IOE Delay for Intel Stratix 10 Devices
For the exact values for each setting, use the latest version of the Intel Quartus Prime software. The values in the table show the delay of programmable IOE
delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings).
Programmable IOE delay settings are only applicable for I/O buffers and do not apply for any other delay elements in the PHY Lite for Parallel Interfaces Intel
Stratix 10 FPGA IP core.
Parameter
(172)
Maximum Offset
Minimum
Offset (173)
Fast Model
Slow Model
Unit
Industrial/
Extended
–E1V, –I1V
–E2V, –I2V
–E3V, –I3V
Input Delay Chain
(INPUT_DELAY_CHAIN)
63
0
1.575
2.310
2.352
2.654
ns
Output Delay Chain
(OUTPUT_DELAY_CHAIN)
15
0
0.387
0.523
0.560
0.629
ns
Glossary
Table 105.
Glossary
Term
Differential I/O Standards
Definition
Receiver Input Waveforms
continued...
(172)
You can set this value in the Intel Quartus Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting
in the Assignment Name column.
(173)
Minimum offset does not include the intrinsic delay.
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Term
Definition
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p-n=0V
VID
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p-n=0V
VOD
fHSCLK
I/O PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications
JTAG Timing Specifications:
continued...
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Term
Definition
TMS
TDI
t JCH
t JCP
t JCL
t JPSU
tJPH
TCK
tJPZX
t JPXZ
tJPCO
TDO
RL
Receiver differential input discrete resistor (external to the Intel Stratix 10 device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold
times determine the ideal strobe position in the sampling window, as shown:
Bit Time
0.5 x TCCS
Single-ended voltage referenced I/O standard
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
continued...
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Term
Definition
V CCIO
V OH
V IH(AC)
V REF
V IH(DC)
V IL(DC)
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%).
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO
Period jitter on the GPIO driven by a PLL.
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
tRISE
Signal low-to-high transition time (20–80%).
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
VCM(DC)
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
VICM(DC)
VCM(DC) DC Common mode input voltage.
VID
Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
continued...
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Term
Definition
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC)
High-level AC input voltage.
VIH(DC)
High-level DC input voltage.
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL(AC)
Low-level AC input voltage.
VIL(DC)
Low-level DC input voltage.
VOCM
Output Common mode voltage—The common mode of the differential signal at the transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a
differential transmission line at the transmitter.
VSWING
Differential input voltage.
VOX
Output differential cross point voltage.
VIX(AC)
Crossing point of differential signal
VCCIO
Crossing Point of
Differential Signal
VSWING
VIX
Ground
W
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High-speed I/O block—Clock Boost Factor.
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Document Revision History for the Intel Stratix 10 Device Datasheet
Document
Version
2020.12.24
Changes
•
•
•
•
•
•
•
2020.07.08
Added Intel Stratix 10 NX and DX 2100 devices in the following sections:
— Absolute Maximum Ratings for Intel Stratix 10 Devices table
— Recommended Operating Conditions for Intel Stratix 10 Devices table
— Performance Specifications of the HBM2 Interface in Intel Stratix 10 MX, NX, and SD 2100 Devices table
— HBM2 Interface Performance section
Updated the E-Tile Receiver Specifications table.
— Updated the Absolute VMAX and VCM specifications.
— Updated the note to VCM.
— Added note to Absolute VMAX and VID (diff p-p).
Updated the P-Tile PLLA Performance table.
— Added PLL bandwidth (BWTX-PKG_PLL1) and PLL peaking (PKGTX-PLL1) specifications for PCIe 5.0 GT/s.
— Updated PLL peaking (PKGTX-PLL2) specifications.
— Added note on PLL bandwidth and PLL peaking.
Updated the P-Tile PLLB Performance table.
— Added PLL bandwidth (BWTX-PKG_PLL2) and PLL peaking (PKGTX-PLL2) specifications.
— Added note on PLL bandwidth and PLL peaking.
Updated the spread-spectrum downspread, absolute VMAX, and absolute VMIN specifications in the P-Tile Reference Clock Specifications table.
Updated the differential peak-to-peak voltage for full swing specifications in the P-Tile Transmitter Specifications table.
Removed VICM (AC coupled) specifications from the P-Tile Receiver Specifications table.
•
•
•
•
Added –C2L speed grade in the Intel Stratix 10 Device Grades and Speed Grades Supported table.
Added a note to mention that the specifications for 1SG065 and 1SX065 devices will be available in a future release.
Added TJ and TSTG specifications for Intel Stratix 10 GX 10M device in the Absolute Maximum Ratings for Intel Stratix 10 Devices table.
Updated the Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Added VCC, VCCP, and TJ specifications for Intel Stratix 10 GX 10M device.
— Removed the note on HPS_PORSEL from tRAMP. HPS_PORSEL pin is not available for Intel Stratix 10 devices.
•
•
•
Updated II_3.3VIO specifications in the I/O Pin Leakage Current for Intel Stratix 10 Devices table.
Removed specifications for VCCIO = 3.3 ±5% and VCCIO3C = 3.0 ±5% in the Internal Weak Pull-Up Resistor Values for Intel Stratix 10 Devices table.
Added –C2L speed grade in the following tables:
— Clock Tree Performance for Intel Stratix 10 Devices
— DSP Block Performance Specifications for Intel Stratix 10 Devices
— Memory Block Performance Specifications for Intel Stratix 10 Devices
Added the DIB Specifications for Intel Stratix 10 GX 10M Device table.
Added –C2L speed grade in the High-Speed I/O Specifications for Intel Stratix 10 Devices table. Added note to transmitter and receiver –2 speed
grade maximum specifications for SERDES factor J = 4 to 10.
•
•
continued...
Intel® Stratix® 10 Device Datasheet
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Document
Version
2020.05.22
Changes
•
•
•
•
•
•
Updated DDR-T specifications in the Memory Standards Supported by the Soft Memory Controller for Intel Stratix 10 Devices table.
Added note to Text_delay in the AS Timing Parameters for Intel Stratix 10 Devices.
Added Intel Stratix 10 GX 10M device in the Configuration Bit Stream Sizes for Intel Stratix 10 Devices table.
Removed SD/MMC configuration mode specifications.
Removed Maximum Configuration Time Estimation specifications.
Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator (PTC).
•
Changed Intel Stratix 10 DX status from Preliminary to Final in the Datasheet Status for Intel Stratix 10 Devices table. Added a note to mention that
specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
Added DDR-T specifications in the Memory Standards Supported by the Soft Memory Controller for Intel Stratix 10 Devices table.
Updated the specifications in the P-Tile Transmitter and Receiver Data Rate Performance table.
Updated VCO frequency in the following tables:
— P-Tile PLLA Performance
— P-Tile PLLB Performance
Updated the note to Input Reference Clock Frequency in the P-Tile Reference Clock Specifications table.
Updated the P-Tile Transmitter Specifications table.
— Updated the Differential peak-to-peak voltage for full swing specifications.
— Removed the Differential peak-to-peak voltage for reduced swing and Differential peak-to-peak voltage during EIEOS for reduce swing
specifications.
Updated the P-Tile Receiver Specifications table.
— Added VID (diff p-p) PCIe 8.0 GT/s and PCIe 16.0 GT/s specifications.
— Added a note to RESREF.
— Added RREF specifications.
•
•
•
•
•
•
2020.03.10
•
•
•
•
•
•
•
Mentioned that the specifications for 1SG040HF35 and 1SX040HF35 devices are still preliminary in the Datasheet Status for Intel Stratix 10 Devices
table.
Updated the Absolute Maximum Ratings for Intel Stratix 10 Devices table.
— Added VCCIO3C and VCCIO3D specifications.
— Updated the description for VCCIO.
— Added VI specifications for 3.3 V I/O.
Added a new table: Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices (for 3.3 V I/O).
Updated the Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Added VCCIO3C, VCCIO3D, and VI (for 3.3 V I/O) specifications.
— Updated the description for VCCIO.
— Updated note to TJ specification for Industrial.
Added II_3.3VIO specifications in the I/O Pin Leakage Current for Intel Stratix 10 Devices table.
Added CIO_3.3VIO specifications in the Pin Capacitance for Intel Stratix 10 Devices table.
Added RPU specifications for 3.3 V I/O in the Internal Weak Pull-Up Resistor Values for Intel Stratix 10 Devices table.
continued...
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Document
Version
Changes
•
•
•
•
2019.12.02
•
•
•
•
2019.09.19
•
•
•
Added 3.3 V LVTTL, 3.3 V LVCMOS, 3.0 V LVTTL, and 3.0 V LVCMOS specifications for 1SG040HF35 or 1SX040HF35 devices I/O bank 3C only in the
Single-Ended I/O Standards Specifications for Intel Stratix 10 Devices table.
Updated the description in the DPA Lock Time Specifications for Intel Stratix 10 Devices table.
Added a note to VICM (AC coupled) in the E-Tile Receiver Specifications table.
Added specifications for Intel Stratix 10 TX 400 devices and updated specifications for Intel Stratix 10 GX 400, SX 400, GX 1650, GX 2100, SX 1650,
and SX 2100 devices in the following tables:
— Configuration Bit Stream Sizes for Intel Stratix 10 Devices
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (Avalon®-ST)
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (AS and SD/MMC)
Updated the note to VOD in the Differential I/O Standards Specifications for Intel Stratix 10 Devices table.
Added description on PCIe applications in the Maximum Configuration Time Estimation for Intel Stratix 10 Devices tables.
Added specifications for Intel Stratix 10 DX devices in the following tables:
— External Temperature Sensing Diode Specifications for Intel Stratix 10 Devices
— Configuration Bit Stream Sizes for Intel Stratix 10 Devices
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (Avalon-ST)
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (AS and SD/MMC)
— Programmable IOE Delay for Intel Stratix 10 Devices
Updated RESREF specification in the P-Tile Receiver Specifications table.
Added Intel Stratix 10 DX as Preliminary in the Datasheet Status for Intel Stratix 10 Devices table.
Updated the definition for the V suffix.
Updated the Absolute Maximum Ratings for Intel Stratix 10 Devices table.
— Added E-tile specific power supplies VCCRT_GXE, VCCRTPLL_GXE, VCCH_GXE, and VCCCLK_GXE.
— Added P-tile specific power supplies VCCRT_GXP, VCCFUSE_GXP, VCCH_GXP, and VCCCLK_GXP.
— Updated the description for VCCPT.
— Added specifications for the following power rails:
• VCCPLLDIG_SDM
• VCCPLL_SDM
• VCCFUSEWR_SDM
• VCCADC
• VCCIO_UIB
• VCCM_WORD
— Updated the maximum specifications for VI.
continued...
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Document
Version
Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated the Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Updated the note on PMBus for VCC and VCCP.
— Updated the note for VCCBAT.
— Updated the description for VCCPT.
— Updated VCCIO specifications.
— Added VCCIO3V specifications.
— Updated the maximum specifications for VI.
— Updated the note on HBM2 for Intel Stratix 10 MX devices for TJ specification.
Updated VCCL_HPS and VCCPLLDIG_HPS specifications and note for SmartVID in the HPS Power Supply Operating Conditions for Intel Stratix 10 Devices
table.
Added description on internal weak pull-down resistor in the Internal Weak Pull-Up Resistor section.
Split M20K block—ROM, all supported widths specifications into single port and dual port in the Memory Block Performance Specifications for Intel
Stratix 10 Devices table.
Updated the External Temperature Sensing Diode Specifications for Intel Stratix 10 Devices table.
— Added Ibias and Vbias specifications for E-Tile TSD.
— Updated Ibias specifications for core fabric, L-Tile, and H-Tile TSD.
— Updated series resistance for core fabric, L-Tile, H-Tile, and E-Tile TSD.
— Updated diode ideality factor for L-Tile, H-Tile, and E-Tile TSD.
Updated the minimum data rates for the receiver fHSDRDPA in the High-Speed I/O Specifications for Intel Stratix 10 Devices table.
Removed figure: DPA Lock Time Specifications with DPA PLL Calibration Enabled.
Updated maximum data transition value and added a note in the DPA Lock Time Specifications for Intel Stratix 10 Devices table.
Updated the QDR II SRAM specifications in the Memory Standards Supported by the Soft Memory Controller for Intel Stratix 10 Devices table.
Updated the note in the HBM2 Interface Performance section.
Updated the supported output frequency in the H-Tile ATX PLL Performance table.
Updated the input reference clock frequency (fPLL) and its note in the H-Tile Reference Clock Specification table.
Removed a note from the H-Tile Receiver Specification table.
Added a note for VOCM (DC coupled) in the H-Tile Transmitter Specification table.
Updated E-Tile Transmitter and Receiver Data Rate Performance Specifications table.
Updated the E-Tile Receiver Specifications table.
— Added Supported I/O Standards specifications.
— Added Absolute VMAX for a receiver pin specifications.
— Added Maximum peak-to-peak differential input voltage VID specifications.
— Added VICM(AC coupled) specifications.
— Removed the Electrical Idle detection voltage specifications.
continued...
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Document
Version
Changes
•
•
•
•
•
•
•
•
•
•
2019.02.25
•
Added P-Tile Transceiver Performance Specification section.
— Added P-Tile Transmitter and Receiver Data Rate Performance table.
— Added P-Tile PLLA Performance table.
— Added P-Tile PLLB Performance table.
— Added P-Tile Reference Clock Specifications table.
— Added P-Tile Transmitter Specifications table.
— Added P-Tile Receiver Specifications table.
Removed description in the HPS GPIO Interface section. Statement removed: Any pulses shorter than 2 debounce clock cycles are filtered by the GPIO
peripheral.
Updated tCF12ST1, tCF02ST0, tST0, and tCD2UM in the General Configuration Timing Specifications for Intel Stratix 10 Devices table.
Added a note on P-tile support to the JTAG Timing Parameters and Values for Intel Stratix 10 Devices table.
Updated the AS Timing Parameters for Intel Stratix 10 Devices table.
— Added notes to Tclk, Tdo, and Text_delay.
— Updated the description for Tdo.
— Removed Text_skew specifications from the datasheet. This specifications are documented in the Intel Stratix 10 Configuration User Guide.
Updated the Configuration Bit Stream Sizes for Intel Stratix 10 Devices table.
— Removed the IOCSR Bit Stream Size (Mbits) specifications.
— Removed unsupported Intel Stratix 10 devices: MX 1100, GX 4500, GX 5500, SX 4500, and SX 5500.
— Added Intel Stratix 10 devices: TX 850, TX 1100, GX 1660, and GX 2110.
— Updated the Compressed Configuration Bit Stream Size specifications.
— Added note on quad SPI flash.
Updated the Maximum Configuration Time Estimation tables.
— Removed non-critical JTAG configuration mode specifications.
— Removed unsupported configuration mode: AS ×1
— Removed unsupported Intel Stratix 10 devices: MX 1100, GX 4500, GX 5500, SX 4500, and SX 5500.
— Added Intel Stratix 10 devices: TX 850, TX 1100, GX 1660, and GX 2110.
Updated the Programmable IOE Delay for Intel Stratix 10 Devices table.
— Corrected the speed grade to –E1V.
— Updated the specifications for Fast Model and Slow Model.
Updated definition for VIX(AC) in the Glossary.
Added description to the following tables to state that the data in the table is preliminary.
— H-Tile Transmitter Specifications
— General Configuration Timing Specifications for Intel Stratix 10 Devices
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (Avalon-ST)
— Maximum Configuration Time Estimation for Intel Stratix 10 Devices (AS and SD/MMC)
Changed the variants datasheet status from Preliminary to Final in the Datasheet Status for Intel Stratix 10 Devices table.
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2019.02.05
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Updated the maximum specifications for VI (for 3 V I/O) from 3.6 V to 3.8 V.
Added the LVPECL DC electrical characteristics table for the E-Tile transceiver reference clock.
Added the electrical and jitter requirements table for the E-Tile transceiver reference clock.
Merged the minimum, typical and maximum specifications for the E-Tile transmitter common mode voltage into one specification.
Updated the NRZ data rate for the E-Tile transceivers.
Added the performance specifications for the HBM2 interface in the Intel Stratix 10 MX devices.
Updated the temperature specifications for the HBM2 interface in Intel Stratix 10 devices.
Updated the Intel Quartus Prime Assignment Names in the Programmable IOE Delay for Intel Stratix 10 Devices table.
2018.10.25
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Updated the description for the X suffix.
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Removed the description on VREFP_ADC and VREFN_ADC I/O pins in the Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices
(for LVDS I/O) table.
Updated the Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Updated the VCC and VCCP specifications for –3X speed grade.
— Removed Pulse-Width Modulation (PWM) from the note to VCC and VCCP for SmartVID devices.
— Updated the note to VCCBAT.
— Removed the VREFP_ADC specifications.
Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile
Devices in a Non-Bonded Configuration" table.
Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile
Devices in a Bonded Configuration" table.
Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX H-Tile
Devices in a Bonded Configuration" table.
Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX H-Tile
Devices in a Bonded Configuration" table.
Updated the footnote specifying pll_powerdown minimum assertion cycles in the "Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices"
section.
Added a noise mask specification column and updated the symbol names in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10
TX/MX E-Tile Devices" table.
Added a note about TX jitter specifications for the SerialLite III protocol in the "Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices"
section.
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Removed the Transmitter REFCLK Phase Jitter (100 MHz) specification from the "L-Tile Reference Clock Specifications" table.
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Added a note about PCI Express reference clock phase jitter specifications to the "Transceiver Specifications for Intel Stratix 10 GX/SX L-Tile Devices"
section
Changed the GXT channel specification for chip-to-chip, -3 speed grade devices in the "Intel Stratix 10 GX/SX H-Tile Transmitter and Receiver Datarate
Performance" table.
Added a note about TX jitter specifications for the SerialLite III protocol in the "Transceiver Performance for Intel Stratix 10 GX/SX H-Tile Devices"
section.
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Removed the Transmitter REFCLK Phase Jitter (100 MHz) specification from the "H-Tile Reference Clock Specifications" table.
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Added a note about PCI Express reference clock phase jitter specifications to the "Transceiver Specifications for Intel Stratix 10 GX/SX H-Tile Devices"
section
Removed PWM from the note to VCCL_HPS and VCCPLLDIG_HPS for SmartVID devices in the HPS Power Supply Operating Conditions for Intel Stratix 10
Devices table.
Updated the I/O PLL Specifications for Intel Stratix 10 Devices table.
— Updated the maximum fVCO specifications for –3 speed grade.
— Updated the description for tCASC_OUTPJ_DC.
Added series resistance and diode ideality factor parameters for E-Tile TSD in the External Temperature Sensing Diode Specifications for Intel Stratix
10 Devices table.
Added a note on half rate support for DDR3 SDRAM in the Memory Standards Supported by the Hard Memory Controller for Intel Stratix 10 Devices
table.
Updated the Memory Standards Supported by the Soft Memory Controller for Intel Stratix 10 Devices table.
— Added a note to RLDRAM 3
— Updated QDR IV SRAM specification
— Added a note on full rate support for QDR II SRAM
Removed the DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Intel Stratix 10 Devices table.
Updated the description in the Memory Output Clock Jitter Specifications section.
Updated the Maximum HPS Clock Frequencies for Intel Stratix 10 Devices table.
— Updated the MPU frequency for VCCL_HPS = 0.94 V.
— Added note to L3 Interconnect Frequency for VCCL_HPS = 0.94 V for –E1V, –I1V, –E2L, –I2L, –E3X, and –I3X.
Updated the specifications in the HPS Internal Oscillator Frequency for Intel Stratix 10 Devices table.
Updated the specifications for Tspi_ref_clk, Tdssfrst, and Tdsslst in the SPI Master Timing Requirements for Intel Stratix 10 Devices table.
Updated the specifications for Tspi_ref_clk and Th in the SPI Slave Timing Requirements for Intel Stratix 10 Devices table.
Updated the HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Stratix 10 Devices table.
— Updated the description for Tsdmmc_clk.
— Removed the note to the minimum and maximum specifications for Td.
— Updated the reference clock in the note for Td and Tsu.
Updated Tclk specifications in the following tables:
— Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Stratix 10 Devices
— RGMII RX Timing Requirements for Intel Stratix 10 Devices
— Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel Stratix 10 Devices
— Management Data Input/Output (MDIO) Timing Requirements for Intel Stratix 10 Devices
Updated Td specification in the Management Data Input/Output (MDIO) Timing Requirements for Intel Stratix 10 Devices table.
Updated the title for the following diagrams:
— RGMII TX and RMII TX Timing Diagram
— RGMII RX and RMII RX Timing Diagram
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Removed tCF02ST0 specifications for Device Security Feature (Zeroization) ON in the General Configuration Timing Specifications for Intel Stratix 10
Devices table.
Updated tJCP specification in the JTAG Timing Parameters and Values for Intel Stratix 10 Devices table.
Added Text_skew specifications in the AS Timing Parameters for Intel Stratix 10 Devices table.
Updated the Avalon-ST Configuration Timing Diagram.
Mentioned that the SD/MMC configuration scheme will be available in a future release of the Intel Quartus Prime software.SD/MMC Timing Parameters
for Intel Stratix 10 Devices table.
Updated the Maximum Configuration Time Estimation section.
— Clarify the maximum configuration time.
— Updated the note to AVST ×8, AVST ×16, and AVST ×32.
Removed Preliminary tags for all table. Refer to the Data Status for Intel Stratix 10 Devices table for the data status for each variant.
2018.07.13
Corrected the typical values for VCC and VCCP in the Recommended Operating Conditions for Intel Stratix 10 Devices table.
2018.07.12
Made the following changes:
• Updated the Absolute Maximum Ratings for Intel Stratix 10 Devices table.
— Updated the maximum values for VCCIO (for LVDS I/O), VCCIO_HPS, and VCCIO_SDM from 2.46 V to 2.19 V.
— Updated the maximum value for VI (for LVDS I/O) from 2.5 V to 2.19 V.
— Updated the IOUT specifications.
• Updated the Maximum Allowed Overshoot and Undershoot Voltage section.
— Updated the overshoot and undershoot values in the description.
— Updated the specifications in the Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices (for LVDS I/O) and Maximum Allowed
Overshoot During Transitions for Intel Stratix 10 Devices (for LVDS I/O) tables.
— Updated the voltages in the Intel Stratix 10 Devices Overshoot Duration diagram.
• Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a NonBonded Configuration" table.
• Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Bonded
Configuration" table.
• Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Non-Bonded
Configuration" table.
• Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Bonded
Configuration" table.
• Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10
GX/SX L-Tile Devices in a Non-Bonded Configuration" table.
• Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10
GX/SX L-Tile Devices in a Bonded Configuration" table.
• Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10
GX/SX H-Tile Devices in a Non-Bonded Configuration" table.
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Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10
GX/SX H-Tile Devices in a Bonded Configuration" table.
Updated VCC, VCCP, VCCBAT, VCCIO, VCCM_WORD, and VI specifications in the Recommended Operating Conditions for Intel Stratix 10 Devices table.
Updated VCCL_HPS and VCCPLLDIG_HPS specifications in the HPS Power Supply Operating Conditions for Intel Stratix 10 Devices table.
Updated the OCT Without Calibration Resistance Tolerance Specifications for Intel Stratix 10 Devices table.
Removed Equation for OCT Variation Without Recalibration.
Added pin capacitance specifications.
Added the resistance tolerance for RPU in the Internal Weak Pull-Up Resistor Values for Intel Stratix 10 Devices table.
Updated the VCCIO specifications for POD12 in the Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Stratix 10
Devices table.
Removed the VOL and VOH specifications for POD12 in the Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Stratix 10
Devices table.
Updated VSWING(DC) specification for SSTL-12 in the Differential SSTL I/O Standards Specifications for Intel Stratix 10 Devices table.
Corrected VX(AC) to VIX(AC) in the Differential SSTL I/O Standards Specifications for Intel Stratix 10 Devices and Glossary tables.
Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile
Devices in a Non-Bonded Configuration" table.
Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile
Devices in a Bonded Configuration" table.
Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices
in a Non-Bonded Configuration" table.
Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices
in a Bonded Configuration" table.
Changed the minimum, typical, and maximum values for VCCT_GXB[L,R] and VCCR_GXB[L,R] for datarates > 17.4 Gbps to 28.3 Gbps in the "Transceiver
Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Bonded Configuration" table.
Changed the footnote for the minimum value of the Input Reference Clock Frequency (fPLL PLL) symbol in the "L-Tile Reference Clock Specifications"
table.
Changed the minimum and maximum frequencies and added a Modes column to the "L-Tile Fractional PLL Performance" table.
Changed the minimum and maximum frequencies and added a Modes column to the "H-Tile Fractional PLL Performance" table.
Changed the minimum supported output frequency in the "L-Tile CMU PLL Performance" table.
Added a footnote to the Transmitter REFCLK Phase Jitter (100 MHz) specification in the "L-Tile Reference Clock Specifications" table.
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Added a footnote to the Transmitter REFCLK Phase Noise (800 MHz) specification in the "H-Tile Reference Clock Specifications" table.
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Removed the DC coupling description from the VICM symbol in the "L-Tile Receiver Specifications" table.
Added a footnote to the VOD Setting column in the "L-Tile Typical Transmitter VOD Settings" table.
Added a footnote to the GXT channels for transceiver speed grade -1 in the "Intel Stratix 10 GX/SX H-Tile Transmitter and Receiver Datarate
Performance" table.
Changed the footnote for the minimum value of the Input Reference Clock Frequency (fPLL PLL) symbol in the "H-Tile Reference Clock Specifications"
table.
Changed the maximum voltage for the VID (before device configuration) parameter in the "H-Tile Receiver Specifications" table.
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Removed DC coupling support from the VICM parameter in the "H-Tile Receiver Specifications" table.
Added a footnote to the VOD Setting column in the "H-Tile Typical Transmitter VOD Settings" table.
Changed the VICM (AC Coupled) typical value in the "H-Tile Reference Clock Specifications" table.
Updated the programmable clock routing specification for –1 speed grade in the Clock Tree Performance for Intel Stratix 10 Devices table.
Updated the Fractional PLL Specifications for Intel Stratix 10 Devices table.
— Updated fVCO specifications.
— Removed tPLL_PSERR specifications.
Updated the Memory Block Performance Specifications for Intel Stratix 10 Devices table.
— Added the specifications for the "Simple dual-port with ECC and optional pipeline registers enabled, with the read-during-write option set to Old
Data, 512 × 32" mode in the M20K block.
— Updated the specifications for eSRAM.
Updated specifications in the External Temperature Sensing Diode Specifications for Intel Stratix 10 Devices table.
Updated the Internal Voltage Sensor Specifications for Intel Stratix 10 Devices table.
Removed the note on pending silicon characterization in the High-Speed I/O Specifications for Intel Stratix 10 Devices table.
Added the following tables:
— Memory Standards Supported by the Hard Memory Controller for Intel Stratix 10 Devices
— Memory Standards Supported by the Soft Memory Controller for Intel Stratix 10 Devices
— Memory Standards Supported by the HPS Hard Memory Controller for Intel Stratix 10 Devices
Removed the note to the DLL reference clock input specification in the DLL Frequency Range Specifications for Intel Stratix 10 Devices table.
Removed the Memory Output Clock Jitter Specifications for Intel Stratix 10 Devices table. Stated that the clock jitter is within the JEDEC specifications.
Updated TRS_RT specification in the OCT Calibration Block Specifications for Intel Stratix 10 Devices table.
Updated the note to SDRAM interconnect frequency in the Maximum HPS Clock Frequencies for Intel Stratix 10 Devices table.
Added HPS Internal Oscillator Frequency specifications.
Updated the minimum specification for clock input accuracy in the HPS PLL Input Requirements for Intel Stratix 10 Devices table.
Updated the minimum specifications for Td, Tsu, and Th in the HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI)
Timing Requirements for Intel Stratix 10 Devices table.
Updated specifications in the HPS Programmable I/O Delay for Intel Stratix 10 Device table.
continued...
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2018.04.06
Removed Preliminary tags for the following tables:
— HPS PLL Input Requirements for Intel Stratix 10 Devices
— HPS PLL Performance for Intel Stratix 10 Devices
— HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Stratix 10 Devices
— HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Stratix 10 Devices
— HPS I2C Timing Requirements for Intel Stratix 10 Devices
— HPS NAND ONFI 1.0 Timing Requirements for Intel Stratix 10 Devices
— HPS GPIO Interface
— HPS JTAG Timing Requirements for Intel Stratix 10 Devices
— HPS Programmable I/O Delay for Intel Stratix 10 Device
Removed information on NAND configuration mode.
— Removed NAND mode in the POR Delay Specification for Intel Stratix 10 Devices table.
— Removed the NAND Configuration Timing section.
— Removed the maximum configuration time estimation for NAND mode.
Updated the note to clock input frequency in the External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements table.
Added description in the SD/MMC Timing Parameters for Intel Stratix 10 Devices table.
Removed the statement stating that the maximum configuration time does not exceed 2× of the minimum configuration time in the Maximum
Configuration Time Estimation section.
Updated the I/O Timing section on the I/O timing information generation guidelines.
Updated the specifications for fast and slow models in the Programmable IOE Delay for Intel Stratix 10 Devices table.
Finalized the data for the Intel Stratix 10 GX variant (L-Tile).
Changed the input reference clock frequency (CMU PLL) minimum specification in the "L-Tile Reference Clock Specifications" table.
Changed the input reference clock frequency (CMU PLL) minimum specification in the "H-Tile Reference Clock Specifications" table.
Made the following changes:
• Added notes to IOUT specification in the Absolute Maximum Ratings for Intel Stratix 10 Devices table.
• Updated the AS Timing Parameters for Intel Stratix 10 Devices table.
— Updated the specifications for Tclk, Tdcsfrs, Tdcslst, and Tdo.
— Removed the Text_skew specifications.
— Updated the description on trace length matching and skew tolerance.
— Updated the note for Text_delay.
• Removed footnote to sampling rate in the Internal Voltage Sensor Specifications for Intel Stratix 10 Devices table.
• Updated the specifications for tSDCLKP, tSU, and tH in the SD/MMC Timing Parameters for Intel Stratix 10 Devices table.
• Updated the compressed configuration bit stream sizes in the Configuration Bit Stream Sizes table.
• Updated the Maximum Configuration Time Estimation for Intel Stratix 10 Devices tables.
— Changed the table title from "Minimum Configuration Time Estimation" to "Maximum Configuration Time Estimation".
— Updated the specifications.
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2017.12.15
Made the following changes:
• Added the Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Non-Bonded Configuration table.
• Added the Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Bonded Configuration table.
• Added the Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Non-Bonded Configuration table.
• Added the Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Bonded Configuration table.
• Removed the Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L- and H-Tile Devices table.
• Removed the L-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications table.
• Added the Intel Stratix 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance table.
• Added the Intel Stratix 10 GX/SX H-Tile Transmitter and Receiver Datarate Performance table.
• Removed the H-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications table
• Added note to the Maximum" column in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L- and H-Tile Devices—
Preliminary table.
• Removed the Minimum differential eye opening at receiver serial input pins specification from the "L-Tile Receiver Specifications" table.
• Updated Absolute Maximum Ratings for Intel Stratix 10 Devices table.
— Updated TSTG minimum specifications from –65°C to –55°C.
— Added VI specifications.
• Added -2 transceiver speed grade,the tARESET, and the tLOCK specification to the "L-Tile ATX PLL Performance" table.
• Added the tARESET and tLOCK specifications to the "L-Tile Fractional PLL Performance" table.
• Added the tARESET and tLOCK specifications to the "L-Tile CMU PLL Performance" table.
• Changed the Channel Span definition in the "L-Tile Transceiver Clock Network Maximum Data Rate Specifications" table.
• Removed the VOCM (DC coupled) specification from the "L-Tile Transmitter Specifications" table.
• Added the xN clock mode to the "L-Tile Transmitter Channel-to-channel Skew Specifications" table.
• Added the xN clock mode to the "H-Tile Transmitter Channel-to-channel Skew Specifications" table.
• Added the tLOCK and tARESET specifications to the "H-Tile ATX PLL Performance" table.
• Added the tLOCK and tARESET specifications to the "H-Tile Fractional PLL Performance" table.
• Added the tLOCK and tARESET specifications to the "H-Tile CMU PLL Performance" table.
• Removed the Minimum differential eye opening at receiver serial input pins specification from the "H-Tile Receiver Specifications" table.
• Split LVDS I/O and 3 V I/O specifications in Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices table into two separate tables.
Updated the LVDS I/O specifications.
• Added Intel Stratix 10 Devices Overshoot Duration figure and description.
• Updated Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Updated VCCIO_UIB specifications.
— Updated note to minimum and maximum columns.
— Changed the symbol from VCCM to VCCM_WORD.
continued...
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Added specifications for VCCIO = 2.5 V in the following tables:
— Bus Hold Parameters for Intel Stratix 10 Devices
— Internal Weak Pull-Up Resistor Values for Intel Stratix 10 Devices
Updated specifications in OCT Calibration Accuracy Specifications for Intel Stratix 10 Devices table.
Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Intel Stratix 10 Devices table.
— Added specifications for VCCIO = 3.0, 2.5
— Updated specifications for VCCIO = 1.8, 1.5, 1.2
Added the following specifications in Single-Ended I/O Standards Specifications for Intel Stratix 10 Devices table.
— 2.5 V I/O standard
— Schmitt trigger input
Updated SSTL-125 and SSTL-135 I/O standards in Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Stratix 10
Devices table.
Added specifications for SSTL-12 I/O standard in the following tables:
— Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Stratix 10 Devices
— Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Stratix 10 Devices
— Differential SSTL I/O Standards Specifications for Intel Stratix 10 Devices
Updated the Fractional PLL Specifications for Intel Stratix 10 Devices table.
— Updated tPLL_PSERR specifications.
— Updated tLOCK description.
— Removed tARESET specifications.
Updated tOUTDUTY in the I/O PLL Specifications for Intel Stratix 10 Devices table.
Updated Internal Temperature Sensing Diode Specifications for Intel Stratix 10 Devices table.
— Added note for temperature range.
— Updated conversion time from < 5 ms to < 1 ms.
— Removed "Resolution" and "Minimum Resolution with no Missing Codes" specifications.
Updated High-Speed I/O Specifications for Intel Stratix 10 Devices table.
— Updated Transmitter—TCCS specifications from 150 ps to 330 ps.
— Updated Sampling Window specifications from 300 ps to 330 ps.
— Updated SERDES factor J = 3 maximum data rate for transmitter and receiver.
Updated from 0.35 to 0.28 for the following:
— LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
— LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
Updated DLL reference clock input specifications in DLL Frequency Range Specifications for Intel Stratix 10 Devices table.
Updated Tdo minimum specification from 0 ns to –1 ns in AS Timing Parameters for Intel Stratix 10 Devices table.
Updated minimum specifications for tH from 0 ns to –1 ns in SD/MMC Timing Parameters for Intel Stratix 10 Devices table.
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Updated Configuration Bit Stream Sizes for Intel Stratix 10 Devices table.
— Added IOCSR bit stream sizes.
— Added specifications for Intel Stratix 10 TX and MX devices.
Updated Minimum Configuration Time Estimation for Intel Stratix 10 Devices tables.
— Added note to AVST ×8, AVST ×16, and AVST ×32.
— Updated specifications for NAND.
— Added specifications for Intel Stratix 10 TX and MX devices.
Added the following tables:
— External Temperature Sensing Diode Specifications for Intel Stratix 10 Devices
— General Configuration Timing Specifications for Intel Stratix 10 Devices
• Moved tST0 specifications from Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Stratix 10 Devices table.
• Moved the specifications from Initialization Time for Intel Stratix 10 Devices table.
— Programmable IOE Delay for Intel Stratix 10 Devices
2017.08.04
Made the following changes:
• Clarified DLL operating frequency range in "DLL Range Specifications"
• Clarified reference clock specifications in "HPS SPI Timing Characteristics"
2017.05.08
Made the following changes:
• Updated description for VCCERAM in Absolute Maximum Ratings for Intel Stratix 10 Devices table.
• Added Maximum Allowed Overshoot During Transitions for Intel Stratix 10 Devices table.
• Updated Recommended Operating Conditions for Intel Stratix 10 Devices table.
— Updated VCC, VCCIO, and VCCBAT specifications.
— Updated symbol from VCCPFUSE_SDM to VCCFUSEWR_SDM.
— Updated description for VCCERAM and VCCIO_UIB .
— Added VCCM specifications.
— Added footnotes to tRAMP and V suffix speed grades.
• Removed table: Temperature Compensation for SmartVID for Intel Stratix 10 Devices. Moved the table to the Intel Stratix 10 Power Management User
Guide.
• Updated the note in the "Transceiver Power Supply Operating Conditions" section.
• Updated HPS Power Supply Operating Conditions for Intel Stratix 10 Devices table.
— Updated VCCL_HPS and VCCPLLDIG_HPS specifications.
— Added footnote for SmartVID.
• Updated footnote to IOL and IOH in Single-Ended I/O Standards Specifications for Intel Stratix 10 Devices table.
• Updated Differential I/O Standards Specifications for Intel Stratix 10 Devices table.
— Changed DMAX to data rate.
— Added a note to VOD.
continued...
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Intel® Stratix® 10 Device Datasheet
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2017.02.17
Updated tOUTPJ_DC and tOUTCCJ_DC specifications in I/O PLL Specifications for Intel Stratix 10 Devices.
Changed the units of measure for the minimum frequency in the "L-Tile CMU PLL Performance" table.
Changed the units of measure for the minimum frequency in the "H-Tile CMU PLL Performance" table.
Updated tINCCJ specification for FREF < 100 MHz in the following tables:
— Fractional PLL Specifications for Intel Stratix 10 Devices
— I/O PLL Specifications for Intel Stratix 10 Devices
Added footnote to the following modes in DSP Block Performance Specifications for Intel Stratix 10 Devices table:
— Fixed-point 27 × 27 multiplication mode
— Fixed-point 18 × 18 multiplier adder mode
— Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode
Updated soft CDR mode specifications in High-Speed I/O Specifications for Intel Stratix 10 Devices table.
Added POR specifications.
Updated Tdo maximum specification in AS Timing Parameters for Intel Stratix 10 Devices table.
Updated notes in Avalon-ST Configuration Timing Diagram.
Added description in NAND ONFI 1.0 Mode 0-5 Timing Requirements for Intel Stratix 10 Devices table.
Updated tSU, tH, and td specifications in SD/MMC Timing Parameters for Intel Stratix 10 Devices table.
Updated table title from "Initialization Clock Source Option and the Maximum Frequency for Intel Stratix 10 Devices" to "Initialization Time for Intel
Stratix 10 Devices".
Updated description in Configuration Bit Stream Sizes for Intel Stratix 10 Devices to mention that the actual sizes may be equal or smaller than the bit
stream sizes in this table.
Updated description in Minimum Configuration Time Estimation section.
Removed AS ×1 specifications in Minimum Configuration Time Estimation for Intel Stratix 10 Devices (AS, NAND, and SD/MMC) table.
Added Glossary.
Removed PowerPlay text from tool name.
Made the following changes:
• Added the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX E-Tile Devices" table.
• Added the "E-Tile Transceiver Performance Specifications" section.
• Added the "Transceiver Performance forIntel Stratix 10 E-Tile Devices" section.
• Added the "Transceiver Reference Clock Specifications" section.
• Added the "Transmitter Specifications for Intel Stratix 10 E-Tile Devices" section.
continued...
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132
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Intel® Stratix® 10 Device Datasheet
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Changes
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2016.12.09
Made the following changes:
• Changed the max tLTR value and unit of measure in the "L-Tile Receiver Specifications" table.
• Made the following changes to the "Transceiver Clocks Specifications for Stratix 10 GX/SX L-Tile Devices" table:
— Changed the value of the reconfig_clk signal
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2016.10.31
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Added the "Receiver Specifications for Intel Stratix 10 E-Tile Devices" section.
Updated the "AS Timing Parameters for Intel Stratix 10 Devices" table.
— Updated Tdcsfrs and Tdcslst.
— Added Text_delay and Text_skew.
— Removed Tsu and Th.
Updated AS Configuration Serial Input Timing Diagram.
— Added a new footnote to the GX channel
— Changed the minimum values for the GXT channel
Changed the max tLTR value and unit of measure in the "H-Tile Receiver Specifications" table.
Removed the QPI footnote from the "H-Tile Transmitter Specifications" table.
Changed the value of the reconfig_clk signal in the "Transceiver Clocks Specifications for Stratix 10 GX/SX H-Tile Devices" table.
Changed the minimum value of fINPFD in the "Fractional PLL Specifications for Stratix 10 Devices" table.
Initial release.
Intel® Stratix® 10 Device Datasheet
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1SG280LH3F55E3VGS1 1SG280HN2F43E2VGS1 1SG280LH2F55E2VG 1SG280LH2F55I2LG
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