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Arria V Device Datasheet Subscribe Send Feedback AV-51002 | 2019.04.26 Latest document on the web: PDF | HTML Contents Contents 1. Arria® V GX, GT, SX, and ST Device Datasheet....................................................................................................................... 4 1.1. Electrical Characteristics................................................................................................................................................ 4 1.1.1. Operating Conditions.........................................................................................................................................4 1.2. Switching Characteristics............................................................................................................................................. 24 1.2.1. Transceiver Performance Specifications.............................................................................................................. 25 1.2.2. Core Performance Specifications....................................................................................................................... 44 1.2.3. Periphery Performance.....................................................................................................................................49 1.2.4. HPS Specifications.......................................................................................................................................... 57 1.3. Configuration Specifications......................................................................................................................................... 74 1.3.1. POR Specifications.......................................................................................................................................... 74 1.3.2. FPGA JTAG Configuration Timing....................................................................................................................... 75 1.3.3. FPP Configuration Timing................................................................................................................................. 75 1.3.4. Active Serial (AS) Configuration Timing..............................................................................................................79 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme..............................................................................80 1.3.6. Passive Serial (PS) Configuration Timing............................................................................................................ 81 1.3.7. Initialization................................................................................................................................................... 82 1.3.8. Configuration Files.......................................................................................................................................... 83 1.3.9. Minimum Configuration Time Estimation.............................................................................................................84 1.3.10. Remote System Upgrades.............................................................................................................................. 85 1.3.11. User Watchdog Internal Oscillator Frequency Specifications.................................................................................85 1.4. I/O Timing................................................................................................................................................................. 85 1.4.1. Programmable IOE Delay................................................................................................................................. 86 1.4.2. Programmable Output Buffer Delay................................................................................................................... 87 1.5. Glossary.................................................................................................................................................................... 87 1.6. Arria V GX, GT, SX, and ST Device Datasheet Revision History......................................................................................... 94 2. Arria V GZ Device Datasheet...............................................................................................................................................100 2.1. Electrical Characteristics............................................................................................................................................ 100 2.1.1. Operating Conditions .................................................................................................................................... 100 2.2. Switching Characteristics ...........................................................................................................................................119 2.2.1. Transceiver Performance Specifications ........................................................................................................... 119 2.2.2. Core Performance Specifications .....................................................................................................................133 Arria V Device Datasheet 2 Send Feedback Contents 2.2.3. Periphery Performance .................................................................................................................................. 139 2.3. Configuration Specification ........................................................................................................................................ 151 2.3.1. POR Specifications ........................................................................................................................................151 2.3.2. JTAG Configuration Specifications ................................................................................................................... 151 2.3.3. Fast Passive Parallel (FPP) Configuration Timing ................................................................................................152 2.3.4. Active Serial Configuration Timing .................................................................................................................. 160 2.3.5. Passive Serial Configuration Timing .................................................................................................................163 2.3.6. Initialization ................................................................................................................................................ 165 2.3.7. Configuration Files ........................................................................................................................................165 2.3.8. Remote System Upgrades Circuitry Timing Specification .................................................................................... 167 2.3.9. User Watchdog Internal Oscillator Frequency Specification ................................................................................. 167 2.4. I/O Timing .............................................................................................................................................................. 167 2.4.1. Programmable IOE Delay .............................................................................................................................. 168 2.4.2. Programmable Output Buffer Delay .................................................................................................................169 2.5. Glossary ................................................................................................................................................................. 169 2.6. Arria V GZ Device Datasheet Revision History ............................................................................................................. 175 Send Feedback Arria V Device Datasheet 3 AV-51002 | 2019.04.26 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Arria® V devices. Arria V devices are offered in commercial and industrial grades. Commercial devices are offered in –C4 (fastest), –C5, and – C6 speed grades. Industrial grade devices are offered in the –I3 and –I5 speed grades. Related Information Arria V Device Overview Provides more information about the densities and packages of devices in the Arria V family. 1.1. Electrical Characteristics The following sections describe the operating conditions and power consumption of Arria V devices. 1.1.1. Operating Conditions Arria V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria V devices, you must consider the operating requirements described in this section. 1.1.1.1. Absolute Maximum Ratings This section defines the maximum operating conditions for Arria V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 1. Absolute Maximum Ratings for Arria V Devices Symbol Description Minimum Maximum Unit VCC Core voltage power supply –0.50 1.43 V VCCP Periphery circuitry, PCI Express* (PCIe*) hard IP block, and transceiver physical coding sublayer (PCS) power supply –0.50 1.43 V VCCPGM Configuration pins power supply –0.50 3.90 V VCC_AUX Auxiliary supply –0.50 3.25 V VCCBAT Battery back-up power supply for design security volatile key register –0.50 3.90 V VCCPD I/O pre-driver power supply –0.50 3.90 V VCCIO I/O power supply –0.50 3.90 V VCCD_FPLL Phase-locked loop (PLL) digital power supply –0.50 1.80 V VCCA_FPLL PLL analog power supply –0.50 3.25 V VCCA_GXB Transceiver high voltage power –0.50 3.25 V VCCH_GXB Transmitter output buffer power –0.50 1.80 V VCCR_GXB Receiver power –0.50 1.50 V VCCT_GXB Transmitter power –0.50 1.50 V VCCL_GXB Transceiver clock network power –0.50 1.50 V VI DC input voltage –0.50 3.80 V VCC_HPS HPS core voltage and periphery circuitry power supply –0.50 1.43 V VCCPD_HPS HPS I/O pre-driver power supply –0.50 3.90 V VCCIO_HPS HPS I/O power supply –0.50 3.90 V VCCRSTCLK_HPS HPS reset and clock input pins power supply –0.50 3.90 V VCCPLL_HPS HPS PLL analog power supply –0.50 3.25 V VCC_AUX_SHARED HPS auxiliary power supply –0.50 3.25 V IOUT DC output current per pin –25 40 mA TJ Operating junction temperature –55 125 °C TSTG Storage temperature (no bias) –65 150 °C Send Feedback Arria V Device Datasheet 5 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years. Table 2. Maximum Allowed Overshoot During Transitions for Arria V Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. Symbol Vi (AC) Description AC input voltage Condition (V) Overshoot Duration as % of High Time Unit 3.8 100 % 3.85 68 % 3.9 45 % 3.95 28 % 4 15 % 4.05 13 % 4.1 11 % 4.15 9 % 4.2 8 % 4.25 7 % 4.3 5.4 % 4.35 3.2 % 4.4 1.9 % 4.45 1.1 % continued... Arria V Device Datasheet 6 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Description Condition (V) Overshoot Duration as % of High Time Unit 4.5 0.6 % 4.55 0.4 % 4.6 0.2 % For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. Figure 1. Arria V Devices Overshoot Duration 4.1 V 4V 3.3 V DT T 1.1.1.3. Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Arria V devices. Send Feedback Arria V Device Datasheet 7 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.1.1.3.1. Recommended Operating Conditions Table 3. Recommended Operating Conditions for Arria V Devices This table lists the steady-state voltage values expected from Arria V devices. Power supply ramps must all be strictly monotonic, without plateaus. Symbol VCC Description Core voltage power supply VCCP Periphery circuitry, PCIe hard IP block, and transceiver PCS power supply VCCPGM Configuration pins power supply Condition Minimum(1) Typical Maximum(1) Unit –C4, –I5, –C5, –C6 1.07 1.1 1.13 V –I3 1.12 1.15 1.18 V –C4, –I5, –C5, –C6 1.07 1.1 1.13 V –I3 1.12 1.15 1.18 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V VCC_AUX Auxiliary supply — 2.375 2.5 2.625 V VCCBAT(2) Battery back-up power supply (For design security volatile key register) — 1.2 — 3.0 V VCCPD(3) I/O pre-driver power supply 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 VCCIO I/O buffers power supply V continued... (1) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (2) If you do not use the design security feature in Arria V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Arria V power-on reset (POR) circuitry monitors VCCBAT. Arria V devices do not exit POR if VCCBAT is not powered up. (3) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is 3.3 V. Arria V Device Datasheet 8 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Description Condition Minimum(1) Typical Maximum(1) Unit 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V 1.283 1.35 1.418 V 1.25 V 1.19 1.25 1.31 V 1.2 V 1.14 1.2 1.26 V VCCD_FPLL PLL digital voltage regulator power supply — 1.425 1.5 1.575 V VCCA_FPLL PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VI DC input voltage — –0.5 — 3.6 V VO Output voltage — 0 — VCCIO V TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C Standard POR 200 µs — 100 ms — Fast POR 200 µs — 4 ms — tRAMP(4) Power supply ramp time (1) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (4) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. Send Feedback Arria V Device Datasheet 9 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.1.1.3.2. Transceiver Power Supply Operating Conditions Table 4. Transceiver Power Supply Operating Conditions for Arria V Devices Symbol VCCA_GXBL Transceiver high voltage power (left side) VCCA_GXBR Transceiver high voltage power (right side) VCCR_GXBL GX and SX speed grades—receiver power (left side) VCCR_GXBR GX and SX speed grades—receiver power (right side) VCCR_GXBL GT and ST speed grades—receiver power (left side) VCCR_GXBR GT and ST speed grades—receiver power (right side) VCCT_GXBL GX and SX speed grades—transmitter power (left side) VCCT_GXBR GX and SX speed grades—transmitter power (right side) VCCT_GXBL GT and ST speed grades—transmitter power (left side) VCCT_GXBR GT and ST speed grades—transmitter power (right side) VCCH_GXBL Transmitter output buffer power (left side) VCCH_GXBR Transmitter output buffer power (right side) VCCL_GXBL GX and SX speed grades—clock network power (left side) VCCL_GXBR GX and SX speed grades—clock network power (right side) VCCL_GXBL GT and ST speed grades—clock network power (left side) VCCL_GXBR GT and ST speed grades—clock network power (right side) Minimum(5) Typical Maximum(5) Unit 2.375 2.500 2.625 V 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V 1.425 1.500 1.575 V 1.08/1.12 1.1/1.15(6) 1.14/1.18 V 1.17 1.20 1.23 V (5) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (6) For data rate 3.2 Gbps, connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines. Arria V Device Datasheet 10 Description Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Related Information Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines Provides more information about the power supply connection for different data rates. 1.1.1.3.3. HPS Power Supply Operating Conditions Table 5. HPS Power Supply Operating Conditions for Arria V SX and ST Devices This table lists the steady-state voltage and current values expected from Arria V system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria V Devices table for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices. Symbol VCC_HPS VCCPD_HPS (8) VCCIO_HPS Description Condition Minimum(7) Typical Maximum(7) Unit HPS core voltage and periphery circuitry power supply –C4, –I5, –C5, –C6 1.07 1.1 1.13 V –I3 1.12 1.15 1.18 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.283 1.35 1.418 HPS I/O predriver power supply HPS I/O buffers power supply 1.35 V (9) V continued... (7) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (8) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when VCCIO_HPS is 3.3 V. Send Feedback Arria V Device Datasheet 11 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol VCCRSTCLK_HPS Description HPS reset and clock input pins power supply Condition Minimum(7) Typical Maximum(7) Unit 1.2 V 1.14 1.2 1.26 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V VCCPLL_HPS HPS PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCC_AUX_SHARED HPS auxiliary power supply — 2.375 2.5 2.625 V Related Information Recommended Operating Conditions on page 8 Provides the steady-state voltage values for the FPGA portion of the device. 1.1.1.4. DC Characteristics 1.1.1.4.1. Supply Current and Power Consumption Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use. (7) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only. Arria V Device Datasheet 12 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information • Early Power Estimator User Guide Provides more information about power estimation tools. • Power Analysis chapter, Intel Quartus Prime Handbook Provides more information about power estimation tools. 1.1.1.4.2. I/O Pin Leakage Current Table 6. I/O Pin Leakage Current for Arria V Devices Symbol Description Condition Min Typ Max Unit II Input pin VI = 0 V to VCCIOMAX –30 — 30 µA IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA 1.1.1.4.3. Bus Hold Specifications Table 7. Bus Hold Parameters for Arria V Devices The bus-hold trip points are based on calculated input voltages from the JEDEC* standard. Parameter Symbol Condition VCCIO (V) 1.2 1.5 1.8 Unit 2.5 3.0 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold, low, sustaining current ISUSL VIN > VIL (max) 8 — 12 — 30 — 50 — 70 — 70 — µA Bus-hold, high, sustaining current ISUSH VIN < VIH (min) –8 — –12 — –30 — –50 — –70 — –70 — µA continued... Send Feedback Arria V Device Datasheet 13 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Parameter Symbol Condition VCCIO (V) 1.2 1.5 1.8 Unit 2.5 3.0 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold, low, overdrive current IODL 0 V < VIN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 µA Bus-hold, high, overdrive current IODH 0 V 700 Mbps 1.60 Related Information • Transceiver Specifications for Arria V GX and SX Devices on page 25 Provides the specifications for transmitter, receiver, and reference clock I/O pin. • Transceiver Specifications for Arria V GT and ST Devices on page 30 Provides the specifications for transmitter, receiver, and reference clock I/O pin. 1.2. Switching Characteristics This section provides performance characteristics of Arria V core and periphery blocks. (16) (17) (18) The minimum VID value is applicable over the entire common mode range, VCM. RL range: 90 ≤ RL ≤ 110 Ω. This applies to default pre-emphasis setting only. (21) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V. (22) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps. Arria V Device Datasheet 24 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.1. Transceiver Performance Specifications 1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices Table 20. Reference Clock Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Min Supported I/O standards Typ Transceiver Speed Grade 6 Max Min 1.2 V PCML, 1.4 V PCML,1.5 V PCML, 2.5 V PCML, Differential Typ LVPECL(23), Unit Max HCSL, and LVDS — 27 — 710 27 — 710 MHz Rise time Measure at ±60 mV of differential signal(24) — — 400 — — 400 ps Fall time Measure at ±60 mV of differential signal(24) — — 400 — — 400 ps Duty cycle — 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 300(25)/ 2000 200 — 300(25)/ 2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to –0.5% — — 0 to –0.5% — — On-chip termination resistors — — 100 — — 100 — Ω — 1.1/1.15(26) — 1.1/1.15(26) — Input frequency from REFCLK input pins VICM (AC coupled) — — V continued... (23) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. (24) REFCLK performance requires to meet transmitter REFCLK phase noise specification. (25) The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link. (26) For data rate ≤3.2 Gbps, connect VCCR_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps, connect VCCR_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines. Send Feedback Arria V Device Datasheet 25 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description VICM (DC coupled) Transmitter REFCLK phase noise(27) RREF Table 21. Transceiver Speed Grade 4 Transceiver Speed Grade 6 Unit Min Typ Max Min Typ Max HCSL I/O standard for the PCIe reference clock 250 — 550 250 — 550 mV 10 Hz — — –50 — — –50 dBc/Hz 100 Hz — — –80 — — –80 dBc/Hz 1 KHz — — –110 — — –110 dBc/Hz 10 KHz — — –120 — — –120 dBc/Hz 100 KHz — — –120 — — –120 dBc/Hz ≥1 MHz — — –130 — — –130 dBc/Hz — — 2000 ±1% — — 2000 ±1% — Ω Transceiver Clocks Specifications for Arria V GX and SX Devices Symbol/Description fixedclk clock frequency Transceiver Reconfiguration Controller Intel FPGA IP (mgmt_clk_clk) clock frequency Table 22. Condition Condition Transceiver Speed Grade 4 Transceiver Speed Grade 6 Unit Min Typ Max Min Typ Max PCIe Receiver Detect — 125 — — 125 — MHz — 75 — 125 75 — 125 MHz Receiver Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Min Supported I/O standards Data rate(28) Typ Max Transceiver Speed Grade 6 Min Typ Max — 3125 Unit 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS — 611 — 6553.6 611 Mbps continued... (27) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12. (28) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Arria V Device Datasheet 26 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Condition Transceiver Speed Grade 4 Transceiver Speed Grade 6 Unit Min Typ Max Min Typ Max — — — 1.2 — — 1.2 V Absolute VMIN for a receiver pin — –0.4 — — –0.4 — — V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 — — 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration — — — 2.2 — — 2.2 V Minimum differential eye opening at the receiver serial input pins(30) — 100 — — 100 — — mV VICM (AC coupled) — — 0.7/0.75/0.8 — — 0.7/0.75/0.8 — mV VICM (DC coupled) ≤ 3.2Gbps(32) 670 700 730 670 700 730 mV 85-Ω setting — 85 — — 85 — Ω 100-Ω setting — 100 — — 100 — Ω 120-Ω setting — 120 — — 120 — Ω 150-Ω setting — 150 — — 150 — Absolute VMAX for a receiver pin(29) Differential on-chip termination resistors (31) (31) Ω continued... (29) The device cannot tolerate prolonged operation at this absolute maximum. (30) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (31) The AC coupled VICM = 700 mV for Arria V GX and SX in PCIe mode only. The AC coupled VICM = 750 mV for Arria V GT and ST in PCIe mode only. (32) For standard protocol compliance, use AC coupling. Send Feedback Arria V Device Datasheet 27 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Condition Unit Typ Max Min Typ Max — — — 10 — — 10 µs — 4 — — 4 — — µs — 4 — — 4 — — µs — 15 — — 15 — — µs tLTR tLTD(34) tLTD_manual(35) tLTR_LTD_manual(36) Programmable ppm detector(37) — Run length — Table 23. Transceiver Speed Grade 6 Min (33) Programmable equalization AC and DC gain Transceiver Speed Grade 4 AC gain setting = 0 to 3(38) DC gain setting = 0 to 1 ±62.5, 100, 125, 200, 250, 300, 500, and 1000 — — 200 — — ppm 200 UI Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices diagrams. dB Transmitter Specifications for Arria V GX and SX Devices Symbol/Description Condition Transceiver Speed Grade 4 Min Typ Supported I/O standards Data rate Max Transceiver Speed Grade 6 Min Typ Max 611 — 3125 Unit 1.5 V PCML — 611 — 6553.6 Mbps continued... (33) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (34) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (35) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (36) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. (37) The rate match FIFO supports only up to ±300 parts per million (ppm). (38) The Intel Quartus Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only. Arria V Device Datasheet 28 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Condition VOCM (AC coupled) Transceiver Speed Grade 4 — VOCM (DC coupled) ≤ Differential on-chip termination resistors 3.2Gbps(32) Transceiver Speed Grade 6 Unit Min Typ Max Min Typ Max — 650 — — 650 — mV 670 700 730 670 700 730 mV 85-Ω setting — 85 — — 85 — Ω 100-Ω setting — 100 — — 100 — Ω 120-Ω setting — 120 — — 120 — Ω 150-Ω setting — 150 — — 150 — Ω TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps — — 15 — — 15 ps Intra-transceiver block transmitter channel-to-channel skew ×6 PMA bonded mode — — 180 — — 180 ps Inter-transceiver block transmitter channel-to-channel skew(39) ×N PMA bonded mode — — 500 — — 500 ps Intra-differential pair skew Table 24. CMU PLL Specifications for Arria V GX and SX Devices Symbol/Description Transceiver Speed Grade 4 Transceiver Speed Grade 6 Unit Min Max Min Max Supported data range 611 6553.6 611 3125 Mbps fPLL supported data range 611 3125 611 3125 Mbps Table 25. Transceiver-FPGA Fabric Interface Specifications for Arria V GX and SX Devices Symbol/Description Transceiver Speed Grade 4 and 6 Unit Min Max Interface speed (single-width mode) 25 187.5 MHz Interface speed (double-width mode) 25 163.84 MHz (39) This specification is only applicable to channels on one side of the device across two transceiver banks. Send Feedback Arria V Device Datasheet 29 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Related Information • CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 36 • CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 37 • Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines Provides more information about the power supply connection for different data rates. 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices Table 26. Reference Clock Specifications for Arria V GT and ST Devices Symbol/Description Condition Transceiver Speed Grade 3 Min Supported I/O standards Typ 1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Differential Unit Max LVPECL(40), HCSL, and LVDS — 27 — 710 MHz Rise time Measure at ±60 mV of differential signal(41) — — 400 ps Fall time Measure at ±60 mV of differential signal(41) — — 400 ps Duty cycle — 45 — 55 % Peak-to-peak differential input voltage — 200 — 300(42)/2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to –0.5% — — On-chip termination resistors — — 100 — Ω VICM (AC coupled) — — 1.2 — Input frequency from REFCLK input pins V continued... (40) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. (41) REFCLK performance requires to meet transmitter REFCLK phase noise specification. (42) The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link. Arria V Device Datasheet 30 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description VICM (DC coupled) Transmitter REFCLK phase noise(43) Condition Typ Max HCSL I/O standard for the PCIe reference clock 250 — 550 mV 10 Hz — — –50 dBc/Hz 100 Hz — — –80 dBc/Hz 1 KHz — — –110 dBc/Hz 10 KHz — — –120 dBc/Hz 100 KHz — — –120 dBc/Hz ≥ 1 MHz — — –130 dBc/Hz — — 2000 ±1% — Ω Transceiver Clocks Specifications for Arria V GT and ST Devices Symbol/Description fixedclk clock frequency Condition Transceiver Speed Grade 3 Unit Min Typ Max PCIe Receiver Detect — 125 — MHz — 75 — 125 MHz Transceiver Reconfiguration Controller Intel FPGA IP (mgmt_clk_clk) clock frequency Table 28. Unit Min RREF Table 27. Transceiver Speed Grade 3 Receiver Specifications for Arria V GT and ST Devices Symbol/Description Condition Transceiver Speed Grade 3 Min Supported I/O Standards Data rate (6-Gbps transceiver)(44) Typ Unit Max 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS — 611 — 6553.6 Mbps continued... (43) The transmitter REFCLK phase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma. (44) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Send Feedback Arria V Device Datasheet 31 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Condition Transceiver Speed Grade 3 Unit Min Typ Max — 0.611 — 10.3125 Gbps — — — 1.2 V Absolute VMIN for a receiver pin — –0.4 — — V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration — — — 2.2 V Minimum differential eye opening at the receiver serial input pins(46) — 100 — — mV VICM (AC coupled) — — 750(47)/800 — mV 670 700 730 mV Data rate (10-Gbps transceiver)(44) pin(45) Absolute VMAX for a receiver VICM (DC coupled) Differential on-chip termination resistors tLTR(49) ≤ 3.2Gbps(48) 85-Ω setting 85 Ω 100-Ω setting 100 Ω 120-Ω setting 120 Ω 150-Ω setting 150 Ω — — — 10 µs continued... (45) The device cannot tolerate prolonged operation at this absolute maximum. (46) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (47) The AC coupled VICM is 750 mV for PCIe mode only. (48) For standard protocol compliance, use AC coupling. (49) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. Arria V Device Datasheet 32 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Condition Typ Max — 4 — — µs — 4 — — µs — 15 — — tLTD_manual(51) tLTR_LTD_manual(52) Programmable ppm detector(53) — Run length — Table 29. Unit Min tLTD(50) Programmable equalization AC and DC gain Transceiver Speed Grade 3 µs ±62.5, 100, 125, 200, 250, 300, 500, and 1000 — AC gain setting = 0 to 3(54) DC gain setting = 0 to 1 — ppm 200 UI Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices diagrams. Transmitter Specifications for Arria V GT and ST Devices Symbol/Description Condition Transceiver Speed Grade 3 Min Supported I/O standards Unit Typ Max 1.5 V PCML Data rate (6-Gbps transceiver) — 611 — 6553.6 Mbps Data rate (10-Gbps transceiver) — 0.611 — 10.3125 Gbps VOCM (AC coupled) — — 650 — mV continued... (50) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (51) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (52) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. (53) The rate match FIFO supports only up to ±300 ppm. (54) The Intel Quartus Prime software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only. Send Feedback Arria V Device Datasheet 33 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Transceiver Speed Grade 3 Unit Min Typ Max 670 700 730 mV 85-Ω setting — 85 — Ω 100-Ω setting — 100 — Ω 120-Ω setting — 120 — Ω 150-Ω setting — 150 — Ω TX VCM = 0.65 V (AC coupled) and slew rate of 15 ps — — 15 ps Intra-transceiver block transmitter channel-tochannel skew ×6 PMA bonded mode — — 180 ps Inter-transceiver block transmitter channel-tochannel skew(55) ×N PMA bonded mode — — 500 ps VOCM (DC coupled) ≤ 3.2 Differential on-chip termination resistors Intra-differential pair skew Table 30. Supported data range fPLL supported data range (55) Gbps(48) CMU PLL Specifications for Arria V GT and ST Devices Symbol/Description Transceiver Speed Grade 3 Unit Min Max 0.611 10.3125 Gbps 611 3125 Mbps This specification is only applicable to channels on one side of the device across two transceiver banks. Arria V Device Datasheet 34 Condition Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 31. Transceiver-FPGA Fabric Interface Specifications for Arria V GT and ST Devices Symbol/Description Transceiver Speed Grade 3 Unit Min Max Interface speed (PMA direct mode) 50 153.6(56), 161(57) MHz Interface speed (single-width mode) 25 187.5 MHz Interface speed (double-width mode) 25 163.84 MHz Related Information • CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 36 • CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 37 (56) The maximum frequency when core transceiver local routing is selected. (57) The maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected. Send Feedback Arria V Device Datasheet 35 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain Figure 3. Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices Arria V Device Datasheet 36 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Figure 4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST Devices Send Feedback Arria V Device Datasheet 37 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.1.5. Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω Table 32. Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω Symbol VOD differential peak-to-peak typical VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV) 6(59) 120 34 680 7(59) 140 35 700 8(59) 160 36 720 9 180 37 740 10 200 38 760 11 220 39 780 12 240 40 800 13 260 41 820 14 280 42 840 15 300 43 860 16 320 44 880 17 340 45 900 18 360 46 920 19 380 47 940 20 400 48 960 21 420 49 980 22 440 50 1000 23 460 51 1020 24 480 52 1040 continued... (58) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. (59) Only valid for data rates ≤ 5 Gbps. Arria V Device Datasheet 38 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol VOD Setting(58) VOD Value (mV) VOD Setting(58) VOD Value (mV) 25 500 53 1060 26 520 54 1080 27 540 55 1100 28 560 56 1120 29 580 57 1140 30 600 58 1160 31 620 59 1180 32 640 60 1200 33 660 1.2.1.6. Transmitter Pre-Emphasis Levels The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions: • Low-frequency data pattern—five 1s and five 0s • Data rate—2.5 Gbps The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the preemphasis levels may change with data pattern and data rate. Arria V devices only support 1st post tap pre-emphasis with the following conditions: (58) • The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st post tap pre-emphasis setting. • |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps. • (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|. Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. Send Feedback Arria V Device Datasheet 39 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Exception for PCIe Gen2 design: VOD setting = 43 and pre-emphasis setting = 19 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Arria V Hard IP for PCI Express Intel FPGA IP and PHY for PCI Express (PIPE) Intel FPGA IP cores. For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid: • |B| + |C| ≤ 60→ 40 + 2 = 42 • |B| – |C| > 5→ 40 – 2 = 38 • (VMAX/VMIN – 1)% < 600%→ (42/38 – 1)% = 10.52% To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Arria V HSSI HSPICE models. Table 33. Transmitter Pre-Emphasis Levels for Arria V Devices Intel Quartus Prime 1st Post Tap Pre-Emphasis Setting Intel Quartus Prime VOD Setting Unit 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 0 0 0 0 0 0 0 0 dB 1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 dB 2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 dB 3 5.35 2.48 1.49 1.2 1 0.83 0.69 dB 4 7.27 3.31 2 1.63 1.36 1.14 0.96 dB 5 — 4.19 2.55 2.1 1.76 1.49 1.26 dB 6 — 5.08 3.11 2.56 2.17 1.83 1.56 dB 7 — 5.99 3.71 3.06 2.58 2.18 1.87 dB 8 — 6.92 4.22 3.47 2.93 2.48 2.11 dB 9 — 7.92 4.86 4 3.38 2.87 2.46 dB 10 — 9.04 5.46 4.51 3.79 3.23 2.77 dB 11 — 10.2 6.09 5.01 4.23 3.61 — dB 12 — 11.56 6.74 5.51 4.68 3.97 — dB continued... Arria V Device Datasheet 40 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Intel Quartus Prime 1st Post Tap Pre-Emphasis Setting Intel Quartus Prime VOD Setting Unit 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 13 — 12.9 7.44 6.1 5.12 4.36 — dB 14 — 14.44 8.12 6.64 5.57 4.76 — dB 15 — — 8.87 7.21 6.06 5.14 — dB 16 — — 9.56 7.73 6.49 — — dB 17 — — 10.43 8.39 7.02 — — dB 18 — — 11.23 9.03 7.52 — — dB 19 — — 12.18 9.7 8.02 — — dB 20 — — 13.17 10.34 8.59 — — dB 21 — — 14.2 11.1 — — — dB 22 — — 15.38 11.87 — — — dB 23 — — — 12.67 — — — dB 24 — — — 13.48 — — — dB 25 — — — 14.37 — — — dB 26 — — — — — — — dB 27 — — — — — — — dB 28 — — — — — — — dB 29 — — — — — — — dB 30 — — — — — — — dB 31 — — — — — — — dB Related Information SPICE Models for Intel Devices Provides the Arria V HSSI HSPICE models. Send Feedback Arria V Device Datasheet 41 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.1.7. Transceiver Compliance Specification The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Arria V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Intel Sales Representative. Table 34. Transceiver Compliance Specification for All Supported Protocol for Arria V GX, GT, SX, and ST Devices Protocol PCIe XAUI Serial RapidIO® (SRIO) Common Public Radio Interface (CPRI) Sub-protocol Data Rate (Mbps) PCIe Gen1 2,500 PCIe Gen2 5,000 PCIe Cable 2,500 XAUI 2135 3,125 SRIO 1250 SR 1,250 SRIO 1250 LR 1,250 SRIO 2500 SR 2,500 SRIO 2500 LR 2,500 SRIO 3125 SR 3,125 SRIO 3125 LR 3,125 SRIO 5000 SR 5,000 SRIO 5000 MR 5,000 SRIO 5000 LR 5,000 SRIO_6250_SR 6,250 SRIO_6250_MR 6,250 SRIO_6250_LR 6,250 CPRI E6LV 614.4 CPRI E6HV 614.4 CPRI E6LVII 614.4 CPRI E12LV 1,228.8 continued... Arria V Device Datasheet 42 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Protocol Sub-protocol Data Rate (Mbps) CPRI E12HV 1,228.8 CPRI E12LVII 1,228.8 CPRI E24LV 2,457.6 CPRI E24LVII 2,457.6 CPRI E30LV 3,072 CPRI E30LVII 3,072 CPRI E48LVII 4,915.2 CPRI E60LVII 6,144 CPRI E96LVIII(60) 9,830.4 Gbps Ethernet (GbE) GbE 1250 1,250 OBSAI OBSAI 768 768 OBSAI 1536 1,536 OBSAI 3072 3,072 OBSAI 6144 6,144 SDI 270 SD 270 SDI 1485 HD 1,485 SDI 2970 3G 2,970 SONET 155 155.52 SONET 622 622.08 SONET 2488 2,488.32 GPON 155 155.52 GPON 622 622.08 Serial digital interface (SDI) SONET Gigabit-capable passive optical network (GPON) continued... (60) You can achieve compliance with TX channel restriction of one HSSI channel per six-channel transceiver bank. Send Feedback Arria V Device Datasheet 43 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Protocol QSGMII Sub-protocol Data Rate (Mbps) GPON 1244 1,244.16 GPON 2488 2,488.32 QSGMII 5000 5,000 1.2.2. Core Performance Specifications 1.2.2.1. Clock Tree Specifications Table 35. Clock Tree Specifications for Arria V Devices Parameter Performance Unit –I3, –C4 –I5, –C5 –C6 Global clock and Regional clock 625 625 525 MHz Peripheral clock 450 400 350 MHz 1.2.2.2. PLL Specifications Table 36. PLL Specifications for Arria V Devices This table lists the Arria V PLL block specifications. Arria V PLL block does not include HPS PLL. Symbol fIN fINPFD Parameter Input clock frequency Integer input clock frequency to the phase frequency detector (PFD) Condition Min Typ Max Unit –3 speed grade 5 — 800(61) MHz –4 speed grade 5 — 800(61) MHz –5 speed grade 5 — 750(61) MHz –6 speed grade 5 — 625(61) MHz — 5 — 325 MHz continued... (61) This specification is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. Arria V Device Datasheet 44 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol fFINPFD (62) fVCO Parameter Fractional input clock frequency to the PFD PLL voltage-controlled oscillator (VCO) operating range tEINDUTY Input clock or external feedback clock input duty cycle fOUT Output frequency for internal global or regional clock fOUT_EXT Output frequency for external clock output Condition Min Typ Max Unit — 50 — 160 MHz –3 speed grade 600 — 1600 MHz –4 speed grade 600 — 1600 MHz –5 speed grade 600 — 1600 MHz –6 speed grade 600 — 1300 MHz — 40 — 60 % –3 speed grade — — 500(63) MHz MHz –4 speed grade — — 500(63) –5 speed grade — — 500(63) MHz –6 speed grade — — 400(63) MHz –3 speed grade — — 670(63) MHz –4 speed grade — — 670(63) MHz –5 speed grade — — 622(63) MHz –6 speed grade — — 500(63) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) — 45 50 55 % tFCOMP External feedback clock compensation time — — — 10 ns tDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 100 MHz tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms continued... (62) The VCO frequency reported by the Intel Quartus Prime software takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification. (63) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL. Send Feedback Arria V Device Datasheet 45 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-postscale counters/delays) fCLBW PLL closed-loop bandwidth Condition Min Typ Max Unit — — — 1 ms Low — 0.3 — MHz Medium — 1.5 — MHz High(64) — 4 — MHz tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps tARESET Minimum pulse width on the areset signal — 10 — — ns FREF ≥ 100 MHz — — 0.15 UI (p-p) FREF < 100 MHz — — ±750 ps (p-p) FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) (65)(66) tINCCJ tOUTPJ_DC(67) tFOUTPJ_DC(67) Input clock cycle-to-cycle jitter Period jitter for dedicated clock output in integer PLL Period jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz FOUT < 100 MHz — — — 250(68), — 25(68), 175(69) 17.5(69) ps (p-p) mUI (p-p) continued... (64) High bandwidth PLL settings are not supported in external feedback mode. (65) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (66) FREF is fIN/N, specification applies when N = 1. (67) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Arria V Devices table. (68) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz. (69) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz. Arria V Device Datasheet 46 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol (67) tOUTCCJ_DC (67) tFOUTCCJ_DC tOUTPJ_IO(67)(70) tFOUTPJ_IO(67)(68)(70) tOUTCCJ_IO(67)(70) tFOUTCCJ_IO(67)(68)(70) tCASC_OUTPJ_DC(67)(71) Parameter Condition Min Typ Max Unit Cycle-to-cycle jitter for dedicated clock output in integer PLL FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) — 250(68), — — 25(68), — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) — — ±10 % Cycle-to-cycle jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz FOUT < 100 MHz Period jitter for clock output on a regular I/O in integer PLL FOUT ≥ 100 MHz Period jitter for clock output on a regular I/O in fractional PLL Cycle-to-cycle jitter for clock output on a regular I/O in integer PLL Cycle-to-cycle jitter for clock output on a regular I/O in fractional PLL Period jitter for dedicated clock output in cascaded PLLs — 175(69) 17.5(69) ps (p-p) mUI (p-p) tDRIFT Frequency drift after PFDENA is disabled for a duration of 100 µs — dKBIT Bit number of Delta Sigma Modulator (DSM) — 8 24 32 bits kVALUE Numerator of fraction — 128 8388608 2147483648 — fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz (70) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Arria V Devices table. (71) The cascaded PLL specification is only applicable with the following conditions: • Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz • Downstream PLL: Downstream PLL BW > 2 MHz Send Feedback Arria V Device Datasheet 47 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Related Information Memory Output Clock Jitter Specifications on page 56 Provides more information about the external memory interface clock output jitter specifications. 1.2.2.3. DSP Block Performance Specifications Table 37. DSP Block Performance Specifications for Arria V Devices Mode Modes using One DSP Block Modes using Two DSP Blocks Performance Unit –I3, –C4 –I5, –C5 –C6 Independent 9 × 9 multiplication 370 310 220 MHz Independent 18 × 19 multiplication 370 310 220 MHz Independent 18 × 25 multiplication 370 310 220 MHz Independent 20 × 24 multiplication 370 310 220 MHz Independent 27 × 27 multiplication 310 250 200 MHz Two 18 × 19 multiplier adder mode 370 310 220 MHz 18 × 18 multiplier added summed with 36-bit input 370 310 220 MHz Complex 18 × 19 multiplication 370 310 220 MHz 1.2.2.4. Memory Block Performance Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Arria V Device Datasheet 48 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 38. Memory Block Performance Specifications for Arria V Devices Memory MLAB M10K Block Mode Resources Used Performance Unit ALUTs Memory –I3, –C4 –I5, –C5 –C6 Single port, all supported widths 0 1 500 450 400 MHz Simple dual-port, all supported widths 0 1 500 450 400 MHz Simple dual-port with read and write at the same address 0 1 400 350 300 MHz ROM, all supported width — — 500 450 400 MHz Single-port, all supported widths 0 1 400 350 285 MHz Simple dual-port, all supported widths 0 1 400 350 285 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 315 275 240 MHz True dual port, all supported widths 0 1 400 350 285 MHz ROM, all supported widths 0 1 400 350 285 MHz 1.2.2.5. Internal Temperature Sensing Diode Specifications Table 39. Internal Temperature Sensing Diode Specifications for Arria V Devices Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time(72) Resolution Minimum Resolution with no Missing Codes –40 to 100°C ±8°C No 1 MHz < 100 ms 8 bits 8 bits Related Information Intel FPGA Temperature Sensor IP Core User Guide Provides more information about the temperature sensing operation. 1.2.3. Periphery Performance This section describes the periphery performance, high-speed I/O, and external memory interface. (72) For more details about the temperature sensing operations, refer to the Intel FPGA Temperature Sensor IP Core User Guide. Send Feedback Arria V Device Datasheet 49 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. 1.2.3.1. High-Speed I/O Specifications Table 40. High-Speed I/O Specifications for Arria V Devices When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. The Arria V devices support the following output standards using true LVDS output buffer types on all I/O banks. • True RSDS output standard with data rates of up to 360 Mbps • True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition –I3, –C4 –I5, –C5 –C6 Unit Min Typ Max Min Typ Max Min Typ Max fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40(73) 5 — 800 5 — 750 5 — 625 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards(74) Clock boost factor W = 1 to 40(73) 5 — 625 5 — 625 5 — 500 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards(75) Clock boost factor W = 1 to 40(73) 5 — 420 5 — 420 5 — 420 MHz — 5 — 625(76) 5 — 625(76 5 — 500(76) MHz SERDES factor J =3 to 10(77) (78) — 1250 (78) — 1250 (78) — 1050 Mbp s fHSCLK_OUT (output clock frequency) Transmitter True Differential I/O Standards - fHSDR (data rate) ) continued... (73) Clock boost factor (W) is the ratio between the input data rate and the input clock rate. (74) This applies to DPA and soft-CDR modes only. (75) This applies to non-DPA mode only. (76) This is achieved by using the LVDS clock network. Arria V Device Datasheet 50 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Condition –I3, –C4 Min Max Min — 1600 (78) (78) — (80) SERDES factor J = 4 to 10(82) (78) — SERDES factor J = 4 to 10(82) (78) Total Jitter for Data Rate 600 Mbps – 1.25 Gbps Total Jitter for Data Rate < 600 Mbps Unit Min Typ Max — 1500 (78) — 1250 Mbp s (78) — (80) (78) — (80) Mbp s 945 (78) — 945 (78) — 945 Mbp s — 200 (78) — 200 (78) — 200 Mbp s — — 160 — — 160 — — 160 ps — — 0.1 — — 0.1 — — 0.1 UI SERDES factor J ≥ (79), LVDS TX with RX DPA (78) SERDES factor J = 1 to 2, Uses DDR Registers Emulated Differential I/O Standards with Three External Output Resistor Network - fHSDR (data rate) Emulated Differential I/O Standards with One External Output Resistor Network fHSDR (data rate)(81) Typ –C6 Max 8(77) Typ –I5, –C5 (81) tx Jitter -True Differential I/O Standards continued... (77) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (78) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. (79) The VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface. (80) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT), provided you can close the design timing and the signal integrity simulation is clean. (81) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. (82) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported. Send Feedback Arria V Device Datasheet 51 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol –I3, –C4 –I5, –C5 –C6 Unit Min Typ Max Min Typ Max Min Typ Max tx Jitter -Emulated Differential I/O Standards with Three External Output Resistor Network Total Jitter for Data Rate 600 Mbps – 1.25 Gbps — — 260 — — 300 — — 350 ps Total Jitter for Data Rate < 600 Mbps — — 0.16 — — 0.18 — — 0.21 UI tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network — — — 0.15 — — 0.15 — — 0.15 UI TX output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 45 50 55 % True Differential I/O Standards(83) — — 160 — — 180 — — 200 ps Emulated Differential I/O Standards with Three External Output Resistor Network — — 250 — — 250 — — 300 ps Emulated Differential I/O Standards with One External Output Resistor Network — — 500 — — 500 — — 500 ps True Differential I/O Standards — — 150 — — 150 — — 150 ps Emulated Differential I/O Standards — — 300 — — 300 — — 300 ps SERDES factor J =3 to 10(77) 150 — 1250 150 — 1250 150 — 1050 Mbp s SERDES factor J ≥ 8 with DPA(77)(79) 150 — 1600 150 — 1500 150 — 1250 Mbp s tDUTY tRISE and tFALL TCCS Receiver Condition True Differential I/O Standards - fHSDRDPA (data rate) continued... (83) This applies to default pre-emphasis and VOD settings only. Arria V Device Datasheet 52 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Condition –I3, –C4 Min fHSDR (data rate) –I5, –C5 –C6 Unit Typ Max Min Typ Max Min Typ Max SERDES factor J = 3 to 10 (78) — (84) (78) — (84) (78) — (84) Mbp s SERDES factor J = 1 to 2, uses DDR registers (78) — (80) (78) — (80) (78) — (80) Mbp s DPA Mode DPA run length — — — 10000 — — 10000 — — 10000 UI Soft-CDR Mode Soft-CDR ppm tolerance — — — 300 — — 300 — — 300 ±pp m Non-DPA Mode Sampling Window — — — 300 — — 300 — — 300 ps 1.2.3.2. DPA Lock Time Specifications Figure 5. Dynamic Phase Alignment (DPA) Lock Time Specifications with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 Data Transitions (84) 96 Slow Clock Cycles 256 Data Transitions 96 Slow Clock Cycles 256 Data Transitions You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Send Feedback Arria V Device Datasheet 53 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 41. DPA Lock Time Specifications for Arria V Devices The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1to-0 transition. Standard SPI-4 Parallel Rapid I/O Miscellaneous Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions(85) Maximum Data Transition 00000000001111111111 2 128 640 00001111 2 128 640 10010000 4 64 640 10101010 8 32 640 01010101 8 32 640 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications LVDS Soft-Clock Data Recovery (CDR)/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps Jitter Amphlitude (UI) Figure 6. 25 8.5 0.35 0.1 F1 F2 (85) F4 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Arria V Device Datasheet 54 F3 Jitter Frequency (Hz) Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 42. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps Jitter Frequency (Hz) Figure 7. Sinusoidal Jitter (UI) F1 10,000 25.000 F2 17,565 25.000 F3 1,493,000 0.350 F4 50,000,000 0.350 LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P baud/1667 20 MHz Frequency 1.2.3.4. DLL Frequency Range Specifications Table 43. DLL Frequency Range Specifications for Arria V Devices Parameter DLL operating frequency range Send Feedback –I3, –C4 –I5, –C5 –C6 Unit 200 – 667 200 – 667 200 – 667 MHz Arria V Device Datasheet 55 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.3.5. DQS Logic Block Specifications Table 44. DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria V Devices This error specification is the absolute maximum and minimum error. Number of DQS Delay Buffer –I3, –C4 –I5, –C5 –C6 Unit 2 40 80 80 ps 1.2.3.6. Memory Output Clock Jitter Specifications Table 45. Memory Output Clock Jitter Specifications for Arria V Devices The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma. Intel recommends using the UniPHY IP cores with PHYCLK connections for better jitter performance. Parameter Clock Network Symbol Clock period jitter PHYCLK tJIT(per) Cycle-to-cycle period jitter PHYCLK tJIT(cc) –I3, –C4 –I5, –C5 –C6 Unit Min Max Min Max Min Max –41 41 –50 50 –55 55 63 90 ps 94 ps 1.2.3.7. OCT Calibration Block Specifications Table 46. OCT Calibration Block Specifications for Arria V Devices Symbol Min Typ Max Unit OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT/RT OCT calibration — 1000 — Cycles TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out — 32 — Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT — 2.5 — ns Arria V Device Datasheet 56 Description Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 8. Timing Diagram for oe and dyn_term_ctrl Signals RX Tristate Tristate TX RX oe dyn_term_ctrl TRS_RT TRS_RT 1.2.3.8. Duty Cycle Distortion (DCD) Specifications Table 47. Worst-Case DCD on Arria V I/O Pins The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD. Symbol Output Duty Cycle –I3, –C4 –C5, –I5 –C6 Unit Min Max Min Max Min Max 45 55 45 55 45 55 % 1.2.4. HPS Specifications This section provides HPS specifications and timing for Arria V devices. For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1. Send Feedback Arria V Device Datasheet 57 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.4.1. HPS Clock Performance Table 48. HPS Clock Performance for Arria V Devices Symbol/Description –I3 –C4 –C5, –I5 –C6 Unit mpu_base_clk (microprocessor unit clock) 1050 925 800 700 MHz main_base_clk (L3/L4 interconnect clock) 400 400 400 350 MHz h2f_user0_clk 100 100 100 100 MHz h2f_user1_clk 100 100 100 100 MHz h2f_user2_clk 200 200 200 160 MHz 1.2.4.2. HPS PLL Specifications 1.2.4.2.1. HPS PLL VCO Frequency Range Table 49. HPS PLL VCO Frequency Range for Arria V Devices Description VCO range Speed Grade Minimum Maximum Unit –C5, –I5, –C6 320 1,600 MHz –C4 320 1,850 MHz –I3 320 2,100 MHz 1.2.4.2.2. HPS PLL Input Clock Range The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs. Related Information Clock Select, Booting and Configuration chapter Provides more information about the clock range for different values of clock select (CSEL). 1.2.4.2.3. HPS PLL Input Jitter Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64. Arria V Device Datasheet 58 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Maximum input jitter = Input clock period × Divide value (N) × 0.02 Table 50. Examples of Maximum Input Jitter Input Reference Clock Period Divide Value (N) Maximum Jitter Unit 40 ns 1 0.8 ns 40 ns 2 1.6 ns 40 ns 4 3.2 ns 1.2.4.3. Quad SPI Flash Timing Characteristics Table 51. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices Symbol Fclk Description SCLK_OUT clock frequency (External clock) Min Typ Max Unit — — 108 MHz Tqspi_clk QSPI_CLK clock period (Internal reference clock) 2.32 — — ns Tdutycycle SCLK_OUT duty cycle 45 — 55 % Tdssfrst Output delay QSPI_SS valid before first clock edge — 1/2 cycle of SCLK_OUT — ns Tdsslst Output delay QSPI_SS valid after last clock edge –1 — 1 ns Tdio I/O data output delay –1 — 1 ns Tdin_start Input data valid start — — (2 + Rdelay) × Tqspi_clk – 7.52 (86) ns Tdin_end Input data valid end (2 + Rdelay) × Tqspi_clk – 1.21 (86) — — ns (86) Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Intel provides automatic Quad SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Arria V Hard Processor System Technical Reference Manual. Send Feedback Arria V Device Datasheet 59 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 9. Quad SPI Flash Timing Diagram This timing diagram illustrates clock polarity mode 0 and clock phase mode 0. Tdsslst QSPI_SS Tdssfrst SCLK_OUT Tdio Data Out QSPI_DATA Tdin_start Data In Tdin_end Related Information Quad SPI Flash Controller Chapter, Arria V Hard Processor System Technical Reference Manual Provides more information about Rdelay. 1.2.4.4. SPI Timing Characteristics Table 52. SPI Master Timing Requirements for Arria V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Symbol Tclk Description CLK clock period Tsu SPI Master-in slave-out (MISO) setup time Th SPI MISO hold time Min Max Unit 16.67 — ns — ns 8.35 1 (87) — ns continued... (87) This value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_OUT. These timings are based on rx_sample_dly of 1. This delay can be adjusted as needed to accommodate slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_sample_dly value because each SPI slave device may have different output delay and each application board may have different path delay. For more information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual. Arria V Device Datasheet 60 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Description Min Max Unit 45 55 % Tdutycycle SPI_CLK duty cycle Tdssfrst Output delay SPI_SS valid before first clock edge 8 — ns Tdsslst Output delay SPI_SS valid after last clock edge 8 — ns Tdio Master-out slave-in (MOSI) output delay –1 1 ns Figure 10. SPI Master Timing Diagram Tdsslst SPI_SS SPI_CLK (scpol = 0) Tdssfrst SPI_CLK (scpol = 1) Tdio SPI_MOSI (scph = 1) Tsu Th SPI_MISO (scph = 1) Tdio SPI_MOSI (scph = 0) Tsu Th SPI_MISO (scph = 0) Send Feedback Arria V Device Datasheet 61 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 53. SPI Slave Timing Requirements for Arria V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Symbol Min Max Unit Tclk CLK clock period 20 — ns Ts MOSI Setup time 5 — ns Th MOSI Hold time 5 — ns Tsuss Setup time SPI_SS valid before first clock edge 8 — ns Thss Hold time SPI_SS valid after last clock edge 8 — ns Td MISO output delay — 6 ns Arria V Device Datasheet 62 Description Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 11. SPI Slave Timing Diagram Thss SPI_SS Tsuss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) Td SPI_MISO (scph = 1) Ts Th SPI_MOSI (scph = 1) Td SPI_MISO (scph = 0) Ts Th SPI_MOSI (scph = 0) Related Information SPI Controller, Arria V Hard Processor System Technical Reference Manual Provides more information about rx_sample_delay. Send Feedback Arria V Device Datasheet 63 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.4.5. SD/MMC Timing Characteristics Table 54. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz. After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager. drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase to a maximum of 200 MHz and 50 MHz respectively. Symbol Min Max Unit SDMMC_CLK clock period (Identification mode) 20 — ns SDMMC_CLK clock period (Default speed mode) 5 — ns SDMMC_CLK clock period (High speed mode) 5 — ns 2500 — ns SDMMC_CLK_OUT clock period (Default speed mode) 40 — ns SDMMC_CLK_OUT clock period (High speed mode) 20 — ns Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 % Td SDMMC_CMD/SDMMC_D output delay (Tsdmmc_clk × drvsel)/2 – 1.23 (Tsdmmc_clk × drvsel)/2 + 1.69 (88) ns Tsu Input setup time 1.05 – (Tsdmmc_clk × smplsel)/2 — ns Th Input hold time — ns Tsdmmc_clk (internal reference clock) Tsdmmc_clk_out (interface output clock) Description SDMMC_CLK_OUT clock period (Identification mode) (88) (89) (88) drvsel is the drive clock phase shift select value. (89) smplsel is the sample clock phase shift select value. Arria V Device Datasheet 64 (Tsdmmc_clk × smplsel)/2 (89) Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 12. SD/MMC Timing Diagram SDMMC_CLK_OUT Td SDMMC_CMD & SDMMC_D (Out) Command/Data Out Tsu Th SDMMC_CMD & SDMMC_D (In) Command/Data In Related Information Booting and Configuration Chapter, Arria V Hard Processor System Technical Reference Manual Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table. 1.2.4.6. USB Timing Characteristics PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Table 55. USB Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit — 16.67 — ns 4.4 — 11 ns Tclk USB CLK clock period Td CLK to USB_STP/USB_DATA[7:0] output delay Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 — — ns Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 — — ns Send Feedback Arria V Device Datasheet 65 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 13. USB Timing Diagram USB_CLK USB_STP USB_DATA[7:0] Td From PHY To PHY Tsu Th USB_DIR & USB_NXT 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics Table 56. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit Tclk (1000Base-T) TX_CLK clock period — 8 — ns Tclk (100Base-T) TX_CLK clock period — 40 — ns Tclk (10Base-T) TX_CLK clock period — 400 — ns Tdutycycle TX_CLK duty cycle 45 — 55 % Td TX_CLK to TXD/TX_CTL output data delay –0.85 — 0.15 ns Figure 14. RGMII TX Timing Diagram TX_CLK TX_D[3:0] Td TX_CTL Arria V Device Datasheet 66 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Table 57. RGMII RX Timing Requirements for Arria V Devices Symbol Description Min Typ Unit Tclk (1000Base-T) RX_CLK clock period — 8 ns Tclk (100Base-T) RX_CLK clock period — 40 ns Tclk (10Base-T) RX_CLK clock period — 400 ns Tsu RX_D/RX_CTL setup time 1 — ns Th RX_D/RX_CTL hold time 1 — ns Figure 15. RGMII RX Timing Diagram RX_CLK Tsu Th RX_D[3:0] RX_CTL Table 58. Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices Symbol Description Min Typ Max Unit Tclk MDC clock period — 400 — ns Td MDC to MDIO output data delay 10 — 20 ns Ts Setup time for MDIO data 10 — — ns Th Hold time for MDIO data 0 — — ns Send Feedback Arria V Device Datasheet 67 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 16. MDIO Timing Diagram MDC Td MDIO_OUT Tsu Th MDIO_IN 1.2.4.8. I2C Timing Characteristics Table 59. I2C Timing Requirements for Arria V Devices Symbol Standard Mode Fast Mode Unit Min Max Min Max Tclk Serial clock (SCL) clock period 10 — 2.5 — µs Tclkhigh SCL high time 4.7 — 0.6 — µs Tclklow SCL low time 4 — 1.3 — µs Ts Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — µs Th Hold time for SCL to SDA data 0 3.45 0 0.9 µs Td SCL to SDA output data delay — 0.2 — 0.2 µs Tsu_start Setup time for a repeated start condition 4.7 — 0.6 — µs Thd_start Hold time for a repeated start condition 4 — 0.6 — µs Tsu_stop Setup time for a stop condition 4 — 0.6 — µs Arria V Device Datasheet 68 Description Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 17. I2C Timing Diagram I2C_SCL Td Ts Tsu_start Thd_start Data Out I2C_SDA Tsu_stop Th Data In 1.2.4.9. NAND Timing Characteristics Table 60. NAND ONFI 1.0 Timing Requirements for Arria V Devices The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. This table lists the requirements for ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL and timing registers provided in the NAND controller. Symbol Description (90) Write enable pulse width (90) Write enable hold time Twp Twh (90) Trp Treh(90) (90) Read enable pulse width Read enable hold time Tclesu Command latch enable to write enable setup time Tcleh(90) Command latch enable to write enable hold time Tcesu(90) Chip enable to write enable setup time Tceh(90) Chip enable to write enable hold time Talesu(90) Address latch enable to write enable setup time Taleh(90) Address latch enable to write enable hold time Tdsu(90) Data to write enable setup time Tdh(90) Data to write enable hold time Min Max Unit 10 — ns 7 — ns 10 — ns 7 — ns 10 — ns 5 — ns 15 — ns 5 — ns 10 — ns 5 — ns 10 — ns 5 — ns continued... (90) Timing of the NAND interface is controlled through the NAND configuration registers. Send Feedback Arria V Device Datasheet 69 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Description Min Max Unit Tcea Chip enable to data access time — 25 ns Trea Read enable to data access time — 16 ns Trhz Read enable to data high impedance — 100 ns Trr Ready to read enable low 20 — ns Figure 18. NAND Command Latch Timing Diagram NAND_CLE NAND_CE Tclesu Tcesu Tcleh Twp Tceh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Arria V Device Datasheet 70 Tdh Command Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 19. NAND Address Latch Timing Diagram NAND_CLE NAND_CE Tcesu Tclesu Twp Twh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Send Feedback Tdh Address Arria V Device Datasheet 71 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 20. NAND Data Write Timing Diagram NAND_CLE NAND_CE Tcleh Twp Tceh NAND_WE Talesu NAND_ALE Tdsu Tdh NAND_DQ[7:0] Arria V Device Datasheet 72 Din Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Figure 21. NAND Data Read Timing Diagram Tcea NAND_CE Trr Trp Treh NAND_RE Trhz NAND_RB Trea NAND_DQ[7:0] Dout 1.2.4.10. Arm Trace Timing Characteristics Table 61. Arm Trace Timing Requirements for Arria V Devices Most debugging tools have a mechanism to adjust the capture point of trace data. Description Min Max Unit 12.5 — ns CLK maximum duty cycle 45 55 % CLK to D0 –D7 output data delay –1 1 ns CLK clock period 1.2.4.11. UART Interface The maximum UART baud rate is 6.25 megasymbols per second. 1.2.4.12. GPIO Interface The minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. The pulse width is based on a debounce clock frequency of 1 MHz. Send Feedback Arria V Device Datasheet 73 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.2.4.13. HPS JTAG Timing Specifications Table 62. HPS JTAG Timing Parameters and Values for Arria V Devices Symbol Description Min Max Unit tJCP TCK clock period 30 — ns tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) TDI JTAG port setup time 2 — ns tJPSU (TMS) TMS JTAG port setup time 3 — ns tJPH JTAG port hold time 5 — ns — 12(91) ns — 14(91) ns — 14(91) ns tJPCO JTAG port clock to output tJPZX JTAG port high impedance to valid output tJPXZ JTAG port valid output to high impedance 1.3. Configuration Specifications This section provides configuration specifications and timing for Arria V devices. 1.3.1. POR Specifications Table 63. Fast and Standard POR Delay Specification for Arria V Devices POR Delay Fast Standard Minimum Maximum Unit 4 12(92) ms 100 300 ms (91) A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. (92) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. Arria V Device Datasheet 74 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Related Information MSEL Pin Settings Provides more information about POR delay based on MSEL pin settings for each configuration scheme. 1.3.2. FPGA JTAG Configuration Timing Table 64. FPGA JTAG Timing Parameters and Values for Arria V Devices Symbol Description Min Unit — ns tJCP TCK clock period tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) TDI JTAG port setup time 2 — ns tJPSU (TMS) TMS JTAG port setup time 3 — ns tJPH JTAG port hold time 5 — ns — 12(94) ns ns ns tJPCO JTAG port clock to output 30, Max 167(93) tJPZX JTAG port high impedance to valid output — 14(94) tJPXZ JTAG port valid output to high impedance — 14(94) 1.3.3. FPP Configuration Timing 1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. (93) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming. (94) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Send Feedback Arria V Device Datasheet 75 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. Table 65. DCLK-to-DATA[] Ratio for Arria V Devices Configuration Scheme FPP (8-bit wide) FPP (16-bit wide) Encryption Compression DCLK-to-DATA[] Ratio (r) Off Off 1 On Off 1 Off On 2 On On 2 Off Off 1 On Off 2 Off On 4 On On 4 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria V Devices table. Table 66. FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506(95) µs continued... (95) You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width. Arria V Device Datasheet 76 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol tCF2ST1 Parameter nCONFIG high to nSTATUS high Minimum Maximum Unit — 1506(96) µs (97) nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK (97) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz tCD2UM CONF_DONE high to user mode(98) 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4× maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles tCF2CK Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (96) You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. (97) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (98) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Send Feedback Arria V Device Datasheet 77 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1 Table 67. FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices Use these timing parameters when you use the decompression and design security features. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506(99) µs tCF2ST1 nCONFIG high to nSTATUS high — 1506(100) µs (101) tCF2CK nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK(101) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK N – 1/fDCLK(102) — s tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz tR Input rise time — 40 ns tF Input fall time — 40 ns continued... (99) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (100) This value can be obtained if you do not delay configuration by externally holding nSTATUS low. (101) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (102) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system. Arria V Device Datasheet 78 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter Minimum Maximum Unit 175 437 µs 4 × maximum DCLK period — — mode(103) tCD2UM CONF_DONE high to user tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. 1.3.4. Active Serial (AS) Configuration Timing Table 68. AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Arria V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low. Symbol tCO (104) Parameter Condition Minimum Maximum Unit DCLK falling edge to the AS_DATA0/ASDO output — — 2 ns tSU(105) Data setup time before the falling edge on DCLK — 1.5 — ns tDH(105) Data hold time after the falling edge on DCLK –3 speed grade 1.7 — ns –4 speed grade 2.0 — ns continued... (103) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. (104) Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation. (105) To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline. Send Feedback Arria V Device Datasheet 79 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter Condition Minimum Maximum Unit –5 speed grade 2.3 — ns –6 speed grade 2.6 — ns tCD2UM CONF_DONE high to user mode — 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization — 8,576 — Cycles Related Information • Passive Serial (PS) Configuration Timing on page 81 • AS Configuration Timing Provides the AS configuration timing waveform. • Evaluating Data Setup and Hold Timing Slack chapter, AN822: Intel FPGA Configuration Device Migration Guideline 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme Table 69. DCLK Frequency Specification in the AS Configuration Scheme This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Parameter DCLK frequency in AS configuration scheme Arria V Device Datasheet 80 Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.3.6. Passive Serial (PS) Configuration Timing Table 70. PS Timing Parameters for Arria V Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506(106) µs — 1506(107) µs tCF2ST1 (108) nCONFIG high to nSTATUS high tCF2CK nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK(108) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency — 125 MHz tCD2UM CONF_DONE high to user mode(109) 175 437 µs continued... (106) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (107) You can obtain this value if you do not delay configuration by externally holding nSTATUS low. (108) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (109) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Send Feedback Arria V Device Datasheet 81 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter Minimum Maximum Unit 4 × maximum DCLK period — — tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Related Information PS Configuration Timing Provides the PS configuration timing waveform. 1.3.7. Initialization Table 71. Initialization Clock Source Option and the Maximum Frequency for Arria V Devices Initialization Clock Source Internal Oscillator CLKUSR(110) DCLK (110) Maximum Frequency (MHz) Minimum Number of Clock Cycles AS, PS, and FPP 12.5 Tinit PS and FPP 125 AS 100 PS and FPP 125 To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Intel Quartus Prime software from the General panel of the Device and Pin Options dialog box. Arria V Device Datasheet 82 Configuration Scheme Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.3.8. Configuration Files Table 72. Uncompressed .rbf Sizes for Arria V Devices Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Intel Quartus Prime software. However, for a specific version of the Intel Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature. Variant Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) Arria V GX A1 71,015,712 439,960 A3 71,015,712 439,960 A5 101,740,800 446,360 A7 101,740,800 446,360 B1 137,785,088 457,368 B3 137,785,088 457,368 B5 185,915,808 463,128 B7 185,915,808 463,128 C3 71,015,712 439,960 Arria V GT Arria V SX Arria V ST Send Feedback C7 101,740,800 446,360 D3 137,785,088 457,368 D7 185,915,808 463,128 B3 185,903,680 450,968 B5 185,903,680 450,968 D3 185,903,680 450,968 D5 185,903,680 450,968 Arria V Device Datasheet 83 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.3.9. Minimum Configuration Time Estimation Table 73. Minimum Configuration Time Estimation for Arria V Devices The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Arria V Devices table. Variant Arria V GX Arria V GT Arria V SX Arria V ST Active Serial(111) Member Code Fast Passive Parallel(112) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) A1 4 100 178 16 125 36 A3 4 100 178 16 125 36 A5 4 100 255 16 125 51 A7 4 100 255 16 125 51 B1 4 100 344 16 125 69 B3 4 100 344 16 125 69 B5 4 100 465 16 125 93 B7 4 100 465 16 125 93 C3 4 100 178 16 125 36 C7 4 100 255 16 125 51 D3 4 100 344 16 125 69 D7 4 100 465 16 125 93 B3 4 100 465 16 125 93 B5 4 100 465 16 125 93 D3 4 100 465 16 125 93 D5 4 100 465 16 125 93 (111) DCLK frequency of 100 MHz using external CLKUSR. (112) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Arria V Device Datasheet 84 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Related Information Configuration Files on page 83 1.3.10. Remote System Upgrades Table 74. Remote System Upgrade Circuitry Timing Specifications for Arria V Devices Parameter (113) tRU_nCONFIG (114) tRU_nRSTIMER Minimum Unit 250 ns 250 ns Related Information • Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal. • User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. 1.3.11. User Watchdog Internal Oscillator Frequency Specifications Table 75. User Watchdog Internal Oscillator Frequency Specifications for Arria V Devices Parameter User watchdog internal oscillator frequency Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 1.4. I/O Timing Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel Quartus Prime Timing Analyzer. (113) This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification. (114) This is equivalent to strobing the reset timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification. Send Feedback Arria V Device Datasheet 85 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information Arria V I/O Timing Spreadsheet Provides the Arria V Excel-based I/O timing spreadsheet. 1.4.1. Programmable IOE Delay Table 76. I/O element (IOE) Programmable Delay for Arria V Devices Parameter(115 Available Settings Minimum Offset(116) D1 32 D3 ) Fast Model Slow Model Unit Industrial Commercial –C4 –C5 –C6 –I3 –I5 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns 8 0 1.763 1.795 2.999 3.496 3.571 3.031 3.643 ns D4 32 0 0.508 0.518 0.869 1.063 1.063 1.063 1.057 ns D5 32 0 0.508 0.517 0.870 1.063 1.063 0.872 1.057 ns (115) You can set this value in the Intel Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor. (116) Minimum offset does not include the intrinsic delay. Arria V Device Datasheet 86 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.4.2. Programmable Output Buffer Delay Table 77. Programmable Output Buffer Delay for Arria V Devices This table lists the delay chain settings that control the rising and falling edge delays of the output buffer. You can set the programmable output buffer delay in the Intel Quartus Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Symbol DOUTBUF Parameter Rising and/or falling edge delay Typical Unit 0 (default) ps 50 ps 100 ps 150 ps 1.5. Glossary Table 78. Glossary Term Differential I/O standards Definition Receiver Input Waveforms continued... Send Feedback Arria V Device Datasheet 87 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Definition Single-Ended Waveform Positive Channel (p) = V IH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms continued... Arria V Device Datasheet 88 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Definition Single-Ended Waveform Positive Channel (p) = V OH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK Left/right PLL input clock frequency. fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI). J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG timing specifications JTAG Timing Specifications continued... Send Feedback Arria V Device Datasheet 89 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Definition TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX tJPCO t JPXZ TDO PLL specifications Diagram of PLL specifications continued... Arria V Device Datasheet 90 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Definition CLKOUT Pins Switchover CLK fOUT_EXT 4 fIN N fINPFD PFD Core Clock CP LF VCO fVCO Counters C0..C17 fOUT GCLK RCLK Delta Sigma Modulator Legend Reconfigurable in User Mode External Feedback Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. RL Receiver differential input discrete resistor (external to the Arria V device). Sampling window (SW) Timing diagram—The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS continued... Send Feedback Arria V Device Datasheet 91 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Single-ended voltage referenced I/O standard Definition The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80–20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input continued... Arria V Device Datasheet 92 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Term Definition tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20–80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage—The common mode of the differential signal at the receiver. VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage—The common mode of the differential signal at the transmitter. VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block—Clock boost factor Send Feedback Arria V Device Datasheet 93 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 1.6. Arria V GX, GT, SX, and ST Device Datasheet Revision History Document Version Changes 2019.04.26 • • Added a note for Conversion Time in the Internal Temperature Sensing Diode Specifications for Arria V Devices table. Updated tDH specifications in the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices table. 2019.01.25 • • Added Arria V Devices Overshoot Duration diagram. • Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices table. — Updated tDH specifications. These specifications are applicable to the commercial and industrial grade devices. — Added note to tCO, tSU, and tDH. Removed PowerPlay text from tool name. Renamed IP cores as per Intel rebranding. • • Date December 2016 Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Arria V Devices table. Version 2016.12.09 Changes • • • June 2016 2016.06.10 • • • • Updated VICM (AC coupled) specifications in Receiver Specifications for Arria V GX and SX Devices table. Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices table. Updated Tinit specifications in the following tables: — FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices — FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices — AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices — PS Timing Parameters for Arria V Devices Changed pin capacitance to maximum values. Updated SPI Master Timing Requirements for Arria V Devices table. — Added Tsu and Th specifications. — Removed Tdinmax specifications. Updated SPI Master Timing Diagram. Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Arria V Devices table. continued... Arria V Device Datasheet 94 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Date December 2015 Version 2015.12.16 Changes • • • • • • June 2015 2015.06.16 • • • • • • • • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices table. — Updated Fclk, Tdutycycle, and Tdssfrst specifications. — Added Tqspi_clk, Tdin_start, and Tdin_end specifications. — Removed Tdinmax specifications. Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Arria V Devices table. Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices table. — Updated T clk to Tsdmmc_clk_out symbol. — Updated Tsdmmc_clk_out and Td specifications. — Added Tsdmmc_clk, Tsu, and Th specifications. — Removed Tdinmax specifications. Updated the following diagrams: — Quad SPI Flash Timing Diagram — SD/MMC Timing Diagram Updated configuration .rbf sizes for Arria V devices. Changed instances of Quartus II to Quartus Prime. Added the supported data rates for the following output standards using true LVDS output buffer types in the High-Speed I/O Specifications for Arria V Devices table: — True RSDS output standard: data rates of up to 360 Mbps — True mini-LVDS output standard: data rates of up to 400 Mbps Added note in the condition for Transmitter—Emulated Differential I/O Standards fHSDR data rate parameter in the HighSpeed I/O Specifications for Arria V Devices table. Note: When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported. Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash. Updated Th location in I2C Timing Diagram. Updated Twp location in NAND Address Latch Timing Diagram. Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices table. Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices table. Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1 — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1 — AS Configuration Timing Waveform — PS Configuration Timing Waveform continued... Send Feedback Arria V Device Datasheet 95 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Date January 2015 Version 2015.01.30 Changes • • • • • • • • • • • • July 2014 3.8 • • • • • • • • • • Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply” in the following tables: — Absolute Maximum Ratings for Arria V Devices — HPS Power Supply Operating Conditions for Arria V SX and ST Devices Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. Updated HPS Clock Performance main_base_clk specifications from 525 MHz (for –I3 speed grade) and 462 MHz (for –C4 speed grade) to 400 MHz. Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C5, –I5, and –C6 speed grades), 1,850 MHz (for –C4 speed grade), and 2,100 MHz (for –I3 speed grade). Changed the symbol for HPS PLL input jitter divide value from NR to N. Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables: — SPI Master Timing Requirements for Arria V Devices — SPI Slave Timing Requirements for Arria V Devices Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Added HPS JTAG timing specifications. Updated FPGA JTAG timing specifications note as follows: A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Updated the value in the VICM (AC Coupled) row and in note 6 from 650 mV to 750 mV in the Transceiver Specifications for Arria V GT and ST Devices table. Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Updated VCC_HPS specification in Table 5. Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V. Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20 and Table 21. Updated description in “HPS PLL Specifications” section. Updated VCO range maximum specification in Table 39. Updated Td and Th specifications in Table 45. Added Th specification in Table 47 and Figure 13. Updated a note in Figure 20, Figure 21, and Figure 23 as follows: Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. Removed “Remote update only in AS mode” specification in Table 58. continued... Arria V Device Datasheet 96 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Date Version Changes • • Added DCLK device initialization clock source specification in Table 60. • Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature. Removed fMAX_RU_CLK specification in Table 63. February 2014 3.7 • • Updated VCCRSTCLK_HPS maximum specification in Table 1. Added VCC_AUX_SHARED specification in Table 1. December 2013 3.6 • • • • • Added “HPS PLL Specifications”. Added Table 24, Table 39, and Table 40. Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, Table 51, Table 55, Table 56, and Table 59. Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19. Removed table: GPIO Pulse Width for Arria V Devices. August 2013 3.5 • • Removed “Pending silicon characterization” note in Table 29. Updated Table 25. August 2013 3.4 • Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 30, Table 31, Table 35, Table 36, Table 51, Table 53, Table 54, Table 55, Table 56, Table 57, Table 60, Table 62, and Table 64. Updated Table 1, Table 3, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, and Table 29. • June 2013 3.3 Updated Table 20, Table 21, Table 25, and Table 38. May 2013 3.2 • • • March 2013 3.1 • Added Table 37. Updated Figure 8, Figure 9, Figure 20, Figure 22, and Figure 23. Updated Table 1, Table 5, Table 10, Table 13, Table 19, Table 20, Table 21, Table 23, Table 29, Table 39, Table 40, Table 46, Table 56, Table 57, Table 60, and Table 64. Updated industrial junction temperature range for –I3 speed grade in “PLL Specifications” section. • • • • Added HPS reset information in the “HPS Specifications” section. Added Table 60. Updated Table 1, Table 3, Table 17, Table 20, Table 29, and Table 59. Updated Figure 21. continued... Send Feedback Arria V Device Datasheet 97 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Date November 2012 Version 3.0 Changes • • • Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21, Table 25, Table 29, Table 36, Table 56, Table 57, and Table 60. Removed table: Transceiver Block Jitter Specifications for Arria V Devices. Added HPS information: — Added “HPS Specifications” section. — Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, and Table 50. — Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, and Figure 19. — Updated Table 3 and Table 5. October 2012 2.4 • • Updated Arria V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum values, and data rate in Table 4. Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM (AC coupled) and VOCM (DC coupled) values in Table 20 and Table 21. August 2012 2.3 Updated the SERDES factor condition in Table 30. July 2012 2.2 • • • • • June 2012 2.1 Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4. June 2012 2.0 • • • • • • • Updated for the Quartus II software v12.0 release: Restructured document. Updated “Supply Current and Power Consumption” section. Updated Table 20, Table 21, Table 24, Table 25, Table 26, Table 35, Table 39, Table 43, and Table 52. Added Table 22, Table 23, and Table 33. Added Figure 1–1 and Figure 1–2. Added “Initialization” and “Configuration Files” sections. February 2012 1.3 • • • Updated Table 2–1. Updated Transceiver-FPGA Fabric Interface rows in Table 2–20. Updated VCCP description. Updated Updated Updated Updated Updated the maximum voltage for VI (DC input voltage) in Table 1. Table 20 to include the Arria V GX -I3 speed grade. the minimum value of the fixedclk clock frequency in Table 20 and Table 21. the SERDES factor condition in Table 30. Table 50 to include the IOE programmable delay settings for the Arria V GX -I3 speed grade. continued... Arria V Device Datasheet 98 Send Feedback 1. Arria® V GX, GT, SX, and ST Device Datasheet AV-51002 | 2019.04.26 Date Version Changes December 2011 1.2 Updated Table 2–1 and Table 2–3. November 2011 1.1 • • • August 2011 1.0 Initial release. Send Feedback Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36. Added Table 2–5. Added Figure 2–4. Arria V Device Datasheet 99 AV-51002 | 2019.04.26 Send Feedback 2. Arria V GZ Device Datasheet This document covers the electrical and switching characteristics for Arria V GZ devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This document also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. Related Information Arria V Device Overview For information regarding the densities and packages of devices in the Arria V GZ family. 2.1. Electrical Characteristics 2.1.1. Operating Conditions When you use Arria V GZ devices, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria V GZ devices, you must consider the operating requirements described in this datasheet. Arria V GZ devices are offered in commercial and industrial temperature grades. Commercial devices are offered in –3 (fastest) and –4 core speed grades. Industrial devices are offered in –3L and –4 core speed grades. Arria V GZ devices are offered in –2 and –3 transceiver speed grades. Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 79. Commercial and Industrial Speed Grade Offering for Arria V GZ Devices C = Commercial temperature grade; I = Industrial temperature grade. Lower number refers to faster speed grade. L = Low power devices. Transceiver Speed Grade Core Speed Grade C3 C4 I3L I4 2 Yes — Yes — 3 — Yes — Yes 2.1.1.1. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Arria V GZ devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions other than those listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 80. Absolute Maximum Ratings for Arria V GZ Devices Symbol Description Minimum Maximum Unit VCC Power supply for core voltage and periphery circuitry –0.5 1.35 V VCCPT Power supply for programmable power technology –0.5 1.8 V VCCPGM Power supply for configuration pins –0.5 3.9 V VCC_AUX Auxiliary supply for the programmable power technology –0.5 3.4 V VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.9 V VCCPD I/O pre-driver power supply –0.5 3.9 V VCCIO I/O power supply –0.5 3.9 V VCCD_FPLL PLL digital power supply –0.5 1.8 V VCCA_FPLL PLL analog power supply –0.5 3.4 V continued... Send Feedback Arria V Device Datasheet 101 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Description Minimum Maximum Unit VI DC input voltage –0.5 3.8 V TJ Operating junction temperature –55 125 °C TSTG Storage temperature (No bias) –65 150 °C IOUT DC output current per pin –25 40 mA Table 81. Transceiver Power Supply Absolute Conditions for Arria V GZ Devices Symbol Description Minimum Maximum Unit VCCA_GXBL Transceiver channel PLL power supply (left side) –0.5 3.75 V VCCA_GXBR Transceiver channel PLL power supply (right side) –0.5 3.75 V VCCHIP_L Transceiver hard IP power supply (left side) –0.5 1.35 V VCCHSSI_L Transceiver PCS power supply (left side) –0.5 1.35 V VCCHSSI_R Transceiver PCS power supply (right side) –0.5 1.35 V VCCR_GXBL Receiver analog power supply (left side) –0.5 1.35 V VCCR_GXBR Receiver analog power supply (right side) –0.5 1.35 V VCCT_GXBL Transmitter analog power supply (left side) –0.5 1.35 V VCCT_GXBR Transmitter analog power supply (right side) –0.5 1.35 V VCCH_GXBL Transmitter output buffer power supply (left side) –0.5 1.8 V VCCH_GXBR Transmitter output buffer power supply (right side) –0.5 1.8 V 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in the following table. They may also undershoot to – 2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% of the duty cycle. For example, a signal that overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for a device lifetime of 10 years, the overshoot duration amounts to ~2 years. Arria V Device Datasheet 102 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 82. Maximum Allowed Overshoot During Transitions for Arria V GZ Devices Symbol Vi (AC) Description AC input voltage Condition (V) Overshoot Duration as % @ TJ = 100°C Unit 3.8 100 % 3.85 64 % 3.9 36 % 3.95 21 % 4 12 % 4.05 7 % 4.1 4 % 4.15 2 % 4.2 1 % For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. Figure 22. Arria V GZ Devices Overshoot Duration 4V 3.95V 3.3 V DT T Send Feedback Arria V Device Datasheet 103 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.1.1.3. Recommended Operating Conditions Table 83. Recommended Operating Conditions for Arria V GZ Devices Power supply ramps must all be strictly monotonic, without plateaus. Symbol Description (118) Condition Minimum(117) Typical — 0.82 0.85 0.88 V Maximum (117) Unit VCC Core voltage and periphery circuitry power supply VCCPT Power supply for programmable power technology — 1.45 1.50 1.55 V Auxiliary supply for the programmable power technology — 2.375 2.5 2.625 V I/O pre-driver (3.0 V) power supply — 2.85 3.0 3.15 V I/O pre-driver (2.5 V) power supply — 2.375 2.5 2.625 V I/O buffers (3.0 V) power supply — 2.85 3.0 3.15 V I/O buffers (2.5 V) power supply — 2.375 2.5 2.625 V I/O buffers (1.8 V) power supply — 1.71 1.8 1.89 V I/O buffers (1.5 V) power supply — 1.425 1.5 1.575 V I/O buffers (1.35 V) power supply — 1.283 1.35 1.45 V I/O buffers (1.25 V) power supply — 1.19 1.25 1.31 V I/O buffers (1.2 V) power supply — 1.14 1.2 1.26 V Configuration pins (3.0 V) power supply — 2.85 3.0 3.15 V Configuration pins (2.5 V) power supply — 2.375 2.5 2.625 V Configuration pins (1.8 V) power supply — 1.71 1.8 1.89 V PLL analog voltage regulator power supply — 2.375 2.5 2.625 VCC_AUX VCCPD (119) VCCIO VCCPGM VCCA_FPLL V continued... (117) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (118) The VCC core supply must be set to 0.9 V if the Partial Reconfiguration (PR) feature is used. (119) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. Arria V Device Datasheet 104 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Condition Minimum(117) Typical PLL digital voltage regulator power supply — 1.45 1.5 1.55 V Battery back-up power supply (For design security volatile key register) — 1.2 — 3.0 V VI DC input voltage — –0.5 — 3.6 V VO Output voltage — 0 — VCCIO V TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C Standard POR 200 µs — 100 ms — Fast POR 200 µs — 4 ms — Typical Maximum(121) Unit 2.85 3.0 3.15 V 2.375 2.5 2.625 2.85 3.0 3.15 Symbol Description VCCD_FPLL VCCBAT (120) tRAMP Power supply ramp time Maximum (117) Unit 2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions Table 84. Recommended Transceiver Power Supply Operating Conditions for Arria V GZ Devices Symbol VCCA_GXBL (122), VCCA_GXBR (123) (122), (123) Description Transceiver channel PLL power supply (left side) Transceiver channel PLL power supply (right side) Minimum (121) V continued... (117) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (120) If you do not use the design security feature in Arria V GZ devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Arria V GZ poweron-reset (POR) circuitry monitors VCCBAT. Arria V GZ devices do not exit POR if VCCBAT is not powered up. (121) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (122) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps, you can connect this supply to either 3.0 V or 2.5 V. (123) When using ATX PLLs, the supply must be 3.0 V. Send Feedback Arria V Device Datasheet 105 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Description Typical Maximum(121) 2.375 2.5 2.625 Minimum (121) Unit VCCHIP_L Transceiver hard IP power supply (left side) 0.82 0.85 0.88 V VCCHSSI_L Transceiver PCS power supply (left side) 0.82 0.85 0.88 V VCCHSSI_R Transceiver PCS power supply (right side) 0.82 0.85 0.88 V VCCR_GXBL (124) Receiver analog power supply (left side) 0.82 0.85 0.88 V 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 0.82 0.85 0.88 0.97 1.0 1.03 1.03 1.05 1.07 VCCR_GXBR (124) VCCT_GXBL (124) VCCT_GXBR (124) Receiver analog power supply (right side) Transmitter analog power supply (left side) Transmitter analog power supply (right side) V V V VCCH_GXBL Transmitter output buffer power supply (left side) 1.425 1.5 1.575 V VCCH_GXBR Transmitter output buffer power supply (right side) 1.425 1.5 1.575 V (121) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (124) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate > 10.3 Gbps when DFE is used. For data rate up to 6.5 Gbps, you can connect this supply to 0.85 V. Arria V Device Datasheet 106 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.1.1.3.2. Transceiver Power Supply Requirements Table 85. Transceiver Power Supply Voltage Requirements for Arria V GZ Devices Conditions VCCR_GXB and VCCT_GXB If BOTH of the following conditions are true: • Data rate > 10.3 Gbps. • DFE is used. If • • • ANY of the following conditions are true (126) : ATX PLL is used. Data rate > 6.5Gbps. DFE (data rate ≤ 10.3 Gbps), AEQ, or EyeQ feature is used. If • • • ALL of the following conditions are true: ATX PLL is not used. Data rate ≤ 6.5Gbps. DFE, AEQ, and EyeQ are not used. 1.05 (125) VCCA_GXB VCCH_GXB Unit 3.0 1.5 V 1.0 0.85 2.5 2.1.1.4. DC Characteristics 2.1.1.4.1. Supply Current Standby current is the current drawn from the respective power rails used for power budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design because these currents vary greatly with the resources you use. Related Information • Early Power Estimator User Guide For more information about the EPE tool. • Power Analysis chapter, Intel Quartus Prime Handbook For more information about power analysis. (125) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and VCCT_GXB are set to 0.85 V, they can be shared with the VCC core supply. (126) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions. Send Feedback Arria V Device Datasheet 107 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.1.1.4.2. Power Consumption Intel offers two ways to estimate power consumption for a design—the Excel-based Early Power Estimator and the Intel Quartus Prime Power Analyzer feature. Note: You typically use the interactive Excel-based EPE before designing the FPGA to get a magnitude estimate of the device power. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information • Early Power Estimator User Guide For more information about the EPE tool. • Power Analysis chapter, Intel Quartus Prime Handbook For more information about power analysis. 2.1.1.4.3. I/O Pin Leakage Current Table 86. I/O Pin Leakage Current for Arria V GZ Devices If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected. Min Typ Max Unit II Symbol Input pin Description VI = 0 V to VCCIOMAX Conditions –30 — 30 µA IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA 2.1.1.4.4. Bus Hold Specifications Table 87. Bus Hold Parameters for Arria V GZ Devices Parameter Symbol Conditions VCCIO 1.2 V Low sustaining current ISUSL VIN > VIL 1.5 V Unit 1.8 V 2.5 V 3.0 V Min Max Min Max Min Max Min Max Min Max 22.5 — 25.0 — 30.0 — 50.0 — 70.0 — µA continued... Arria V Device Datasheet 108 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Parameter Symbol Conditions VCCIO 1.2 V 1.5 V Unit 1.8 V 2.5 V 3.0 V Min Max Min Max Min Max Min Max Min Max –22.5 — –25.0 — –30.0 — –50.0 — –70.0 — µA (maximum) High sustaining current ISUSH VIN < VIH (minimum) Low overdrive current IODL 0V < VIN < VCCIO — 120 — 160 — 200 — 300 — 500 µA High overdrive current IODH 0V < VIN < VCCIO — –120 — –160 — –200 — –300 — –500 µA Bus-hold trip point VTRIP — 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V 2.1.1.4.5. On-Chip Termination (OCT) Specifications If you enable OCT calibration, calibration is automatically performed at power-up for I/Os connected to the calibration block. Table 88. OCT Calibration Accuracy Specifications for Arria V GZ Devices OCT calibration accuracy is valid at the time of calibration only. Symbol Description Conditions Calibration Accuracy C3, I3L C4, I4 Unit 25-Ω RS Internal series termination with calibration (25-Ω setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 % 50-Ω RS Internal series termination with calibration (50-Ω setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 % 34-Ω and 40-Ω RS Internal series termination with calibration (34-Ω and 40-Ω setting) VCCIO = 1.5, 1.35, 1.25, 1.2 V ±15 ±15 % 48-Ω, 60-Ω, 80-Ω, and 240-Ω RS Internal series termination with calibration (48Ω, 60-Ω, 80-Ω, and 240-Ω setting) VCCIO = 1.2 V ±15 ±15 % 50-Ω RT Internal parallel termination with calibration (50Ω setting) VCCIO = 2.5, 1.8, 1.5, 1.2 V –10 to +40 –10 to +40 % continued... Send Feedback Arria V Device Datasheet 109 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Conditions Calibration Accuracy Unit C3, I3L C4, I4 20-Ω, 30-Ω, 40-Ω, 60-Ω, and 120Ω RT Internal parallel termination with calibration (20Ω , 30-Ω, 40-Ω, 60-Ω, and 120-Ω setting) VCCIO = 1.5, 1.35, 1.25 V –10 to +40 –10 to +40 % 60-Ω and 120-Ω RT Internal parallel termination with calibration (60Ω and 120-Ω setting) VCCIO = 1.2 –10 to +40 –10 to +40 % 25-Ω RS_left_shift Internal left shift series termination with calibration (25-Ω RS_left_shift setting) VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 V ±15 ±15 % Table 89. OCT Without Calibration Resistance Tolerance Specifications for Arria V GZ Devices Symbol Description Conditions Resistance Tolerance C3, I3L C4, I4 Unit 25-Ω R, 50-Ω RS Internal series termination without calibration (25-Ω setting) VCCIO = 3.0 and 2.5 V ±40 ±40 % 25-Ω RS Internal series termination without calibration (25-Ω setting) VCCIO = 1.8 and 1.5 V ±40 ±40 % 25-Ω RS Internal series termination without calibration (25-Ω setting) VCCIO = 1.2 V ±50 ±50 % 50-Ω RS Internal series termination without calibration (50-Ω setting) VCCIO = 1.8 and 1.5 V ±40 ±40 % 50-Ω RS Internal series termination without calibration (50-Ω setting) VCCIO = 1.2 V ±50 ±50 % 100-Ω RD Internal differential termination (100-Ω setting) VCCIO = 2.5 V ±25 ±25 % Arria V Device Datasheet 110 Description Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Figure 23. OCT Variation Without Re-Calibration for Arria V GZ Devices ( ROCT = RSCAL 1 + ( dR x dT T ) ± ( dR x dV V) ( Notes: 1. The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO. 2. RSCAL is the OCT resistance value at power-up. 3. ΔT is the variation of temperature with respect to the temperature at power-up. 4. ΔV is the variation of voltage with respect to the VCCIO at power-up. 5. dR/dT is the percentage change of RSCAL with temperature. 6. dR/dV is the percentage change of RSCAL with voltage. Table 90. OCT Variation after Power-Up Calibration for Arria V GZ Devices Valid for a VCCIO range of ±5% and a temperature range of 0° to 85°C. Symbol dR/dV dR/dT Send Feedback Description OCT variation with voltage without re-calibration OCT variation with temperature without re-calibration VCCIO (V) Typical Unit 3.0 0.0297 %/mV 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 3.0 0.189 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 %/°C Arria V Device Datasheet 111 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.1.1.4.6. Pin Capacitance Table 91. Pin Capacitance for Arria V GZ Devices Maximum Unit CIOTB Symbol Input capacitance on the top and bottom I/O pins Description 6 pF CIOLR Input capacitance on the left and right I/O pins 6 pF COUTFB Input capacitance on dual-purpose clock output and feedback pins 6 pF 2.1.1.4.7. Hot Socketing Table 92. Hot Socketing Specifications for Arria V GZ Devices Symbol IIOPIN (DC) DC current per I/O pin IIOPIN (AC) AC current per I/O pin IXCVR-TX (DC) DC current per transceiver transmitter pin IXCVR-RX (DC) DC current per transceiver receiver pin (127) Maximum 300 μA 8 mA (127) 100 mA 50 mA The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. Arria V Device Datasheet 112 Description Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.1.1.4.8. Internal Weak Pull-Up Resistor Table 93. Internal Weak Pull-Up Resistor for Arria V GZ Devices All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins. The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is approximately 25 kΩ . Symbol RPU Description VCCIO Conditions (V) Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option. (128) Value (129) Unit 3.0 ±5% 25 kΩ 2.5 ±5% 25 kΩ 1.8 ±5% 25 kΩ 1.5 ±5% 25 kΩ 1.35 ±5% 25 kΩ 1.25 ±5% 25 kΩ 1.2 ±5% 25 kΩ 2.1.1.5. I/O Standard Specifications The VOL and VOH values are valid at the corresponding IOH and IOL, respectively. Table 94. Single-Ended I/O Standards for Arria V GZ Devices I/O Standard VOL (V) VOH (V) Min Typ Max Min Max Min Max Max Min LVTTL 2.85 3 3.15 –0.3 0.8 1.7 3.6 0.4 LVCMOS 2.85 3 3.15 –0.3 0.8 1.7 3.6 2.375 2.5 2.625 –0.3 0.7 1.7 3.6 2.5 V VCCIO (V) VIL (V) VIH (V) IOL (mA) IOH (mA) 2.4 2 –2 0.2 VCCIO – 0.2 0.1 –0.1 0.4 2 1 –1 continued... (128) The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (129) These specifications are valid with a ±10% tolerance to cover changes over PVT. Send Feedback Arria V Device Datasheet 113 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 I/O Standard VCCIO (V) VIH (V) VOL (V) VOH (V) IOL (mA) IOH (mA) Min Typ Max Min Max Min Max Max Min 1.8 V 1.71 1.8 1.89 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO – 0.45 2 –2 1.5 V 1.425 1.5 1.575 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2 1.2 V 1.14 1.2 1.26 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2 Table 95. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V GZ Devices I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF – 0.04 VREF VREF + 0.04 SSTL-18 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO SSTL-135 Class I, II 1.283 1.35 1.418 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO SSTL-125 Class I, II 1.19 1.25 1.26 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO SSTL-12 Class I, II 1.14 1.20 1.26 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 — VCCIO/2 — HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 — VCCIO/2 — HSTL-12 Class I, II 1.14 1.2 1.26 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO — VCCIO/2 — HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO — — — Arria V Device Datasheet 114 VIL (V) Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 96. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V GZ Devices I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) Iol (mA) Ioh (mA) Min Max Min Max Max Min Max Min SSTL-2 Class I –0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.608 VTT + 0.608 8.1 –8.1 SSTL-2 Class II –0.3 VREF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.81 VTT + 0.81 16.2 –16.2 SSTL-18 Class I –0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 VTT – 0.603 VTT + 0.603 6.7 –6.7 SSTL-18 Class II –0.3 VREF – 0.125 VREF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 0.28 VCCIO – 0.28 13.4 –13.4 SSTL-15 Class I — VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8 –8 SSTL-15 Class II — VREF – 0.1 VREF + 0.1 — VREF – 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 –16 SSTL-135 Class I, II — VREF – 0.09 VREF + 0.09 — VREF – 0.16 VREF + 0.16 0.2 * VCCIO 0.8 * VCCIO — — SSTL-125 Class I, II — VREF – 0.85 VREF + 0.85 — VREF – 0.15 VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO — — SSTL-12 Class I, II — VREF – 0.1 VREF + 0.1 — VREF – 0.15 VREF + 0.15 0.2 * VCCIO 0.8 * VCCIO — — HSTL-18 Class I — VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8 HSTL-18 Class II — VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16 HSTL-15 Class I — VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8 HSTL-15 Class II — VREF – 0.1 VREF + 0.1 — VREF – 0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16 HSTL-12 Class I –0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 8 –8 HSTL-12 Class II –0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 16 –16 — VREF – 0.13 VREF + 0.13 — VREF – 0.22 VREF + 0.22 0.1 × VCCIO 0.9 × VCCIO — — HSUL-12 Send Feedback Arria V Device Datasheet 115 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 97. Differential SSTL I/O Standards for Arria V GZ Devices I/O Standard VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V) Min Typ Max Min Max Min Typ Max Min Max 2.375 2.5 2.625 0.3 VCCIO + 0.6 VCCIO/2 – 0.2 — VCCIO/2 + 0.2 0.62 VCCIO + 0.6 SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 VCCIO/2 – 0.175 — VCCIO/2 + 0.175 0.5 VCCIO + 0.6 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 (130) VCCIO/2 – 0.15 — VCCIO/2 + 0.15 0.35 — SSTL-135 Class I, II 1.283 1.35 1.45 0.2 (130) VCCIO/2 – 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) VREF) 2(VIL(AC) - VREF) SSTL-125 Class I, II 1.19 1.25 1.31 0.18 (130) VCCIO/2 – 0.15 VCCIO/2 VCCIO/2 + 0.15 2(VIH(AC) VREF) — SSTL-12 Class I, II 1.14 1.2 1.26 0.18 — VREF –0.15 VCCIO/2 VREF + 0.15 –0.30 0.30 SSTL-2 Class I, II Table 98. Differential HSTL and HSUL I/O Standards for Arria V GZ Devices I/O Standard VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-18 Class I, II 1.71 1.8 1.89 0.2 — 0.78 — 1.12 0.78 — 1.12 0.4 — HSTL-15 Class I, II 1.425 1.5 1.575 0.2 — 0.68 — 0.9 0.68 — 0.9 0.4 — HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO + 0.3 — 0.5 × VCCIO — 0.4 × VCCIO 0.5 × VCCI 0.6 × VCCIO 0.3 VCCIO + 0.48 0.6 × VCCIO 0.44 0.44 O HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 × VCCIO – 0.12 0.5 × VCCIO 0.5 × VCCIO + 0.12 0.4 × VCCIO 0.5 × VCCI O (130) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)). Arria V Device Datasheet 116 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 99. Differential I/O Standard Specifications for Arria V GZ Devices I/O Standard VCCIO (V) Min PCML (134) (135) RSDS (HIO) (136) Max VID (mV) Min (132) Condition VICM(DC) (V) Max Min Condition VOD (V) Max Min (133) Typ VOCM (V) Max Min Typ (133) Max Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to the "Transceiver Performance Specifications" section. 2.5 V LVDS BLVDS Typ (131) 2.375 2.5 2.625 100 VCM = 1.25 V — 0.05 DMAX ≤ 700 Mbps 1.8 0.247 — 0.6 1.125 1.25 1.375 — 1.05 DMAX > 700 Mbps 1.55 0.247 — 0.6 1.125 1.25 1.375 2.375 2.5 2.625 100 — — — — — — — — — — — 2.375 2.5 2.625 100 VCM = 1.25 V — 0.3 — 1.4 0.1 0.2 0.6 0.5 1.2 1.4 continued... (131) Differential inputs are powered by VCCPD which requires 2.5 V. (132) The minimum VID value is applicable over the entire common mode range, VCM. (133) RL range: 90 ≤ RL ≤ 110 Ω. (134) For optimized LVDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85 V for data rates below 700 Mbps. (135) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology. (136) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V. Send Feedback Arria V Device Datasheet 117 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 I/O Standard VCCIO (V) (131) VID (mV) (132) VICM(DC) (V) VOD (V) (133) VOCM (V) (133) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max Mini-LVDS (HIO) (137) 2.375 2.5 2.625 200 — 600 0.4 — 1.325 0.25 — 0.6 1 1.2 1.4 LVPECL (138), (139) — — — 300 — — 0.6 DMAX ≤ 700 Mbps 1.8 — — — — — — — — — 300 — — 1 DMAX > 700 Mbps 1.6 — — — — — — Related Information Glossary on page 169 (131) Differential inputs are powered by VCCPD which requires 2.5 V. (132) The minimum VID value is applicable over the entire common mode range, VCM. (133) RL range: 90 ≤ RL ≤ 110 Ω. (137) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V. (138) LVPECL is only supported on dedicated clock input pins. (139) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps. Arria V Device Datasheet 118 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2. Switching Characteristics 2.2.1. Transceiver Performance Specifications 2.2.1.1. Reference Clock Table 100. Reference Clock Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions Transceiver Speed Grade 2 Min Typ Max Transceiver Speed Grade 3 Min Typ Unit Max Reference Clock Supported I/O Standards Dedicated reference clock pin 1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL RX reference clock pin 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Input Reference Clock Frequency (CMU PLL) (140) — 40 — 710 40 — 710 MHz Input Reference Clock Frequency (ATX PLL)(140) — 100 — 710 100 — 710 MHz Rise time Measure at ±60 mV of differential signal (141) — — 400 — — 400 ps Fall time Measure at ±60 mV of differential signal (141) — — 400 — — 400 Duty cycle — 45 — 55 45 — 55 % Spread-spectrum modulating clock frequency PCI Express (PCIe) 30 — 33 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to –0.5 — — 0 to –0.5 — % continued... (140) The input reference clock frequency options depend on the data rate and the device speed grade. (141) REFCLK performance requires to meet transmitter REFCLK phase noise specification. Send Feedback Arria V Device Datasheet 119 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit On-chip termination resistors — — 100 — — 100 — Ω Absolute VMAX Dedicated reference clock pin — — 1.6 — — 1.6 V — — 1.2 — — 1.2 Absolute VMIN RX reference clock pin — –0.4 — — –0.4 — — V Peak-to-peak differential input voltage — 200 — 1600 200 — 1600 mV VICM (AC coupled) Dedicated reference clock pin 1000/900/850 RX reference clock pin VICM (DC coupled) HCSL I/O standard for PCIe reference clock Transmitter REFCLK Phase Noise (622 MHz) (144) 1.0/0.9/0.85 (142) 1000/900/850 (143) (142) mV 1.0/0.9/0.85(143) mV 250 — 550 250 — 550 mV 100 Hz — — -70 — — -70 dBc/Hz 1 kHz — — -90 — — -90 dBc/Hz 10 kHz — — -100 — — -100 dBc/Hz 100 kHz — — -110 — — -110 dBc/Hz ≥1 MHz — — -120 — — -120 dBc/Hz Transmitter REFCLK Phase Jitter (100 MHz) (145) 10 kHz to 1.5 MHz (PCIe) — — 3 — — 3 ps (rms) RREF — — 1800 ±1% — — 1800 ±1% — Ω (142) The reference clock common mode voltage is equal to the VCCR_GXB power supply level. (143) This supply follows VCCR_GXB (144) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622). (145) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f. Arria V Device Datasheet 120 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Related Information Arria V Device Overview For more information about device ordering codes. 2.2.1.2. Transceiver Clocks Table 101. Transceiver Clocks Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions fixedclk clock frequency PCIe Receiver Detect Reconfiguration clock (mgmt_clk_clk) frequency — Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max — 100 or 125 — — 100 or 125 — MHz 100 — 125 100 — 125 MHz Related Information Arria V Device Overview For more information about device ordering codes. 2.2.1.3. Receiver Table 102. Receiver Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions Transceiver Speed Grade 2 Min Supported I/O Standards Data rate (Standard PCS) Typ Transceiver Speed Grade 3 Max Min Typ Max 9900 600 — 8800 Unit 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS (146), (147) — 600 — Mbps continued... Send Feedback Arria V Device Datasheet 121 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Data rate (10G PCS) (146), (147) Absolute VMAX for a receiver pin (148) Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max — 600 — 12500 600 — 10312.5 Mbps — — — 1.2 — — 1.2 V Absolute VMIN for a receiver pin — –0.4 — — –0.4 — — V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 — — 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration (149) VCCR_GXB = 1.0 V (VICM = 0.75 V) — — 1.8 — — 1.8 V VCCR_GXB = 0.85 V (VICM = 0.6 V) — — 2.4 — — 2.4 V — 85 — — 85 — — mV 85−Ω setting — 85 ± 30% — — 85 ± 30% — Ω 100−Ω setting — 100 ± 30% — — 100 ± 30% — Ω 120−Ω setting — 120 ± 30% — — 120 ± 30% — Ω Minimum differential eye opening at receiver serial input pins (150)(151) Differential on-chip termination resistors continued... (146) The line data rate may be limited by PCS-FPGA interface speed grade. (147) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. (148) The device cannot tolerate prolonged operation at this absolute maximum. (149) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin VICM). (150) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (151) Minimum eye opening of 85 mV is only for the unstressed input eye condition. Arria V Device Datasheet 122 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol/Description VICM (AC and DC coupled) tLTR (152) tLTD (153) tLTD_manual (154) tLTR_LTD_manual (155) Programmable equalization (AC Gain) Programmable DC gain Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max 150−Ω setting — 150 ± 30% — — 150 ± 30% — Ω VCCR_GXB = 0.85 V full bandwidth — 600 — — 600 — mV VCCR_GXB = 0.85 V half bandwidth — 600 — — 600 — mV VCCR_GXB = 1.0 V full bandwidth — 700 — — 700 — mV VCCR_GXB = 1.0 V half bandwidth — 700 — — 700 — mV — — — 10 — — 10 µs — 4 — — 4 — — µs — 4 — — 4 — — µs — 15 — — 15 — — µs Full bandwidth (6.25 GHz) Half bandwidth (3.125 GHz) — — 16 — — 16 dB DC gain setting = 0 — 0 — — 0 — dB DC gain setting = 1 — 2 — — 2 — dB continued... (152) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (153) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (154) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (155) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. Send Feedback Arria V Device Datasheet 123 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max DC gain setting = 2 — 4 — — 4 — dB DC gain setting = 3 — 6 — — 6 — dB DC gain setting = 4 — 8 — — 8 — dB Related Information Arria V Device Overview For more information about device ordering codes. 2.2.1.4. Transmitter Table 103. Transmitter Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Supported I/O Standards Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit 1.4-V and 1.5-V PCML Data rate (Standard PCS) — 600 — 9900 600 — 8800 Mbps Data rate (10G PCS) — 600 — 12500 600 — 10312.5 Mbps 85-Ω setting — 85 ± 20% — — 85 ± 20% — Ω 100-Ω setting — 100 ± 20% — — 100 ± 20% — Ω 120-Ω setting — 120 ± 20% — — 120 ± 20% — Ω 150-Ω setting — 150 ± 20% — — 150 ± 20% — Ω VOCM (AC coupled) 0.65-V setting — 650 — — 650 — mV VOCM (DC coupled) — — 650 — — 650 — Differential on-chip termination resistors mV continued... Arria V Device Datasheet 124 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max Tx VCM = 0.5 V and slew rate of 15 ps — — 15 — — 15 ps Intra-transceiver block transmitter channel-tochannel skew x6 PMA bonded mode — — 120 — — 120 ps Inter-transceiver block transmitter channel-tochannel skew xN PMA bonded mode — — 500 — — 500 ps Intra-differential pair skew Related Information Arria V Device Overview For more information about device ordering codes. 2.2.1.5. CMU PLL Table 104. CMU PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Supported data range tpll_powerdown tpll_lock (156) (157) Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max — 600 — 12500 600 — 10312.5 Mbps — 1 — — 1 — — µs — 10 — — 10 µs — Related Information Arria V Device Overview For more information about device ordering codes. (156) tpll_powerdown is the PLL powerdown minimum pulse width. (157) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. Send Feedback Arria V Device Datasheet 125 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.1.6. ATX PLL Table 105. ATX PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Supported data rate range Conditions tpll_lock (160) Transceiver Speed Grade 3 Unit Min Typ Max Min Typ Max VCO post-divider L=2 8000 — 12500 8000 — 10312.5 Mbps L=4 4000 — 6600 4000 — 6600 Mbps 2000 — 3300 2000 — 3300 Mbps — 1 — — 1 — — µs — — — 10 — — 10 µs L=8 tpll_powerdown (159) Transceiver Speed Grade 2 (158) Related Information • Arria V Device Overview For more information about device ordering codes. • Transceiver Clocking in Arria V Devices For more information about clocking ATX PLLs. • Dynamic Reconfiguration in Arria V Devices For more information about reconfiguring ATX PLLs. (158) This clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more information about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconfiguration in Arria V Devices chapter. (159) tpll_powerdown is the PLL powerdown minimum pulse width. (160) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. Arria V Device Datasheet 126 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.1.7. Fractional PLL Table 106. Fractional PLL Specifications for Arria V GZ Devices Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Intel Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the Arria V Device Overview. Symbol/Description Conditions Transceiver Speed Grade 2 Transceiver Speed Grade 3 Min Typ Max Min Typ Max Unit Supported data range — 600 — 3250/ 3125(161) 600 — 3250/ 3125 (161) Mbps tpll_powerdown(162) — 1 — — 1 — — µs tpll_lock (163) — — — 10 — 10 µs Related Information Arria V Device Overview For more information about device ordering codes. (161) When you use fPLL as a TXPLL of the transceiver. (162) tpll_powerdown is the PLL powerdown minimum pulse width. (163) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset. Send Feedback Arria V Device Datasheet 127 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.1.8. Clock Network Data Rate Table 107. Clock Network Maximum Data Rate Transmitter Specifications Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the Parameter Editor message during the Arria V Transceiver Native PHY Intel FPGA IP core instantiation. Clock Network ATX PLL CMU PLL Non-bonded Bonded Mode Mode (Gbps) (Gbps) x1 (165) x6 (165) Channel Span (164) fPLL Non-bonded Bonded Mode Mode (Gbps) (Gbps) Channel Span Non-bonded Bonded Mode Mode (Gbps) (Gbps) Channel Span 12.5 — 6 12.5 — 6 3.125 — 3 — 12.5 6 — 12.5 6 — 3.125 6 — 12.5 Side-wide — 12.5 Side-wide — — — xN (PCIe) — 8.0 8 — 5.0 8 — — — xN (Arria V Transceiver Native PHY Intel FPGA IP core) 8.0 8.0 Up to 13 channels above and below PLL 7.99 7.99 Up to 13 channels above and below PLL 3.125 3.125 Up to 13 channels above and below PLL — 8.01 to 9.8304 Up to 7 channels above and below PLL x6 PLL Feedback (166) (164) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance. (165) Channel span is within a transceiver bank. (166) Side-wide channel bonding is allowed up to the maximum supported by the Arria V Transceiver Native PHY Intel FPGA IP core. Arria V Device Datasheet 128 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.1.9. Standard PCS Data Rate Table 108. Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices The maximum data rate is also constrained by the transceiver speed grade. Refer to the “Commercial and Industrial Speed Grade Offering for Arria V GZ Devices” table for the transceiver speed grade. Mode (167) FIFO Register Transceiver Speed Grade PMA Width 20 20 16 16 10 10 8 8 PCS/Core Width 40 20 32 16 20 10 16 8 2 C3, I3L core speed grade 9.9 9 7.84 7.2 5.3 4.7 4.24 3.76 3 C4, I4 core speed grade 8.8 8.2 7.2 6.56 4.8 4.3 3.84 3.44 2 C3, I3L core speed grade 9.9 9 7.92 7.2 4.9 4.,5 3.92 3.6 3 C4, I4 core speed grade 8.8 8.2 7.04 6.56 4.4 4.1 3.52 3.28 Related Information Operating Conditions on page 100 (167) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can vary. In the register mode the pointers are fixed for low latency. Send Feedback Arria V Device Datasheet 129 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.1.10. 10G PCS Data Rate Table 109. Mode 10G PCS Approximate Maximum Data Rate (Gbps) for Arria V GZ Devices (168) Transceiver Speed Grade PMA Width 64 40 40 40 32 32 PCS Width 64 66/67 50 40 64/66/67 32 2 C3, I3L core speed grade 12.5 12.5 10.69 12.5 10.88 10.88 3 C4, I4 core speed grade 10.3125 10.3125 10.69 10.3125 9.92 9.92 2 C3, I3L core speed grade 12.5 12.5 10.69 12.5 10.88 10.88 3 C4, I4 core speed grade 10.3125 10.3125 10.69 10.3125 9.92 9.92 FIFO Register 2.2.1.11. Typical VOD Settings Table 110. Typical VOD Setting for Arria V GZ Channel, TX Termination = 100 Ω The tolerance is +/-20% for all VOD settings except for settings 2 and below. Symbol VOD differential peak to peak typical VOD Setting 0 (169) VOD Value (mV) VOD Setting VOD Value (mV) 0 32 640 1(169) 20 33 660 2(169) 40 34 680 3(169) 60 35 700 4(169) 80 36 720 5(169) 100 37 740 6 120 38 760 7 140 39 780 8 160 40 800 continued... (168) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can vary. In the register mode the pointers are fixed for low latency. (169) If TX termination resistance = 100 Ω,this VOD setting is illegal. Arria V Device Datasheet 130 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol VOD differential peak to peak typical Send Feedback VOD Setting VOD Value (mV) VOD Setting VOD Value (mV) 9 180 41 820 10 200 42 840 11 220 43 860 12 240 44 880 13 260 45 900 14 280 46 920 15 300 47 940 16 320 48 960 17 340 49 980 18 360 50 1000 19 380 51 1020 20 400 52 1040 21 420 53 1060 22 440 54 1080 23 460 55 1100 24 480 56 1120 25 500 57 1140 26 520 58 1160 27 540 59 1180 28 560 60 1200 29 580 61 1220 30 600 62 1240 31 620 63 1260 Arria V Device Datasheet 131 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Figure 24. AC Gain Curves for Arria V GZ Channels (full bandwidth) Arria V Device Datasheet 132 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.2. Core Performance Specifications 2.2.2.1. Clock Tree Specifications Table 111. Clock Tree Performance for Arria V GZ Devices Symbol Performance Unit C3, I3L C4, I4 Global and Regional Clock 650 580 MHz Periphery Clock 500 500 MHz 2.2.2.2. PLL Specifications Table 112. PLL Specifications for Arria V GZ Devices Symbol Min Typ Max Unit Input clock frequency (C3, I3L speed grade) 5 — 800 MHz Input clock frequency (C4, I4 speed grade) 5 — 650 MHz fINPFD Input frequency to the PFD 5 — 325 MHz fFINPFD Fractional Input clock frequency to the PFD 50 — 160 MHz PLL VCO operating range (C3, I3L speed grade) 600 — 1600 MHz PLL VCO operating range (C4, I4 speed grade) 600 — 1300 MHz 40 — 60 fIN (170) fVCO (171) tEINDUTY Parameter Input clock or external feedback clock input duty cycle % continued... (170) This specification is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (171) The VCO frequency reported by the Intel Quartus Prime software in the PLL Usage Summary section of the compilation report takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification. Send Feedback Arria V Device Datasheet 133 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter Min Typ Max Unit Output frequency for an internal global or regional clock (C3, I3L speed grade) — — 650 MHz Output frequency for an internal global or regional clock (C4, I4 speed grade) — — 580 MHz Output frequency for an external clock output (C3, I3L speed grade) — — 667 MHz Output frequency for an external clock output (C4, I4 speed grade) — — 533 MHz tOUTDUTY Duty cycle for a dedicated external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time — — 10 ns fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — 100 MHz tLOCK Time required to lock from the end-of-device configuration or deassertion of areset — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — 1 ms fCLBW PLL closed-loop low bandwidth — 0.3 — MHz PLL closed-loop medium bandwidth — 1.5 — MHz — 4 — MHz fOUT (172) fOUT_EXT (172) PLL closed-loop high bandwidth (173) tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on the areset signal 10 — — ns Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz) — — 0.15 tINCCJ (174), (175) UI (p-p) continued... (172) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL. (173) High bandwidth PLL settings are not supported in external feedback mode. (174) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. Arria V Device Datasheet 134 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter Min Typ Max Unit -750 — +750 ps (p-p) Period Jitter for dedicated clock output in integer PLL (fOUT ≥ 100 MHz) — — 175 ps (p-p) Period Jitter for dedicated clock output in integer PLL (fOUT < 100 Mhz) — — 17.5 mUI (p-p) Period Jitter for dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) — — 250(179), 175(177) ps (p-p) Period Jitter for dedicated clock output in fractional PLL (fOUT < 100 MHz) — — 25(179), 17.5 (177) mUI (p-p) Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT ≥ 100 MHz) — — 175 ps (p-p) Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT < 100 MHz) — — 17.5 mUI (p-p) Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) — — 250(179), 175 (177) ps (p-p) Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT < 100 MHz) — — 25(179), 17.5 (177) mUI (p-p) Period Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p) Period Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) — — 60 mUI (p-p) Input clock cycle-to-cycle jitter (fREF < 100 MHz) tOUTPJ_DC (176) tFOUTPJ_DC tOUTCCJ_DC (176) (176) tFOUTCCJ_DC tOUTPJ_IO, (176) (176), (178) continued... (175) The fREF is fIN/N specification applies when N = 1. (176) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in the Worst-Case DCD on Arria V GZ I/O Pins table. (177) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz. (178) The external memory interface clock output jitter specifications use a different measurement method, which is available in the Memory Output Clock Jitter Specification for Arria V GZ Devices table. Send Feedback Arria V Device Datasheet 135 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Min Typ Max Unit Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p) Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) — — 60 mUI (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) — — 60 mUI (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p) Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) — — 60 mUI (p-p) Period Jitter for a dedicated clock output in cascaded PLLs (fOUT ≥ 100 MHz) — — 175 ps (p-p) Period Jitter for a dedicated clock output in cascaded PLLS (fOUT < 100 MHz) — — 17.5 mUI (p-p) dKBIT Bit number of Delta Sigma Modulator (DSM) 8 24 32 Bits kVALUE Numerator of Fraction 128 8388608 2147483648 — fRES Resolution of VCO frequency (fINPFD = 100 MHz) 390625 5.96 0.023 Hz tFOUTPJ_IO tOUTCCJ_IO (176), (178), (179) (176), (178) tFOUTCCJ_IO (176), (178), (179) tCASC_OUTPJ_DC (176), (180) Parameter Related Information • Duty Cycle Distortion (DCD) Specifications on page 150 • DLL Range Specifications on page 148 (179) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz. (180) The cascaded PLL specification is only applicable with the following condition: a. Upstream PLL: 0.59Mhz ≤ Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz Arria V Device Datasheet 136 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.2.3. DSP Block Specifications Table 113. DSP Block Performance Specifications for Arria V GZ Devices Mode Performance C3, I3L Unit C4 I4 Modes using One DSP Block Three 9 × 9 480 420 MHz One 18 × 18 480 420 400 MHz Two partial 18 × 18 (or 16 × 16) 480 420 400 MHz One 27 × 27 400 350 MHz One 36 × 18 400 350 MHz One sum of two 18 × 18 (One sum of two 16 × 16) 400 350 MHz One sum of square 400 350 MHz One 18 × 18 plus 36 (a × b) + c 400 350 MHz Modes using Two DSP Blocks Three 18 × 18 400 350 MHz One sum of four 18 × 18 380 300 MHz One sum of two 27 × 27 380 One sum of two 36 × 18 380 300 MHz One complex 18 × 18 400 350 MHz One 36 × 36 380 300 MHz 300 290 MHz Modes using Three DSP Blocks One complex 18 × 25 340 275 265 MHz Modes using Four DSP Blocks One complex 27 × 27 Send Feedback 350 310 MHz Arria V Device Datasheet 137 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.2.4. Memory Block Specifications Table 114. Memory Block Performance Specifications for Arria V GZ Devices To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for this and other memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX. Memory MLAB Mode (181) Unit Memory C3 C4 I3L I4 Single port, all supported widths 0 1 400 315 400 315 MHz Simple dual-port, x32/x64 depth 0 1 400 315 400 315 MHz (181) 0 1 533 400 533 400 MHz ROM, all supported widths 0 1 500 450 500 450 MHz Single-port, all supported widths 0 1 650 550 500 450 MHz Simple dual-port, all supported widths 0 1 650 550 500 450 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 455 400 455 400 MHz Simple dual-port with ECC enabled, 512 × 32 0 1 400 350 400 350 MHz Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 0 1 500 450 500 450 MHz True dual port, all supported widths 0 1 650 550 500 450 MHz ROM, all supported widths 0 1 650 550 500 450 MHz The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled. Arria V Device Datasheet 138 Performance ALUTs Simple dual-port, x16 depth M20K Block Resources Used Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.2.2.5. Temperature Sensing Diode Specifications Table 115. Internal Temperature Sensing Diode Specification for Arria V GZ Devices Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time(182) Resolution Minimum Resolution with no Missing Codes –40°C to 100°C ±8°C No 1 MHz, 500 kHz < 100 ms 8 bits 8 bits Table 116. External Temperature Sensing Diode Specifications for Arria V GZ Devices Description Min Typ Max Unit Ibias, diode source current 8 — 200 μA Vbias, voltage across diode 0.3 — 0.9 V — — 1 Figure 30. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 , Timing when using a MAX II device, MAX V device, or microprocessor as an external host. tCFG nCONFIG nSTATUS (3) CONF_DONE (4) DCLK (6) tCF2ST1 tCF2CK tSTATUS tCF2ST0 tCL tCH tCF2CD tST2CK 1 DATA[31..0] (8) User I/O tDSU High-Z 2 r 1 (8) 2 tCLK Word 0 Word 1 tDH tDH r (7) 1 Word 3 r 1 (5) 2 User Mode Word (n-1) User Mode INIT_DONE (9) tCD2UM Notes: 1. To find out the DCLK-to-DATA[] ratio for your system, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table. 2. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. 3. After power-up, the Arria V GZ device holds nSTATUS low for the time as specified by the POR delay. 4. After power-up, before and during configuration, CONF_DONE is low. 5. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. 6. “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable settings, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table. 7. If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending the first DCLK rising edge. 8. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. 9. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Send Feedback Arria V Device Datasheet 157 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 135. FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1 Use these timing parameters when you use the decompression and design security features. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — μs tSTATUS tCF2ST1 tCF2CK (216) nSTATUS low pulse width nCONFIG high to nSTATUS high 268 — 1,506 (214) μs 1,506 (215) μs nCONFIG high to first rising edge on DCLK 1,506 — μs tST2CK(216) nSTATUS high to first rising edge of DCLK 2 — μs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns (217) — s tDH DATA[] hold time after rising edge on DCLK N–1/fDCLK tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/×16) — 125 MHz DCLK frequency (FPP ×32) — 100 MHz tR Input rise time — 40 ns tF Input fall time — 40 ns continued... (214) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (215) You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. (216) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (217) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating. Arria V Device Datasheet 158 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Symbol Parameter (218) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Minimum Maximum Unit 175 437 μs 4 × maximum DCLK period — — tCD2CU + (8576 × CLKUSR period) — — (219) Related Information • DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 152 • Configuration, Design Security, and Remote System Upgrades in Arria V Devices (218) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device. (219) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the Initialization section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Send Feedback Arria V Device Datasheet 159 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.3.4. Active Serial Configuration Timing Figure 31. AS Configuration Timing Timing waveform for the active serial (AS) x1 mode and AS x4 mode configuration timing. tCF2ST1 nCONFIG nSTATUS CONF_DONE nCSO DCLK AS_DATA0/ASDO tCO Read Address tDH tSU AS_DATA1 (1) bit 0 bit 1 bit (n - 2) bit (n - 1) tCD2UM(2) INIT_DONE (3) User I/O User Mode Notes: 1. If you are using AS ×4 mode, this signal rep rese nts the AS_DATA[3..0] and EPCQ sends in 4-bits of d ata for each DCLKcycle. 2. The initialization clock can be from internal oscillator or CLKUSR pin . 3. After the option bit to enable the INIT_DONE pin isconfigu red into the d evice, the INIT_DONE oges low. Arria V Device Datasheet 160 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 136. AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in the "PS Timing Parameters for Arria V GZ Devices" table. Symbol Parameter Condition Minimum Maximum Unit tCO (220) DCLK falling edge to AS_DATA0/ASDO output — — 4 ns tSU (221) Data setup time before falling edge on DCLK — 1.5 — ns tDH (221) Data hold time after falling edge on DCLK –3 speed grade 3.7 — ns –4 speed grade 3.9 — ns — 175 437 μs (222) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (8576 × CLKUSR period) — — (220) Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, and termination resistors) through IBIS or HSPICE simulation. (221) To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline. (222) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the “Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Send Feedback Arria V Device Datasheet 161 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 137. DCLK Frequency Specification in the AS Configuration Scheme This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz Related Information • Passive Serial Configuration Timing on page 163 • Evaluating Data Setup and Hold Timing Slack chapter, AN822: Intel FPGA Configuration Device Migration Guideline • Configuration, Design Security, and Remote System Upgrades in Arria V Devices Arria V Device Datasheet 162 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.3.5. Passive Serial Configuration Timing Figure 32. PS Configuration Timing Waveform Timing waveform for a passive serial (PS) configuration when using a MAX II device, MAX V device, or microprocessor as an external host. tCFG nCONFIG nSTATUS (2) CONF_DONE (3) tCF2ST1 tCF2CK tCF2ST0 tSTATUS tCLK tCH tCL tCF2CD t ST2CK (4) DCLK DATA0 User I/O (6) tDH Bit 0 Bit 1 Bit 2 tDSU Bit 3 (5) Bit (n-1) User Mode High-Z INIT_DONE (7) tCD2UM Notes: 1. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. 2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay. 3. After power-up, before and during configuration, CONF_DONE is low. 4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. 5. DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins Option. 6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. 7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Send Feedback Arria V Device Datasheet 163 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 138. PS Timing Parameters for Arria V GZ Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — μs tSTATUS tCF2ST1 268 nSTATUS low pulse width nCONFIG high to nSTATUS high — 1,506 (223) μs 1,506 (224) μs tCF2CK (225) nCONFIG high to first rising edge on DCLK 1,506 — μs tST2CK (225) nSTATUS high to first rising edge of DCLK 2 — μs 5.5 — ns 0 — ns tDSU DATA[] setup time before rising edge on DCLK tDH DATA[] hold time after rising edge on DCLK tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency — 125 MHz tCD2UM CONF_DONE high to user mode 175 437 μs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (8576 × CLKUSR period) (227) — — (226) (223) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (224) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (225) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (226) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. Arria V Device Datasheet 164 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Related Information Configuration, Design Security, and Remote System Upgrades in Arria V Devices 2.3.6. Initialization Table 139. Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices Initialization Clock Source Internal Oscillator CLKUSR (228) DCLK Configuration Schemes Maximum Frequency (MHz) Minimum Number of Clock Cycles AS, PS, FPP 12.5 8576 PS, FPP 125 AS 100 PS, FPP 125 2.3.7. Configuration Files Use the following table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Intel Quartus Prime software. However, for a specific version of the Intel Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. (227) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the Initialization section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. (228) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Intel Quartus Prime software from the General panel of the Device and Pin Options dialog box. Send Feedback Arria V Device Datasheet 165 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Table 140. Uncompressed .rbf Sizes for Arria V GZ Devices Variant Arria V GZ Table 141. Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) E1 137,598,880 562,208 E3 137,598,880 562,208 E5 213,798,880 561,760 E7 213,798,880 561,760 Minimum Configuration Time Estimation for Arria V GZ Devices Variant Arria V GZ Member Code Active Serial (230) Fast Passive Parallel DCLK (MHz) Min Config Time (ms) Width DCLK (MHz) Min Config Time (ms) E1 4 100 344 32 100 43 E3 4 100 344 32 100 43 E5 4 100 534 32 100 67 E7 4 100 534 32 100 67 The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature. (230) DCLK frequency of 100 MHz using external CLKUSR. (231) Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Arria V Device Datasheet (231) Width (229) 166 (229) Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.3.8. Remote System Upgrades Circuitry Timing Specification Table 142. Remote System Upgrade Circuitry Timing Specifications Parameter tRU_nCONFIG (232) tRU_nRSTIMER (233) Minimum Maximum Unit 250 — ns 250 — ns Related Information • Configuration, Design Security, and Remote System Upgrades in Arria V Devices For more information about the reconfiguration input for the Remote Update Intel FPGA IP core, refer to the User Watchdog Timer section. • Configuration, Design Security, and Remote System Upgrades in Arria V Devices For more information about the reset_timer input for the Remote Update Intel FPGA IP core, refer to the Remote System Upgrade State Machine section. 2.3.9. User Watchdog Internal Oscillator Frequency Specification Table 143. User Watchdog Internal Oscillator Frequency Specifications Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 2.4. I/O Timing Intel offers two ways to determine I/O timing—the Excel-based I/O Timing and the Intel Quartus Prime Timing Analyzer. (232) This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification. For more information, refer to the Remote System Upgrade State Machine section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. (233) This is equivalent to strobing the reset_timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification. For more information, refer to the User Watchdog Timer section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter. Send Feedback Arria V Device Datasheet 167 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information Arria V Devices Documentation page For the Excel-based I/O Timing spreadsheet. 2.4.1. Programmable IOE Delay Table 144. Parameter IOE Programmable Delay for Arria V GZ Devices (234) Available Settings Min Offset (235) Fast Model Slow Model Unit Industrial Commercial C3 C4 I3L I4 D1 64 0 0.464 0.493 0.924 1.011 0.921 1.006 ns D2 32 0 0.230 0.244 0.459 0.503 0.456 0.500 ns D3 8 0 1.587 1.699 2.992 3.192 3.047 3.257 ns D4 64 0 0.464 0.492 0.924 1.011 0.920 1.006 ns D5 64 0 0.464 0.493 0.924 1.011 0.921 1.006 ns D6 32 0 0.229 0.244 0.458 0.503 0.456 0.499 ns (234) You can set this value in the Intel Quartus Prime software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column of Assignment Editor. (235) Minimum offset does not include the intrinsic delay. Arria V Device Datasheet 168 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.4.2. Programmable Output Buffer Delay Table 145. Programmable Output Buffer Delay for Arria V GZ Devices You can set the programmable output buffer delay in the Intel Quartus Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Symbol DOUTBUF Parameter Typical Unit Rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps 2.5. Glossary Table 146. Glossary Term Differential I/O Standards Definition Receiver Input Waveforms continued... Send Feedback Arria V Device Datasheet 169 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Term Definition Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms continued... Arria V Device Datasheet 170 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Term Definition Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK Left and right PLL input clock frequency. fHSDR High-speed I/O block—Maximum and minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block—Maximum and minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: continued... Send Feedback Arria V Device Datasheet 171 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Term Definition TMS TDI tJCH tJCP t JCL tJPH tJPSU TCK tJPZX tJPXZ tJPCO TDO PLL Specifications Diagram of PLL Specifications CLKOUT Pins Switchover CLK fOUT_EXT 4 fIN Core Clock N fINPFD PFD CP LF VCO fVCO Counters C 0..C 17 fOUT GCLK RCLK Delta Sigma Modulator Key Reconfigurable in User Mode External Feedback Note: 1. Core Clock can only be fed by dedicated clock input pins or PLL outputs. RL Receiver differential input discrete resistor (external to the Arria V GZ device). SW (sampling window) Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window, as shown: continued... Arria V Device Datasheet 172 Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Term Definition Bit Time 0.5 x TCCS Single-ended voltage referenced I/O standard RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS tC High-speed receiver and transmitter input and output clock period. TCCS (channel-to-channelskew) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on the high-speed transmitter output clock. tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input. tOUTPJ_IO Period jitter on the general purpose I/O driven by a PLL. tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL. tRISE Signal low-to-high transition time (20-80%) continued... Send Feedback Arria V Device Datasheet 173 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Term Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(receiver input clock frequency multiplication factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage—The common mode of the differential signal at the receiver. VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage—The common mode of the differential signal at the transmitter. VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block—clock boost factor Arria V Device Datasheet 174 Definition Send Feedback 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 2.6. Arria V GZ Device Datasheet Revision History Document Version Changes 2019.04.26 Added a note for Conversion Time in the Internal Temperature Sensing Diode Specification for Arria V GZ Devices table. 2019.01.25 • • • • • • Date February 2017 Added Arria V GZ Devices Overshoot Duration diagram. Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Arria V GZ Devices table. Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V GZ Devices table. — Updated tDH specifications. These specifications are applicable to the commercial and industrial grade devices. — Added note to tCO, tSU, and tDH. Changed instances of Quartus II to Intel Quartus Prime. Removed PowerPlay text from tool name. Renamed IP cores as per Intel rebranding. Version 2017.02.10 Changes • • • • • June 2016 December 2015 2016.06.20 2015.12.16 • • Changed the minimum value for tCD2UMC in the “FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1” table. Changed the minimum value for tCD2UMC in the "FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1" table. Changed the minimum value for tCD2UMC in the "AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices" table. Changed the minimum value for tCD2UMC in the "PS Timing Parameters for Arria V GZ Devices" table. Changed the minimum number of clock cycles value in the "Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices" table. • Changed column heading from "Value" to "Maximum" in the "Pin Capacitance for Arria V GZ Devices" table. Changed the minimum supported data rate range values from "1000" to "2000" in the "ATX PLL Specifications for Arria V GZ Devices" table. Added the supported data rates for the following output standards using true LVDS output buffer types in the "High-Speed Clock Specifications for Arria V GZ Devices" table: — True RSDS output standard: data rates of up to 230 Mbps — True mini-LVDS output standard: data rates of up to 340 Mbps • • • • Removed the CDR ppm tolerance specification from the "Receiver Specifications for Arria V GZ Devices" table. Removed transmitter rise and fall time specifications from the "Transmitter Specifications for Arria V GZ Devices" table. Changed the .rbf sizes in the "Uncompressed .rbf Sizes for Arria V GZ Devices" table. Added a footnote to the "Transmitter High-Speed I/O Specifications for Arria V GZ Devices" table. continued... Send Feedback Arria V Device Datasheet 175 2. Arria V GZ Device Datasheet AV-51002 | 2019.04.26 Date June 2015 Version 2015.06.16 Changes • • January 2015 2015.01.30 • • • Added 240-Ω to the "OCT Calibration Accuracy Specifications for Arria V GZ Devices" table. Changed the CDR PPM tolerance spec in the "Receiver Specifications for Arria V GZ Devices" table. Added additional max data rate for fPLL in the "Fractional PLL Specifications for Arria V GZ Devices" table. July 2014 3.8 • • • • • • • Updated Table 21. Updated Table 22 VOCM (DC Coupled) condition. Updated the DCLK note to Figure 6, Figure 7, and Figure 9. Added note to Table 5 and Table 6. Added the DCLK specification to Table 50. Added note to Table 51. Updated the list of parameters in Table 53. February 2014 3.7 Updated Table 28. December 2013 3.6 • • Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37, Table 38, Table 45, Table 46, Table 47, Table 56, Table 49. Updated “PLL Specifications”. August 2013 3.5 Updated Table 28. August 2013 3.4 • • Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28, Table 29, Table 31, Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, and Table 54. Updated Table 2 and Table 28. June 2013 3.3 Updated Table 23, Table 28, Table 51, and Table 55. May 2013 3.2 • • • Added Table 23. Updated Table 5, Table 22, Table 26, and Table 57. Updated Figure 6, Figure 7, Figure 8, and Figure 9. March 2013 3.1 • • Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52. Updated “Maximum Allowed Overshoot and Undershoot Voltage”. December 2012 3.0 Initial release. Arria V Device Datasheet 176 Changed the conditions for the reference clock rise and fall time and added a note to the condition in the "Reference Clock Specifications for Arria V GZ Devices" table. Added a note to the "Minimum differential eye opening at receiver serial input pins" specification in the "Receiver Specifications for Arria V GZ Devices" table. Send Feedback