Stratix V Device Datasheet
SV53001-4.1
This document covers the electrical and switching characteristics for Stratix® V
devices. Electrical characteristics include operating conditions and power
consumption. Switching characteristics include transceiver specifications, core, and
periphery performance. This document also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
f For information regarding the densities and packages of devices in the Stratix V
family, refer to the Stratix V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Stratix V devices.
Operating Conditions
When you use Stratix V devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of Stratix V
devices, you must consider the operating requirements described in this chapter.
Stratix V devices are offered in commercial and industrial temperature grades.
Commercial devices are offered in –1 (fastest), –2, –3, and –4 core speed grades.
Industrial devices are offered in –2, –3, and –4 core speed grades. Stratix V E devices
are offered based on core speed grades while Stratix V GX, GS, and GT devices are
also offered in -1, -2, and -3 transceiver speed grades.
Table 1 lists the industrial and commercial speed grades for the Stratix V GX and
Stratix V GS devices.
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
Transceiver Speed
Grade
1
GX channel—14.1 Gbps
2
GX channel—12.5 Gbps
101 Innovation Drive
San Jose, CA 95134
www.altera.com
June 2019
(1), (2), (3)
(Part 1 of 2)
Core Speed Grade
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
Yes
Yes
—
—
Yes
—
—
—
Yes
Yes
Yes
—
Yes
Yes
—
—
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products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
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Page 2
Electrical Characteristics
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
(1), (2), (3)
(Part 2 of 2)
Core Speed Grade
Transceiver Speed
Grade
3
GX channel—8.5 Gbps
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
—
Yes
Yes
Yes
—
Yes
Yes (4)
Yes
Notes to Table 1:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
(3) C2L, I2L, and I3L speed grades are for low-power devices.
(4) I3YY speed grades can achieve up to 10.3125 Gbps.
Table 2 lists the industrial and commercial speed grades for the Stratix V GT devices.
Table 2. Stratix V GT Commercial and Industrial Speed Grade Offering
(1), (2)
Core Speed Grade
Transceiver Speed Grade
C1
C2
I2
I3
Yes
Yes
—
—
Yes
Yes
Yes
Yes
2
GX channel—12.5 Gbps
GT channel—28.05 Gbps
3
GX channel—12.5 Gbps
GT channel—25.78 Gbps
Notes to Table 2:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
c Conditions other than those listed in Table 3 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 1 of 2)
Symbol
Description
Minimum
Maximum
Unit
VCC
Power supply for core voltage and periphery circuitry
–0.5
1.35
V
VCCPT
Power supply for programmable power technology
–0.5
1.8
V
VCCPGM
Power supply for configuration pins
–0.5
3.9
V
VCC_AUX
Auxiliary supply for the programmable power technology
–0.5
3.4
V
VCCBAT
Battery back-up power supply for design security volatile key register
–0.5
3.9
V
VCCPD
I/O pre-driver power supply
–0.5
3.9
V
VCCIO
I/O power supply
–0.5
3.9
V
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 3
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 2 of 2)
Symbol
Description
Minimum
Maximum
Unit
VCCD_FPLL
PLL digital power supply
–0.5
1.8
V
VCCA_FPLL
PLL analog power supply
–0.5
3.4
V
VI
DC input voltage
–0.5
3.8
V
TJ
Operating junction temperature
–55
125
°C
TSTG
Storage temperature (No bias)
–65
150
°C
IOUT
DC output current per pin
–25
40
mA
Table 4 lists the absolute conditions for the transceiver power supply for Stratix V GX,
GS, and GT devices.
Table 4. Transceiver Power Supply Absolute Conditions for Stratix V GX, GS, and GT Devices
Symbol
Description
Devices
Minimum
Maximum
Unit
GX, GS, GT
–0.5
3.75
V
VCCA_GXBL
Transceiver channel PLL power supply (left side)
VCCA_GXBR
Transceiver channel PLL power supply (right side)
GX, GS
–0.5
3.75
V
VCCA_GTBR
Transceiver channel PLL power supply (right side)
GT
–0.5
3.75
V
VCCHIP_L
Transceiver hard IP power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCHIP_R
Transceiver hard IP power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCHSSI_L
Transceiver PCS power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCHSSI_R
Transceiver PCS power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCR_GXBL
Receiver analog power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCR_GXBR
Receiver analog power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCR_GTBR
Receiver analog power supply for GT channels (right side)
GT
–0.5
1.35
V
VCCT_GXBL
Transmitter analog power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCT_GXBR
Transmitter analog power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCT_GTBR
Transmitter analog power supply for GT channels (right side)
GT
–0.5
1.35
V
VCCL_GTBR
Transmitter clock network power supply (right side)
GT
–0.5
1.35
V
VCCH_GXBL
Transmitter output buffer power supply (left side)
GX, GS, GT
–0.5
1.8
V
VCCH_GXBR
Transmitter output buffer power supply (right side)
GX, GS, GT
–0.5
1.8
V
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 5 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 4
Electrical Characteristics
Table 5 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for
a device lifetime of 10 years, the overshoot duration amounts to ~2 years.
Table 5. Maximum Allowed Overshoot During Transitions
Symbol
Vi (AC)
Description
Condition (V)
Overshoot Duration as %
@ TJ = 100°C
Unit
3.8
100
%
3.85
64
%
3.9
36
%
3.95
21
%
4
12
%
4.05
7
%
4.1
4
%
4.15
2
%
4.2
1
%
AC input voltage
Figure 1. Stratix V Device Overshoot Duration
4.0 V
Overshoot
3.95 V
3.3 V
Undershoot
DT
T
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 5
Recommended Operating Conditions
This section lists the functional operating limits for the AC and DC parameters for
Stratix V devices. Table 6 lists the steady-state voltage and current values expected
from Stratix V devices. Power supply ramps must all be strictly monotonic, without
plateaus.
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 1 of 2)
Description
Condition
Min (4)
Typ
Max (4)
Unit
Core voltage and periphery circuitry power
supply (C1, C2, I2, and I3YY speed grades)
—
0.87
0.9
0.93
V
Core voltage and periphery circuitry power
supply (C2L, C3, C4, I2L, I3, I3L, and I4
speed grades) (3)
—
0.82
0.85
0.88
V
VCCPT
Power supply for programmable power
technology
—
1.45
1.50
1.55
V
VCC_AUX
Auxiliary supply for the programmable
power technology
—
2.375
2.5
2.625
V
I/O pre-driver (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O pre-driver (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O buffers (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (1.8 V) power supply
—
1.71
1.8
1.89
V
I/O buffers (1.5 V) power supply
—
1.425
1.5
1.575
V
I/O buffers (1.35 V) power supply
—
1.283
1.35
1.45
V
I/O buffers (1.25 V) power supply
—
1.19
1.25
1.31
V
I/O buffers (1.2 V) power supply
—
1.14
1.2
1.26
V
Symbol
VCC
VCCPD (1)
VCCIO
Configuration pins (3.0 V) power supply
—
2.85
3.0
3.15
V
Configuration pins (2.5 V) power supply
—
2.375
2.5
2.625
V
Configuration pins (1.8 V) power supply
—
1.71
1.8
1.89
V
VCCA_FPLL
PLL analog voltage regulator power supply
—
2.375
2.5
2.625
V
VCCD_FPLL
PLL digital voltage regulator power supply
—
1.45
1.5
1.55
V
(2)
Battery back-up power supply (For design
security volatile key register)
—
1.2
—
3.0
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
Output voltage
VCCPGM
VCCBAT
TJ
June 2019
Operating junction temperature
Altera Corporation
—
0
—
VCCIO
V
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
Stratix V Device Datasheet
Page 6
Electrical Characteristics
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 2 of 2)
Symbol
tRAMP
Description
Power supply ramp time
Condition
Min (4)
Typ
Max (4)
Unit
Standard POR
200 µs
—
100 ms
—
Fast POR
200 µs
—
4 ms
—
Notes to Table 6:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(2) If you do not use the design security feature in Stratix V devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Stratix V power-on-reset (POR)
circuitry monitors VCCBAT. Stratix V devices will not exit POR if VCCBAT stays at logic low.
(3) C2L and I2L can also be run at 0.90 V for legacy boards that were designed for the C2 and I2 speed grades.
(4) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance
requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
Table 7 lists the transceiver power supply recommended operating conditions for
Stratix V GX, GS, and GT devices.
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 1 of 2)
Symbol
VCCA_GXBL
(1), (3)
VCCA_GXBR
(1), (3)
VCCA_GTBR
VCCHIP_L
VCCHIP_R
VCCHSSI_L
VCCHSSI_R
VCCR_GXBL
(2)
Description
Devices
Transceiver channel PLL power supply (left
side)
GX, GS, GT
Transceiver channel PLL power supply (right
side)
GX, GS
Transceiver channel PLL power supply (right
side)
Minimum (4)
Typical
Maximum (4)
2.85
3.0
3.15
2.375
2.5
2.625
Unit
V
2.85
3.0
3.15
2.375
2.5
2.625
GT
2.85
3.0
3.15
V
Transceiver hard IP power supply (left side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver hard IP power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver hard IP power supply (right side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver hard IP power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver PCS power supply (left side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver PCS power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver PCS power supply (right side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver PCS power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Receiver analog power supply (left side)
Stratix V Device Datasheet
GX, GS, GT
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
June 2019
V
V
Altera Corporation
Electrical Characteristics
Page 7
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 2 of 2)
Symbol
VCCR_GXBR
(2)
VCCR_GTBR
VCCT_GXBL
(2)
VCCT_GXBR
(2)
Description
Receiver analog power supply (right side)
Devices
GX, GS, GT
Receiver analog power supply for GT
channels (right side)
Transmitter analog power supply (left side)
Transmitter analog power supply (right side)
GT
GX, GS, GT
GX, GS, GT
Minimum (4)
Typical
Maximum (4)
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
1.02
1.05
1.08
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
Unit
V
V
V
V
VCCT_GTBR
Transmitter analog power supply for GT
channels (right side)
GT
1.02
1.05
1.08
V
VCCL_GTBR
Transmitter clock network power supply
GT
1.02
1.05
1.08
V
VCCH_GXBL
Transmitter output buffer power supply (left
side)
GX, GS, GT
1.425
1.5
1.575
V
VCCH_GXBR
Transmitter output buffer power supply
(right side)
GX, GS, GT
1.425
1.5
1.575
V
Notes to Table 7:
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
you can connect this supply to either 3.0 V or 2.5 V.
(2) Refer to Table 8 to select the correct power supply level for your design.
(3) When using ATX PLLs, the supply must be 3.0 V.
(4) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to
the PDN tool for the additional budget for the dynamic tolerance requirements.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 8
Electrical Characteristics
Table 8 shows the transceiver power supply voltage requirements for various
conditions.
Table 8. Transceiver Power Supply Voltage Requirements
Conditions
Core Speed Grade
VCCR_GXB &
VCCT_GXB (2)
All
1.05
VCCA_GXB
VCCH_GXB
Unit
1.5
V
If BOTH of the following
conditions are true:
■
Data rate > 10.3 Gbps.
■
DFE is used.
If ANY of the following
conditions are true (1):
3.0
■
ATX PLL is used.
■
Data rate > 6.5Gbps.
■
1.0
DFE (data rate
10.3 Gbps), AEQ, or
EyeQ feature is used.
If ALL of the following
conditions are true:
■
ATX PLL is not used.
■
Data rate 6.5Gbps.
■
All
C1, C2, I2, and I3YY
0.90
2.5
C2L, C3, C4, I2L, I3, I3L, and I4
0.85
2.5
DFE, AEQ, and EyeQ are
not used.
Notes to Table 8:
(1) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions.
(2) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and
VCCT_GXB are set to either 0.90 V or 0.85 V, they can be shared with the VCC core supply.
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Supply current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 9
I/O Pin Leakage Current
Table 9 lists the Stratix V I/O pin leakage current specifications.
Table 9. I/O Pin Leakage Current for Stratix V Devices (1)
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–30
—
30
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–30
—
30
µA
Note to Table 9:
(1) If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected.
Bus Hold Specifications
Table 10 lists the Stratix V device family bus hold specifications.
Table 10. Bus Hold Parameters for Stratix V Devices
VCCIO
Parameter Symbol
1.2 V
Conditions
1.5 V
1.8 V
2.5 V
3.0 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
22.5
—
25.0
—
30.0
—
50.0
—
70.0
—
µA
–22.5
—
–25.0
—
–30.0
—
–50.0
—
–70.0
—
µA
Low
sustaining
current
ISUSL
High
sustaining
current
ISUSH
Low
overdrive
current
IODL
0V < VIN <
VCCIO
—
120
—
160
—
200
—
300
—
500
µA
High
overdrive
current
IODH
0V < VIN <
VCCIO
—
–120
—
–160
—
–200
—
–300
—
–500
µA
Bus-hold
trip point
VTRIP
—
0.45
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
2.00
V
VIN > VIL
(maximum)
VIN < VIH
(minimum)
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 11 lists the Stratix V OCT termination
calibration accuracy specifications.
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 1 of 2)
Calibration Accuracy
Symbol
25- RS
June 2019
Description
Internal series termination
with calibration (25-
setting)
Altera Corporation
Conditions
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
Unit
C1
C2,I2
C3,I3,
I3YY
C4,I4
±15
±15
±15
±15
%
Stratix V Device Datasheet
Page 10
Electrical Characteristics
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 2 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C1
C2,I2
C3,I3,
I3YY
C4,I4
50- RS
Internal series termination
with calibration (50-
setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
±15
±15
±15
±15
%
34- and
40- RS
Internal series termination
with calibration (34- and
40- setting)
VCCIO = 1.5, 1.35,
1.25, 1.2 V
±15
±15
±15
±15
%
VCCIO = 1.2 V
±15
±15
±15
±15
%
Internal series termination
48--
with calibration (48-
80-and
60-80-and -
240-RS
setting)
Internal parallel
termination with
calibration (50- setting)
VCCIO = 2.5, 1.8,
1.5, 1.2 V
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
Internal parallel
20- , 30- ,
termination with
40- ,60-
calibration (20- , 30-
and
40-60-and 120-
120- RT
setting)
VCCIO = 1.5, 1.35,
1.25 V
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
50- RT
60- and
120-RT
Internal parallel
termination with
calibration (60- and
120- setting)
VCCIO = 1.2
25-
RS_left_shift
Internal left shift series
termination with
calibration (25-
RS_left_shift setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
±15
±15
±15
±15
%
Note to Table 11:
(1) OCT calibration accuracy is valid at the time of calibration only.
Table 12 lists the Stratix V OCT without calibration resistance tolerance to PVT
changes.
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 1 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C1
C2,I2
C3, I3,
I3YY
C4, I4
25- R, 50- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 3.0 and 2.5 V
±30
±30
±40
±40
%
25- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 1.8 and 1.5 V
±30
±30
±40
±40
%
25- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 1.2 V
±35
±35
±50
±50
%
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 11
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 2 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C1
C2,I2
C3, I3,
I3YY
C4, I4
50- RS
Internal series termination
without calibration (50-
setting)
VCCIO = 1.8 and 1.5 V
±30
±30
±40
±40
%
50- RS
Internal series termination
without calibration (50-
setting)
VCCIO = 1.2 V
±35
±35
±50
±50
%
100- RD
Internal differential
termination (100- setting)
VCCPD = 2.5 V
±25
±25
±25
±25
%
Calibration accuracy for the calibrated series and parallel OCTs are applicable at the
moment of calibration. When voltage and temperature conditions change after
calibration, the tolerance may change.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 13 lists the OCT variation with temperature and voltage after power-up
calibration. Use Table 13 to determine the OCT variation after power-up calibration
and Equation 1 to determine the OCT variation without recalibration.
Equation 1. OCT Variation Without Recalibration for Stratix V Devices (1),
(2), (3), (4), (5), (6)
dR
dR
R OCT = R SCAL 1 + ------- T ------- V
dT
dV
Notes to Equation 1:
(1) The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 13 lists the on-chip termination variation after power-up calibration.
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 1 of 2) (1)
Symbol
dR/dV
June 2019
Altera Corporation
Description
OCT variation with voltage without
recalibration
VCCIO (V)
Typical
3.0
0.0297
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
Unit
%/mV
Stratix V Device Datasheet
Page 12
Electrical Characteristics
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 2 of 2) (1)
Symbol
dR/dT
Description
VCCIO (V)
Typical
3.0
0.189
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
OCT variation with temperature
without recalibration
Unit
%/°C
Note to Table 13:
(1) Valid for a VCCIO range of ±5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 14 lists the Stratix V device family pin capacitance.
Table 14. Pin Capacitance for Stratix V Devices
Symbol
Description
Value
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
6
pF
CIOLR
Input capacitance on the left and right I/O pins
6
pF
COUTFB
Input capacitance on dual-purpose clock output and feedback pins
6
pF
Hot Socketing
Table 15 lists the hot socketing specifications for Stratix V devices.
Table 15. Hot Socketing Specifications for Stratix V Devices
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300 A
IIOPIN (AC)
AC current per I/O pin
8 mA (1)
IXCVR-TX (DC)
DC current per transceiver transmitter pin
100 mA
IXCVR-RX (DC)
DC current per transceiver receiver pin
50 mA
Note to Table 15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 13
Internal Weak Pull-Up Resistor
Table 16 lists the weak pull-up resistor values for Stratix V devices.
Table 16. Internal Weak Pull-Up Resistor for Stratix V Devices (1),
Symbol
RPU
Description
(2)
VCCIO Conditions
(V) (3)
Value (4)
Unit
3.0 ±5%
25
k
2.5 ±5%
25
k
1.8 ±5%
25
k
1.5 ±5%
25
k
1.35 ±5%
25
k
1.25 ±5%
25
k
1.2 ±5%
25
k
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if you enable the programmable
pull-up resistor option.
Notes to Table 16:
(1) All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak
pull-down resistor is approximately 25 k
(3) The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(4) These specifications are valid with a ±10% tolerance to cover changes over PVT.
I/O Standard Specifications
Table 17 through Table 22 list the input voltage (VIH and VIL), output voltage (VOH and
VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Stratix V devices. These tables also show the Stratix V device family I/O
standard specifications. The VOL and VOH values are valid at the corresponding IOH
and IOL, respectively.
For an explanation of the terms used in Table 17 through Table 22, refer to “Glossary”
on page 66. For tolerance calculations across all SSTL and HSTL I/O standards, refer
to Altera knowledge base solution rd07262012_486.
Table 17. Single-Ended I/O Standards for Stratix V Devices
I/O
Standard
LVTTL
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
IOL
(mA)
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
2.5 V
2.375
2.5
2.625
–0.3
0.7
1.7
3.6
0.4
2
1
–1
1.8 V
1.71
1.8
1.89
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.45
VCCIO –
0.45
2
–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 14
Electrical Characteristics
Table 18. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Stratix V Devices
VCCIO (V)
I/O Standard
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
VREF –
0.04
VREF
VREF +
0.04
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF –
0.04
VREF
VREF +
0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-135
Class I, II
1.283
1.35
1.418
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-125
Class I, II
1.19
1.25
1.26
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-12
Class I, II
1.14
1.20
1.26
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 *
VCCIO
0.5 * VCCIO
0.53 *
VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
—
—
—
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 1 of 2)
I/O Standard
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Iol (mA)
Ioh
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
SSTL-2
Class I
–0.3
VREF –
0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31
VREF + 0.31
VTT –
0.608
VTT +
0.608
8.1
–8.1
SSTL-2
Class II
–0.3
VREF –
0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31
VREF + 0.31
VTT –
0.81
VTT +
0.81
16.2
–16.2
SSTL-18
Class I
–0.3
VREF –
0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25
VREF + 0.25
VTT –
0.603
VTT +
0.603
6.7
–6.7
SSTL-18
Class II
–0.3
VREF –
0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25
VREF + 0.25
0.28
VCCIO –
0.28
13.4
–13.4
SSTL-15
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
8
–8
SSTL-15
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
16
–16
SSTL-135
Class I, II
—
VREF –
0.09
VREF +
0.09
—
VREF –
0.16
VREF + 0.16
0.2 *
VCCIO
0.8 *
VCCIO
—
—
SSTL-125
Class I, II
—
VREF –
0.85
VREF +
0.85
—
VREF –
0.15
VREF + 0.15
0.2 *
VCCIO
0.8 *
VCCIO
—
—
SSTL-12
Class I, II
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.15
VREF + 0.15
0.2 *
VCCIO
0.8 *
VCCIO
—
—
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
Page 15
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 2 of 2)
VIL(DC) (V)
I/O Standard
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Iol (mA)
Ioh
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
HSTL-18
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
8
–8
HSTL-18
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
16
–16
HSTL-15
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
8
–8
HSTL-15
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
16
–16
HSTL-12
Class I
–0.15
VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15
VREF + 0.15
0.25*
VCCIO
0.75*
VCCIO
8
–8
HSTL-12
Class II
–0.15
VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15
VREF + 0.15
0.25*
VCCIO
0.75*
VCCIO
16
–16
HSUL-12
—
VREF –
0.13
VREF +
0.13
—
VREF –
0.22
VREF + 0.22
0.1*
VCCIO
0.9*
VCCIO
—
—
Table 20. Differential SSTL I/O Standards for Stratix V Devices
VCCIO (V)
I/O Standard
VSWING(DC) (V)
VX(AC) (V)
VSWING(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
SSTL-2 Class
I, II
2.375
2.5
2.625
0.3
VCCIO +
0.6
VCCIO/2 –
0.2
—
VCCIO/2 +
0.2
0.62
VCCIO +
0.6
SSTL-18 Class
I, II
1.71
1.8
1.89
0.25
VCCIO +
0.6
VCCIO/2 –
0.175
—
VCCIO/2 +
0.175
0.5
VCCIO +
0.6
SSTL-15 Class
I, II
1.425
1.5
1.575
0.2
(1)
VCCIO/2 –
0.15
—
VCCIO/2 +
0.15
0.35
—
SSTL-135
Class I, II
1.283
1.35
1.45
0.2
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) VREF)
2(VIL(AC)
- VREF)
SSTL-125
Class I, II
1.19
1.25
1.31
0.18
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) VREF)
—
SSTL-12
Class I, II
1.14
1.2
1.26
0.18
—
VREF
–0.15
VCCIO/2
VREF +
0.15
–0.30
0.30
Note to Table 20:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 1 of 2)
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.78
—
1.12
0.78
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.68
—
0.9
0.68
—
0.9
0.4
—
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 16
Electrical Characteristics
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 2 of 2)
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
—
0.5*
VCCIO
—
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
0.3
VCCIO
+ 0.48
HSUL-12
1.14
1.2
1.3
0.26
0.26
0.5*VCCIO
– 0.12
0.5*
VCCIO
0.5*VCCIO
+ 0.12
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
0.44
0.44
VOCM (V)
(6)
Table 22. Differential I/O Standard Specifications for Stratix V Devices (7)
I/O
Standard
Min
Typ
(10)
Max
VID (mV) (8)
Min
Condition
VICM(DC) (V)
Max
Min
Condition
VOD (V)
Max
Min
(6)
Typ Max
Min
Typ
Max
Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 23 on page 18.
PCML
2.5 V
LVDS
VCCIO (V)
2.375
(1)
BLVDS (5)
2.5
2.375 2.5
2.625
—
0.05
DMAX
700 Mbps
1.8
0.247
—
0.6
1.125
1.25
1.375
—
1.05
DMAX >
700 Mbps
1.55
0.247
—
0.6
1.125
1.25
1.375
100
—
—
—
—
—
—
—
—
—
—
—
2.625
100
VCM =
1.25 V
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.4
2.5
2.625
200
—
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.4
—
—
—
300
—
—
0.6
DMAX
700 Mbps
1.8
—
—
—
—
—
—
—
—
—
300
—
—
1
DMAX >
700 Mbps
1.6
—
—
—
—
—
—
RSDS
(HIO) (2)
2.375
2.5
MiniLVDS
(HIO)
2.375
2.625
100
VCM =
1.25 V
(3)
LVPECL (4
), (9)
Notes to Table 22:
(1) For optimized LVDS receiver performance, the receiver voltage input range must be between 1.0 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85
V for data rates below 700 Mbps.
(2) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(3) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(4) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V
to 1.95 V for data rate below 700 Mbps.
(5) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(6) RL range: 90 RL 110 .
(7) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 18.
(8) The minimum VID value is applicable over the entire common mode range, VCM.
(9) LVPECL is only supported on dedicated clock input pins.
(10) Differential inputs are powered by VCCPD which requires 2.5 V.
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
Stratix V Device Datasheet
June 2019
Altera Corporation
Electrical Characteristics
1
Page 17
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 18
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of the Stratix V core and periphery
blocks.
These characteristics can be designated as Preliminary or Final.
■
Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
■
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 23 lists the Stratix V GX and GS transceiver specifications.
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
Min
Typ
Max
(1)
(Part 1 of 7)
Transceiver Speed
Grade 2
Min
Typ
Max
Transceiver Speed
Grade 3
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and
HCSL
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference
Clock Frequency
(CMU PLL) (8)
—
40
—
710
40
—
710
40
—
710
MHz
Input Reference
Clock Frequency
(ATX PLL) (8)
—
100
—
710
100
—
710
100
—
710
MHz
Rise time
Measure at
±60 mV of
differential
signal (26)
—
—
400
—
—
400
—
—
400
Fall time
Measure at
±60 mV of
differential
signal (26)
—
—
400
—
—
400
—
—
400
—
45
—
55
45
—
55
45
—
55
%
PCI Express®
(PCIe®)
30
—
33
30
—
33
30
—
33
kHz
Duty cycle
Spread-spectrum
modulating clock
frequency
Stratix V Device Datasheet
ps
June 2019
Altera Corporation
Switching Characteristics
Page 19
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
Min
Spread-spectrum
downspread
Typ
0 to
(1)
(Part 2 of 7)
Transceiver Speed
Grade 2
Max
Min
—
—
Typ
0 to
Transceiver Speed
Grade 3
Max
Min
—
—
Typ
0 to
Unit
Max
—
%
100
—
—
1.6
PCIe
—
—
—
100
—
—
100
—
—
Dedicated
reference
clock pin
—
—
1.6
—
—
1.6
—
RX reference
clock pin
—
—
1.2
—
—
1.2
—
—
1.2
Absolute VMIN
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
On-chip
termination
resistors (21)
Absolute VMAX (5)
VICM (AC
coupled) (3)
VICM (DC coupled)
Transmitter
REFCLK Phase
Noise
(622 MHz) (20)
Transmitter
REFCLK Phase
Jitter
(100 MHz) (17)
RREF
Dedicated
reference
clock pin
–0.5
–0.5
–0.5
V
1050/1000/900/850
RX reference
clock pin
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
(2)
1.0/0.9/0.85 (4)
mV
V
HCSL I/O
standard for
PCIe
reference
clock
250
—
550
250
—
550
250
—
550
mV
100 Hz
—
—
-70
—
—
-70
—
—
-70
dBc/Hz
1 kHz
—
—
-90
—
—
-90
—
—
-90
dBc/Hz
10 kHz
—
—
-100
—
—
-100
—
—
-100
dBc/Hz
100 kHz
—
—
-110
—
—
-110
—
—
-110
dBc/Hz
≥1 MHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
10 kHz to
1.5 MHz
(PCIe)
—
—
3
—
—
3
—
—
3
ps
(rms)
—
—
1800
±1%
—
—
1800
±1%
—
—
180
0
±1%
—
PCIe
Receiver
Detect
—
100
or
125
—
—
100
or
125
—
—
100
or
125
—
MHz
(19)
Transceiver Clocks
fixedclk clock
frequency
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 20
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Reconfiguration
clock
(mgmt_clk_clk)
frequency
—
Transceiver Speed
Grade 1
(1)
(Part 3 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
100
—
125
100
—
125
100
—
125
Unit
MHz
Receiver
Supported I/O
Standards
—
Data rate
(Standard PCS)
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
600
—
12200
600
—
12200
600
—
8500/
10312.5
(9), (23)
Data rate
(10G PCS) (9),
Mbps
(24)
—
(23)
600
—
14100
600
—
12500
600
—
8500/
10312.5
Mbps
(24)
Absolute VMAX for
a receiver pin (5)
—
—
—
1.2
—
—
1.2
—
—
1.2
V
Absolute VMIN for
a receiver pin
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Maximum peakto-peak
differential input
voltage VID (diff pp) before device
configuration (22)
—
—
—
1.6
—
—
1.6
—
—
1.6
V
VCCR_GXB =
1.0 V/1.05 V
(VICM =
0.70 V)
—
—
2.0
—
—
2.0
—
—
2.0
V
—
—
2.4
—
—
2.4
—
—
2.4
V
—
—
2.4
—
—
2.4
—
—
2.4
V
85
—
—
85
—
—
85
—
—
mV
Maximum peakto-peak
differential input
VCCR_GXB =
voltage VID (diff p0.90 V
p) after device
(VICM = 0.6 V)
(18)
configuration ,
(22)
VCCR_GXB =
0.85 V
(VICM = 0.6 V)
Minimum
differential eye
opening at
receiver serial
input pins (6), (22),
—
(27)
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 21
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Differential onchip termination
resistors (21)
VICM
(AC and DC
coupled)
tLTR
(11)
tLTD
(12)
tLTD_manual
Conditions
Transceiver Speed
Grade 3
Unit
Max
Min
Typ
Max
Min
Typ
Max
85 setting
—
85 ±
30%
—
—
85 ±
30%
—
—
85 ±
30%
—
100
setting
—
100
±
30%
—
—
100
±
30%
—
—
100
±
30%
—
120
setting
—
120
±
30%
—
—
120
±
30%
—
—
120
±
30%
—
150-
setting
—
150
±
30%
—
—
150
±
30%
—
—
150
±
30%
—
VCCR_GXB =
0.85 V or 0.9
V
full
bandwidth
—
600
—
—
600
—
—
600
—
mV
VCCR_GXB =
0.85 V or 0.9
V
half
bandwidth
—
600
—
—
600
—
—
600
—
mV
VCCR_GXB =
1.0 V/1.05 V
full
bandwidth
—
700
—
—
700
—
—
700
—
mV
VCCR_GXB =
1.0 V
half
bandwidth
—
750
—
—
750
—
—
750
—
mV
—
—
—
10
—
—
10
—
—
10
µs
—
4
—
—
4
—
—
4
—
—
µs
—
4
—
—
4
—
—
4
—
—
µs
—
15
—
—
15
—
—
15
—
—
µs
—
—
—
200
—
—
200
—
—
200
UI
—
—
16
—
—
16
—
—
16
dB
Run Length
June 2019
Transceiver Speed
Grade 2
Typ
(14)
Programmable
equalization
(AC Gain) (10)
(Part 4 of 7)
Min
(13)
tLTR_LTD_manual
Transceiver Speed
Grade 1
(1)
Full
bandwidth
(6.25 GHz)
Half
bandwidth
(3.125 GHz)
Altera Corporation
Stratix V Device Datasheet
Page 22
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Programmable
DC gain
Transceiver Speed
Grade 1
(1)
(Part 5 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
DC Gain
Setting = 0
—
0
—
—
0
—
—
0
—
dB
DC Gain
Setting = 1
—
2
—
—
2
—
—
2
—
dB
DC Gain
Setting = 2
—
4
—
—
4
—
—
4
—
dB
DC Gain
Setting = 3
—
6
—
—
6
—
—
6
—
dB
DC Gain
Setting = 4
—
8
—
—
8
—
—
8
—
dB
—
8500/
10312.5
Mbps
Transmitter
Supported I/O
Standards
—
Data rate
(Standard PCS)
—
Data rate
(10G PCS)
—
1.4-V and 1.5-V PCML
600
—
12200
600
—
12200
600
(24)
600
—
14100
600
—
12500
600
—
8500/
10312.5
Mbps
(24)
85-
setting
—
85 ±
20%
—
—
85 ±
20%
—
—
85 ±
20%
—
100-
setting
—
100
±
20%
—
—
100
±
20%
—
—
100
±
20%
—
120-
setting
—
120
±
20%
—
—
120
±
20%
—
—
120
±
20%
—
150-
setting
—
150
±
20%
—
—
150
±
20%
—
—
150
±
20%
—
VOCM (AC
coupled)
0.65-V
setting
—
650
—
—
650
—
—
650
—
mV
VOCM (DC
coupled)
—
—
650
—
—
650
—
—
650
—
mV
20% to 80%
30
—
160
30
—
160
30
—
160
ps
80% to 20%
30
—
160
30
—
160
30
—
160
ps
Intra-differential
pair skew
Tx VCM =
0.5 V and
slew rate of
15 ps
—
—
15
—
—
15
—
—
15
ps
Intra-transceiver
block transmitter
channel-tochannel skew
x6 PMA
bonded mode
—
—
120
—
—
120
—
—
120
ps
Differential onchip termination
resistors
Rise time
Fall time
(7)
(7)
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 23
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
(1)
(Part 6 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
xN PMA
bonded mode
—
—
500
—
—
500
—
—
500
ps
Supported Data
Range
—
600
—
12500
600
—
12500
600
—
8500/
10312.5
Mbps
tpll_powerdown (15)
—
1
—
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
—
—
10
µs
VCO
post-divider
L=2
8000
—
14100
8000
—
12500
8000
—
8500/
10312.5
Mbps
L=4
4000
—
7050
4000
—
6600
4000
—
6600
Mbps
L=8
2000
—
3525
2000
—
3300
2000
—
3300
Mbps
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5
1000
—
1762.5
1000
—
1762.5
Mbps
—
1
—
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
—
—
10
µs
Supported Data
Range
—
600
—
3250/
3125 (25)
600
—
3250/
3125 (25)
600
—
3250/
3125 (25)
Mbps
tpll_powerdown (15)
—
1
—
—
1
—
—
1
—
—
µs
Inter-transceiver
block transmitter
channel-tochannel skew
CMU PLL
tpll_lock
(24)
(16)
ATX PLL
Supported Data
Rate Range
tpll_powerdown
tpll_lock
(15)
(16)
(24)
fPLL
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 24
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
tpll_lock (16)
Conditions
—
Transceiver Speed
Grade 1
(1)
(Part 7 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
10
—
—
10
—
—
10
Unit
µs
Notes to Table 23:
(1) Speed grades shown in Table 23 refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the
Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination
offered. For more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate >
10.3 Gbps when DFE is used. For data rates up to 6.5 Gbps, you can connect this supply to 0.85 V.
(4) This supply follows VCCR_GXB.
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(8) The input reference clock frequency options depend on the data rate and the device speed grade.
(9) The line data rate may be limited by PCS-FPGA interface speed grade.
(10) Refer to Figure 1 for the GX channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(11) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(15) tpll_powerdown is the PLL powerdown minimum pulse width.
(16) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(17) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(18) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(19) For ES devices, RREF is 2000 ±1%.
(20) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(21) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(22) Refer to Figure 2.
(23) For oversampling designs to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(24) I3YY devices can achieve data rates up to 10.3125 Gbps.
(25) When you use fPLL as a TXPLL of the transceiver.
(26) REFCLK performance requires to meet transmitter REFCLK phase noise specification.
(27) Minimum eye opening of 85 mV is only for the unstressed input eye condition.
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 25
Table 24 shows the maximum transmitter data rate for the clock network.
Table 24. Clock Network Maximum Data Rate Transmitter Specifications
(1)
CMU PLL (2)
ATX PLL
fPLL
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
x1 (3)
14.1
—
6
12.5
—
6
3.125
—
3
x6 (3)
—
14.1
6
—
12.5
6
—
3.125
6
—
12.5
Sidewide
—
—
—
—
5.0
8
—
—
—
7.99
Up to 13
channels
above
and
below
PLL
3.125
Up to 13
channels
above
and
below
PLL
Clock Network
x6 PLL
Feedback (4)
—
14.1
Sidewide
xN (PCIe)
—
8.0
8
8.0
Up to 13
channels
above
and
below
PLL
8.01 to
9.8304
Up to 7
channels
above
and
below
PLL
8.0
xN (Native PHY IP)
—
7.99
3.125
Notes to Table 24:
(1) Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
(2) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(3) Channel span is within a transceiver bank.
(4) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 26
Switching Characteristics
Table 25 shows the approximate maximum data rate using the standard PCS.
Table 25. Stratix V Standard PCS Approximate Maximum Date Rate
Mode
(2)
Transceiver
Speed Grade
1
2
FIFO
3
1
2
Register
3
(1), (3)
PMA Width
20
20
16
16
10
10
8
8
PCS/Core Width
40
20
32
16
20
10
16
8
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.5
5.8
5.2
4.72
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.5
5.8
5.2
4.72
C3, I3, I3L
core speed grade
9.8
9.0
7.84
7.2
5.3
4.7
4.24
3.76
C1, C2, C2L, I2, I2L
core speed grade
8.5
8.5
8.5
8.5
6.5
5.8
5.2
4.72
I3YY
core speed grade
10.3125
10.3125
7.84
7.2
5.3
4.7
4.24
3.76
C3, I3, I3L
core speed grade
8.5
8.5
7.84
7.2
5.3
4.7
4.24
3.76
C4, I4
core speed grade
8.5
8.2
7.04
6.56
4.8
4.2
3.84
3.44
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.1
5.7
4.88
4.56
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.1
5.7
4.88
4.56
C3, I3, I3L
core speed grade
9.8
9.0
7.92
7.2
4.9
4.5
3.96
3.6
C1, C2, C2L, I2, I2L
core speed grade
10.3125
10.3125
10.3125
10.3125
6.1
5.7
4.88
4.56
I3YY
core speed grade
10.3125
10.3125
7.92
7.2
4.9
4.5
3.96
3.6
C3, I3, I3L
core speed grade
8.5
8.5
7.92
7.2
4.9
4.5
3.96
3.6
C4, I4
core speed grade
8.5
8.2
7.04
6.56
4.4
4.1
3.52
3.28
Notes to Table 25:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
(3) The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 for the transceiver speed grade.
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 27
Table 26 shows the approximate maximum data rate using the 10G PCS.
Table 26. Stratix V 10G PCS Approximate Maximum Data Rate
Mode
(2)
PMA Width
64
40
40
40
32
32
PCS Width
64
66/67
50
40
64/66/67
32
C1, C2, C2L, I2, I2L
core speed grade
14.1
14.1
10.69
14.1
13.6
13.6
C1, C2, C2L, I2, I2L
core speed grade
12.5
12.5
10.69
12.5
12.5
12.5
C3, I3, I3L
core speed grade
12.5
12.5
10.69
12.5
10.88
10.88
Transceiver
Speed Grade
1
2
FIFO or
Register
(1)
C1, C2, C2L, I2, I2L
core speed grade
3
C3, I3, I3L
core speed grade
8.5 Gbps
C4, I4
core speed grade
I3YY
core speed grade
10.3125 Gbps
Notes to Table 26:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 28
Switching Characteristics
Table 27 shows
the VOD settings for the GX channel.
Table 27. Typical VOD Setting for GX Channel, TX Termination = 100 (2)
Symbol
VOD differential peak to peak
typical (3)
VOD Value
(mV)
VOD Setting
VOD Setting
VOD Value
(mV)
0 (1)
0
32
640
1 (1)
20
33
660
2 (1)
40
34
680
3 (1)
60
35
700
4 (1)
80
36
720
5 (1)
100
37
740
6
120
38
760
7
140
39
780
8
160
40
800
9
180
41
820
10
200
42
840
11
220
43
860
12
240
44
880
13
260
45
900
14
280
46
920
15
300
47
940
16
320
48
960
17
340
49
980
18
360
50
1000
19
380
51
1020
20
400
52
1040
21
420
53
1060
22
440
54
1080
23
460
55
1100
24
480
56
1120
25
500
57
1140
26
520
58
1160
27
540
59
1180
28
560
60
1200
29
580
61
1220
30
600
62
1240
31
620
63
1260
Note to Table 27:
(1) If TX termination resistance = 100this VOD setting is illegal.
(2) The tolerance is +/-20% for all VOD settings except for settings 2 and below.
(3) Refer to Figure 2.
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 29
Figure 2 shows the differential transmitter output waveform.
Figure 2. Differential Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
VOD/VID (single-ended)
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD/VID (differential peak to peak typical) = 2 x VOD/VID (single-ended)
VOD/VID (single-ended)
VOD/VID (single-ended)
Figure 3 shows the Stratix V AC gain curves for GX channels.
Figure 3. AC Gain Curves for GX Channels (full bandwidth)
1
Stratix V GT devices contain both GX and GT channels. All transceiver specifications
for the GX channels not listed in Table 28 are the same as those listed in Table 23.
Table 28 lists the Stratix V GT transceiver specifications.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 30
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 1 of 5) (1)
Symbol/
Description
Transceiver
Speed Grade 2
Conditions
Min
Typ
Transceiver
Speed Grade 3
Max
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS,
and HCSL
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock
Frequency (CMU
PLL) (6)
—
40
—
710
40
—
710
MHz
Input Reference Clock
Frequency (ATX PLL) (6)
—
100
—
710
100
—
710
MHz
Rise time
20% to 80%
—
—
400
—
—
400
Fall time
80% to 20%
—
—
400
—
—
400
—
45
—
55
45
—
55
%
Spread-spectrum
modulating clock
frequency
PCI Express
(PCIe)
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
0 to –0.5
—
—
0 to –0.5
—
%
—
—
100
—
—
100
—
Dedicated
reference
clock pin
—
—
1.6
—
—
1.6
RX reference
clock pin
—
—
1.2
—
—
1.2
Absolute VMIN
—
-0.4
—
—
-0.4
—
—
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
mV
Duty cycle
On-chip termination
resistors (19)
Absolute VMAX
(3)
VICM (AC coupled)
VICM (DC coupled)
Stratix V Device Datasheet
ps
V
Dedicated
reference
clock pin
1050/1000 (2)
1050/1000 (2)
mV
RX reference
clock pin
1.0/0.9/0.85 (22)
1.0/0.9/0.85 (22)
V
HCSL I/O
standard for
PCIe
reference
clock
250
—
550
250
—
550
June 2019
mV
Altera Corporation
Switching Characteristics
Page 31
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 2 of 5) (1)
Symbol/
Description
Transmitter REFCLK
Phase Noise (622
MHz) (18)
Transmitter REFCLK
Phase Jitter (100
MHz) (15)
RREF (17)
Transceiver
Speed Grade 2
Conditions
Min
Typ
100 Hz
—
—
1 kHz
—
10 kHz
Transceiver
Speed Grade 3
Min
Typ
-70
—
—
-70
—
-90
—
—
-90
—
—
-100
—
—
-100
100 kHz
—
—
-110
—
—
-110
≥ 1 MHz
—
—
-120
—
—
-120
10 kHz to
1.5 MHz
(PCIe)
—
—
3
—
—
3
ps (rms)
—
—
—
—
—
PCIe
Receiver
Detect
—
100 or
125
—
—
100 or
125
—
MHz
—
100
—
125
100
—
125
MHz
1800
± 1%
Max
Unit
1800
± 1%
Max
dBc/Hz
Transceiver Clocks
fixedclk clock
frequency
Reconfiguration clock
(mgmt_clk_clk)
frequency
Receiver
Supported I/O
Standards
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate
(Standard PCS) (21)
GX channels
600
—
8500
600
—
8500
Mbps
Data rate
(10G PCS) (21)
GX channels
600
—
12,500
600
—
12,500
Mbps
Data rate
GT channels
19,600
—
28,050
19,600
—
25,780
Mbps
Absolute VMAX for a
receiver pin (3)
GT channels
—
—
1.2
—
—
1.2
V
Absolute VMIN for a
receiver pin
GT channels
–0.4
—
—
–0.4
—
—
V
GT channels
—
—
1.6
—
—
1.6
V
—
2.2
V
—
—
mV
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration (20)
(8)
GX channels
GT channels
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
after device
configuration (16), (20)
VCCR_GTB =
1.05 V
(VICM =
0.65 V)
—
—
2.2
(8)
GX channels
Minimum differential
eye opening at receiver
serial input pins (4), (20)
June 2019
Altera Corporation
GT channels
GX channels
—
200
—
—
200
(8)
Stratix V Device Datasheet
Page 32
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 3 of 5) (1)
Symbol/
Description
Differential on-chip
termination resistors (7)
Differential on-chip
termination resistors
for GX channels (19)
VICM (AC coupled)
VICM (AC and DC
coupled) for GX
Channels
tLTR (9)
tLTD
(10)
tLTD_manual
(11)
tLTR_LTD_manual (12)
Run Length
CDR PPM
Programmable
equalization
(AC Gain) (5)
Programmable
DC gain (6)
Differential on-chip
termination resistors (7)
Transceiver
Speed Grade 2
Conditions
Transceiver
Speed Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
GT channels
—
100
—
—
100
—
85-setting
—
85 ± 30%
—
—
—
100-
setting
—
—
—
—
120-
setting
—
—
—
—
150-
setting
—
—
—
—
GT channels
—
650
—
—
650
—
mV
VCCR_GXB =
0.85 V or
0.9 V
—
600
—
—
600
—
mV
VCCR_GXB =
1.0 V full
bandwidth
—
700
—
—
700
—
mV
VCCR_GXB =
1.0 V half
bandwidth
—
750
—
—
750
—
mV
—
—
—
10
—
—
10
µs
—
4
—
—
4
—
—
µs
100
± 30%
120
± 30%
150
± 30%
85
± 30%
100
± 30%
120
± 30%
150
± 30%
—
4
—
—
4
—
—
µs
—
15
—
—
15
—
—
µs
GT channels
—
—
72
—
—
72
CID
—
1000
± PPM
—
14
dB
—
7.5
dB
100
—
(8)
GX channels
GT channels
—
—
1000
GX channels
GT channels
—
—
14
—
—
7.5
—
(8)
GX channels
GT channels
—
(8)
GX channels
GT channels
—
(8)
—
100
—
—
Transmitter
Supported I/O
Standards
—
1.4-V and 1.5-V PCML
Data rate
(Standard PCS)
GX channels
600
—
8500
600
—
8500
Mbps
Data rate
(10G PCS)
GX channels
600
—
12,500
600
—
12,500
Mbps
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 33
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 4 of 5) (1)
Symbol/
Description
Transceiver
Speed Grade 2
Conditions
Transceiver
Speed Grade 3
Min
Typ
Max
Min
Typ
Max
19,600
—
25,780
Mbps
—
100
—
500
—
mV
15
—
ps
Data rate
GT channels
19,600
—
28,050
Differential on-chip
termination resistors
GT channels
—
100
—
VOCM (AC coupled)
Rise/Fall time
(8)
GX channels
GT channels
—
500
—
—
(8)
GX channels
GT channels
Unit
—
15
—
—
GX channels
(8)
Intra-differential pair
skew
GX channels
(8)
Intra-transceiver block
transmitter channel-tochannel skew
GX channels
(8)
Inter-transceiver block
transmitter channel-tochannel skew
GX channels
(8)
CMU PLL
Supported Data Range
tpll_powerdown
tpll_lock
(13)
(14)
—
600
—
12500
600
—
8500
Mbps
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
µs
VCO postdivider L=2
8000
—
12500
8000
—
8500
Mbps
L=4
4000
—
6600
4000
—
6600
Mbps
L=8
2000
—
3300
2000
—
3300
Mbps
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5
1000
—
1762.5
Mbps
VCO postdivider L=2
9800
—
14025
9800
—
12890
Mbps
ATX PLL
Supported Data Rate
Range for GX Channels
Supported Data Rate
Range for GT Channels
tpll_powerdown (13)
—
1
—
—
1
—
—
µs
tpll_lock (14)
—
—
—
10
—
—
10
µs
Supported Data Range
—
600
—
3250/
3.125 (23)
600
—
3250/
3.125 (23)
Mbps
tpll_powerdown (13)
—
1
—
—
1
—
—
µs
fPLL
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 34
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 5 of 5) (1)
Symbol/
Description
tpll_lock (14)
Transceiver
Speed Grade 2
Conditions
—
Transceiver
Speed Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
—
—
10
—
—
10
µs
Notes to Table 28:
(1) Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS
speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For
more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. If you enable receiver
equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) Refer to Figure 5 for the GT channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(6) Refer to Figure 6 for the GT channel DC gain curves.
(7) CFP2 optical modules require the host interface to have the receiver data pins differentially terminated with 100 . The internal OCT feature is
available after the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the
optical module. Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(8) Specifications for this parameter are the same as for Stratix V GX and GS devices. See Table 23 for specifications.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when
the CDR is functioning in the manual mode.
(13) tpll_powerdown is the PLL powerdown minimum pulse width.
(14) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(15) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(16) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(17) For ES devices, RREF is 2000 ±1%.
(18) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(19) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(20) Refer to Figure 4.
(21) For oversampling design to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(22) This supply follows VCCR_GXB for both GX and GT channels.
(23) When you use fPLL as a TXPLL of the transceiver.
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 35
Table 29 shows the VOD settings for the GT channel.
Table 29. Typical VOD Setting for GT Channel, TX Termination = 100
VOD Setting
Symbol
VOD differential peak to peak typical (1)
VOD Value (mV)
0
0
1
200
2
400
3
600
4
800
5
1000
Note:
(1) Refer to Figure 4.
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 36
Switching Characteristics
Figure 4 shows the differential transmitter output waveform.
Figure 4. Differential Transmitter/Receiver Output/Input Waveform
Single-Ended Waveform
Positive Channel (p)
VOD/VID (single-ended)
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD/VID (differential peak to peak typical) = 2 x VOD/VID (single-ended)
VOD/VID (single-ended)
VOD/VID (single-ended)
Figure 5 shows the Stratix V AC gain curves for GT channels.
Figure 5. AC Gain Curves for GT Channels
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 37
Figure 6 shows the Stratix V DC gain curves for GT channels.
Figure 6. DC Gain Curves for GT Channels
Transceiver Characterization
This section summarizes the Stratix V transceiver characterization results for
compliance with the following protocols:
June 2019
■
Interlaken
■
40G (XLAUI)/100G (CAUI)
■
10GBase-KR
■
QSGMII
■
XAUI
■
SFI
■
Gigabit Ethernet (Gbe / GIGE)
■
SPAUI
■
Serial Rapid IO (SRIO)
■
CPRI
■
OBSAI
■
Hyper Transport (HT)
■
SATA
■
SAS
■
CEI
Altera Corporation
Stratix V Device Datasheet
Page 38
Switching Characteristics
■
XFI
■
ASI
■
HiGig/HiGig+
■
HiGig2/HiGig2+
■
Serial Data Converter (SDC)
■
GPON
■
SDI
■
SONET
■
Fibre Channel (FC)
■
PCIe
■
QPI
■
SFF-8431
Download the Stratix V Characterization Report Tool to view the characterization
report summary for these protocols.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 30 lists the clock tree specifications for Stratix V devices.
Table 30. Clock Tree Performance for Stratix V Devices
(1)
Performance
Symbol
Unit
C1, C2, C2L, I2, and
I2L
C3, I3, I3L, and
I3YY
C4, I4
Global and
Regional Clock
717
650
580
MHz
Periphery Clock
550
500
500
MHz
Note to Table 30:
(1) The Stratix V ES devices are limited to 600 MHz core clock tree performance.
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 39
PLL Specifications
Table 31 lists the Stratix V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 31. PLL Specifications for Stratix V Devices (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Input clock frequency (C1, C2, C2L, I2, and I2L speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C3, I3, I3L, and I3YY speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C4, I4 speed grades)
5
—
650 (1)
MHz
fINPFD
Input frequency to the PFD
5
—
325
MHz
fFINPFD
Fractional Input clock frequency to the PFD
50
—
160
MHz
PLL VCO operating range (C1, C2, C2L, I2, I2L speed
grades)
600
—
1600
MHz
PLL VCO operating range (C3, I3, I3L, I3YY speed
grades)
600
—
1600
MHz
PLL VCO operating range (C4, I4 speed grades)
600
—
1300
MHz
Input clock or external feedback clock input duty cycle
40
—
60
%
Output frequency for an internal global or regional
clock (C1, C2, C2L, I2, I2L speed grades)
—
—
717 (2)
MHz
Output frequency for an internal global or regional
clock (C3, I3, I3L speed grades)
—
—
650
(2)
MHz
Output frequency for an internal global or regional
clock (C4, I4 speed grades)
—
—
580 (2)
MHz
Output frequency for an external clock output (C1, C2,
C2L, I2, I2L speed grades)
—
—
800 (2)
MHz
Output frequency for an external clock output (C3, I3,
I3L speed grades)
—
—
667
(2)
MHz
Output frequency for an external clock output (C4, I4
speed grades)
—
—
553
(2)
MHz
tOUTDUTY
Duty cycle for a dedicated external clock output (when
set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
10
ns
fDYCONFIGCLK
Dynamic Configuration Clock used for mgmt_clk and
scanclk
—
—
100
MHz
tLOCK
Time required to lock from the end-of-device
configuration or deassertion of areset
—
—
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
—
0.3
—
MHz
—
1.5
—
MHz
—
4
—
MHz
fIN
fVCO (9)
tEINDUTY
fOUT
fOUT_EXT
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
(7)
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
—
ns
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 40
Switching Characteristics
Table 31. PLL Specifications for Stratix V Devices (Part 2 of 3)
Symbol
Min
Typ
Max
Unit
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
—
—
0.15
UI (p-p)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
–750
—
+750
ps (p-p)
Period Jitter for dedicated clock output (fOUT ≥
100 MHz)
—
—
175
(1)
ps (p-p)
Period Jitter for dedicated clock output (fOUT <
100 MHz)
—
—
17.5
(1)
mUI (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT 100 MHz)
—
—
250 (11),
175 (12)
ps (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
—
—
25 (11),
17.5 (12)
mUI (p-p)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT < 100 MHz)
—
—
17.5
mUI (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT 100 MHz)
—
—
250 (11),
175 (12)
ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)+
—
—
25 (11),
17.5 (12)
mUI (p-p)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
—
—
600
ps (p-p)
Period Jitter for a clock output on a regular I/O
(fOUT < 100 MHz)
—
—
60
mUI (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT 100 MHz)
—
—
600 (10)
ps (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
—
—
60 (10)
mUI (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT 100 MHz)
—
—
600
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT < 100 MHz)
—
—
60 (10)
mUI (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT 100 MHz)
—
—
600 (10)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT < 100 MHz)
—
—
60
mUI (p-p)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT < 100 MHz)
—
—
17.5
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for a duration
of 100 µs
—
—
±10
%
dKBIT
Bit number of Delta Sigma Modulator (DSM)
8
24
32
Bits
kVALUE
Numerator of Fraction
128
8388608
2147483648
—
tINCCJ
(3), (4)
(5)
tOUTPJ_DC
tFOUTPJ_DC
tOUTCCJ_DC
(5)
(5)
tFOUTCCJ_DC (5)
tOUTPJ_IO
(5),
(8)
tFOUTPJ_IO (5),
(8), (11)
tOUTCCJ_IO
(5),
(8)
tFOUTCCJ_IO (5),
(8), (11)
tCASC_OUTPJ_DC
(5), (6)
Parameter
Stratix V Device Datasheet
June 2019
Altera Corporation
Switching Characteristics
Page 41
Table 31. PLL Specifications for Stratix V Devices (Part 3 of 3)
Symbol
fRES
Parameter
Resolution of VCO frequency (fINPFD = 100 MHz)
Min
Typ
Max
Unit
390625
5.96
0.023
Hz
Notes to Table 31:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(4) fREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 44 on page 52.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) The external memory interface clock output jitter specifications use a different measurement method, which is available in Table 42 on page 50.
(9) The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration
the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification.
(10) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05 - 0.95 must be 1000 MHz, while fVCO
for fractional value range 0.20 - 0.80 must be 1200 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be 1000 MHz.
(12) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be 1200 MHz.
DSP Block Specifications
Table 32 lists the Stratix V DSP block performance specifications.
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 1 of 2)
Peformance
Mode
C1
C2, C2L
I2, I2L
C3
I3, I3L,
I3YY
Unit
C4
I4
Modes using one DSP
Three 9 x 9
600
600
600
480
480
420
420
MHz
One 18 x 18
600
600
600
480
480
420
400
MHz
Two partial 18 x 18 (or 16 x 16)
600
600
600
480
480
420
400
MHz
One 27 x 27
500
500
500
400
400
350
350
MHz
One 36 x 18
500
500
500
400
400
350
350
MHz
One sum of two 18 x 18(One sum of
2 16 x 16)
500
500
500
400
400
350
350
MHz
One sum of square
500
500
500
400
400
350
350
MHz
One 18 x 18 plus 36 (a x b) + c
500
500
500
400
400
350
350
MHz
Modes using two DSPs
Three 18 x 18
500
500
500
400
400
350
350
MHz
One sum of four 18 x 18
475
475
475
380
380
300
300
MHz
One sum of two 27 x 27
465
465
450
380
380
300
290
MHz
One sum of two 36 x 18
475
475
475
380
380
300
300
MHz
One complex 18 x 18
500
500
500
400
400
350
350
MHz
One 36 x 36
475
475
475
380
380
300
300
MHz
June 2019
Altera Corporation
Stratix V Device Datasheet
Page 42
Switching Characteristics
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 2 of 2)
Peformance
Mode
C1
C2, C2L
I2, I2L
Unit
I3, I3L,
I3YY
C3
C4
I4
Modes using Three DSPs
One complex 18 x 25
425
425
415
340
340
275
265
MHz
380
300
290
MHz
Modes using Four DSPs
One complex 27 x 27
465
465
465
380
Memory Block Specifications
Table 33 lists the Stratix V memory block specifications.
Table 33. Memory Block Performance Specifications for Stratix V Devices (1),
Resources Used
Memory
MLAB
(2)
(Part 1 of 2)
Performance
ALUTs
Memory
C1
C2,
C2L
C3
C4
I2, I2L
I3,
I3L,
I3YY
I4
Single port, all
supported widths
0
1
450
450
400
315
450
400
315
MHz
Simple dual-port,
x32/x64 depth
0
1
450
450
400
315
450
400
315
MHz
Simple dual-port, x16
depth (3)
0
1
675
675
533
400
675
533
400
MHz
ROM, all supported
widths
0
1
600
600
500
450
600
500
450
MHz
Mode
Stratix V Device Datasheet
June 2019
Unit
Altera Corporation
Switching Characteristics
Page 43
Table 33. Memory Block Performance Specifications for Stratix V Devices (1),
Resources Used
(Part 2 of 2)
Performance
ALUTs
Memory
C1
C2,
C2L
C3
C4
I2, I2L
I3,
I3L,
I3YY
I4
Single-port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
Simple dual-port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
Simple dual-port with
the read-during-write
option set to Old Data,
all supported widths
0
1
525
525
455
400
525
455
400
MHz
Simple dual-port with
ECC enabled, 512 × 32
0
1
450
450
400
350
450
400
350
MHz
Simple dual-port with
ECC and optional
pipeline registers
enabled, 512 × 32
0
1
600
600
500
450
600
500
450
MHz
True dual port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
ROM, all supported
widths
0
1
700
700
650
550
700
500
450
MHz
Memory
M20K
Block
(2)
Mode
Unit
Notes to Table 33:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX.
(3) The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
Temperature Sensing Diode Specifications
Table 34 lists the internal TSD specification.
Table 34. Internal Temperature Sensing Diode Specification
Temperature
Range
–40°C to 100°C
Accuracy
Offset
Calibrated
Option
±8°C
No
Sampling Rate
Conversion
Time (1)
Resolution
Minimum
Resolution
with no
Missing Codes
1 MHz, 500 KHz
< 100 ms
8 bits
8 bits
Note to Table 34:
(1) For more details about the temperature sensing operations, refer to the Intel FPGA Temperature Sensor IP Core User Guide.
Table 35 lists the specifications for the Stratix V external temperature sensing diode.
Table 35. External Temperature Sensing Diode Specifications for Stratix V Devices (Part 1 of 2)
Description
June 2019
Min
Typ
Max
Unit
Ibias, diode source current
8
—
200
A
Vbias, voltage across diode
0.3
—
0.9
V
Altera Corporation
Stratix V Device Datasheet
Page 44
Switching Characteristics
Table 35. External Temperature Sensing Diode Specifications for Stratix V Devices (Part 2 of 2)
Description
Min
Typ
Max
Unit
—
—
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