80960CF-40, -33, -25
32-Bit High-Performance Superscalar
Embedded Microprocessor
Datasheet
Product Features
■
■
■
■
Socket and Object Code Compatible with 80960CA
Two Instructions/Clock Sustained Execution
Four 71 Mbytes/s DMA Channels with Data Chaining
Demultiplexed 32-Bit Burst Bus with Pipelining
■
■
■
■
■
■
32-Bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Manipulates 64-Bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
On-Chip Instruction Cache
— 4 Kbyte Two-Way Set Associative
— 128-Bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
Selectable Big or Little Endian Byte
Ordering
■
■
■
■
Four On-Chip DMA Channels
— 71 Mbytes/s Fly-by Transfers
— 40 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
32-Bit Demultiplexed Burst Bus
— 128-Bit Internal Data Paths to and from
Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-Bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-Bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 625 ns Typical
On-Chip Data Cache
— 1 Kbyte Direct-Mapped, Write Through
— 128 bits per Clock Access on Cache Hit
Order Number: 272886-002
September 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960CF-40, -33, -25 32-Bit High-Performance Superscalar Embedded Microprocessor may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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Copyright © Intel Corporation, 2002
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2
Datasheet
Contents
Contents
1.0
Purpose .......................................................................................................................................... 7
2.0
80960CF Processor Overview ...................................................................................................... 7
2.1
2.2
2.3
2.4
2.5
3.0
The 80960C-Series Core ...................................................................................................... 8
Pipelined, Burst Bus ............................................................................................................. 9
Instruction Set Summary ...................................................................................................... 9
Flexible DMA Controller ........................................................................................................9
Priority Interrupt Controller.................................................................................................... 9
Package Information ...................................................................................................................10
3.1
3.2
3.3
3.4
3.5
3.6
4.0
Package Introduction ..........................................................................................................10
Pin Descriptions ..................................................................................................................11
80960CF Mechanical Data .................................................................................................16
3.3.1 80960CF PGA Pinout ............................................................................................16
3.3.2 80960CF PQFP Pinout (80960CF-33 and -25 Only) .............................................20
Package Thermal Specifications ........................................................................................22
Stepping Register Information ............................................................................................24
Sources for Accessories .....................................................................................................25
Electrical Specifications .............................................................................................................26
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings ................................................................................................26
Operating Conditions ..........................................................................................................26
Recommended Connections ..............................................................................................27
D.C. Specifications .............................................................................................................27
A.C. Specifications..............................................................................................................29
4.5.1 A.C. Test Conditions ..............................................................................................35
4.5.2 A.C. Timing Waveforms .........................................................................................36
4.5.3 Derating Curves .....................................................................................................40
5.0
Reset, Backoff and Hold Acknowledge .....................................................................................41
6.0
Bus Waveforms ...........................................................................................................................43
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
80960CF Processor-Block Diagram ............................................................................................. 7
80960CF PGA Pinout—View from Top (Pins Facing Down) ......................................................16
80960CF PGA Pinout—View from Bottom (Pins Facing Up) .....................................................17
80960CF PQFP Pinout—Top View (80960CF-33 and -25 Only) ...............................................22
Measuring 80960CF PGA and PQFP Case Temperature..........................................................23
Register g0 .................................................................................................................................25
A.C. Test Load............................................................................................................................35
Input and Output Clocks Waveform............................................................................................36
CLKIN Waveform........................................................................................................................36
Output Delay and Float Waveform .............................................................................................37
Input Setup and Hold Waveform.................................................................................................37
NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................38
Hold Acknowledge Timings ........................................................................................................38
Datasheet
3
Contents
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Bus Backoff (BOFF) Timings ...................................................................................................... 39
Relative Timings Waveforms ...................................................................................................... 39
Output Delay or Hold vs. Load Capacitance .............................................................................. 40
Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC ................ 40
ICC vs. Frequency and Temperature—80960CF-33 and -25...................................................... 40
ICC vs. Frequency and Temperature—80960CF-40................................................................... 41
Cold Reset Waveform ................................................................................................................ 43
Warm Reset Waveform .............................................................................................................. 44
Entering the ONCE State ........................................................................................................... 45
Clock Synchronization in the 2-x Clock Mode ............................................................................ 46
Clock Synchronization in the 1-x Clock Mode ............................................................................ 46
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 47
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 48
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 49
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 50
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 51
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus........................................ 52
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus............................................. 53
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 54
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus .............................................. 55
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 56
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 57
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 58
Burst, Pipelined Read Request With Wait States, 32-Bit Bus .................................................... 59
Burst, Pipelined Read Request With Wait States, 16-Bit Bus .................................................... 60
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ...................................................... 61
Using External READY ............................................................................................................... 62
Terminating a Burst with BTERM ............................................................................................... 63
BOFF Functional Timing............................................................................................................. 64
HOLD Functional Timing ............................................................................................................ 65
DREQ and DACK Functional Timing .......................................................................................... 66
EOP Functional Timing............................................................................................................... 66
Terminal Count Functional Timing.............................................................................................. 67
FAIL Functional Timing............................................................................................................... 67
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................... 68
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................... 69
Idle Bus Operation ...................................................................................................................... 70
Tables
1
2
3
4
5
6
7
8
9
10
11
4
80960CF Instruction Set............................................................................................................. 10
Symbol Legend........................................................................................................................... 11
80960CF Pin Description—External Bus Signals ....................................................................... 12
80960CF Pin Description—Processor Control Signals .............................................................. 14
80960CF Pin Description—DMA and Interrupt Unit Control Signals .......................................... 15
80960CF PGA Pinout—In Signal Order ..................................................................................... 18
80960CF PGA Pinout—In Pin Order .......................................................................................... 19
80960CF PQFP Pinout—In Signal Order (80960CF-33 and -25 Only) ...................................... 20
80960CF PQFP Pinout—In Pin Order (80960CF-33 and -25 Only) ........................................... 21
Maximum TA at Various Airflows in oC (PGA Package Only) ..................................................... 23
80960CF PGA Package Thermal Characteristics ...................................................................... 24
Datasheet
Contents
12
13
14
15
16
17
18
19
20
21
80960CF PQFP Package Thermal Characteristics ....................................................................24
Die Stepping Cross Reference ...................................................................................................25
Absolute Maximum Ratings ........................................................................................................26
Operating Conditions ..................................................................................................................26
D.C. Specifications .....................................................................................................................28
80960CF AC Characteristics (40 MHz) ......................................................................................29
80960CF AC Characteristics (33 MHz) ......................................................................................31
80960CF AC Characteristics (25 MHz) ......................................................................................33
Reset Conditions ........................................................................................................................42
Hold Acknowledge and Backoff Conditions ................................................................................42
Revision History
Datasheet
Date
Revision
Description
September 2002
002
References to the -16 MHz product have been removed from the datasheet.
June 1996
001
Initial release of the datasheet.
5
Contents
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6
Datasheet
80960-40, -33, -25
1.0
Purpose
This document provides electrical characteristics of Intel’s i960® CF embedded microprocessor.
For functional descriptions consult the i960® CA/CF Microprocessor User’s Manual (order
number 270710). To obtain data sheet updates and errata, visit the Intel World Wide Web site at
http://www.intel.com or contact your Intel field sales representative.
2.0
80960CF Processor Overview
Intel’s 80960CF is the second processor in the series of superscalar i960 microprocessors that also
includes the 80960CA and the 80960HA/HD/HT. Upgrading from the 80960CA to the 80960CF is
straightforward because the two processors are socket- and object code-compatible.
As shown in Figure 1, the 80960CF’s instruction cache is 4 Kbytes; data cache is 1 Kbyte
(80960CA instruction cache is 1 Kbyte; it does not have a data cache.) This extra cache on the CF
adds a significant performance boost over the CA.
Figure 1. 80960CF Processor-Block Diagram
Four-Channel
Instruction
Prefetch Queue
Memory Region
Instruction Cache
(4 Kbyte, Two-Way
Set Associative)
Interrupt
Port
128-BIT CACHE BUS
Programmable
Interrupt Controller
Parallel
Instruction
Scheduler
Multiply/Divide
Unit
Execution
Unit
Register-side
Memory-side
Machine Bus
Machine Bus
Six-Port
Register File
64-Bit
SRC1 Bus
32-Bit
Base Bus
64-Bit
SRC2 Bus
128-Bit
Load Bus
64-Bit
DST Bus
128-Bit
Store Bus
DMA Port
DMA Controller
Control
Configuration
Bus Controller
Bus Request
Queues
Address
Data
1 Kbyte
Direct Mapped
Data Cache
1 Kbyte
Data RAM
5 to 15 Sets
Register Cache
Address
Generation Unit
F_CF001A
Datasheet
7
80960-40, -33, -25
The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special
Function Register extensions to control on-chip peripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip
instruction caching and a sophisticated instruction scheduler allow the processor to sustain
execution of two instructions per clock with peak execution of three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory subsystem. Also, the 80960CF’s on-chip caching of instructions,
procedure context and critical program data substantially decouples system performance from the
wait states associated with accesses to the system’s slower, cost sensitive, main memory
subsystem.
The 80960CF bus controller integrates full wait state and bus width control for highest system
performance with minimal system design complexity. Unaligned access and Big Endian byte order
support reduces the cost of porting existing applications to the 80960CF.
The processor also integrates four complete data-chaining DMA channels and a high-speed
interrupt controller on-chip. DMA channels perform single-cycle or two-cycle transfers, data
packing and unpacking and data chaining. Block transfers — in addition to source or destination
synchronized transfers — are supported.
The interrupt controller provides full programmability of 248 interrupt sources into 32 priority
levels with a typical interrupt task switch (latency) time of 625 ns.
2.1
The 80960C-Series Core
The C-Series core is a very high performance microarchitectural implementation of the 80960 Core
Architecture. This core may sustain execution of two instructions per clock (80 MIPS at 40 MHz).
To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and
innovative microarchitectural constructs into the C-Series core implementation. Factors that
contribute to the core’s performance include:
• Parallel instruction decoding allows issuance of up to three instructions per clock.
• Single-clock execution of most instructions
• Parallel instruction decode allows sustained, simultaneous execution of two single-clock
instructions every clock cycle.
•
•
•
•
•
•
•
8
Efficient instruction pipeline minimizes pipeline break losses.
Register and resource scoreboarding allow simultaneous multi-clock instruction execution.
Branch look-ahead and prediction allows many branches to execute with no pipeline break.
Local Register Cache integrated on-chip caches Call/Return context.
Two-way set associative, 4 Kbyte integrated instruction cache
1 Kbyte integrated Data RAM sustains a four-word (128-bit) access every clock cycle.
Direct mapped, 1 Kbyte data cache, write through, write allocate
Datasheet
80960-40, -33, -25
2.2
Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960CF to external memory and
peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at
40 MHz). Internally programmable wait states and 16 separately configurable memory regions
allow the processor to interface with a variety of memory subsystems with a minimum of system
complexity and a maximum of performance. The Bus Control Unit’s main features include:
•
•
•
•
•
•
•
2.3
Demultiplexed, burst bus to exploit most efficient DRAM access modes
Address pipelining to reduce memory cost while maintaining performance
32-, 16- and 8-bit modes for I/O interfacing ease
Full internal wait state generation to reduce system cost
Little and Big Endian support to ease application development
Unaligned access support for code portability
Three-deep request queue to decouple the bus from the core
Instruction Set Summary
Table 1 summarizes the 80960CF instruction set by logical groupings. For a complete description
of the instruction set, see the i960® CA/CF Microprocessor User’s Manual (order number 270710).
2.4
Flexible DMA Controller
A four-channel DMA controller provides high speed DMA control for data transfers involving
peripherals and memory. The DMA provides advanced features such as data chaining, byte
assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to
71 Mbytes per second at 40 MHz. The DMA controller features a performance and flexibility
which is only possible by integrating the DMA controller and the 80960CF core.
2.5
Priority Interrupt Controller
A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit
external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA
controller and a single non-maskable interrupt input. The 8-bit interrupt port may also be
configured to provide individual interrupt sources that are level or edge triggered.
80960CF interrupts are prioritized and signaled within 225 ns of the request. When the interrupt is
of higher priority than the processor priority, the context switch to the interrupt routine typically
completes in another 400 ns. The interrupt unit provides the mechanism for the low latency and
high throughput interrupt service which is essential for embedded applications.
Table 1 presents the 80960CF Instruction Set.
Datasheet
9
80960-40, -33, -25
Table 1.
80960CF Instruction Set
Data Movement
Arithmetic
Logical
Bit / Bit Field / Byte
Add
Load
Store
Move
Load Address
Subtract
And
Multiply
Not And
Set Bit
Divide
And Not
Clear Bit
Remainder
Or
Not Bit
Modulo
Exclusive Or
Alter Bit
Shift
Not Or
Scan For Bit
*Extended Shift
Or Not
Span Over Bit
Extended Multiply
Nor
Extract
Extended Divide
Exclusive Nor
Modify
Add with Carry
Not
Scan Byte for Equal
Subtract with Carry
Nand
Rotate
Comparison
Branch
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Fault
Call
Unconditional Branch
Call Extended
Conditional Branch
Call System
Compare and Branch
Return
Conditional Fault
Synchronize Faults
Branch and Link
Check Bit
Debug
Call/Return
Processor Mgmt
Atomic
Flush Local Registers
Modify Trace Controls
Mark
Force Mark
Modify Arithmetic
Controls
Atomic Add
Modify Process Controls
Atomic Modify
*System Control
*DMA Control
NOTE: Instructions marked by (*) are 80960Cx extensions to the 80960 instruction set.
3.0
Package Information
3.1
Package Introduction
This section describes the pins, pinouts and thermal characteristics for the 80960CF in the 168-pin
Ceramic Pin Grid Array (PGA) package; the 80960CF-33 and -25 devices are also available in the
196-pin Plastic Quad Flat Package (PQFP). For complete package specifications and information,
see the Intel Packaging Databook, available in individual chapters, at http://www.intel.com.
10
Datasheet
80960-40, -33, -25
3.2
Pin Descriptions
This section defines the 80960CF pins. Table 2 presents the legend for interpreting the pin
descriptions in Tables 3 through 5. Table 3 presents the external bus signals. Table 4 presents
processor control signals. Table 5 presents the DMA and Interrupt Unit control signals.
Note:
Table 2.
All pins float while the processor is in the ONCE mode.
Symbol Legend
Symbol
I
Input only pin
O
Output only pin
I/O
Pin may be either an input or output
–
Datasheet
Description
Pins “must be” connected as described
S(...)
Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation.
Outputs are synchronous to PCLK2:1.
S(E) Edge sensitive input
S(L) Level sensitive input
A(...)
Asynchronous. Inputs may be asynchronous to PCLK2:1.
A(E)Edge sensitive input
A(L)Level sensitive input
H(...)
While the bus is in the Hold Acknowledge or Bus Backoff state, the pin:
H(1) is driven to VCC
H(0)is driven to VSS
H(Z) floats
H(Q)continues to be a valid input
R(...)
While the processor’s RESET pin is low, the pin:
R(1) is driven to VCC
R(0)is driven to VSS
R(Z) floats
R(Q)continues to be a valid output
11
80960-40, -33, -25
Table 3.
80960CF Pin Description—External Bus Signals (Sheet 1 of 2)
Name
Type
Description
A31:2
O
S
H(Z)
R(Z)
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant
bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to
word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word.
During burst accesses, A3:2 increment to indicate successive data cycles.
D31:0
I/O
S(L)
H(Z)
R(Z)
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width
configuration. The least significant bit is carried on D0 and the most significant on D31.
When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3 applies to
D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
32-bit bus:
BE3
BE2
BE1
BE0
BE3:0
O
S
H(Z)
R(1)
Byte Enable 3
Byte Enable 2
Byte Enable 1
Byte Enable 0
enable D31:24
enable D23:16
enable D15:8
enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the processor
uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3
BE2
BE1
BE0
Byte High Enable (BHE)
enable D15:8
Not used (driven high or low)
Address Bit 1 (A1)
Byte Low Enable (BLE)
enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the processor
uses the BE1 and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3
BE2
BE1
BE0
W/R
O
S
H(Z)
R(0)
WRITE/READ is asserted for read requests and deasserted for write requests.
The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R is not ensured to be valid in
the last cycle of a read access.
ADS
O
S
H(Z)
R(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS
is asserted for the first clock of a bus access.
I
S(L)
H(Z)
R(Z)
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. When READY is enabled in a region, the pin is sampled after the
programmed number of wait-states has expired. When the READY pin is deasserted,
wait states continue to be inserted until READY becomes asserted. This is true for the
NRAD, NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended.
BTERM
I
S(L)
H(Z)
R(Z)
BURST TERMINATE is an input which breaks up a burst access and causes another
address cycle to occur. The BTERM signal works in conjunction with the internally
programmed wait-state generator. When READY and BTERM are enabled in a region,
the BTERM pin is sampled after the programmed number of wait states has expired.
When BTERM is asserted, a new ADS signal is generated and the access is completed.
The READY input is ignored when BTERM is asserted. BTERM must be externally
synchronized to satisfy BTERM setup and hold times.
WAIT
O
S
H(Z)
R(1)
WAIT indicates internal wait state generator status. WAIT is asserted when wait states
are being caused by the internal wait state generator and not by the READY or BTERM
inputs. WAIT may be used to derive a write-data strobe. WAIT may also be thought of
as a READY output that the processor provides when it is inserting wait states.
READY
12
Not used (driven high or low)
Not used (driven high or low)
Address Bit 1 (A1)
Address Bit 0 (A0)
Datasheet
80960-40, -33, -25
Table 3.
Datasheet
80960CF Pin Description—External Bus Signals (Sheet 2 of 2)
Name
Type
Description
BLAST
O
S
H(Z)
R(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last
data transfer of burst and non-burst accesses after the wait state counter reaches zero.
BLAST remains asserted until the clock following the last cycle of the last data transfer
of a bus access. When the READY or BTERM input is used to extend wait states, the
BLAST signal remains asserted until READY or BTERM terminates the access.
DT/R
O
S
H(Z)
R(0)
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in
conjunction with DEN to provide control for data transceivers attached to the external
bus. When DT/R is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R changes only while DEN
is high.
DEN
O
S
H(Z)
R(1)
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle. DEN
is used in conjunction with DT/R to provide control for data transceivers attached to the
external bus. DEN remains asserted for sequential reads from pipelined memory
regions. DEN is deasserted when DT/R changes.
LOCK
O
S
H(Z)
R(1)
BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK
may be used to prevent external agents from accessing memory which is currently
involved in an atomic operation. LOCK is asserted in the first clock of an atomic
operation and deasserted in the clock cycle following the last bus access for the atomic
operation. To allow the most flexibility for memory system enforcement of locked
accesses, the processor acknowledges a bus hold request when LOCK is asserted.
The processor performs DMA transfers while LOCK is active.
HOLD
I
S(L)
H(Z)
R(Z)
HOLD REQUEST signals that an external agent requests access to the external bus.
The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA
and BREQ are used together to arbitrate access to the processor’s external bus by
external bus agents.
BOFF
I
S(L)
H(Z)
R(Z)
BUS BACKOFF, when asserted, suspends the current access and causes the bus pins
to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle
and the access is resumed.
HOLDA
O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are
used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET is asserted, the state of the HOLDA pin is independent of the
RESET pin.
BREQ
O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending. BREQ may
be used by external bus arbitration logic in conjunction with HOLD and HOLDA to
determine when to return mastership of the external bus to the processor.
D/C
O
S
H(Z)
R(Z)
DATA OR CODE is asserted for a data request and deasserted for instruction requests.
D/C has the same timing as W/R.
DMA
O
S
H(Z)
R(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA is asserted for any DMA request. DMA is deasserted for all other requests.
SUP
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor
mode. SUP is asserted when the request has supervisor privileges and is deasserted
otherwise. SUP may be used to isolate supervisor code and data structures from nonsupervisor requests.
13
80960-40, -33, -25
Table 4.
80960CF Pin Description—Processor Control Signals (Sheet 1 of 2)
Name
RESET
FAIL
STEST
Type
I
A(L)
H(Z)
R(Z)
O
S
H(Q)
R(0)
I
S(L)
H(Z)
R(Z)
Description
RESET causes the chip to reset. When RESET is asserted, all external signals return
to the reset state. When RESET is deasserted, initialization begins. When the 2-x
clock mode is selected, RESET must remain asserted for 32 CLKIN cycles before
being deasserted to ensure correct processor initialization. When the 1-x clock mode
is selected, RESET must remain asserted for 10,000 CLKIN cycles before being
deasserted to ensure correct processor initialization. The CLKMODE pin selects 1-x
or 2-x input clock division of the CLKIN pin.
The Hold Acknowledge bus state functions while the chip is reset. When the bus is in
the Hold Acknowledge state when RESET is asserted, the processor internally
resets, but maintains the Hold Acknowledge state on external pins until the Hold
request is removed. When a Hold request is made while the processor is in the reset
state, the processor bus grants HOLDA and enters the Hold Acknowledge state.
FAIL indicates failure of the self-test performed at initialization. When RESET is
deasserted and initialization begins, the FAIL pin is asserted. An internal self-test is
performed as part of the initialization process. When this self-test passes, the FAIL
pin is deasserted; otherwise it remains asserted. The FAIL pin is reasserted while the
processor performs an external bus self-confidence test. When this self-test passes,
the processor deasserts the FAIL pin and branches to the user’s initialization routine;
otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAIL pin
may be disabled with the STEST pin.
SELF TEST enables or disables the internal self-test feature at initialization. STEST
is read on the rising edge of RESET. When asserted, internal self-test and external
bus confidence tests are performed during processor initialization. When deasserted,
only the bus confidence tests are performed during initialization.
ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE is
continuously sampled while RESET is low and is latched on the rising edge of
RESET. To place the processor in the ONCE state:
(1) Assert RESET and ONCE (order does not matter)
(2) Wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN
periods in 1-x mode—after VCC and CLKIN are within operating
specifications
ONCE
I
A(L)
H(Z)
R(Z)
(3) Deassert RESET
(4) Wait at least 32 CLKIN periods
(The processor may now be latched in the ONCE state while RESET is high.)
To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert
RESET and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions until Step 4 completes.
CLKIN may then be changed to DC to achieve the lowest possible ONCE mode
leakage current.
ONCE may be used by emulator products or board testers to effectively make an
installed processor transparent in the board.
14
CLKIN
I
A(E)
H(Z)
R(Z)
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
CLKMODE
I
A(L)
H(Z)
R(Z)
CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
a system as the clock mode is not latched by the processor. When left unconnected,
the processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
Datasheet
80960-40, -33, -25
Table 4.
Table 5.
80960CF Pin Description—Processor Control Signals (Sheet 2 of 2)
Name
Type
Description
PCLK2:1
O
S
H(Q)
R(Q)
VSS
–
GROUND connections must be connected externally to a VSS board plane.
VCC
–
POWER connections must be connected externally to a VCC board plane.
VCCPLL
–
VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.
Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in
noisy environments. Otherwise, VCCPLL should be connected to VCC.
NC
–
NO CONNECT pins must not be connected in a system.
PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and
outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.
PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow
flexibility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may
also be connected at the processor to form a single clock signal.
80960CF Pin Description—DMA and Interrupt Unit Control Signals
Name
Type
Description
DREQ3:0
I
A(L)
H(Z)
R(Z)
DMA REQUEST is used to request a DMA transfer. Each of the four signals
requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1
requests channel 1, etc. When two or more channels are requested simultaneously,
the channel with the highest priority is serviced first. Channel priority mode is
programmable.
DACK3:0
O
S
H(1)
R(1)
DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of
the four signals acknowledges a transfer for a single channel. DACK0
acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are
asserted when the requesting device of a DMA is accessed.
EOP/TC3:0
I/O
A(L)
H(Z/Q)
R(Z)
END OF PROCESS/TERMINAL COUNT may be programmed as either an input
(EOP3:0) or output (TC3:0), but not both. Each pin is individually programmable.
When programmed as an input, EOPx causes termination of a current DMA transfer
for the channel that corresponds to the EOPx pin. EOP0 corresponds to channel 0,
EOP1 corresponds to channel 1, etc. When a channel is configured for source and
destination chaining, the EOP pin for that channel causes termination of only the
current buffer transferred and causes the next buffer to be transferred. EOP3:0 are
asynchronous inputs.
When programmed as an output, the channel’s TCx pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx is driven with the same
timing as DACKx during the last DMA transfer for a buffer. When the last bus
request is executed as multiple bus accesses, TCx stays asserted for the entire bus
request.
EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins may
be configured in three modes:
Dedicated Mode: Each pin is a dedicated external interrupt source. Dedicated
inputs may be individually programmed to be level (low) or edge (falling) activated.
XINT7:0
I
A(E/L)
H(Z)
R(Z)
Expanded Mode: The eight pins act together as an 8-bit vectored interrupt source.
The interrupt pins in this mode are level activated. Since the interrupt pins are active
low, the vector number requested is the 1’s complement of the positive logic value
place on the port. This eliminates glue logic to interface to combinational priority
encoders which output negative logic.
Mixed Mode: XINT7:5 are dedicated sources and XINT4:0 act as the five most
significant bits of an expanded mode vector. The least significant bits are set to 010
internally.
NMI
Datasheet
I
A(E)
H(Z)
R(Z)
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated
source.
15
80960-40, -33, -25
3.3
80960CF Mechanical Data
3.3.1
80960CF PGA Pinout
Figure 2 shows the complete 80960CF PGA pinout as viewed from the top side of the component
(i.e., pins facing down). Figure 3 shows the complete 80960CF PGA pinout as viewed from the
pin-side of the package (i.e., pins facing up).
Table 6 presents the 80960CF pin names and package location in signal order. Table 7 presents the
pin names and package location in pin order. See Section 4.0, “Electrical Specifications” on
page 26 for specifications and recommended connections.
Figure 2. 80960CF PGA Pinout—View from Top (Pins Facing Down)
1
2
3
4
5
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
D25
D24
D21
D19
D17
D16
D15
D13
D12
D11
D9
D8
D7
D5
D3
BOFF
NC
D29
D27
D23
D20
D18
VCC
D14
VCC
VCC
D10
VCC
D6
D4
D2
D1
STEST
FAIL
READY D31
D26
D22
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
D0
NC
ONCE
NC
NC
NC
NC
NC
DREQ0
NC
HOLDA BTERM D28
BE2
ADS
VCC
VCC DREQ2 DREQ1
BE1
VCC
VSS
VSS
BLAST
VCC
VSS
VSS
DEN
BE0
VSS
VSS
W/R
VCC
VSS
VSS
DT/R
VCC
VSS
VSS
VCC EOP/TC0
WAIT
DMA
SUP
VSS
VCC EOP/TC1
D/C
BREQ
A30
CLKIN PCLK2 EOP/TC2
LOCK
A29
A28
CLKMODE PCLK1 EOP/TC3
A31
A26
A24
A20
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
NMI
A27
A23
A21
A19
A16
VCC
A13
VCC
VCC
VCC
A7
VCC
A4
A2
XINT6 XINT3 RESET
A25
A22
A18
A17
A15
A14
A12
A11
A10
A9
A8
A6
A5
A3
XINT7 XINT5
R
Q
P
N
M
L
K
J
H
G
F
E
D
10
11
16
5
NC
9
15
4
D30
8
14
3
HOLD
7
13
2
BE3
6
12
1
6
7
VCC
DREQ3
8
DACK0 DACK1
9
VCC
DACK2
VCCPLL DACK3
10
11
12
13
14
XINT4 XINT0
15
XINT1
17
16
17
S
C
B
XINT2
A
F_CA002A
16
Datasheet
80960-40, -33, -25
Figure 3. 80960CF PGA Pinout—View from Bottom (Pins Facing Up)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
NC
BOFF
D3
D5
D7
D8
D9
D11
D12
D13
D15
D16
D17
D19
D21
D24
D25
FAIL
STEST
D1
D2
D4
D6
VCC
D10
VCC
VCC
D14
VCC
D18
D20
D23
D27
D29
NC
NC
ONCE
NC
D0
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
D22
D26
D31
READY
NC
NC
NC
D28
NC
DREQ0
NC
D30
HOLD
BE3
DREQ1 DREQ2
VCC
VCC
ADS
BE2
DREQ3
VSS
VSS
VCC
BE1
VSS
VCC
BLAST
1
1
2
2
3
3
4
4
BTERM HOLDA
5
5
6
6
7
7
VCC
8
8
DACK1 DACK0
VSS
DACK2
VSS
VSS
BE0
DEN
VSS
VSS
VCC
W/R
Metal Lid
9
9
VCC
10
10
DACK3 VCCPLL
11
11
EOP/TC0
VCC
VSS
VSS
VCC
DT/R
EOP/TC1
VCC
VSS
SUP
DMA
WAIT
EOP/TC2 PCLK2 CLKIN
A30
BREQ
D/C
EOP/TC3 PCLK1 CLK MODE
A28
A29
LOCK
12
12
13
13
14
14
15
15
XINT1
XINT0 XINT4
NMI
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
A20
A24
A26
A31
RESET
XINT3 XINT6
A2
A4
VCC
A7
VCC
VCC
VCC
A13
VCC
A16
A19
A21
A23
A27
XINT2
XINT5 XINT7
A3
A5
A6
A8
A9
A10
A11
A12
A14
A15
A17
A18
A22
A25
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
16
16
17
17
A
B
C
F_CA003A
Datasheet
17
80960-40, -33, -25
Table 6.
80960CF PGA Pinout—In Signal Order
Address Bus
18
Data Bus
Bus Control
Processor Control
I/O
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A31
S15
D31
R3
BE3
S5
RESET
A16
DREQ3
A7
A30
Q13
D30
Q5
BE2
S6
DREQ2
B6
A29
R14
D29
S2
BE1
S7
FAIL
A2
DREQ1
A6
A28
Q14
D28
Q4
BE0
R9
DREQ0
B5
A27
S16
D27
R2
DACK3
A10
DACK2
A9
DACK1
A8
DACK0
B8
A26
R15
D26
Q3
A25
S17
D25
S1
A24
Q15
D24
R1
A23
R16
D23
Q2
W/R
ADS
STEST
B2
ONCE
C3
S10
R6
CLKIN
C13
A22
R17
D22
P3
READY
S3
CLKMODE
C14
A21
Q16
D21
Q1
BTERM
R4
PLCK1
B14
EOP/TC3
A14
A20
P15
D20
P2
PLCK2
B13
EOP/TC2
A13
A19
P16
D19
P1
WAIT
S12
EOP/TC1
A12
BLAST
S8
EOP/TC0
A11
XINT7
C17
XINT6
C16
A18
Q17
D18
N2
A17
P17
D17
N1
A16
N16
D16
M1
DT/R
S11
A15
N17
D15
L1
DEN
S9
A14
M17
D14
L2
A13
L16
D13
K1
LOCK
S14
A12
L17
D12
J1
A11
K17
D11
H1
A10
J17
D10
H2
HOLD
R5
A9
H17
D9
G1
HOLDA
S4
A8
G17
D8
F1
BREQ
R13
A7
G16
D7
E1
VSS
Location
C7, C8, C9, C10, C11,
C12, F15, G3, G15,
H3, H15, J3, J15, K3,
K15, L3, L15, M3,
M15, Q7, Q8, Q9,
Q10, Q11
XINT5
B17
XINT4
C15
XINT3
B16
XINT2
A17
Location
XINT1
A15
B7, B9, B11, B12, C6,
E15, F3, F16, G2,
H16, J2, J16, K2, K16,
M2, M16, N3, N15,
Q6, R7, R8, R10, R11
XINT0
B15
NMI
D15
VCC
A6
F17
D6
F2
D/C
S13
A5
E17
D5
D1
DMA
R12
A4
E16
D4
E2
SUP
Q12
A3
D17
D3
C1
A2
D16
D2
D2
D1
C2
D0
E3
VCCPLL
B10
No Connect
BOFF
B1
Location
A1, A3, A4, A5, B3,
B4, C4, C5, D3
Datasheet
80960-40, -33, -25
Table 7.
80960CF PGA Pinout—In Pin Order
Pin
Datasheet
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A1
NC
C1
D3
F17
A6
A2
FAIL
C2
D1
G1
D9
A3
NC
C3
ONCE
G2
A4
NC
C4
NC
A5
NC
C5
A6
DREQ1
C6
A7
DREQ3
C7
A8
DACK1
Signal
M15
VSS
R3
D31
M16
VCC
R4
BTERM
VCC
M17
A14
R5
HOLD
G3
VSS
N1
D17
R6
ADS
NC
G15
VSS
N2
D18
R7
VCC
VCC
G16
A7
N3
VCC
R8
VCC
VSS
G17
A8
N15
VCC
R9
BE0
C8
VSS
H1
D11
N16
A16
R10
VCC
A9
DACK2
C9
VSS
H2
D10
N17
A15
R11
VCC
A10
DACK3
C10
VSS
H3
VSS
P1
D19
R12
DMA
A11
EOP/TC0
C11
VSS
H15
VSS
P2
D20
R13
BREQ
A12
EOP/TC1
C12
VSS
H16
VCC
P3
D22
R14
A29
A13
EOP/TC2
C13
CLKIN
H17
A9
P15
A20
R15
A26
A14
EOP/TC3
C14
CLKMODE
J1
D12
P16
A19
R16
A23
A15
XINT1
C15
XINT4
J2
VCC
P17
A17
R17
A22
A16
RESET
C16
XINT6
J3
VSS
Q1
D21
S1
D25
A17
XINT2
C17
XINT7
J15
VSS
Q2
D23
S2
D29
B1
BOFF
D1
D5
J16
VCC
Q3
D26
S3
READY
B2
STEST
D2
D2
J17
A10
Q4
D28
S4
HOLDA
B3
NC
D3
NC
K1
D13
Q5
D30
S5
BE3
B4
NC
D15
NMI
K2
VCC
Q6
VCC
S6
BE2
B5
DREQ0
D16
A2
K3
VSS
Q7
VSS
S7
BE1
B6
DREQ2
D17
A3
K15
VSS
Q8
VSS
S8
BLAST
B7
VCC
E1
D7
K16
VCC
Q9
VSS
S9
DEN
B8
DACK0
E2
D4
K17
A11
Q10
VSS
S10
W/R
B9
VCC
E3
D0
L1
D15
Q11
VSS
S11
DT/R
B10
VCCPLL
E15
VCC
L2
D14
Q12
SUP
S12
WAIT
B11
VCC
E16
A4
L3
VSS
Q13
A30
S13
D/C
B12
VCC
E17
A5
L15
VSS
Q14
A28
S14
LOCK
B13
PCLK2
F1
D8
L16
A13
Q15
A24
S15
A31
B14
PCLK1
F2
D6
L17
A12
Q16
A21
S16
A27
B15
XINT0
F3
VCC
M1
D16
Q17
A18
S17
A25
B16
XINT3
F15
VSS
M2
VCC
R1
D24
B17
XINT5
F16
VCC
M3
VSS
R2
D27
19
80960-40, -33, -25
3.3.2
80960CF PQFP Pinout (80960CF-33 and -25 Only)
Table 8 and Table 9 present the 80960CF pin names with package location. Figure 4 shows the
80960CF PQFP pinout as viewed from the top side. See Section 4.0, “Electrical Specifications” on
page 26 for specifications and recommended connections.
Table 8.
80960CF PQFP Pinout—In Signal Order (80960CF-33 and -25 Only)
Address Bus
20
Data Bus
Bus Control
Processor Control
I/O
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A31
153
D31
186
BE3
176
RESET
91
DREQ3
60
A30
152
D30
187
BE2
175
FAIL
45
DREQ2
59
A29
151
D29
188
BE1
172
STEST
46
DREQ1
58
A28
145
D28
189
BE0
170
DREQ0
57
A27
144
D27
191
A26
143
D26
192
A25
142
D25
194
A24
141
D24
195
A23
139
D23
3
A22
138
D22
A21
137
A20
W/R
164
ADS
178
4
READY
182
D21
5
BTERM
184
136
D20
6
A19
134
D19
8
WAIT
162
A18
133
D18
9
BLAST
169
A17
132
D17
10
A16
130
D16
11
DT/R
163
A15
129
D15
13
DEN
167
A14
128
D14
14
A13
124
D13
15
A12
123
D12
17
ONCE
43
CLKIN
87
CLKMOD
E
85
DACK3
65
PCLK2
74
DACK2
64
PCLK1
78
DACK1
63
DACK0
62
EOP/TC3
69
EOP/TC2
68
EOP/TC1
67
EOP/TC0
66
XINT7
107
VSS
LOCK
156
Location
2, 7, 16, 24, 30, 38,
39, 49, 56, 70, 75,
77, 81, 83, 88, 89,
92, 98, 105, 109,
110, 121, 125, 131,
135, 147, 150, 161,
165, 173, 174, 185,
196
VCC
XINT6
106
Location
XINT5
102
1, 12, 20, 28, 32, 37,
44, 50, 61, 71, 79,
82, 96, 99, 103, 115,
127, 140, 148, 154,
168, 171, 180, 190
XINT4
101
XINT3
100
A11
122
D11
18
HOLD
181
XINT2
95
A10
120
D10
19
HOLDA
179
XINT1
94
A9
119
D9
21
BREQ
155
XINT0
93
A8
118
D8
22
NMI
108
VCCPLL
72
A7
117
D7
23
D/C
159
No Connect
A6
116
D6
25
DMA
160
Location
A5
114
D5
26
SUP
158
A4
113
D4
27
A3
112
D3
33
BOFF
40
A2
111
D2
34
29, 31, 41, 42, 47,
48, 51, 52, 53, 54,
55, 73, 76, 80, 84,
86, 90, 97, 104, 126,
146, 149, 157, 166,
177, 183, 193
D1
35
D0
36
Datasheet
80960-40, -33, -25
Table 9.
Datasheet
80960CF PQFP Pinout—In Pin Order (80960CF-33 and -25 Only)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
VCC
34
D2
67
EOP/TC1
100
XINT3
133
A18
166
NC
2
VSS
35
D1
68
EOP/TC2
101
XINT4
134
A19
167
DEN
3
D23
36
D0
69
EOP/TC3
102
XINT5
135
VSS
168
VCC
4
D22
37
VCC
70
VSS
103
VCC
136
A20
169
BLAST
5
D21
38
VSS
71
VCC
104
NC
137
A21
170
BE0
6
D20
39
VSS
72
VCCPLL
105
VSS
138
A22
171
VCC
7
VSS
40
BOFF
73
NC
106
XINT6
139
A23
172
BE1
8
D19
41
NC
74
PCLK2
107
XINT7
140
VCC
173
VSS
9
D18
42
NC
75
VSS
108
NMI
141
A24
174
VSS
10
D17
43
ONCE
76
NC
109
VSS
142
A25
175
BE2
11
D16
44
VCC
77
VSS
110
VSS
143
A26
176
BE3
12
VCC
45
FAIL
78
PCLK1
111
A2
144
A27
177
NC
13
D15
46
STEST
79
VCC
112
A3
145
A28
178
ADS
14
D14
47
NC
80
NC
113
A4
146
NC
179
HOLDA
15
D13
48
NC
81
VSS
114
A5
147
VSS
180
VCC
16
VSS
49
VSS
82
VCC
115
VCC
148
VCC
181
HOLD
17
D12
50
VCC
83
VSS
116
A6
149
NC
182
READY
18
D11
51
NC
84
NC
117
A7
150
VSS
183
NC
19
D10
52
NC
85
CLKMODE
118
A8
151
A29
184
BTERM
20
VCC
53
NC
86
NC
119
A9
152
A30
185
VSS
21
D9
54
NC
87
CLKIN
120
A10
153
A31
186
D31
22
D8
55
NC
88
VSS
121
VSS
154
VCC
187
D30
23
D7
56
VSS
89
VSS
122
A11
155
BREQ
188
D29
24
VSS
57
DREQ0
90
NC
123
A12
156
LOCK
189
D28
25
D6
58
DREQ1
91
RESET
124
A13
157
NC
190
VCC
26
D5
59
DREQ2
92
VSS
125
VSS
158
SUP
191
D27
27
D4
60
DREQ3
93
XINT0
126
NC
159
D/C
192
D26
28
VCC
61
VCC
94
XINT1
127
VCC
160
DMA
193
NC
29
NC
62
DACK0
95
XINT2
128
A14
161
VSS
194
D25
30
VSS
63
DACK1
96
VCC
129
A15
162
WAIT
195
D24
31
NC
64
DACK2
97
NC
130
A16
163
DT/R
196
VSS
32
VCC
65
DACK3
98
VSS
131
VSS
164
W/R
33
D3
66
EOP/TC0
99
VCC
132
A17
165
VSS
21
80960-40, -33, -25
Figure 4. 80960CF PQFP Pinout—Top View (80960CF-33 and -25 Only)
98
50
99
49
147
Pin 1
196
148
F_CA004A
3.4
Package Thermal Specifications
The 80960CF is specified for operation when case temperature (TC) is within the range of
0 °C–100 °C for 33 and 25 MHz, and 0 °C–85 °C for 40 MHz. TC may be measured in any
environment to determine whether the 80960CF is within specified operating range. Case
temperature should be measured at the center of the top surface, opposite the pins.
Refer to Figure 5 for more information.
Ambient temperature (TA) is calculated from thermal resistance from case to ambient (θCA) using
Equation 1:
Equation 1. Calculation of Ambient Temperature (TA)
T A = T C – ( P ⋅ θ CA )
Table 10 shows the maximum TA allowable (without exceeding TC) at various airflows and
operating frequencies (fPCLK).
Note that TA is greatly improved by attaching fins or a heatsink to the package. Maximum power
consumption (P) is calculated by using the typical ICC as tabulated in Section 4.4, “D.C.
Specifications” on page 27 and VCC of 5 V.
22
Datasheet
80960-40, -33, -25
Figure 5. Measuring 80960CF PGA and PQFP Case Temperature
Measure PGA temperature at
center of top surface
Measure PQFP case temperature
at center of top surface.
168 - Pin PGA
Pin 196
Pin 1
Table 10. Maximum TA at Various Airflows in oC (PGA Package Only)
Airflow-ft/min (m/sec)
TA with Heatsink (†)
TA without Heatsink (†)
fPCLK
(MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
40
20
40
58
60
66
68
33
38
57
74
76
81
84
25
50
65
79
81
85
87
16
63
74
84
86
89
90
40
0
15
30
40
50
52
33
18
33
47
57
66
67
25
34
46
57
65
72
74
16
51
60
68
74
80
81
† 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Datasheet
23
80960-40, -33, -25
Table 11. 80960CF PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
200
(1.01)
400
(2.03)
600
(3.07)
800
(4.06)
1000
(5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5.)
1.5
1.5
1.5
1.5
1.5
1.5
θ Case-to-Ambient
(No Heatsink)
17
14
11
9
7.1
6.6
13
9
5.5
5
3.9
3.4
θ Case-to-Ambient
(With Heatsink)
θJA
θJC
(See Note 3.)
NOTES:
1. This table applies to 80960CF PGA plugged into socket or soldered directly to board.
2. θJA = θJC + θCA
3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 12. 80960CF PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
50
(0.25)
100
(0.50)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
θ Junction-to-Case (Case Measured
as shown in Figure 5.)
5
5
5
5
5
5
5
θ Case-to-Ambient (No Heatsink)
19
18
17
15
12
10
9
NOTES:
1. This table applies to 80960CF PQFP soldered directly to board.
2. θJA = θJC + θCA
θJC
3.5
Stepping Register Information
Upon reset, register g0 contains die stepping information (see Figure 6). The most significant byte
contains ASCII 0; the upper middle byte contains an ASCII C; the lower middle byte contains an
ASCII F. The least significant byte contains the stepping number in ASCII, and g0 retains this
information until it is overwritten by the user program. Table 13 contains a cross reference of the
number in the least significant byte of register g0 to the die stepping number.
24
Datasheet
80960-40, -33, -25
Figure 6. Register g0
ASCII
DECIMAL
00
43
46 Stepping Number
0
C
F
MSB
Stepping Number
LSB
Table 13. Die Stepping Cross Reference
3.6
g0 Least Significant Byte
Die Stepping
01
A
02
B
03
C
04
D
05
E
Sources for Accessories
The following is a list of suggested sources for 80960CF accessories. This is neither an
endorsement nor a warranty of the performance of any of the listed products and/or companies.
Sockets
1. 3M Textool Test and Interconnection Products
6801 River Place Blvd. Mail Stop 130-3N-29
Austin, TX 78726-9000
(800) 328-0411
2. Augat, Inc. Interconnection Products Group
452 John Dietsch Blvd.
Attleboro Falls, MA 02763
(508) 699-7646
3. Concept Mfg., Inc. (Decoupling Sockets)
400 Walnut St. Suite 609
Redwood City, CA 94063
(415) 365-1162 FAX: (415)265-1164
Heatsinks/Fins
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234
(214) 243-4321
FAX: (214) 241-4656
2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
Datasheet
25
80960-40, -33, -25
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Table 14 presents the absolute maximum ratings for the 80960CF.
Table 14. Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature
–65 °C to +150 °C
Case Temperature Under Bias
–65 °C to +110 °C
Supply Voltage wrt. VSS
–0.5 V to + 6.5 V
Voltage on Other Pins wrt. VSS
Note:
Warning:
4.2
–0.5 V to VCC + 0.5 V
The specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Operating Conditions
Table 15 presents the operating conditions for the 80960CF.
Table 15. Operating Conditions
Symbol
Parameter
Min
Max
Units
4.75
4.50
4.50
5.25
5.50
5.50
V
0
0
0
80
66
50
MHz
8
8
8
40
33
25
MHz
0
0
0
85
100
100
Notes
Supply Voltage
VCC
80960CF-40
80960CF-33
80960CF-25
Input Clock Frequency (2-x Mode)
fCLK2x
80960CF-40
80960CF-33
80960CF-25
Input Clock Frequency (1-x Mode)
fCLK1x
80960CF-40
80960CF-33
80960CF-25
(†)
Case Temp Under Bias
TC
PGA Pkg. (80960CF-40)
PGA Pkg. (80960CF-33, -25 Only)
196-Pin PQFP (80960CF-33, -25 Only)
o
C
† When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a
minimum frequency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still
be stopped when the processor is in a reset condition. When CLKIN is stopped, the specified RESET low
time must be provided once CLKIN restarts and has stabilized.
26
Datasheet
80960-40, -33, -25
4.3
Recommended Connections
Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every
80960CF-based circuit board should include power (VCC) and ground (VSS) planes for power
distribution. Every VCC pin must be connected to the power plane, and every VSS pin must be
connected to the ground plane. Pins identified as ‘NC’ must not be connected in the system.
Liberal decoupling capacitance should be placed near the 80960CF. The processor may cause
transient power surges when its numerous output buffers transition, particularly when connected to
large capacitive loads.
Low inductance capacitors and interconnects are recommended for best high frequency electrical
performance. Inductance may be reduced by shortening the board traces between the processor and
decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages
may offer the lowest possible inductance.
For reliable operation, always connect unused inputs to an appropriate signal level. In particular,
any unused interrupt (XINT, NMI), DMA (DREQ), or BTERM input should be connected to VCC
through a pull-up resistor. Pull-up resistors should be in the in the range of 20 KW for each pin tied
high. When READY or HOLD are not used, the unused input should be connected to ground. N.C.
pins must always remain unconnected. For additional information refer to the i960® CA/CF
Microprocessor User’s Manual (order number 270710).
4.4
D.C. Specifications
Table 16 presents the D.C. specifications of the 80960CF.
Datasheet
27
80960-40, -33, -25
Table 16. D.C. Specifications
Symbol
Parameter (1)
Min
Max
Units
VIL
Input Low Voltage for all pins except RESET
– 0.3
+0.8
V
VIH
Input High Voltage for all pins except RESET
2.0
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
IOH = –1 mA
IOH = – 200 µA
Notes
IOL = 5 mA
V
V
2.4
VCC – 0.5
VILR
Input Low Voltage for RESET
– 0.3
1.5
V
VIHR
Input High Voltage for RESET
3.5
VCC + 0.3
V
±15
µA
0 ≤ VIN ≤ VCC (2)
ILI1
Input Leakage Current for each pin except:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY,
HOLD, CLKMODE
Input Leakage Current for:
BTERM, ONCE, DREQ3:0, STEST,
EOP3:0/TC3:0, NMI, XINT7:0, BOFF
0
– 300
µA
VIN = 0.45 V (3)
ILI3
Input Leakage Current for:
READY, HOLD, CLKMODE
0
500
µA
VIN = 2.4 V (4, 8)
ILO
Output Leakage Current
±15
µA
0.45 ≤ VOUT ≤
VCC
ICC
Supply Current (80960CF-40, 33):
ICC Max
ICCTyp
1150
1000
mA
mA
(5)
(6)
ICC
Supply Current (80960CF-25):
ICC Max
ICCTyp
950
775
mA
mA
(5)
(6)
ICC
Supply Current (80960CF-16):
ICC Max
ICCTyp
750
575
mA
(5)
(6)
225
150
mA
12
pF
FC = 1 MHz
Output Capacitance of each output pin
12
pF
FC = 1 MHz (7)
I/O Pin Capacitance
12
pF
FC = 1 MHz
ILI2
ONCE-mode Supply Current
IONCE
CIN
COUT
CI/O
80960CF-40
80960CF-33, -25, -16
Input Capacitance for: CLKIN, RESET, ONCE,
READY, HOLD, DREQ3:0, BOFF, XINT7:0,
NMI, BTERM, CLKMODE
0
NOTES:
1. 80960CF-33 and -25 under the conditions described in Section 4.2, “Operating Conditions” on page 26.
2. No pullup or pulldown.
3. These pins have internal pullup resistors.
4. These pins have internal pulldown resistors.
5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the
test conditions described in Section 4.5.1, “A.C. Test Conditions” on page 35.
6. ICC Typical is not tested.
7. Output Capacitance is the capacitive load of a floating output.
8. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.
28
Datasheet
80960-40, -33, -25
4.5
A.C. Specifications
Table 17. 80960CF AC Characteristics (40 MHz) (Sheet 1 of 2)
Symbol
Parameter (1)
Min
Max
Units
Notes
0
80
MHz
25
12.5
125
∞
ns
ns
(12)
±0.1%
∆
(13)
Input Clock (2, 10)
TF
TC
TCS
TCH
TCL
CLKIN Frequency
CLKIN Period
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
CLKIN Period Stability
In 1-x Mode (fCLK1x)
CLKIN High Time
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
5
5
62.5
∞
ns
ns
(12)
CLKIN Low Time
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
5
5
62.5
∞
ns
ns
(12)
TCR
CLKIN Rise Time
0
6
ns
TCF
CLKIN Fall Time
0
6
ns
–2
2
2
25
ns
ns
(4, 13)
(4)
ns
ns
(13)
(4)
Output Clocks (2, 9)
TCP
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
PCLK2:1 Period
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
TC
2TC
TPH
PCLK2:1 High Time
(T/2) – 2
T/2
ns
(13)
TPL
PCLK2:1 Low Time
(T/2) – 2
T/2
ns
(13)
TPR
PCLK2:1 Rise Time
1
4
ns
(4)
TPF
PCLK2:1 Fall Time
1
4
ns
(4)
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
14
16
16
16
16
16
16
16
16
16
16
T/2 + 14
14
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
3
22
ns
(7)
Synchronous Outputs (9)
TOH
TOV
TOF
Output Valid Delay, Output Hold
TOH1, TOV1
TOH2, TOV2
TOH3, TOV3
TOH4, TOV4
TOH5, TOV5
TOH6, TOV6
TOH7, TOV7
TOH8, TOV8
TOH9, TOV9
TOH10, TOV10
TOH11, TOV11
TOH12, TOV12
TOH13, TOV13
TOH14, TOV14
(7, 11)
A31:2
BE3:0
ADS
W/R
D/C, SUP, DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
DACK3:0
D31:0
DT/R
FAIL
EOP3:0/TC3:0
Output Float for all outputs
Synchronous Inputs (2, 10, 11)
TIS
Datasheet
Input Setup
TIS1
TIS2
TIS3
TIS4
D31:0
BOFF
BTERM/READY
HOLD
3
15
7
5
ns
ns
ns
ns
29
80960-40, -33, -25
Table 17. 80960CF AC Characteristics (40 MHz) (Sheet 2 of 2)
Symbol
TIH
Parameter (1)
Input Hold
TIH1
TIH2
TIH3
TIH4
Min
Max
5
5
2
3
D31:0
BOFF
BTERM/READY
HOLD
Units
Notes
ns
ns
ns
ns
Relative Output Timings (2, 3, 4, 9)
TAVSH1
A31:2 Valid to ADS Rising
T–4
T+4
ns
TAVSH2
BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS
Rising
T–6
T+6
ns
TAVEL1
A31:2 Valid to DEN Falling
T–4
T+4
ns
TAVEL2
BE3:0, W/R, SUP, INST,DMA, DACK3:0 Valid to DEN
Falling
T–6
T+6
ns
TNLQV
WAIT Falling to Output Data Valid
TDVNH
Output Data Valid to WAIT Rising
TNLNH
WAIT Falling to WAIT Rising
TNHQX
Output Data Hold after WAIT Rising
TEHTV
DT/R Hold after DEN High
T/2 – 7
TTVEL
DT/R Valid to DEN Falling
T/2 – 4
ns
±6
N*T – 6
ns
N*T + 6
N*T ± 4
(N+1)*T–8
(N+1)*T+6
ns
(5)
ns
(5)
ns
(6)
ns
(7)
Relative Input Timings (2, 3, 4)
TIS5
RESET Input Setup (2-x Clock Mode)
6
ns
(14)
TIH5
RESET Input Hold (2-x Clock Mode)
5
ns
(14)
TIS6
DREQ3:0 Input Setup
12
ns
(8)
TIH6
DREQ3:0 Input Hold
7
ns
(8)
TIS7
XINT7:0, NMI Input Setup
7
ns
(16)
TIH7
XINT7:0, NMI Input Hold
3
ns
(16)
TIS8
RESET Input Setup (1-x Clock Mode)
3
ns
(15)
TIH8
RESET Input Hold (1-x Clock Mode)
T/4 + 1
ns
(15)
NOTES:
1. 80960CF-40 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test
Conditions.
2. See Table 19 for all notes related to AC specifications.
30
Datasheet
80960-40, -33, -25
Table 18. 80960CF AC Characteristics (33 MHz) (Sheet 1 of 2)
Symbol
Parameter (1)
Min
Max
Units
Notes
0
66.66
MHz
30
15
125
∞
ns
ns
(12)
±0.1%
∆
(13)
Input Clock (2, 10)
TF
TC
TCS
TCH
TCL
CLKIN Frequency
CLKIN Period
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
CLKIN Period Stability
In 1-x Mode (fCLK1x)
CLKIN High Time
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
5
5
62.5
∞
ns
ns
(12)
CLKIN Low Time
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
5
5
62.5
∞
ns
ns
(12)
TCR
CLKIN Rise Time
0
6
ns
TCF
CLKIN Fall Time
0
6
ns
–2
2
2
25
ns
ns
(4,13)
(4)
ns
ns
(13)
(4)
Output Clocks (2, 9)
TCP
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
PCLK2:1 Period
In 1-x Mode (fCLK1x)
In 2-x Mode (fCLK2x)
TC
2TC
TPH
PCLK2:1 High Time
(T/2) – 2
T/2
ns
(13)
TPL
PCLK2:1 Low Time
(T/2) – 2
T/2
ns
(13)
TPR
PCLK2:1 Rise Time
1
4
ns
(4)
TPF
PCLK2:1 Fall Time
1
4
ns
(4)
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
14
16
18
18
16
16
16
16
16
18
16
T/2 + 14
14
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
3
22
ns
(7)
Synchronous Outputs (9)
TOH
TOV
TOF
Output Valid Delay, Output Hold
A31:2
TOH1, TOV1
BE3:0
TOH2, TOV2
TOH3, TOV3
ADS
TOH4, TOV4
W/R
TOH5, TOV5
D/C, SUP, DMA
TOH6, TOV6
BLAST, WAIT
TOH7, TOV7
DEN
TOH8, TOV8
HOLDA, BREQ
LOCK
TOH9, TOV9
TOH10, TOV10
DACK3:0
TOH11, TOV11
D31:0
DT/R
TOH12, TOV12
TOH13, TOV13
FAIL
TOH14, TOV14
EOP3:0/TC3:0
(7, 11)
Output Float for all outputs
Synchronous Inputs (2, 10, 11)
Datasheet
TIS
Input Setup
TIS1
TIS2
TIS3
TIS4
D31:0
BOFF
BTERM/READY
HOLD
3
17
7
7
ns
ns
ns
ns
TIH
Input Hold
TIH1
TIH2
TIH3
TIH4
D31:0
BOFF
BTERM/READY
HOLD
5
5
2
3
ns
ns
ns
ns
31
80960-40, -33, -25
Table 18. 80960CF AC Characteristics (33 MHz) (Sheet 2 of 2)
Symbol
Parameter (1)
Min
Max
Units
Notes
Relative Output Timings (2, 3, 4, 9)
TAVSH1
A31:2 Valid to ADS Rising
T–4
T+4
ns
TAVSH2
BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS
Rising
T–6
T+6
ns
TAVEL1
A31:2 Valid to DEN Falling
T–4
T+4
ns
TAVEL2
BE3:0, W/R, SUP, INST,DMA, DACK3:0 Valid to DEN
Falling
T–6
T+6
ns
N*T + 6
ns
(5)
ns
(5)
TNLQV
WAIT Falling to Output Data Valid
TDVNH
Output Data Valid to WAIT Rising
TNLNH
WAIT Falling to WAIT Rising
TNHQX
Output Data Hold after WAIT Rising
TEHTV
TTVEL
±6
N*T – 6
ns
N*T ± 4
(N+1)*T–8
(N+1)*T+6
ns
(6)
DT/R Hold after DEN High
T/2 – 7
∞
ns
(7)
DT/R Valid to DEN Falling
T/2 – 4
ns
Relative Input Timings (2, 3, 4)
TIS5
RESET Input Setup (2-x Clock Mode)
6
ns
(14)
TIH5
RESET Input Hold (2-x Clock Mode)
TIS6
DREQ3:0 Input Setup
5
ns
(14)
12
ns
(8)
TIH6
DREQ3:0 Input Hold
7
ns
(8)
TIS7
XINT7:0, NMI Input Setup
7
ns
(16)
TIH7
XINT7:0, NMI Input Hold
3
ns
(16)
TIS8
RESET Input Setup (1-x Clock Mode)
3
ns
(15)
TIH8
RESET Input Hold (1-x Clock Mode)
T/4 + 1
ns
(15)
NOTES:
1. 80960CF-33 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test
Conditions.
2. See Table 19 for all notes related to AC specifications.
32
Datasheet
80960-40, -33, -25
Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 1 of 3)
Symbol
Parameter (1)
Min
Max
Unit
Notes
0
50
MHz
40
20
125
∞
ns
ns
(12)
±0.1%
∆
(13)
Input Clock (2, 10)
TF
TC
TCS
TCH
TCL
CLKIN Frequency
CLKIN Period
In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)
CLKIN Period Stability
In 1-x Mode (f CLK1x)
CLKIN High Time
In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)
8
8
62.5
∞
ns
ns
(12)
CLKIN Low Time
In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)
8
8
62.5
∞
ns
ns
(12)
TCR
CLKIN Rise Time
0
6
ns
TCF
CLKIN Fall Time
0
6
ns
–2
2
2
25
ns
ns
(4, 13)
(4)
ns
ns
(13)
(4)
Output Clocks (2, 9)
TCP
T
CLKIN to PCLK2:1 Delay
In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)
PCLK2:1 Period
In 1-x Mode (f CLK1x)
In 2-x Mode (f CLK2x)
TC
2TC
TPH
PCLK2:1 High Time
(T/2) – 3
T/2
ns
(13)
TPL
PCLK2:1 Low Time
(T/2) – 3
T/2
ns
(13)
TPR
PCLK2:1 Rise Time
1
4
ns
(4)
TPF
PCLK2:1 Fall Time
1
4
ns
(4)
3
3
6
3
4
5
3
4
4
4
3
T/2 + 3
2
3
16
18
20
20
18
18
18
18
18
20
18
T/2 + 16
16
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(7, 11)
3
22
ns
(7)
Synchronous Outputs (9)
TOH
TOV
Output Valid Delay, Output Hold
TOH1, TOV1
TOH2, TOV2
TOH3, TOV3
TOH4, TOV4
TOH5, TOV5
TOH6, TOV6
TOH7, TOV7
TOH8, TOV8
TOH9, TOV9
TOH10, TOV10
TOH11, TOV11
TOH12, TOV12
TOH13, TOV13
TOH14, TOV14
TOF
Output Float for all outputs
(7, 11)
A31:2
BE3:0
ADS
W/R
D/C, SUP, DMA
BLAST, WAIT
DEN
HOLDA, BREQ
LOCK
DACK3:0
D31:0
DT/R
FAIL
EOP3:0/TC3:0
Synchronous Inputs (2, 10, 11)
TIS
TIH
Datasheet
Input Setup
TIS1
TIS2
TIS3
TIS4
Input Hold
TIH1
TIH2
TIH3
TIH4
D31:0
BOFF
BTERM/READY
HOLD
D31:0
BOFF
BTERM/READY
HOLD
5
19
9
9
ns
ns
ns
ns
5
19
9
9
ns
ns
ns
ns
33
80960-40, -33, -25
Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 2 of 3)
Symbol
Parameter (1)
Min
Max
Unit
Notes
Relative Output Timings (2, 3, 4, 9)
TAVSH1
A31:2 Valid to ADS Rising
T–4
T+4
ns
TAVSH2
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
T–6
T+6
ns
TAVEL1
A31:2 Valid to DEN Falling
T–4
T+4
ns
TAVEL2
BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling
T–6
T+6
ns
TNLQV
WAIT Falling to Output Data Valid
TDVNH
Output Data Valid to WAIT Rising
TNLNH
WAIT Falling to WAIT Rising
±6
N*T – F
ns
N*T + 6
N*T ± 4
ns
(5)
ns
(5)
(N+1)*T–
8
(N+1)*T+6
ns
(6)
∞
ns
(7)
TNHQX
Output Data Hold after WAIT Rising
TEHTV
DT/R Hold after DEN High
T/2 – 7
TTVEL
DT/R Valid to DEN Falling
T/2 – 4
ns
Relative Input Timings (2, 3, 4)
34
TIS5
RESET Input Setup (2-x Clock Mode)
8
ns
(14)
TIH5
RESET Input Hold (2-x Clock Mode)
7
ns
(14)
TIS6
DREQ3:0 Input Setup
14
ns
(8)
TIH6
DREQ3:0 Input Hold
9
ns
(8)
TIS7
XINT7:0, NMI Input Setup
9
ns
(16)
TIH7
XINT7:0, NMI Input Hold
5
ns
(16)
TIS8
RESET Input Setup (1-x Clock Mode)
3
ns
(15)
TIH8
RESET Input Hold (1-x Clock Mode)
T/4 + 1
ns
(15)
Datasheet
80960-40, -33, -25
Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 3 of 3)
Symbol
Parameter (1)
Min
Max
Unit
Notes
NOTES:
1. 80960CF-25 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test
Conditions.
2. See Section 4.5.2, A.C. Timing Waveforms for waveforms and definitions.
3. See Figure 16 for capacitive derating information for output delays and hold times.
4. See Figure 17 for capacitive derating information for rise and fall times.
5. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus
Controller Region Table. WAIT never goes active when there are no wait states in an access.
6. N = Number of wait states inserted with READY.
7. Output Data and/or DT/R may be driven indefinitely following a cycle when there is no subsequent bus
activity.
8. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or
hold times to be recognized and for proper operation. However, to ensure recognition of the input at a
particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for
at least two consecutive PCLK2:1 rising edges to be seen by the processor.
9. These specifications are ensured by the processor.
10.These specifications must be met by the system for proper operation of the processor.
11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating
Curves to adjust the timing for PCLK2:1 loading.
12.In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is
operating. When the processor is in reset, the input clock may stop even in 1-x mode.
13.When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation
of less than ± 0.1% between adjacent cycles.
14.In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET
pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 23.)
15.In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper
operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET
pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 24.)
16.The interrupt pins are synchronized internally by the 80960CF. They have no required setup or hold times
for proper operation. These pins are sampled by the interrupt controller every other clock and must be
active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To ensure
recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive
PCLK2:1 rising edges.
4.5.1
A.C. Test Conditions
The AC Specifications in Section 4.5, “A.C. Specifications” on page 29 are tested with the 50 pF
load shown in Figure 7. Figure 16 shows how timings vary with load capacitance.
Specifications are measured at the 1.5 V crossing point, unless otherwise indicated. Input
waveforms are assumed to have a rise and fall time of < 2 ns from 0.8 V to 2.0 V. See Section 4.5.2,
“A.C. Timing Waveforms” on page 36 for AC specification definitions, test points and
illustrations.
Figure 7. A.C. Test Load
Output Pin
CL
CL = 50 pF for all signals
Datasheet
F_CX008A
35
80960-40, -33, -25
4.5.2
A.C. Timing Waveforms
Figure 8. Input and Output Clocks Waveform
CLKIN
1.5 V
TCP
T
2.4 V
1.5 V
0.45 V
1.5 V
PCLK2:1
TPH
TPR
TPL
TPF
F_CX009A
Figure 9. CLKIN Waveform
TCR
TCF
2.0 V
1.5 V
0.8 V
TCH
TCL
TC
F_CX010A
36
Datasheet
80960-40, -33, -25
Figure 10. Output Delay and Float Waveform
1.5 V
PCLK2:1
TOV
TOH
Outputs
Max
Min
1.5 V
1.5 V
TOF
Outputs
1.5 V
Min
Max
1.5 V
1.5 V
F_CX011A
NOTES:
1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum
output delay is referred to as Output Hold (TOH).
2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes
less that ILO in magnitude.
Figure 11. Input Setup and Hold Waveform
PCLK2:1
1.5 V
1.5 V
TIH
TIS
Min
Inputs:
(READY, HOLD, BTERM,
BOFF, DREQ3:0,
D31:0 on reads)
1.5 V
Max
Valid
F_CX012A
NOTE: TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling
window during which synchronous inputs must be stable for correct processor operation.
Datasheet
37
80960-40, -33, -25
Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform
PCLK2:1
1.5 V
1.5 V
Min
NMI, XINT7:0
1.5 V
TIH
TIS
Min
1.5 V
Valid
1.5 V
F_CX013A
Figure 13. Hold Acknowledge Timings
PCLK2:1
1.5 V
1.5 V
1.5 V
TOV
TOF
Min
Outputs:
A31:2, D31:0, BE3:0,
ADS, BLAST, WAIT, W/R,
DT/R, DEN, LOCK,
D/C, SUP, DMA
Max
Min
Max
1.5 V Valid
Valid
TIH
TIS
Min
TIH
Min
TIS
Min
Min
HOLD
1.5 V
1.5 V
1.5 V
TOV
TOV
Min
Min Max
HOLDA
1.5 V
1.5 V
Max
1.5 V
F_CX014A
NOTES:
1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum
output delay is referred to as Output Hold (TOH).
2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes
less that ILO in magnitude.
3. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window
during which synchronous inputs must be stable for correct processor operation.
38
Datasheet
80960-40, -33, -25
Figure 14. Bus Backoff (BOFF) Timings
1.5 V
PCLK2:1
1.5 V
1.5 V
TOV
TOF
Max
Min
Outputs:
A31:2, D31:0, BE3:0,
ADS, BLAST, WAIT, W/R,
DT/R, DEN, LOCK,
D/C, SUP, DMA
1.5 V Valid
1.5 V
TIS
TIS
TIH
BOFF
Min
1.5 V
Valid
Max
TIH
1.5 V
1.5 V
1.5 V
F_CX015A
Figure 15. Relative Timings Waveforms
PCLK2:1
ADS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
TAVSH
A31:2, BE3:0,
W/R, LOCK,
SUP, D/C, DMA
1.5 V
1.5 V
D31:0
TNLQV
TAVEL
DT/R
D31:0
TNHQX
1.5 V
TNLNH
1.5 V
TEHTV
DEN
TDVNH
1.5 V
WAIT
1.5 V
Out
1.5 V
TVEL
1.5 V
In
VIH
VIL
F_CX016A
Datasheet
39
80960-40, -33, -25
4.5.3
Derating Curves
Figure 16. Output Delay or Hold vs. Load Capacitance
Output Valid Delays (ns) @ 1.5 V
nom + 10
All outputs except: LOCK,
DMA, SUP, BREQ, DACK3:0,
EOP3:0/TC3:0, FAIL
nom + 5
LOCK, DMA, SUP, BREQ,
DACK3:0, EOP3:0/TC3:0, FAIL
nom
50
100
CL (pF)
150
Note: PCLK Load = 50pF
F_CX017A
Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC
10
0.8 V to 2.0 V
8
Time (ns)
Time (ns)
8
6
4
2
CL (pF) 50
0.8 V to 2.0 V
10
6
4
2
100
150
CL (pF)
50
100
150
a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ
b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0,
DACK3:0, EOP3:0/TC3:0, FAIL
EOP3:0/TC3:0, FAIL
F_CX019A
Figure 18. ICC vs. Frequency and Temperature—80960CF-33 and -25
900
TC = 100° C
ICC (mA)
TC = 0° C
0
0
ICC - ICC under test conditions
40
fPCLK (MHz)
33
F_CX020A
Datasheet
80960-40, -33, -25
Figure 19. ICC vs. Frequency and Temperature—80960CF-40
1100
ICC (mA)
TC = 1000°
ICC - ICC under test conditions
TC = 85° C
0
0
5.0
fPCLK (MHz)
40
F_CX020A
Reset, Backoff and Hold Acknowledge
Table 20 lists the condition of each processor output pin while RESET is asserted (low). Table 21
lists the condition of each processor output pin while HOLDA is asserted (high).
In Table 21, with regard to bus output pin state only, the Hold Acknowledge state takes precedence
over the reset state. Although asserting the RESET pin internally resets the processor, the
processor’s bus output pins do not enter the reset state when Hold Acknowledge has been granted
to a previous HOLD request (HOLDA is active). Furthermore, the processor grants new HOLD
requests and enters the Hold Acknowledge state even while in reset.
For example, when HOLD is asserted while HOLDA is inactive and the processor is in the reset
state, the processor’s bus pins enter the Hold Acknowledge state and HOLDA is granted. The
processor is not able to perform memory accesses until the HOLD request is removed, even when
the RESET pin is brought high. This operation is provided to simplify boot-up synchronization
among multiple processors sharing the same bus.
Datasheet
41
80960-40, -33, -25
Table 20. Reset Conditions
Pins
State During Reset (HOLDA inactive)
A31:2
Floating
D31:0
Floating
BE3:0
Driven high (Inactive)
W/R
Driven low (Read)
ADS
Driven high (Inactive)
WAIT
Driven high (Inactive)
BLAST
Driven low (Active)
DT/R
Driven low (Receive)
DEN
Driven high (Inactive)
LOCK
Driven high (Inactive)
BREQ
Driven low (Inactive)
D/C
Floating
DMA
Floating
SUP
Floating
FAIL
Driven low (Active)
DACK3:0
EOP3:0/TC3:0
Driven high (Inactive)
Floating (Set to input mode)
Table 21. Hold Acknowledge and Backoff Conditions
Pins
42
State During HOLDA
A31:2
Floating
D31:0
Floating
BE3:0
Floating
W/R
Floating
ADS
Floating
WAIT
Floating
BLAST
Floating
DT/R
Floating
DEN
Floating
LOCK
Floating
BREQ
Driven (High or low)
D/C
Floating
DMA
Floating
SUP
Floating
FAIL
Driven high (Inactive)
DACK3:0
Driven high (Inactive)
EOP3:0/TC3:0
Driven (When output)
Datasheet
RESET
STEST
D31:0,
EOP/TC3:0
INST, SUP,
DMA, A31:2,
D/C, BE3:0
BLAST
W/R, DT/R,
BREQ, FAIL
ADS,
LOCK, WAIT,
DEN, DACK3:0
Inputs
Tdelay
1 PCLK
Valid
Invalid
CLKIN and VCC Stable to RESET high,
minimum 32 CLKIN Periods in 2x Mode,
10,000 CLKIN periods in 1x Mode.
Tsetup
1PCLK
RESET high to First Bus
activity, approximately
32 PCLK periods.
Thold
1 PCLK
∼
∼
∼
∼
PCLK2:1
VCC and CLKIN Stable
to Outputs Valid, maximum
32 CLKIN Periods.
∼
∼ ∼
∼
∼
∼
VCC - ONCE
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
Datasheet
∼
∼ ∼
∼
F_CX021A
6.0
∼
∼
CLKIN
80960-40, -33, -25
Bus Waveforms
Figure 20. Cold Reset Waveform
43
∼
∼
∼
∼
∼
∼
Tdelay
1PCLK
∼
∼
STEST
Maximum RESET Low to RESET State
4 PCLK Periods
∼
∼
Valid
Thold
1 PCLK
∼
∼
Tsetup
1 PCLK
∼
∼ ∼
∼
∼
∼ ∼
∼
∼
∼
D31:0,
EOP/TC3:0
∼
∼
SUP,
DMA, A31:2,
D/C, BE3:0
∼
∼ ∼
∼
∼
∼
BLAST
RESET
∼
∼
∼
∼
∼
∼
∼
∼
W/R, DT/R,
BREQ, FAIL
Figure 21. Warm Reset Waveform
ADS,
LOCK, WAIT,
DEN, DACK3:0
RESET High to First Bus Activity,
Approximately 32 PCLK Periods
Datasheet
Minimum RESET Low Time
16 PCLK Periods
F_CX022A
80960-40, -33, -25
44
PCLK2:1
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
ONCE
∼
∼
RESET
∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼
∼
∼ ∼
∼∼
∼
∼
∼
∼
∼
Maximum 32 CLKIN Periods
Required after ONCE Mode entered
VCC and CLKIN Stable
to Outputs Valid, maximum
32 CLKIN Periods.
∼
∼ ∼
∼
ADS, BE3:0, A31:2,
D31:0, LOCK, WAIT,
BLAST,W/R, D/C, DEN,
DT/R, HOLD, HOLDA,
BLAST, FAIL, SUP,BREQ,
DMA, EOP3:0/TC3:0,
STEST, XINT7:0, NMI,
DACK3:0, DREQ3:0
READY, BTERM
∼
∼
PCLK2:1
∼
∼
VCC
Figure 22. Entering the ONCE State
Datasheet
CLKIN
CLKIN may not float. It must be
driven high or low or continue to run
F_CX023A
45
80960-40, -33, -25
CLKIN and VCC Stable and RESET low and ONCE low to
RESET high, minimum 32 CLKIN Periods in 2x Mode,
10,000 CLKIN Periods in 1x Mode.
80960-40, -33, -25
Figure 23. Clock Synchronization in the 2-x Clock Mode
1.5 V
CLKIN
TIH
RESET
1.5 V
1.5 V
1.5 V
1.5 V
TIS
1.5 V
PCLK2:1
(Case 1)
1.5 V
1.5 V
Max
Min
TCP
PCLK2:1
(Case 2)
1.5 V
Max
Min
1.5 V
Min
TCP Max
1.5 V
TCP
1.5 V
SYNC
Note: Case 1 and Case 2 show two possible polarities of PCLK2:1
F_CX024A
Figure 24. Clock Synchronization in the 1-x Clock Mode
2x CLK
CLKIN
1.5 V
1.5 V
TIH
RESET
TIS
1.5 V
Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal
generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising
edge of CLKIN. The RESET pin is sampled when PCLK is high.
F_CX025A
46
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 25. Non-Burst, Non-Pipelined Requests Without Wait States
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
X
xx
X
xx
0
00000
0
00
X
xx
0
00000
OFF
0
A
D
A
D
A
PipeLining
External
Ready
Control
Burst
1
0
Disabled Disabled
0
0
D
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
Valid
Valid
Valid
Valid
W/R
BLAST
DT/R
DEN
A3:2
Valid
WAIT
D31:0
In
Out
In
F_CX026A
Datasheet
47
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 26. Non-Burst, Non-Pipelined Read Request With Wait States
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
X
xx
X
xx
X
xxxxx
1
01
X
xx
3
00011
OFF
0
A
3
2
1
D
PipeLining
1
External
Ready
Control
Burst
1
0
Disabled Disabled
0
0
A
PCLK
ADS
A31:2, BE3:0
Valid
W/R
BLAST
DT/R
DEN
DMA, D/C,
SUP, LOCK
Valid
WAIT
D31:0
In
F_CX027A
48
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 27. Non-Burst, Non-Pipelined Write Request With Wait States
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
X
xx
X
xx
3
00011
1
01
X
xx
X
xxxxxx
OFF
0
A
3
2
1
D
PipeLining
1
External
Ready
Control
Burst
1
0
Disabled Disabled
0
0
A
PCLK
ADS
A31:2,
BE3:0
Valid
W/R
BLAST
DT/R
DEN
SUP, DMA,
D/C, LOCK
Valid
WAIT
D31:0
Out
F_CX028A
Datasheet
49
80960-40, -33, -25
Bit
Value
Byte
Order
reserved
Function
reserved
Figure 28. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus
31-23
22
0
0..0
X
x
PipeLining
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-Bit
10
X
xx
X
xxxxx
0
00
0
00
0
00000
OFF
0
A
D
D
D
D
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0
In0
In1
In2
In3
F_CX029A
50
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
A
reserved
Function
reserved
Figure 29. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-bit
10
X
xx
X
xxxxx
1
01
1
01
2
00010
OFF
0
D
1
2
1
D
1
D
1
PipeLining
D
1
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0
In0
In1
In2
In3
F_CX030A
Datasheet
51
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 30. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-bit
10
0
00
0
00000
0
00
X
xx
X
xxxxx
OFF
0
A
D
D
D
PipeLining
D
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
Out2
Out3
WAIT
D31:0
Out0
Out1
F_CX031A
52
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
A
reserved
Function
reserved
Figure 31. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-bit
10
1
01
2
00010
1
01
X
xx
X
xxxxx
OFF
0
2
1
D
1
D
1
D
1
PipeLining
D
1
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
A
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0
Out0
Out1
Out2
Out3
F_CX032A
Datasheet
53
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 32. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
16-bit
01
X
xx
X
xxxxx
1
01
1
01
2
00010
OFF
0
Disabled Enabled
1
0
D
1
A
2
1
D
1
D
1
D
1
PipeLining
External
Ready
Control
Burst
1
0
A
PCLK
ADS
SUP, DMA,
D/C, LOCK,
A31:4, BE3/BHE,
BE0/BLE
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
WAIT
D31:0
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
F_CX033A
54
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 33. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
8-bit
00
X
xx
X
xxxxx
1
01
1
01
2
00010
OFF
0
Disabled Enabled
1
0
D
1
A
2
1
D
1
D
1
D
1
PipeLining
External
Ready
Control
Burst
1
0
A
PCLK
ADS
SUP, DMA,
D/C, LOCK,
A31:4
Valid
W/R
BLAST
DT/R
DEN
A3:2
BE1/A1,
BE0/A0
A3:2 = 00, 01, 10 or 11
A1:0 = 00
A1:0 = 01
A1:0 = 10
A1:0 =11
WAIT
D31:0
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
F_CX034A
Datasheet
55
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 34. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
PipeLining
External
Ready
Control
21
20-19
18-17
16-12
11-10
9-8
7-3
2
1
0
0
0
X
xx
X
xx
X
xxxxx
X
xx
X
xx
0
00000
ON
1
X
x
Disabled
0
A
A’
D
A’’
D’
A’’’
D’’
A’’’’
D’’’
Burst
D’’’’
PCLK
ADS
A31:4, SUP,
DMA, D/C,
LOCK
Valid
Valid
Valid
Valid
Valid
Invalid
W/R
A3:2
BE3:0
D31:0
Invalid
Valid
Valid
IN
D
Valid
IN
D’
Valid
IN
D’’
Valid
IN
D’’’
Invalid
IN
D’’’’
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes
pipelined reads begin.
56
Pipelined reads conclude,
non-pipelined requests begin.
F_CX035A
Datasheet
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 35. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
1
0
0
0
X
xx
X
xx
X
xxxxx
X
xx
X
xx
1
00001
ON
1
X
x
Disabled
1
A
1
A’
D
1
PipeLining
External
Ready
Control
Burst
D’
PCLK
ADS
A31:4, SUP,
DMA, D/C,
LOCK
Valid
Valid
Invalid
W/R
A3:2
BE3:0
Invalid
Valid
Valid
IN
D
D31:0
Invalid
IN
D’
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes
pipelined reads begin.
Datasheet
Pipelined reads conclude,
non-pipelined requests begin.
F_CX036A
57
80960-40, -33, -25
Bit
Value
Byte
Order
31-23
22
0
0..0
X
x
reserved
Function
reserved
Figure 36. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-bit
10
X
xx
X
xxxxx
X
xx
0
00
0
00000
ON
1
A
D
D
D
A’
D
D’
PipeLining
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
D’
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
InValid
Valid
InValid
W/R
A3:2
D31:0
00
01
IN
D
10
11
IN
D
IN
D
Valid
Valid
IN
D
IN
D
InValid
IN
D
WAIT
BLAST
DT/R
DEN
Non-pipelined request
concludes, pipelined
reads begin
58
Pipelined reads
conclude, non-pipelined
requests begin
F_CX037A
Datasheet
80960-40, -33, -25
Byte
Order
31-23
22
0
0..0
X
x
Function
Bit
Value
A
reserved
reserved
Figure 37. Burst, Pipelined Read Request With Wait States, 32-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
32-bit
10
X
xx
X
xxxxx
X
xx
1
01
2
00010
ON
1
2
1
D
1
D
1
D
1
PipeLining
A’
D
2
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
1
D’
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
Valid
Valid
Invalid
W/R
A3:2
D31:0
Invalid
00
01
IN
D
10
IN
D
11
IN
D
Valid
IN
D
Invalid
IN
D’
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes,
pipelined reads begin.
Pipelined reads conclude,
non-pipelined requests begin.
F_CX038A
Datasheet
59
80960-40, -33, -25
Byte
Order
31-23
22
0
0..0
X
x
Function
Bit
Value
A
reserved
reserved
Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
16-bit
01
X
xx
X
xxxxx
X
xx
1
01
2
00010
ON
1
2
1
D
1
D
1
D
1
PipeLining
A’
D
2
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
1
D’
PCLK
ADS
A31:4, SUP,
DMA, D/C,
BE0/BLE,
BE3/BHE,
LOCK
Valid
Valid
Invalid
W/R
A3:2
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
D31:0
Invalid
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
Valid
Invalid
Valid
Invalid
D15:0
A1=1
D15:0
D’
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes,
pipelined reads begin.
Pipelined reads conclude,
non-pipelined requests begin.
F_CX040A
60
Datasheet
80960-40, -33, -25
Byte
Order
31-23
22
0
0..0
X
x
Function
Bit
Value
A
reserved
reserved
Figure 39. Burst, Pipelined Read Request With Wait States, 8-Bit Bus
Bus
Width
NWDD
NWAD
NXDA
NRDD
NRAD
21
20-19
18-17
16-12
11-10
9-8
7-3
2
0
0
8-bit
00
X
xx
X
xxxxx
X
xx
1
01
2
00010
ON
1
2
1
D
1
D
1
D
1
A’
D
PipeLining
External
Ready
Control
Burst
1
0
Disabled Enabled
1
0
2
1
D’
PCLK
ADS
A31:4, SUP,
Valid
DMA, D/C,
LOCK
Valid
Invalid
W/R
A3:2
BE1/A1,
BE0/A0
D31:0
Invalid
A3:2 = 00, 01, 10, or 11
A1:0 = 00
Valid
A1:0 = 01
A1:0 = 10
A1:0 = 11
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
Valid
D7:0
Byte 3
Invalid
Invalid
D7:0
D’
WAIT
BLAST
DT/R
DEN
Non-pipelined request concludes,
pipelined reads begin.
Pipelined reads conclude,
non-pipelined requests begin.
F_CX039A
Datasheet
61
80960-40, -33, -25
Figure 40. Using External READY
Quad-Word Write Request
NWAD = 1, NWDD = 0, NWDA = 0
Ready Enabled
Quad-Word Read Request
NRAD = 0, NRDD = 0, NXDA = 0
Ready Enabled
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0,
LOCK
Valid
Valid
W/R
BLAST
DT/R
DEN
READY
BTERM
A3:2
00
01
10
11
00
01
10
11
D1
D2
D3
WAIT
D31:0
D0
D1
D2
D3
D0
F_CX041A
62
Datasheet
80960-40, -33, -25
Figure 41. Terminating a Burst with BTERM
Quad-Word Write Request
NWAD = 0, NWDD = 0, NWDA = 0
Ready Enabled
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0,
LOCK
Valid
W/R
BLAST
DT/R
DEN
READY
See Note
BTERM
A3:2
00
01
10
11
WAIT
D31:0
D0
D1
D2
D3
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal may terminate a bus access when the signal is asserted during
the last (or only) data transfer of the bus access.
Datasheet
F_CX042A
63
80960-40, -33, -25
Figure 42. BOFF Functional Timing
NON-BURST
A31:2, SUP,
DMA, D/C,
BE3:0, WAIT,
DEN, DT/R
D31:0,
(WRITES)
RESUME REQUEST
∼
∼
∼ ∼
∼ ∼
∼ ∼
∼
∼
∼
∼
∼ ∼
∼ ∼
∼ ∼
SUSPEND REQUEST
∼
∼
MAY CHANGE
READY
BOFF
∼
∼ ∼
∼ ∼
∼
BLAST
BURST
∼
∼
∼
∼
∼ ∼
∼ ∼
BURST
∼
∼
∼ ∼
ADS
∼
∼
∼
∼
∼
∼
Regenerate ADS
Begin Request
BOFF may be asserted to suspend request
BOFF may not
be asserted
Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0
64
End Request
BOFF may not
be asserted
F_CX043A
Datasheet
80960-40, -33, -25
Figure 43. HOLD Functional Timing
Word Read Request
NRAD=1, NXDA=1
Hold State
Word Read
Request
NRAD=0,
NXDA=0
Hold State
PCLK2:1
ADS
A31:2, SUP,
DMA, D/C,
BE3:0, WAIT,
DEN, DT/R
Valid
Valid
BLAST
HOLD
HOLDA
F_CX044A
Datasheet
65
80960-40, -33, -25
Figure 44. DREQ and DACK Functional Timing
System
Clock
∼
∼
Start DMA
Bus Request
∼
∼
PCLK2:1
End DMA
Bus Request
(see Note)
DMA
Acknowledge
ADS
! (BLAST
& READY
& !WAIT)
∼
∼∼
∼∼
∼∼
∼∼
∼
DACKx
(All Modes)
DREQx
(Case 1)
DREQx
(Case 2)
high to prevent next bus cycle
tIS6
tIH6
high to prevent next bus cycle
tIS6
DMA
Request
tIH6
Note:
1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized
packing modes and destination synchronized unpacking modes.
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
This applies to all other DMA transfers.
F_CX018A
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
accesses (defined by ADS and BLAST).
Figure 45. EOP Functional Timing
∼
∼
∼ ∼
∼ ∼
PCLK2:1
EOP
2 CLKs Min
15 CLKs Max
Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
triggered. EOP must beheld for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
F_CX045A
66
Datasheet
80960-40, -33, -25
Figure 46. Terminal Count Functional Timing
PCLK2:1
DREQ
ADS
DACK
TC
Note: Terminal Count becomes active during the last bus request of a buffer transfer. When the
last LOAD/STORE bus request is executed as multiple bus accesses, the TC may be active
for the entire bus request. Refer to the i960® Cx Microprocessor User’s Manual for
further information.
F_CX046A
∼
∼
∼
∼
Figure 47. FAIL Functional Timing
RESET
(Bus Test)
Pass
~65,000 Cycles
Fail
5 Cycles
∼
∼
FAIL
∼
∼
(Internal Self-Test)
Pass
Fail
102 Cycles
F_CX047A
Datasheet
67
80960-40, -33, -25
Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
0
4
8
12
16
20
24
Word Offset 0
1
2
3
4
5
6
Byte Offset
Short Request (Aligned)
Byte, Byte Requests
Short-Word
Load/Store
Short Request (Aligned)
Byte, Byte Requests
Word Request (Aligned)
Byte, Short, Byte, Requests
Word
Load/Store
Short, Short Requests
Byte, Short, Byte Requests
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Requests
Short, Word, Short Requests
Double-Word
Load/Store
Byte, Word, Short, Byte Requests
Word, Word Requests
One Double-Word
Request (Aligned)
F_CX048A
68
Datasheet
80960-40, -33, -25
Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions
0
4
8
12
16
20
24
1
2
3
4
5
6
Byte Offset
Word Offset
0
One Three-Word
Request (Aligned)
Byte, Short, Word,
Word, Byte Requests
Triple-Word
Load/Store
Short, Word, Word,
Short Requests
Byte, Word, Word,
Short, Byte Requests
Word, Word,
Word Requests
Word, Word,
Word Requests
Word,
Word,
Word
Requests
One Four-Word
Request (Aligned)
Byte, Short, Word, Word,
Word, Byte Requests
Quad-Word
Load/Store
Short, Word, Word, Word,
Short Requests
Byte, Word, Word, Word,
Short, Byte Requests
Word, Word, Word,
Word Requests
DoubleWord,
DoubleWord,
Requests
F_CX049A
Datasheet
69
80960-40, -33, -25
Figure 50. Idle Bus Operation
Write Request
NWAD=2, NXDA = 0
Ready Disabled
Idle Bus
(not in Hold Acknowledge state)
Read Request
NWAD=2, NXDA = 0
Ready Disabled
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0
Valid
Valid
LOCK
Valid
Valid
W/R
BLAST
DT/R
DEN
A3:2
Valid
Valid
WAIT
D31:0
Out
In
READY,
BTERM
F_CX050A
70
Datasheet
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