87C196LA-20 MHz CHMOS 16-bit
Microcontroller
Automotive
Advanced Information Datasheet
Product Features
■
■
■
■
■
■
■
■
Up to 20 MHz operation
24 Kbytes of on-chip OTPROM
768 bytes of on-chip register RAM
Register-to-register architecture
Peripheral transaction server (PTS) with
high-speed, microcoded interrupt service
routines
Six-channel/10-bit A/D with sample and
hold
High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
Full-duplex serial I/O port with dedicated
baud-rate generator
■
■
■
■
■
■
■
■
■
Enhanced full-duplex, synchronous serial
I/O port (SSIO)
Programmable 8- or 16-bit external bus
Selectable clock doubler with
programmable clock output signal
SFR register that indicates the source of the
last reset
Design enhancements for EMI reduction
Oscillator failure detection circuitry
Watchdog timer (WDT)
-40° C to +125° C ambient temperature
52-pin PLCC package
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272806-004
August 2004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 87C196LA-20 MHz CHMOS 16-bit Microcontroller may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998, 2004
*Third-party brands and names are the property of their respective owners.
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Contents
1.0
Introduction .................................................................................................................. 5
2.0
Nomenclature Overview .......................................................................................... 7
3.0
Pinout .............................................................................................................................. 8
4.0
Signals .......................................................................................................................... 11
5.0
Address Map .............................................................................................................. 17
6.0
Electrical Characteristics ...................................................................................... 18
6.1
6.2
7.0
DC Characteristics .............................................................................................. 19
AC Characteristics (Over Specified Operating Conditions) ............................................. 20
6.2.1 Test Condition ........................................................................................ 20
6.2.2 Explanation of AC Symbols.................................................................... 22
EPROM Specifications ........................................................................................... 25
7.1
7.2
Operating Conditions........................................................................................... 25
EPROM Programming Waveforms ..................................................................... 26
8.0
A/D Converter Specifications .............................................................................. 27
9.0
AC Characteristics - Serial Port - Shift Register Mode ............................. 29
9.1
9.2
Test Conditions ................................................................................................... 29
Waveform - Serial Port - Shift Register Mode0 ................................................... 29
10.0
Thermal Characteristics ........................................................................................ 30
11.0
Design Considerations .......................................................................................... 30
12.0
Device Errata .............................................................................................................. 30
13.0
Datasheet Revision History ................................................................................. 30
Figures
1
2
3
4
5
6
7
8
9
10
11
87C196LA Block Diagram ..................................................................................... 6
Product Nomenclature........................................................................................... 7
87C196LA 52-pin Package ................................................................................... 8
System Bus Timing ............................................................................................. 23
External Clock Drive Waveform .......................................................................... 24
AC Testing Input, Output Waveforms.................................................................. 24
Float Waveform ................................................................................................... 24
Slave Programming Mode Data Program Mode with Single Program Pulse ...... 26
Slave Programming Mode in WORD Dump or Data Verify Mode with
Auto Increment .................................................................................................... 26
Slave Programming Mode Timing in Data Program Mode with Repeated
Program Pulse and Auto Increment .................................................................... 27
Serial Port Waveform - Shift Register Mode ....................................................... 29
Advance Information Datasheet
3
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
Description of Product Nomenclature ................................................................... 7
87C196LA 52-pin Package Pin Assignments ....................................................... 9
Pin Assignment Arranged by Functional Categories........................................... 10
Signal Descriptions ............................................................................................. 11
Address Map ....................................................................................................... 17
Absolute Maximum Ratings ................................................................................ 18
Operating Conditions .......................................................................................... 18
DC Characteristics at VCC = 4.5 V to 5.5 V......................................................... 19
AC Characteristics .............................................................................................. 21
AC Timing Symbol Definitions............................................................................. 22
External Clock Drive............................................................................................ 23
AC EPROM Programming Characteristics.......................................................... 25
DC EPROM Programming Characteristics ......................................................... 25
A/D Operating Conditions - Symbol Descriptions ............................................... 28
A/D Operating Conditions - Parameter Descriptions........................................... 28
Serial Port Timing - Shift Register Mode ............................................................. 29
Thermal Characteristics ...................................................................................... 30
Revision History .................................................................................................. 30
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
1.0
Introduction
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a
high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096
compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port
with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a
flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six
modularized, multiplexed high-speed I/O for capture and compare (called event processor array)
with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt
structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and
oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a
more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices
where a separate resonator was required in the past. Another cost-savings feature is the fact that the
I/O ports are driven low at reset, avoiding the need for pull-up resistors.
Advance Information Datasheet
5
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Figure 1. 87C196LA Block Diagram
Watchdog
Timer
Port 6
Port 0
Enhanced
SSIO
A/D
Converter
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
Bus Control
Bus
Controller
AD15:0
Memory Addr Bus (16)
Memory Data Bus (16)
Port 2
SIO
Peripheral
Transaction
Server
Bus-Control
Interface Unit
Queue
Interrupt
Controller
Microcode
Engine
Baud-rate
Generator
6 Capture/
Compare
Channels †
EPA
2 Timers
2
Compare-only
Channels
Source (16)
Port 1,6
ALU
Register RAM
768 Bytes
Memory
Interface
Unit
Destination (16)
OTPROM
24 Kbytes
† Two additional capture/compare channels (EPA6 and EPA7) are available as software timers.
They are not connected to package pins.
A3417-01
6
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
2.0
Nomenclature Overview
Figure 2. Product Nomenclature
X
XX
8
X
X
XXXXX
XX
ed
pe
eS
v ic
De
ily
am
tF
uc
od
on
Pr
ati
ns
rm
tio
nfo
Op
sI
ry
es
mo
oc
Pr
me
mra
og
Pr
ns
tio
ns
Op
tio
in
Op
nur
ing
ag
dB
ck
an
Pa
re
a tu
er
mp
Te
A2815-01
Table 1. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in Options
x
Automotive operating temperature range (-40°C to
125°C ambient) with Intel standard burn-in.
Packaging Options
x
PLCC
Program-memory Options
7
OTPROM
Process Information
C
CHMOS
Product Family
196Lx
Device Speed
20
8XC196Lx family of products
20 MHz
NOTE: To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
Advance Information Datasheet
7
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
3.0
Pinout
7
6
5
4
3
2
1
52
51
50
49
48
47
AD15 / P4.7 / PBUS.15
P5.2 / PLLEN / WR# / WRL#
P5.3 / RD#
VPP
VSS
P5.0 / ADV# / ALE
VSS1
XTAL1
XTAL2
P6.7 / SD1
P6.6 / SC1
P6.5 / SD0
P6.4 / SC0
Figure 3. 87C196LA 52-pin Package
8
9
10
11
12
13
14
15
16
17
18
19
20
xx87C196LA20
View of component as
mounted on PC board
46
45
44
43
42
41
40
39
38
37
36
35
34
P6.1 / EPA9 / COMP1
P6.0 / EPA8 / COMP0
P1.0 / EPA0 / T2CLK
P1.1 / EPA1
P1.2 / EPA2 / T2DIR
P1.3 / EPA3
VREF
ANGND
P0.7 / ACH7 / PMODE.3
P0.6 / ACH6 / PMODE.2
P0.5 / ACH5 / PMODE.1
P0.4 / ACH4 / PMODE.0
P0.3 / ACH3
AD1 / P3.1 / PBUS.1
AD0 / P3.0 / PBUS.0
RESET#
EA#
VSS1
VCC
P2.0 / TXD / PVER
P2.1 / RXD / PALE#
P2.2 / EXTINT / PROG#
P2.4 / AINC#
P2.6 / ONCE / CPVER
P2.7 / CLKOUT / PACT#
P0.2 / ACH2
21
22
23
24
25
26
27
28
29
30
31
32
33
AD14 / P4.6 / PBUS.14
AD13 / P4.5 / PBUS.13
AD12 / P4.4 / PBUS.12
AD11 / P4.3 / PBUS.11
AD10 / P4.2 / PBUS.10
AD9 / P4.1 / PBUS.9
AD8 / P4.0 / PBUS.8
AD7 / P3.7 / PBUS.7
AD6 / P3.6 / PBUS.6
AD5 / P3.5 / PBUS.5
AD4 / P3.4 / PBUS.4
AD3 / P3.3 / PBUS.3
AD2 / P3.2 / PBUS.2
A3419-03
8
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 2. 87C196LA 52-pin Package Pin Assignments
Pin
Name
Pin
Name
Pin
Name
1
VSS1
19
AD3 / P3.3 / PBUS.3
37
P0.6 / ACH6 / PMODE.2
2
P5.0 / ADV# / ALE
20
AD2 / P3.2 / PBUS.2
38
P0.7 / ACH7 / PMODE.3
3
VSS
21
AD1 / P3.1 / PBUS.1
39
ANGND
4
VPP
22
AD0 / P3.0 / PBUS.0
40
VREF
5
P5.3 / RD#
23
RESET#
41
P1.3 / EPA3
6
P5.2 / PLLEN / WR# / WRL#
24
EA#
42
P1.2 / EPA2 / T2DIR
7
AD15 / P4.7 / PBUS.15
25
VSS1
43
P1.1 / EPA1
8
AD14 / P4.6 / PBUS.14
26
VCC
44
P1.0 / EPA0 / T2CLK
9
AD13 / P4.5 / PBUS.13
27
P2.0 / TXD / PVER
45
P6.0 / EPA8 / COMP0
10
AD12 / P4.4 / PBUS.12
28
P2.1 / RXD / PALE#
46
P6.1 / EPA9 / COMP1
11
AD11 / P4.3 / PBUS.11
29
P2.2 / EXTINT / PROG#
47
P6.4 / SC0
12
AD10 / P4.2 / PBUS.10
30
P2.4 / AINC#
48
P6.5 / SD0
13
AD9 / P4.1 / PBUS.9
31
P2.6 / ONCE/CPVER
49
P6.6 / SC1
14
AD8 / P4.0 / PBUS.8
32
P2.7 / CLKOUT / PACT#
50
P6.7 / SD1
15
AD7 / P3.7 / PBUS.7
33
P0.2 / ACH2
51
XTAL2
16
AD6 / P3.6 / PBUS.6
34
P0.3 / ACH3
52
XTAL1
17
AD5 / P3.5 / PBUS.5
35
P0.4 / ACH4 / PMODE.0
18
AD4 / P3.4 / PBUS.4
36
P0.5 / ACH5 / PMODE.1
Advance Information Datasheet
9
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 3. Pin Assignment Arranged by Functional Categories
Addr & Data
Name
Input/Output (Cont’d)
Pin
AD0
22
P2.1 / RXD
AD1
21
P2.2
AD2
20
P2.4
AD3
19
P2.6
AD4
18
P2.7
AD5
17
AD6
16
AD7
AD8
Pin
28
Name
Processor Control
Pin
Name
Pin
AINC#
30
EA#
24
29
CPVER
31
EXTINT
29
30
PACT#
32
PLLEN
6
31
PALE#
28
RESET#
23
32
PBUS.0
22
XTAL1
52
P3.0
22
PBUS.1
21
XTAL2
51
P3.1
21
PBUS.2
20
15
P3.2
20
PBUS.3
19
14
P3.3
19
PBUS.4
18
Name
AD9
13
P3.4
18
PBUS.5
17
ADV# / ALE
2
AD10
12
P3.5
17
PBUS.6
16
CLKOUT
32
AD11
11
P3.6
16
PBUS.7
15
RD#
5
AD12
10
P3.7
15
PBUS.8
14
WR# / WRL#
6
AD13
9
P4.0
14
PBUS.9
13
AD14
8
P4.1
13
PBUS.10
12
AD15
7
P4.2
12
PBUS.11
11
P4.3
11
PBUS.12
10
ANGND
39
P4.4
10
PBUS.13
9
VCC
26
Input/Output
10
Name
Program Control
Bus Cont & Status
Pin
Power & Ground
Name
Pin
Name
Pin
P4.5
9
PBUS.14
8
VPP
4
P0.2 / ACH2
33
P4.6
8
PBUS.15
7
VREF
40
P0.3 / ACH3
34
P4.7
7
PMODE.0
35
VSS
3
P0.4 / ACH4
35
P5.0
2
PMODE.1
36
VSS1
1
P0.5 / ACH5
36
P5.2
6
PMODE.2
37
VSS1
25
P0.6 / ACH6
37
P5.3
5
PMODE.3
38
P0.7 / ACH7
38
P6.0 / EPA8 /
COMP0
45
PROG#
29
P1.0 / EPA0 /
T2CLK
44
P6.1 / EPA9 /
COMP1
46
PVER
27
P1.1 / EPA1
43
P6.4 / SC0
47
P1.2 / EPA2 /
T2DIR
42
P6.5 / SD0
48
P1.3 / EPA3
41
P6.6 / SC1
49
P2.0 / TXD
27
P6.7 / SD1
50
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
4.0
Signals
Table 4. Signal Descriptions (Sheet 1 of 6)
Name
Type
Description
Analog Channels
These signals are analog inputs to the A/D converter.
ACH7:2
I
The A/D inputs share package pins with port 0. These pins may individually be
used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the
pins to function simultaneously as analog and digital inputs, this is not
recommended because reading port 0 while a conversion is in process can
produce unreliable conversion results.
The ANGND and VREF pins must be connected for the A/D converter and port 0 to
function.
ACH7:2 share package pins with the following signals: ACH2/P0.2, ACH3/P0.3,
ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1, ACH6/P0.6/PMODE.2, and ACH7/
P0.7/PMODE.3.
Address/Data Lines
AD15:0
I/O
These pins provide a multiplexed address and data bus. During the address phase
of the bus cycle, address bits 0–15 are presented on the bus and can be latched
using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred.
AD7:0 share package pins with P3.7:0 and PBUS.7:0. AD15:8 share package pins
with P4.7:0 and PBUS.15:8.
Address Valid
ADV#
O
This active-low output signal is asserted only during external memory accesses.
ADV# indicates that valid address information is available on the system address/
data bus. The signal remains low while a valid bus cycle is in progress and is
returned high as soon as the bus cycle completes.
An external latch can use this signal to demultiplex the address from the address/
data bus. A decoder can also use this signal to generate chip selects for external
memory.
ADV# shares a package pin with P5.0 and ALE.
Auto Increment
AINC#
I
During slave programming, this active-low input enables the auto-increment
feature. (Auto increment allows reading or writing of sequential OTPROM
locations, without requiring address transactions across the programming bus for
each read or write.) AINC# is sampled after each location is programmed or
dumped. If AINC# is asserted, the address is incremented and the next data word
is programmed or dumped.
AINC# shares a package pin with P2.4.
Advance Information Datasheet
11
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 4. Signal Descriptions (Sheet 2 of 6)
Name
Type
Description
Address Latch Enable
ALE
O
This active-high output signal is asserted only during external memory cycles. ALE
signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus.
An external latch can use this signal to demultiplex the address from the address/
data bus.
ALE shares a package pin with P5.0 and ADV#.
Analog Ground
ANGND
GND
ANGND must be connected for A/D converter and port 0 operation. ANGND and
VSS should be nominally at the same potential.
Clock Output
CLKOUT
O
Output of the internal clock generator. You can select one of three frequencies:
f, f/2, or f/4. CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7 and PACT#.
Event Processor Array (EPA) Compare Pins
COMP1:0
O
These signals are the outputs of the EPA compare-only channels.
COMP1:0 share package pins with the following signals: COMP0/P6.0/EPA8 and
COMP1/P6.1/EPA9.
Cumulative Program Verification
CPVER
O
During slave or programming, a high signal indicates that all locations programmed
correctly, while a low signal indicates that an error occurred during the program
operation.
CPVER shares a package pin with P2.6 and ONCE#.
External Access
EA#
I
This input determines whether memory accesses to special-purpose and program
memory partitions are directed to internal or external memory. These accesses are
directed to internal memory if EA# is held high and to external memory if EA# is
held low. For an access to any other memory location, the value of EA# is
irrelevant.
EA# also controls entry into the programming modes. If EA# is at VPP voltage
(typically +12.5 V) on the rising edge of RESET#, the microcontroller enters a
programming mode.
EA# is sampled and latched only on the rising edge of RESET#. Changing the level
of EA# after reset has no effect.
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
EPA9:8
EPA3:0
12
I/O
The EPA signals share package pins with the following signals: EPA0/P1.0/T2CLK,
EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3, EPA8/P6.0/COMP0, and EPA9/P6.1/
COMP1. EPA7:6 do not connect to package pins. They cannot be used to capture
an event, but they can function as software timers. EPA5:4 are not implemented.
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 4. Signal Descriptions (Sheet 3 of 6)
Name
Type
Description
External Interrupt
In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending bit. EXTINT is sampled during phase 2. The minimum high time is one
state time.
EXTINT
I
In powerdown mode, asserting the EXTINT signal causes the device to resume
normal operation. The interrupt does not need to be enabled.
In idle mode, asserting any enabled interrupt causes the device to resume normal
operation.
EXTINT shares a package pin with P2.2 and PROG#.
Port 0
This is a high-impedance, input-only port. Port 0 pins should not be left floating.
P0.7:2
I
The port 0 signals share package pins with the A/D inputs. These pins may
individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is
possible for the pins to function simultaneously as analog and digital inputs, this is
not recommended because reading port 0 while a conversion is in process can
produce unreliable conversion results.
ANGND and VREF must be connected for port 0 to function.
P0.3:2 share package pins with ACH3:2 and P0.7:4 share package pins with
ACH7:4 and PMODE.3:0.
Port 1
P1.3:0
I/O
This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.
Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK, P1.1/
EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3.
Port 2
P2.7:6
P2.4
P2.2:0
I/O
This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.
Port 2 shares package pins with the following signals: P2.0/TXD/PVER, P2.1/RXD/
PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#, P2.6/ONCE/CPVER.
P2.7/OSCOUT/PACT# is output pin only.
Port 3
P3.7:0
I/O
This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain
or complementary output modes. The pins are shared with the multiplexed
address/data bus, which has complementary drivers.
P3.7:0 share package pins with AD7:0 and PBUS.7:0.
Port 4
P4.7:0
I/O
This is a memory-mapped, 8-bit, bidirectional port with open-drain or
complementary output modes. The pins are shared with the multiplexed address/
data bus, which has complementary drivers.
P4.7:0 share package pins with AD15:8 and PBUS.15:8.
Port 5
P5.3:2
P5.0
I/O
Advance Information Datasheet
This is a memory-mapped, bidirectional port.
Port 5 shares package pins with the following signals: P5.0/ADV#/ALE, P5.2/WR#/
WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not implemented.
13
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 4. Signal Descriptions (Sheet 4 of 6)
Name
Type
Description
Port 6
P6.7:4
P6.1:0
O
This is a standard bidirectional port.
Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0, P6.1/
EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1.
Programming Active
PACT#
O
During auto programming or slave dump, a low signal indicates that programming
or dumping is in progress, while a high signal indicates that the operation is
complete.
PACT# shares a package pin with P2.7 and OSCOUT.
Programming ALE
PALE#
I
During slave programming, a falling edge causes the device to read a command
and address from the programming bus.
PALE# is multiplexed with P2.1 and RXD.
Address/Command/Data Bus
During slave programming, ports 3 and 4 serve as a bidirectional port with opendrain outputs to pass commands, addresses, and data to or from the device. Slave
programming requires external pull-up resistors.
PBUS.15:0
I/O
During auto programming and ROM-dump, ports 3 and 4 serve as a regular system
bus to access external memory. P4.6 and P4.7 are left unconnected; P1.1 and
P1.2 serve as the upper address lines.
Slave programming:
PBUS.7:0 share package pins with AD7:0 and P3.7:0.
PBUS.15:8 share package pins with AD15:8 and P4.7:0.
Auto programming:
PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share package
pins with AD7:0 and P3.7:0.
Phase-locked Loop Enable
PLLEN
I
This active-high input pin enables the on-chip clock multiplier. Tie this pin to VCC at
power-up to bypass the on-chip clock multiplier.
Programming Mode Select
PMODE.3:0
I
These pins determine the programming mode. PMODE3:0 are sampled after a
device reset and must be static while the microcontroller is operating.
PMODE3:0 share package pins with P0.7:4 and ACH7:4.
Programming Start
PROG#
I
During programming, a falling edge latches data on the programming bus and
begins programming, while a rising edge ends programming. The current location
is programmed with the same data as long as PROG# remains asserted, so the
data on the programming bus must remain stable while PROG# is active.
During a word dump, a falling edge causes the contents of an OTPROM location to
be output on the PBUS, while a rising edge ends the data transfer.
PROG# shares a package pin with P2.2 and EXTINT.
Program Verification
PVER
O
During slave or auto programming, PVER is updated after each programming
pulse. A high output signal indicates successful programming of a location, while a
low signal indicates a detected error.
PVER shares a package pin with P2.0 and TXD.
14
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 4. Signal Descriptions (Sheet 5 of 6)
Name
Type
Description
Read
RD#
O
Read-signal output to external memory. RD# is asserted during external memory
reads.
RD# shares a package pin with P5.3.
Reset
RESET#
I/O
A level-sensitive reset input to, and an open-drain system reset output from, the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times.
In the powerdown and idle modes, asserting RESET# causes the microcontroller to
reset and return to normal operating mode. After a reset, the first instruction fetch is
from 2080H.
Receive Serial Data
RXD
I/O
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as
either an input or an open-drain output for data.
RXD shares a package pin with P2.1 and PALE#.
Clock Pins for SSIO0 and 1
For handshaking transfers, configure SC1:0 as open-drain outputs.
SC1:0
I/O
This pin carries a signal only during receptions and transmissions. When the SSIO
port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6.
Data Pins for SSIO0 and 1
SD1:0
I/O
These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure
SDx as a complementary output signal. For receptions, configure SDx as a highimpedance input signal.
SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7.
Timer 2 External Clock
T2CLK
I
External clock for timer 2. Timer 2 increments (or decrements) on both rising and
falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature
counting mode.
T2CLK shares a package pin with P1.0 and EPA0.
Timer 2 External Direction
T2DIR
I
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. It is also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR shares a package pin with P1.2 and EPA2.
Transmit Serial Data
TXD
O
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it
is the serial clock output.
TXD shares a package pin with P2.0 and PVER.
Advance Information Datasheet
15
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 4. Signal Descriptions (Sheet 6 of 6)
Name
Type
Description
Digital Supply Voltage
VCC
PWR
Connect each VCC pin to the digital supply voltage.
Programming Voltage
VPP
PWR
VPP causes the device to exit powerdown mode when it is driven low for at least 50
ns. Use this method to exit powerdown only when using an external clock source
because it enables the internal phase clocks, but not the internal oscillator.
If you do not plan to use the powerdown feature, connect VPP to VCC.
Reference Voltage for the A/D Converter
VREF
PWR
This pin supplies operating voltage to the A/D converter.
Digital Circuit Ground
VSS, VSS1
GND
These pins supply ground for the digital circuitry. Connect each VSS and VSS1 pin to
ground through the lowest possible impedance path. VSS pins are connected to the
core ground region of the microcontroller, while VSS1 pins are connected to the port
ground region. (ANGND is connected to the analog ground region.) Separating the
ground regions provides noise isolation.
Write†
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR#
O
Forcing WR# high while RESET# is low causes the device to enter PLL-bypass
mode. When the device is in PLL-bypass mode, the internal phase clocks operate
at one-half the frequency of the frequency on XTAL1.
WR# shares a package pin with P5.2, WRL#, and PLLEN.
† When
this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR# or
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Write Low†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes to external memory. During 8-bit bus cycles, WRL# is
asserted for all write operations.
WRL#
O
WRL# shares a package pin with P5.2, WR#, and PLLEN.
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR# or
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Input Crystal/Resonator or External Clock Input
XTAL1
I
Input to the on-chip oscillator and the internal clock generators. The internal clock
generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When
using an external clock source instead of the on-chip oscillator, connect the clock
input to XTAL1. The external clock signal must meet the VIH specification for
XTAL1.
Inverted Output for the Crystal/Resonator
XTAL2
16
O
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
5.0
Address Map
Table 5. Address Map
Hex
Address
Range
Description
Addressing
Modes
FFFF 8000
External device (memory or I/O) connected to address/data bus
Indirect or indexed
7FFF 2080
Program memory (internal nonvolatile or external memory); see
Note 1.
Indirect or indexed
207F 2000
Special-purpose memory (internal nonvolatile or external memory)
Indirect or indexed
1FFF 1FE0
Memory-mapped SFRs
Indirect or indexed
1FDF 1F00
Peripheral SFRs
Indirect, indexed, or
windowed direct
1EFF 0300
External device (memory or I/O) connected to address/data bus;
(future SFR expansion; see Note 2).
Indirect or indexed
02FF 0100
Upper register file (general-purpose register RAM)
Indirect, indexed, or
windowed direct
00FF 0000
Lower register file (register RAM, stack pointer, and CPU SFRs)
Direct, indirect, or
indexed
NOTES:
1. After a reset, the microcontroller fetches its first instruction from 2080H.
2. The content or function of these locations may change in future microcontroller revisions, in which case a
program that relies on a location in this range might not function properly.
Advance Information Datasheet
17
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
6.0
Electrical Characteristics
Note:
This document contains information on products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is
available. Verify with your local Intel sales office that you have the latest datasheet before
finalizing a design.
Table 6. Absolute Maximum Ratings
Parameter
Storage Temperature
–60°C to +150°C
Voltage from VPP or EA# to VSS or ANGND
–0.5 V to +13.0 V
Voltage from any other pin to VSS or ANGND
–0.5 V to +7.0 V
Power Dissipation
Warning:
Maximum Rating
0.5 W
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
Table 7. Operating Conditions
Parameter
TA (Ambient Temperature Under Bias)
Values
–40°C to +125°C
VCC (Digital Supply Voltage)
4.75 V to 5.25 V
VREF (Analog Supply Voltage) (Notes 1, 2)
4.75 V to 5.25 V
FXTAL1 (Input Frequency):
- PLL in 2x mode
- PLL bypassed
4 MHz to 10 MHz
8 MHz to 20 MHz
NOTES:
1. ANGND and VSS should be nominally at the same potential.
2. VREF should not exceed VCC by more than 0.5 V.
Warning:
18
Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
6.1
DC Characteristics
Table 8. DC Characteristics at VCC = 4.75 V to 5.25 V (Sheet 1 of 2)
Symbol
Parameter
Min
Typical
Max
Units
50
95
mA
Test Conditions (Note 1)
VCC supply current
ICC
(-40°C to +125°C
ambient)
FXTAL1 = 20 MHz,
VCC = VPP = VREF = 5.25 V
(While device is in reset)
ICC1
Active mode supply
current (typical)
50
IREF
A/D reference supply
current
2
5
mA
IIDLE
Idle mode current
15
42
mA
VIL
Input low voltage
(all pins)
0.5 V
0.3 VCC
V
VIH
Input high voltage (all
pins)
0.7 VCC
VCC + 0.5
V
(3)
VOL
Output low voltage
(outputs configured as
complementary)
0.3
0.45
1.5
V
V
V
IOL = 200 µA (4)
IOL = 3.2 mA
IOL = 7.0 mA
VOH
Output high voltage
(outputs configured as
complementary)
V
V
V
IOH = – 200 µA (4)
IOH = – 3.2 mA
IOH = – 7.0 mA
ILI
Input leakage current
(standard inputs)
±8
µA
VSS ≤ VIN ≤ VCC (5)
ILI1
Input leakage current
(port 0—A/D inputs)
±1
µA
VSS ≤ VIN ≤ VREF
VOL2
Output low voltage in
reset (all pins except
P2.6)
1
V
IOL = 15 µA (6, 7)
IOL2
Output low current in
reset (all pins except
P2.6)
15
30
35
110
185
215
µA
µA
µA
VOL2 = 1.0 V
VOL2 = 2.5 V
VOL2 = 4.0 V
RRST
Reset pullup resistor
6K
65 K
Ω
Output low voltage in
reset (RESET# pin
only)
0.3
0.5
0.8
V
VOL3
V
IOL3 = 4 mA (7)
IOL3 = 6 mA
IOL3 = 10 mA
VOL4
Output low voltage in
reset (P2.6 only)
1
V
IOL4 = 500 µA
mA
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
FXTAL1 = 20 MHz,
VCC = VPP = VREF = 5.25 V
NOTES:
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL enabled.
With the PLL bypassed, the device is tested only down to 8 MHz.
2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room
temperature and VREF = VCC = 5.25 V.
3. VIH max for port 0 is VREF + 0.5 V.
4. All bidirectional pins when configured as complementary outputs.
5. Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
6. All bidirectional pins except P2.7/CLKOUT, which is excluded because it is not weakly pulled low in reset.
Bidirectional pins include ports 1–6.
7. This specification is not tested in production and is based upon theoretical estimates and/or product
characterization.
Advance Information Datasheet
19
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 8. DC Characteristics at VCC = 4.75 V to 5.25 V (Sheet 2 of 2)
Symbol
Parameter
CS
Pin capacitance
(any pin to VSS)
RWPD2
Weak pulldown
resistance (all pins
except P2.6)
IOL4
P2.6 only
RWPD4
P2.6 only
Min
Typical
Max
Units
10
pF
FTEST = 1.0 MHz
Ω
(Note 2)
~100 K
0.4
1.0
1.2
2.0
3.5
4.0
mA
mA
mA
Test Conditions (Note 1)
VOL4 = 1.0 V
VOL4 = 2.5 V
VOL4 = 4.0 V
Ω
3K
NOTES:
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL enabled.
With the PLL bypassed, the device is tested only down to 8 MHz.
2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room
temperature and VREF = VCC = 5.25 V.
3. VIH max for port 0 is VREF + 0.5 V.
4. All bidirectional pins when configured as complementary outputs.
5. Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
6. All bidirectional pins except P2.7/CLKOUT, which is excluded because it is not weakly pulled low in reset.
Bidirectional pins include ports 1–6.
7. This specification is not tested in production and is based upon theoretical estimates and/or product
characterization.
6.2
AC Characteristics (Over Specified Operating Conditions)
6.2.1
Test Condition
• Capacitive load on all pins = 100 pF
• Rise and fall times = 10 ns
• FXTAL1 = 8 MHz with PLL enabled in clock-doubler mode
20
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 9. AC Characteristics (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
The 87C196LA meets these specifications
FXTAL1
Frequency on XTAL1, PLL bypassed
8
20
Frequency on XTAL1, PLL in 2x mode
4
10
8
20
MHz(1)
Operating frequency, f = FXTAL1; PLL in 1x mode
f
Operating frequency, f = 2FXTAL1; PLL in 2x
mode
MHz
t
Period t = 1/f
50
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
20
110
ns(2)
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
t - 10
t + 20
ns
TCLLH
CLKOUT Falling to ALE Rising
- 10
30
ns
TLLCH
ALE Falling to CLKOUT Rising
- 35
15
ns
TLHLH
ALE Cycle Time
TLHLL
ALE High Period
t - 10
TAVLL
Address Setup to ALE Low
t - 15
ns
TLLAX
Address Hold after ALE Low
t - 40
ns
TLLRL
ALE Low to RD# Low
t -– 30
ns
TRLCL
RD# Low to CLKOUT Low
TRHLH
RD# High to ALE Rising
TRLRH
RD# Low to RD# High
TRLAZ
RD# Low to Address Float
TLLWL
ALE Low to WR# Low
2t
ns
4t
0
ns
t + 10
30
ns
t + 25
ns(3)
10
ns
t-5
t
ns
ns
t - 10
ns
TCLWL
CLKOUT Low to WR# Falling Edge
TQVWH
Data Valid to WR# High
TCHWH
CLKOUT High to WR# Rising Edge
TWLWH
WR# Low to WR# High
TWHQX
Data Hold after WR# High
t - 25
TWHLH
WR# High to ALE High
t - 10
TWHAX
AD15:8 Hold after WR# High
t - 30
ns(4)
TRHAX
AD15:8 Hold after RD# High
t - 30
ns(4)
-5
25
t - 23
-5
ns
ns
30
t - 20
ns
ns
ns
t + 15
ns(3)
NOTES:
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down
to 8 MHz. However, the device is static by design and typically operates below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
Advance Information Datasheet
21
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 9. AC Characteristics (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
The system must meet these specifications to work with the 87C196LA
TAVDV
Address Valid to Input Data Valid
3t - 55
ns
TRLDV
RD# Low to Input Data Valid
t - 22
ns
TCLDV
CLKOUT Low to Input Data Valid
t - 50
ns
TRHDZ
RD# High to Input Data Float
TRXDX
Data Hold after RD# Inactive
t
0
ns
ns
NOTES:
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down
to 8 MHz. However, the device is static by design and typically operates below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
6.2.2
Explanation of AC Symbols
Each symbol is two pairs of letters prefixed by “t” for time. The characters in a pair indicate a
signal and its condition, respectively. Symbols represent the time between the two signal/condition
points.
Table 10. AC Timing Symbol Definitions
A
AD15:0
C
CLKOUT
D
AD15:0, AD7:0
L
ALE
Q
AD15:0, AD7:0
R
RD#
W
WR#, WRL#
Character
22
Condition
H
High
L
Low
V
Valid
X
No Longer Valid
Z
Floating (low impedance)
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Figure 4. System Bus Timing
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TLLCH
TCLLH
TLHLH
ALE/ADV#
TLHLL
TLLRL
TRHLH
TRLRH
RD#
AD15:0
(read)
TRHDZ
TRLAZ
TAVLL
TLLAX
TRLDV
Address Out
TAVDV
Data In
TLLWL
TWHLH
TWLWH
WR#
AD15:0
(write)
TWHQX
TQVWH
Address Out
Data Out
Address Out
TWHAX, TRHAX
AD15:8
(8-bit data bus)
High Address Out
A4458-01
Table 11. External Clock Drive
Symbol
Parameter
Min
Max
Units
Frequency on XTAL1, PLL bypassed
8
20
Frequency on XTAL1, PLL in 2x mode
4
10
TXLXL
Oscillator Period (TOSC)
50
250
ns
TXHXX
High Time
0.35T
0.65T
ns
TXLXX
Low Time
0.35T
0.65T
ns
TXLXH
Rise Time
10
ns
TXHLX
Fall Time
10
ns
1/TXLXL
MHz(1)
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down
to 8 MHz. However, the device is static by design and typically operates below 1 Hz.
Advance Information Datasheet
23
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Figure 5. External Clock Drive Waveform
TXHXX
TXHXL
TXLXH
0.7 VCC + 0.5 V
TXLXX
0.3 VCC – 0.5 V
XTAL1
0.7 VCC + 0.5 V
0.3 VCC – 0.5 V
TXLXL
A2119-03
Figure 6. AC Testing Input, Output Waveforms
3.5 V
2.0 V
2.0 V
Test Points
0.45 V
0.8 V
0.8 V
Note:
AC testing inputs are driven at 3.5 V for a logic “ 1” and 0.45 V for a logic
“ 0” . Timing measurements are made at 2.0 V for a logic “ 1” and 0.8 V for
a logic “ 0”.
A2120-04
Figure 7. Float Waveform
VOH – 0.15 V
VLOAD + 0.15 V
VLOAD
VLOAD – 0.15 V
Timing Reference
Points
VOL + 0.15 V
Note:
For timing purposes, a port pin is no longer floating when a 150 mV change from load
voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL
level occurs with IOL/IOH ≤ 15 mA.
A2121-03
24
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
7.0
EPROM Specifications
7.1
Operating Conditions
• Load Capacitance = 150 pF
• VSS
• EA# = 12.5 V ±0.25 V
• TC = 25°C ±5°C
• ANGND = 0.0 V
• FOSC = 5.0 MHz
• VREF = 5.0 V ±0.25 V
• VPP = 12.5 V ±0.25 V
Table 12. AC EPROM Programming Characteristics
Symbol
Parameter
Min
Max
Units
TAVLL
Address Setup Time
0
TOSC
TLLAX
Address Hold Time
100
TOSC
TDVPL
Data Setup Time
0
TOSC
TPLDX
Data Hold Time
400
TOSC
TLLLH
PALE# Pulse Width
50
TOSC
50
TOSC
3
TPLPH
PROG# Pulse Width
TLHPL
PALE# High to PROG# Low
220
TOSC
TPHLL
PROG# High to Next PALE# Low
220
TOSC
TPHDX
Word Dump Hold Time
TPHPL
PROG# High to Next PROG# Low
220
TLHPL
PALE# High to PROG# Low
220
TPLDV
PROG# Low to Word Dump Valid
TSHLL
RESET# High to First PALE# Low
TPHIL
PROG# High to AINC# Low
TILIH
TILVH
50
TOSC
TOSC
TOSC
50
TOSC
1100
TOSC
0
TOSC
AINC# Pulse Width
240
TOSC
PVER# Hold after AINC# Low
50
TOSC
TILPL
AINC# Low to PROG# Low
170
TOSC
TPHVL
PROG# High to PVER# Valid
220
TOSC
NOTES:
1. Run-time programming is done with FOSC = 6.0 MHz to 10.0 MHz, VCC, VPD, VREF = 5.0 V ±0.25 V, TC =
25°C ±5°C and VPP = 12.5 V ±0.25 V. For run-time programming over a full operating range, contact
factory.
2. Programming Specifications are not tested, but guaranteed by design.
3. This specification is for the word dump mode. For programming pulses use 300 TOSC + 100 µs.
Table 13. DC EPROM Programming Characteristics
Symbol
IPP
Parameter
VPP Programming Supply Current
Min
Max
Units
100
mA
NOTE: VPP must be within 1 V of VCC while VCC 4.5 V.
Advance Information Datasheet
25
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
7.2
EPROM Programming Waveforms
Figure 8. Slave Programming Mode Data Program Mode with Single Program Pulse
RESET#
TAVLL
PORTS 3/4
TDVPL
Address/Command
TSHLL
Data
TLLAX
Address/Command
TPLDX
PALE#
P2.1
TLLLH
TLHPL
TPLPH
TPHLL
PROG#
P2.2
TPHVL
PVER#
P2.0
Valid
TLLVH
A4428-01
Figure 9. Slave Programming Mode in WORD Dump or Data Verify Mode with Auto Increment
RESET#
ADDR
PORTS 3/4
Address/Command
TSHLL
TPLDV
ADDR + 2
Ver Bits/WD Dump
Ver Bits/WD Dump
TPHDX
TPLDV
TPHDX
PALE#
P2.1
PROG#
P2.2
TILPL
TPHPL
PVER#
P2.0
A4429-01
26
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Figure 10. Slave Programming Mode Timing in Data Program Mode with Repeated Program
Pulse and Auto Increment
RESET#
PORTS 3/4
Address/Command
Data
PALE#
P2.1
PROG#
P2.2
Data
TPHPL
P1
TILPL
P2
TILVH
PVER#
P2.0
Valid For P1
Valid
For P2
TILIH
AINC#
P2.4
TPHIL
A4430-01
8.0
A/D Converter Specifications
The speed of the A/D converter in the 10-bit or 8-bit modes can be adjusted by setting the
AD_TIME special function register to the appropriate value. The AD_TIME register only
programs the speed at which the conversions are performed, not the speed at which it can convert
correctly.
The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of
VREF. VREF must be within 0.5 V of VCC since it supplies both the resistor ladder and the digital
portion of the converter and input port pins.
For testing purposes, after a conversion is started, the device is placed in the IDLE mode until the
conversion is complete. Testing is performed at VREF = 5.12 V and 20 MHz operating frequency.
There is an AD_TEST register that allows for conversion on ANGND and VREF, as well as zero
offset adjustment. The absolute error listed is without doing any adjustments.
Advance Information Datasheet
27
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
Table 14. A/D Operating Conditions - Symbol Descriptions1
Symbol
Description
Min
Max
Units
TA
Automotive Ambient Temperature
-40
+125
°C
VCC
Digital Supply Voltage
4.75
5.25
V
(2,3)
VREF
Analog Supply Voltage
4.75
TSAM
Sample Time
2.0
TCONV
Conversion Time
15
18
µs(4)
FOSC
Oscillator Frequency
4
20
MHz
Min
Max
Units‡
1024
10
1024
10
Level
Bits
0
±3
LSBs
5.25
V
µs(4)
NOTES:
1. ANGND and VSS should nominally be at the same potential.
2. VREF must not exceed VCC by more than +0.5 V.
3. Testing is performed at VREF = 5.12 V.
4. The value of AD_TIME must be selected to meet these specifications.
Table 15. A/D Operating Conditions - Parameter Descriptions
Parameter
Typical†,1
Resolution
Absolute Error
Full Scale Error
±2
Zero Offset Error
±2
LSBs
LSBs
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
±0.25
Temperature Coefficients:
Offset
Fullscale
Differential Non-Linearity
0.009
Off Isolation
±3
LSBs
≥0.5
+0.5
LSBs
0
±1
LSBs
LSBs(1)
0
LSBs/C(1)
dB(1,2,3)
- 60
Feedthrough
- 60
dB(1,2)
VCC Power Supply Rejection
- 60
dB(1,2)
Input Resistance
DC Input Leakage
750
1.2 K
Ω(1)
0
2
µA
NOTES:
†
‡
These values are expected for most parts at 25°C, but are not tested or guaranteed.
An “LSB”, as used here, has a value of approximately 5 mV. (See Automotive Handbook for
A/D glossary of terms).
1. These values are not tested in production and are based on theoretical estimates and/or laboratory test.
2. DC to 100 KHz.
3. Multiplexer Break-Make Guaranteed.
28
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
9.0
AC Characteristics - Serial Port Shift Register Mode
9.1
Test Conditions
• TA = -40°C to +125°C
• VSS = 0.0 V
• VCC = 5.0 V ±5%
• Load Capacitance = 100 pF
Table 16. Serial Port Timing - Shift Register Mode
Symbol
Parameter
Min
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold after Clock Rising Edge
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX1
Input Data Hold after Clock Rising Edge
TXHQZ1
Last Clock Rising to Output Float
Max
Units
8T
ns
4T - 50
4T + 50
ns
3T
ns
2T - 50
ns
2T + 50
ns
2T + 200
ns
0
ns
5T
ns
1. Parameter not tested.
9.2
Waveform - Serial Port - Shift Register Mode0
Figure 11. Serial Port Waveform - Shift Register Mode
TXLXL
TXD
TQVXH
TXLXH
0
RXD (out)
1
2
3
TDVXH
RXD (in)
Valid
TXHQX
TXHQV
4
5
TXHQZ
6
7
TXHDX
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A4427-01
Advance Information Datasheet
29
87C196LA-20 MHz CHMOS 16-bit Microcontroller — Automotive
10.0
Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation.
Values change depending on operating conditions and the application. The Intel Packaging
Handbook (order number 240800) describes Intel’s thermal impedance test methodology. The
Components Quality and Reliability Handbook (order number 210997) provides quality and
reliability information.
Table 17. Thermal Characteristics
Package Type
θJA
θJC
xx87C196LA (52-pin PLCC)
42 °C/W
15°C/W
NOTES:
1. θJA = Thermal resistance between junction and the surrounding environment (ambient). Measurements
are taken 1 foot away from case in static air flow environment.
θJC = Thermal resistance between junction and package surface (case).
2. All values of θJA and θJC may fluctuate depending on the environment (with or without airflow, and how
much airflow) and device power dissipation at temperature of operation. Typical variations are ± 2°C/W.
3. Values listed are at a maximum power dissipation of 0.5 W.
4. To address the fact that many of the package prefix variables have changed, all package prefix variables
in this document are now indicated with an "x".
11.0
Design Considerations
To be supplied.
12.0
Device Errata
Contact your Intel sales representative for this product’s specification update.
13.0
Datasheet Revision History
For revision (004), to address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
These revisions were made for the (003) datasheet.
Table 18. Revision History (Sheet 1 of 2)
30
Revision
Item
Change
002
All
002
Cover
002
Figure 3
Modified to include PLLEN designation on pin 6.
002
Table 4
Signal descriptions modified for the PLLEN pin, to reflect the method for
bypassing the on-chip PLL.
002
Section 6.0
Data sheet moved from Product Preview to Advance Information status.
List of features changed to reflect 24 Kbytes of OTPROM and 768 bytes of
register RAM.
Changed “PLL in 1x mode” to “PLL bypassed”.
Advance Information Datasheet
Automotive — 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 18. Revision History (Sheet 2 of 2)
Revision
Item
Change
Changes to DC Characteristics as follows:
• ICCMax from TBD to 95 mA
• IREFMax from TBD to 5 mA
• IIDLEMax from TBD to 42 mA
•
PDDeleted
• IHDeleted
002
Section 6.1
• IOL2 (All pins except P2.6) Min, Max, @ VOL2 from TBD to:
Min = 15 mAMax = 110 µA@ VOL2 = 1.0 V
Min = 30 mAMax = 185 µA@ VOL2 = 2.5 V
Min = 35 mAMax = 215 µA@ VOL2 = 4.0 V
• RWPU replaced with RWPD2 to accurately reflect the weak pulldown
device. Typical set to 100 KΩ for all pins except P2.6.
• IOL2 (Added for P2.6 only)
Min = 0.4 mAMax = 2.0 µA@ VOL4 = 1.0 V
Min = 1.0 mAMax = 3.5 µA@ VOL4 = 2.5 V
Min = 1.2 mAMax = 4.0 µA@ VOL4 = 4.0 V
• RWPD4 (Added for P2.6 only) To accurately reflect the weak pulldown
device for P2.6. Typical set to 3 KΩ.
Changes to AC Characteristics as follows:
• TCHCLMax from T+15 to T+20 ns
• TCLLHMax from 15 to 30 ns
002
Table 9
• TLLCHMin from -20 to -35 ns
• TRLCLMin from 4 to 0
• TRLAZMax from 5 to 10 ns
• TCHWHMin from -10 to -5 ns
Max from 15 to 30 ns
002
Table 11 and
Figure 5
002
Figure 6
Added AC testing input/output waveform.
002
Figure 7
Added Float Waveform.
002
Section 7.2
Added EPROM specifications for programming characteristics.
002
Section 8.0
Added A/D converter specifications.
002
Section 9.0
Added AC characteristics for the serial port.
003
All
Advance Information Datasheet
Added External clock drive specifications and waveform.
Changed VCC and VREF operating spec conditions.
31
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