January
Stratix IV Device Handbook
Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIV5V1-4.8
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
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ISO
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semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Section I. Device Core
Chapter 1. Overview for the Stratix IV Device Family
Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Stratix IV GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Stratix IV E Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Stratix IV GT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
High-Speed Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Highest Aggregate Data Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Wide Range of Protocol Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
FPGA Fabric and I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Device Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Digital Signal Processing (DSP) Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
High-Speed Differential I/O with DPA and Soft-CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Integrated Software Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
LAB Power Management Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
TriMatrix Memory Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
iv
Contents
Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Mixed Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Error Correction Code (ECC) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Single-Port RAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Shift-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Input/Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Read/Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Selecting TriMatrix Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
Read-During-Write Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Chapter 4. DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Stratix IV Simplified DSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Stratix IV Operational Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Stratix IV DSP Block Resource Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Multiplier and First-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
Pipeline Register Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Second-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Rounding and Saturation Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
Second Adder and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
Stratix IV Operational Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
Independent Multiplier Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
9-, 12-, and 18-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
36-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Double Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
18 x 18 Complex Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
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January 2016 Altera Corporation
Contents
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Chapter 5. Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Regional Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Periphery Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Clock Sources Per Quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Clock Network Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Dedicated Clock Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
LABs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
PLL Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Clock Input Connections to the PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Clock Source Control for PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Cascading PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
PLLs in Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Stratix IV PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
PLL Clock I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
Source Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29
Source-Synchronous Mode for LVDS Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
No-Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31
Zero-Delay Buffer (ZDB) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31
External Feedback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32
Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33
Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34
Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35
Programmable Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35
Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–37
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–37
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38
Spread-Spectrum Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–40
Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–43
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–43
PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–44
PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45
Post-Scale Counters (C0 to C9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–47
Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–48
Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–50
Bypassing a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51
Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–51
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–54
Section II. I/O Interfaces
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
vi
Contents
Chapter 6. I/O Features in Stratix IV Devices
I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
I/O Standards and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
3.3-V I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Programmable I/O Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Programmable Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
On-Chip Termination Support and I/O Termination Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
On-Chip Series (RS) Termination Without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25
On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
Left-Shift Series Termination Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
On-Chip Parallel Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
Expanded On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
Dynamic On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
LVDS Input OCT (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–31
Summary of OCT Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–31
OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32
OCT Calibration Block Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32
Sharing an OCT Calibration Block on Multiple I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34
OCT Calibration Block Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
Power-Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36
OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
Serial Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
Example of Using Multiple OCT Calibration Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
RS Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
Single-Ended I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
Differential I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–43
Differential LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–44
RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–45
Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46
I/O Bank Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46
Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . 6–47
Chapter 7. External Memory Interfaces in Stratix IV Devices
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Contents
vii
Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
Using the RUP and RDN Pins in a DQS/DQ Group Used for Memory Interfaces . . . . . . . . . . . . . . 7–26
Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . 7–26
Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27
Stratix IV External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29
DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29
DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–31
Phase Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41
DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43
DQS Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44
Update Enable Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44
DQS Postamble Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–45
Leveling Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46
Dynamic On-Chip Termination Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48
I/O Element Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49
Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52
I/O Configuration Block and DQS Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54
Chapter 8. High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
Locations of the I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
LVDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
LVDS SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
ALTLVDS Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
Programmable VOD and Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
Programmable VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
Differential I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18
Receiver Hardware Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
DPA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20
Data Realignment Block (Bit Slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20
Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22
Receiver Data Path Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22
Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22
DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24
Soft-CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25
LVDS Interface with the Use External PLL Option Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26
Left and Right PLLs (PLL_Lx and PLL_Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–29
Stratix IV Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30
Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31
Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31
Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31
Transmitter Channel-to-Channel Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33
Receiver Skew Margin for Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33
Differential Pin Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
Guidelines for DPA-Enabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
DPA-Enabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
DPA-Enabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
Using Corner and Center Left and Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38
Using Both Center Left and Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–40
Guidelines for DPA-Disabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42
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Contents
DPA-Disabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42
DPA-Disabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42
Using Corner and Center Left and Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42
Using Both Center Left and Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–45
Section III. System Integration
Chapter 9. Hot Socketing and Power-On Reset in Stratix IV Devices
Stratix IV Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
Stratix IV Devices can be Driven Before Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
I/O Pins Remain Tri-Stated During Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
Insertion or Removal of a Stratix IV Device from a Powered-Up System . . . . . . . . . . . . . . . . . . . . . . 9–2
Hot-Socketing Feature Implementation in Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Power-On Reset Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
Chapter 10. Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4
Power-On Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
VCCPGM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
VCCPD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
Fast Passive Parallel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6
FPP Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6
FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–12
FPP Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–16
Fast Active Serial Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–16
Estimating Active Serial Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–22
Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–23
Guidelines for Connecting Serial Configuration Devices on an AS Interface . . . . . . . . . . . . . . . . . 10–25
Passive Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–25
PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–26
PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–31
PS Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32
PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32
JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–35
Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40
Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40
Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–48
Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–50
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–51
Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–53
Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54
Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54
Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54
Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–57
Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–58
Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–58
Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–59
Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–60
User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–62
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Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–63
ALTREMOTE_UPDATE Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–63
Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–64
Stratix IV Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
Flexible Security Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–65
Stratix IV Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–66
Security Modes Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–67
Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–67
Non-Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–67
Non-Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–67
No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–68
Supported Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–68
Chapter 11. SEU Mitigation in Stratix IV Devices
Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Automated Single-Event Upset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
Error Detection Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6
Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7
Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8
Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10
Recovering From CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11
Chapter 12. JTAG Boundary-Scan Testing in Stratix IV Devices
BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1
BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4
BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4
BSDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4
Chapter 13. Power Management in Stratix IV Devices
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
Stratix IV Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
Programmable Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
Stratix IV External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3
Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
Additional Information
About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
x
Stratix IV Device Handbook
Volume 1
Contents
January 2016 Altera Corporation
Chapter Revision Dates
The chapters in this document, Stratix IV Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1.
Overview for the Stratix IV Device Family
Revised:
January 2016
Part Number: SIV51001-3.5
Chapter 2.
Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51002-3.1
Chapter 3.
TriMatrix Embedded Memory Blocks in Stratix IV Devices
Revised:
December 2011
Part Number: SIV51003-3.3
Chapter 4.
DSP Blocks in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51004-3.1
Chapter 5.
Clock Networks and PLLs in Stratix IV Devices
Revised:
September 2012
Part Number: SIV51005-3.4
Chapter 6.
I/O Features in Stratix IV Devices
Revised:
September 2012
Part Number: SIV51006-3.4
Chapter 7.
External Memory Interfaces in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51007-3.2
Chapter 8.
High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Revised:
September 2012
Part Number: SIV51008-3.4
Chapter 9.
Hot Socketing and Power-On Reset in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51009-3.2
Chapter 10. Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Revised:
September 2012
Part Number: SIV51010-3.5
Chapter 11. SEU Mitigation in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51011-3.2
Chapter 12. JTAG Boundary-Scan Testing in Stratix IV Devices
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
xii
Chapter Revision Dates
Revised:
February 2011
Part Number: SIV51012-3.2
Chapter 13. Power Management in Stratix IV Devices
Revised:
February 2011
Part Number: SIV51013-3.2
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Section I. Device Core
This section provides a complete overview of all features relating to the Stratix® IV
device family, which is the most architecturally advanced, high-performance,
low-power FPGA in the market place. This section includes the following chapters:
■
Chapter 1, Overview for the Stratix IV Device Family
■
Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
■
Chapter 3, TriMatrix Embedded Memory Blocks in Stratix IV Devices
■
Chapter 4, DSP Blocks in Stratix IV Devices
■
Chapter 5, Clock Networks and PLLs in Stratix IV Devices
Revision History
Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
I–2
Stratix IV Device Handbook
Volume 1
Section I: Device Core
January 2016 Altera Corporation
1. Overview for the Stratix IV Device
Family
January 2016
SIV51001-3.5
SIV51001-3.5
Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor
Manufacturing Company (TSMC) 40-nm process technology and surpass all other
high-end FPGAs, with the highest logic density, most transceivers, and lowest power
requirements.
The Stratix IV device family contains three optimized variants to meet different
application requirements:
■
Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits
(Kb) RAM, and 1,288 18 x 18 bit multipliers
■
Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288
18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based
transceivers at up to 8.5 Gbps
■
Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers,
and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps
The complete Altera high-end solution includes the lowest risk, lowest total cost path
to volume using HardCopy® IV ASICs for all the family variants, a comprehensive
portfolio of application solutions customized for end-markets, and the industry
leading Quartus® II software to increase productivity and performance.
f For information about upcoming Stratix IV device features, refer to the Upcoming
Stratix IV Device Features document.
f For information about changes to the currently published Stratix IV Device Handbook,
refer to the Addendum to the Stratix IV Device Handbook chapter.
This chapter contains the following sections:
■
“Feature Summary” on page 1–2
■
“Architecture Features” on page 1–6
■
“Integrated Software Platform” on page 1–19
■
“Ordering Information” on page 1–19
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 1
January 2016
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1–2
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
Feature Summary
The following list summarizes the Stratix IV device family features:
■
Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices
supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively
■
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE),
Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken
■
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, Data Link layer, and Transaction layer functionality
f For more information, refer to the IP Compiler for PCI Express User Guide.
Stratix IV Device Handbook
Volume 1
■
Programmable transmitter pre-emphasis and receiver equalization circuitry to
compensate for frequency-dependent losses in the physical medium
■
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps and 135 mW at 6.375 Gbps per channel
■
72,600 to 813,050 equivalent LEs per device
■
7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block
sizes to implement true dual-port memory and FIFO buffers
■
High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit,
12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
■
Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery
clocks (PCLK) per device
■
Programmable power technology that minimizes power while maximizing device
performance
■
Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide
range of single-ended and differential I/O standards
■
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
■
High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic
phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps
■
Support for source-synchronous bus standards, including SGMII, GbE, SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■
Pinouts for Stratix IV E devices designed to allow migration of designs from
Stratix III to Stratix IV E with minimal PCB impact
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
1–3
Stratix IV GX Devices
Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels
per device:
■
Thirty-two out of the 48 transceiver channels have dedicated physical coding
sublayer (PCS) and physical medium attachment (PMA) circuitry and support
data rates between 600 Mbps and 8.5 Gbps
■
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
1
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to Table 1–1
on page 1–11.
1
For more information about transceiver architecture, refer to the Transceiver
Architecture in Stratix IV Devices chapter.
Figure 1–1 shows a high-level Stratix IV GX chip view.
Figure 1–1. Stratix IV GX Chip View (1)
PLL
General Purpose
I/O and Memory
Interface
PLL
PLL
General Purpose
I/O and Memory
Interface
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
PLL
PLL
PLL
PCI Express
Hard IP Block
PLL
PCI Express
Hard IP Block
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
PLL
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
PLL
PLL
PCI Express
Hard IP Block
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
General Purpose
I/O and Memory
Interface
General Purpose
I/O and Memory
Interface
600 Mbps-8.5 Gbps CDR-based Transceiver
General Purpose I/O and 150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to Figure 1–1:
(1) Resource counts vary with device selection, package selection, or both.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–4
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
Stratix IV E Device
Stratix IV E devices provide an excellent solution for applications that do not require
high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.
Figure 1–2 shows a high-level Stratix IV E chip view.
Figure 1–2. Stratix IV E Chip View (1)
General Purpose
I/O and Memory PLL
Interface
PLL
General Purpose
I/O and Memory
Interface
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL
PLL
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
PLL
PLL
General Purpose
I/O and Memory PLL
Interface
General Purpose I/O and
High-Speed LVDS I/O with DPA
and Soft-CDR
PLL
General Purpose
I/O and Memory
Interface
General Purpose I/O and
150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to Figure 1–2:
(1) Resource counts vary with device selection, package selection, or both.
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
1–5
Stratix IV GT Devices
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
■
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
1
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to Table 1–7
on page 1–16.
1
For more information about Stratix IV GT devices and transceiver architecture, refer
to the Transceiver Architecture in Stratix IV Devices chapter.
Figure 1–3 shows a high-level Stratix IV GT chip view.
(1)
FPGA Fabric
PLL
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
PLL
Transceiver Transceiver
Block
Block
General Purpose
I/O and Memory
Interface
Transceiver Transceiver
Block
Block
PLL
PCI Express
Hard IP Block
PLL
PLL
PCI Express
Hard IP Block
Transceiver Transceiver
Block
Block
Transceiver Transceiver
Block
Block
General Purpose
I/O and Memory
Interface
PCI Express
Hard IP Block
Figure 1–3. Stratix IV GT Chip View
PLL
General Purpose
I/O and Memory
Interface
Transceiver Block
General Purpose I/O and
High-Speed LVDS I/O
with DPA and Soft CDR
PLL
PLL
PLL
General Purpose
I/O and Memory
Interface
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
Note to Figure 1–3:
(1) Resource counts vary with device selection, package selection, or both.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–6
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
Architecture Features
The Stratix IV device family features are divided into high-speed transceiver features
and FPGA fabric and I/O features.
1
The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT
devices.
High-Speed Transceiver Features
The following sections describe high-speed transceiver features for Stratix IV GX and
GT devices.
Highest Aggregate Data Bandwidth
Up to 48 full-duplex transceiver channels supporting data rates up to 8.5 Gbps in
Stratix IV GX devices and up to 11.3 Gbps in Stratix IV GT devices.
Wide Range of Protocol Support
Physical layer support for the following serial protocols:
■
Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH,
XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
■
Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO,
SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel
■
Extremely flexible and easy-to-configure transceiver data path to implement
proprietary protocols
■
PCIe Support
■
Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI
Express base specification 2.0 that includes PHY-MAC, Data Link, and
transaction layer circuitry embedded in PCI Express hard IP blocks
f For more information, refer to the PCI Express Compiler User Guide.
Stratix IV Device Handbook
Volume 1
■
Root complex and end-point applications
■
x1, x4, and x8 lane configurations
■
PIPE 2.0-compliant interface
■
Embedded circuitry to switch between Gen1 and Gen2 data rates
■
Built-in circuitry for electrical idle generation and detection, receiver detect,
power state transitions, lane reversal, and polarity inversion
■
8B/10B encoder and decoder, receiver synchronization state machine, and
± 300 parts per million (ppm) clock compensation circuitry
■
Transaction layer support for up to two virtual channels (VCs)
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
■
■
■
1–7
XAUI/HiGig Support
■
Compliant to IEEE802.3ae specification
■
Embedded state machine circuitry to convert XGMII idle code groups (||I||)
to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and
receiver, respectively
■
8B/10B encoder and decoder, receiver synchronization state machine, lane
deskew, and ± 100 ppm clock compensation circuitry
GbE Support
■
Compliant to IEEE802.3-2005 specification
■
Automatic idle ordered set (/I1/, /I2/) generation at the transmitter,
depending on the current running disparity
■
8B/10B encoder and decoder, receiver synchronization state machine, and
± 100 ppm clock compensation circuitry
Support for other protocol features such as MSB-to-LSB transmission in
SONET/SDH configuration and spread-spectrum clocking in PCIe configurations
Diagnostic Features
■
Serial loopback from the transmitter serializer to the receiver CDR for transceiver
PCS and PMA diagnostics
■
Reverse serial loopback pre- and post-CDR to transmitter buffer for physical link
diagnostics
■
Loopback master and slave capability in PCI Express hard IP blocks
f For more information, refer to the PCI Express Compiler User Guide.
Signal Integrity
Stratix IV devices simplify the challenge of signal integrity through a number of chip,
package, and board-level enhancements to enable efficient high-speed data transfer
into and out of the device. These enhancements include:
January 2016
■
Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis
levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI)
■
Up to 900% boost capability on the first pre-emphasis post-tap
■
User-controlled and adaptive 4-stage receiver equalization with up to 16 dB of
high-frequency gain
■
On-die power supply regulators for transmitter and receiver phase-locked loop
(PLL) charge pump and voltage controlled oscillator (VCO) for superior noise
immunity
■
On-package and on-chip power supply decoupling to satisfy transient current
requirements at higher frequencies, thereby reducing the need for on-board
decoupling capacitors
■
Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–8
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
FPGA Fabric and I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features.
Device Core Features
■
Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in
Stratix IV E devices, efficiently packed in unique and innovative adaptive logic
modules (ALMs)
■
Ten ALMs per logic array block (LAB) deliver faster performance, improved logic
utilization, and optimized routing
■
Programmable power technology, including a variety of process, circuit, and
architecture optimizations and innovations
■
Programmable power technology available to select power-driven compilation
options for reduced static power consumption
Embedded Memory
■
TriMatrix embedded memory architecture provides three different memory block
sizes to efficiently address the needs of diversified FPGA designs:
■
640-bit MLAB
■
9-Kb M9K
■
144-Kb M144K
■
Up to 33,294 Kb of embedded memory operating at up to 600 MHz
■
Each memory block is independently configurable to be a single- or dual-port
RAM, FIFO, ROM, or shift register
Digital Signal Processing (DSP) Blocks
■
Flexible DSP blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit
full-precision multipliers at up to 600 MHz with rounding and saturation
capabilities
■
Faster operation due to fully pipelined architecture and built-in addition,
subtraction, and accumulation units to combine multiplication results
■
Optimally designed to support advanced features such as adaptive filtering, barrel
shifters, and finite and infinite impulse response (FIR and IIR) filters
Clock Networks
Stratix IV Device Handbook
Volume 1
■
Up to 16 global clocks and 88 regional clocks optimally routed to meet the
maximum performance of 800 MHz
■
Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices,
respectively
■
Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in
Stratix IV GX and Stratix IV GT devices
■
Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in
Stratix IV E devices
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
1–9
PLLs
■
Three to 12 PLLs per device supporting spread-spectrum input tracking,
programmable bandwidth, clock switchover, dynamic reconfiguration, and delay
compensation
■
On-chip PLL power supply regulators to minimize noise coupling
I/O Features
■
Sixteen to 24 modular I/O banks per device with 24 to 48 I/Os per bank designed
and packaged for optimal simultaneous switching noise (SSN) performance and
migration capability
■
Support for a wide range of industry I/O standards, including single-ended
(LVTTL/CMOS/PCI/PCIX), differential (LVDS/mini-LVDS/RSDS),
voltage-referenced single-ended and differential (SSTL/HSTL Class I/II) I/O
standards
■
On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for
single-ended I/Os and on-chip differential (RD) termination for differential I/Os
■
Programmable output drive strength, slew rate control, bus hold, and weak
pull-up capability for single-ended I/Os
■
User I/O:GND:VCC ratio of 8:1:1 to reduce loop inductance in the package—PCB
interface
■
Programmable transmitter differential output voltage (VOD) and pre-emphasis for
high-speed LVDS I/O
High-Speed Differential I/O with DPA and Soft-CDR
■
Dedicated circuitry on the left and right sides of the device to support differential
links at data rates from 150 Mbps to 1.6 Gbps
■
Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential
SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT
devices
■
DPA circuitry at the receiver automatically compensates for channel-to-channel
and channel-to-clock skew in source synchronous interfaces
■
Soft-CDR circuitry at the receiver allows implementation of asynchronous serial
interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE)
External Memory Interfaces
January 2016
■
Support for existing and emerging memory interface standards such as DDR
SDRAM, DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, QDRII+ SRAM, and
RLDRAM II
■
DDR3 up to 1,067 Mbps/533 MHz
■
Programmable DQ group widths of 4 to 36 bits (includes parity bits)
■
Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate
register capabilities provide a robust external memory interface solution
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–10
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
System Integration
■
All Stratix IV devices support hot socketing
■
Four configuration modes:
■
Passive Serial (PS)
■
Fast Passive Parallel (FPP)
■
Fast Active Serial (FAS)
■
JTAG configuration
■
Ability to perform remote system upgrades
■
256-bit advanced encryption standard (AES) encryption of configuration bits
protects your design against copying, reverse engineering, and tampering
■
Built-in soft error detection for configuration RAM cells
f For more information about how to connect the PLL, external memory interfaces, I/O,
high-speed differential I/O, power, and the JTAG pins to PCB, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines and the
Stratix IV GT Device Family Pin Connection Guidelines.
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Table 1–1. Stratix IV GX Device Features (Part 1 of 2)
F1932
F1760
F1932
EP4SGX530
F1760
F1517
F1152
F780
F1932
EP4SGX360
F1760
F1517
F780
F1152
EP4SGX290
F1517
F780
F1152
EP4SGX230
F1517
F780
F1152
EP4SGX180
F1152
EP4SGX110
F780
F1152
Altera Corporation
Package
Option
EP4SGX70
F780
Feature
ALMs
29,040
42,240
70,300
91,200
116,480
141,440
212,480
LEs
72,600
105,600
175,750
228,000
291,200
353,600
531,200
0.6 Gbps8.5 Gbps
Transceivers
(PMA + PCS)
—
16
—
—
16
—
—
16
24
—
—
16
24
—
—
16
24
24
32
—
—
16
24
24
32
24
32
8
—
8
16
—
8
16
—
—
8
16
—
—
16
16
—
—
—
—
16
16
—
—
—
—
—
—
PMA-only
CMU
Channels
(0.6 Gbps6.5 Gbps)
—
8
—
—
8
—
—
8
12
—
—
8
12
—
—
8
12
12
16
—
—
8
12
12
16
12
16
PCI Express
hard IP
Blocks
1
2
1
28
56
28
(1)
0.6 Gbps6.5 Gbps
Transceivers
(PMA + PCS)
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
January 2016
Table 1–1 lists the Stratix IV GX device features.
(1)
High-Speed
LVDS
SERDES (up
to 1.6 Gbps)
2
28
1
56
2
1
2
2
28
44
88
28
44
88
—
44
1
2
4
1
2
4
—
2
4
88
88
98
2
—
44
—
2
4
4
88
88
98
88
98
(4)
1
1
4
4
4
1–11
Stratix IV Device Handbook
Volume 1
SPI-4.2 Links
F1932
F1760
F1932
EP4SGX530
F1760
F1517
F1152
F780
F1932
EP4SGX360
F1760
F1517
F780
F1152
EP4SGX290
F1517
F780
F1152
EP4SGX230
F1517
F1152
EP4SGX180
F780
F780
F1152
EP4SGX110
F1152
Package
Option
EP4SGX70
F780
Feature
1–12
Stratix IV Device Handbook
Volume 1
Table 1–1. Stratix IV GX Device Features (Part 2 of 2)
M9K Blocks
(256 x
36 bits)
462
660
950
1,235
936
1,248
1,280
M144K
Blocks
(2048 x
72 bits)
16
16
20
22
36
48
64
7,370
9,564
13,627
17,133
17,248
22,564
27,376
384
512
920
1,288
832
Total Memory
(MLAB+M9K
+M144K) Kb
Embedded
Multipliers
18 x 18 (2)
PLLs
4
3
(3)
372
488
372
372
48
8
372
56
4
Speed Grade
(fastest to
slowest) (5)
–2,
–3,
–4
–2,
–3,
–4
–2
,
–3,
–4
–2
,
–3,
–4
–2,
–3,
–4
–2
,
–3,
–4
–2
,
–3,
–4
User I/Os
4
3
6
8
3
6
8
4
56
4
74
4
372
564
74
4
289
564
56
4
–2
,
–3
,
–4
–2,
–3,
–4
–2
,
–3,
–4
–2
–2
–2, –2,
,
,
–3, –3,
–3,
–3,
–4 –4
–4
–4
–2
,
–3,
–4
56
4
6
8
12
12
4
6
74
4
88
0
92
0
289
564
–2, –2, –2, –2,
–3, –3, –3, –3,
–4 –4 –4 –4
–2
,
–3,
–4
1,024
8
12
12
12
12
74
4
88
0
920
880
920
–2
–2, –2, –2,
,
–3, –3, –3,
–3,
–4 –4 –4
–4
–2,
–3,
–4
–2, –3,
–4
–2, –3,
–4
56
4
Notes to Table 1–1:
(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only
on the right side of the device.
(2) Four multiplier adder mode.
January 2016 Altera Corporation
(3) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in
the pin count.
(4) Total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.
(5) The difference between the Stratix IV GX devices in the –2 and –2x speed grades is the number of available transceiver channels. The –2 device allows you to use the transceiver CMU blocks as
transceiver channels. The –2x device does NOT allow you to use the CMU blocks as transceiver channels. In addition to the reduction of available transceiver channels in the Stratix IV GX –2x device,
the data rates in the –2x device are limited to 6.5 Gbps.
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
3
1,02
4
1,040
Table 1–2. Stratix IV GX Device Package Options
Altera Corporation
F780
(29 mm x 29 mm)
Device
(1), (2)
F1152
(35 mm x 35 mm)
(6)
(6)
F1152
(35 mm x 35 mm)
(5), (7)
F1517
(40 mm x 40 mm)
(5), (7)
F1760
(42.5 mm x 42.5 mm)
F1932
(45 mm x 45 mm)
(7)
(7)
EP4SGX70
DF29
—
—
HF35
—
—
—
—
EP4SGX110
DF29
—
FF35
HF35
—
—
—
—
EP4SGX180
DF29
—
FF35
—
HF35
KF40
—
—
EP4SGX230
DF29
—
EP4SGX290
—
FF35
—
HF35
KF40
—
—
FH29
(3)
FF35
—
HF35
KF40
KF43
NF45
(3)
FF35
—
—
—
EP4SGX360
—
FH29
EP4SGX530
—
—
HF35
HH35
KF40
(4)
KH40
(4)
KF43
NF45
KF43
NF45
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
January 2016
Table 1–2 lists the Stratix IV GX device package options.
Notes to Table 1–2:
(1) Device packages in the same column and marked under the same arrow sign have vertical migration capability.
(2) Use the Pin Migration Viewer in the Pin Planner to verify the pin migration compatibility when migrating devices. For more information, refer to I/O Management in the Quartus II Handbook, Volume 2.
(3) The 780-pin EP4SGX290 and EP4SGX360 devices are available only in 33 mm x 33 mm Hybrid flip chip package.
(4) The 1152-pin and 1517-pin EP4SGX530 devices are available only in 42.5 mm x 42.5 mm Hybrid flip chip packages.
(5) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Package Information Datasheet for Altera Devices.
(6) Devices listed in this column are available in –2x, –3, and –4 speed grades. These devices do not have on-package decoupling capacitors.
(7) Devices listed in this column are available in –2, –3, and –4 speed grades. These devices have on-package decoupling capacitors. For more information about on-package decoupling capacitor value
in each device, refer to Table 1–3.
1
On-package decoupling reduces the need for on-board or PCB decoupling capacitors by satisfying the transient current
requirements at higher frequencies. The Power Delivery Network design tool for Stratix IV devices accounts for the on-package
decoupling and reflects the reduced requirements for PCB decoupling capacitors.
1–13
Stratix IV Device Handbook
Volume 1
1–14
Stratix IV Device Handbook
Volume 1
Table 1–3 lists the Stratix IV GX device on-package decoupling information.
Table 1–3. Stratix IV GX Device On-Package Decoupling Information (1)
Ordering Information
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
HF35
HF35
HF35
KF40
HF35
KF40
VCC
VCCL_GXB
VCCA_L/R
VCCT and VCCR (Shared)
10nF per bank
(2)
100nF per transceiver block
100nF
1470nF + 147nF per side
21uF + 2470nF
10nF per bank
(2)
100nF per transceiver block
100nF
1470nF + 147nF per side
21uF + 2470nF
10nF per bank
(2)
100nF per transceiver block
100nF
1470nF + 147nF per side
21 uF + 2470 nF
10 nF per bank
(2)
100 nF per transceiver block
100 nF
1470 nF + 147 nF
per side
41 uF + 4470 nF
10 nF per bank
(2)
100 nF per transceiver block
100nF
1470 nF + 147 nF
per side
41 uF + 4470 nF
10 nF per bank
(2)
100 nF per transceiver block
100 nF
1470 nF + 147 nF
per side
41 uF + 4470 nF
10 nF per bank
(2)
100 nF per transceiver block
100 nF
1470 nF + 147 nF
per side
21uF + 2470nF
VCCIO
HF35
EP4SGX290
KF40
KF43
NF45
HF35
EP4SGX360
KF40
KF43
NF45
HH35
KH40
KF43
NF45
Notes to Table 1–3:
January 2016 Altera Corporation
(1) Table 1–3 refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES) devices, contact Altera Technical Support.
(2) For I/O banks 3(*), 4(*), 7(*), and 8(*) only. There is no OPD for I/O bank 1(*), 2(*), 5(*), and 6(*).
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
EP4SGX530
Table 1–4. Stratix IV E Device Features
Feature
EP4SE230
Altera Corporation
Package Pin Count
780
EP4SE360
780
EP4SE530
1152
1152
EP4SE820
1517
1760
1152
1517
ALMs
91,200
141,440
212,480
325,220
LEs
228,000
353,600
531,200
813,050
High-Speed LVDS
SERDES (up to
1.6 Gbps) (1)
56
56
88
88
SPI-4.2 Links
3
3
4
4
M9K Blocks
(256 x 36 bits)
1,235
1,248
1,280
1610
M144K Blocks
(2048 x 72 bits)
22
48
64
60
Total Memory
(MLAB+M9K+
M144K) Kb
17,133
22,564
27,376
33,294
Embedded Multipliers
(18 x 18) (2)
1,288
1,040
1,024
960
PLLs
User I/Os
112
6
88
112
132
4
6
6
4
4
8
8
12
12
8
488
488
744
744
976
976
744
–2, –3, –4
–2, –3, –4
–2, –3, –4
–2, –3, –4
–2, –3, –4
–2, –3, –4
(3)
Speed Grade
(fastest to slowest)
112
1760
12
(4)
–3, –4
976
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
January 2016
Table 1–4 lists the Stratix IV E device features.
12
(4)
–3, –4
1120
(4)
–3, –4
Notes to Table 1–4:
(1) The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins
and dedicated configuration pins are not included in the pin count.
(2) Four multiplier adder mode.
(4) This data is preliminary.
1–15
Stratix IV Device Handbook
Volume 1
(3) Total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.
1–16
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
Table 1–5 summarizes the Stratix IV E device package options.
Table 1–5. Stratix IV E Device Package Options (1),
F780
(29 mm x 29 mm)
Device
EP4SE230
(5), (6)
(2)
F1152
(35 mm x 35 mm)
F29
EP4SE360
H29
(3)
F1517
(40 mm x 40 mm)
(5), (7)
F1760
(42.5 mm x 42.5 mm)
(7)
—
—
—
F35
—
—
EP4SE530
—
H35
(4)
H40
(4)
F43
EP4SE820
—
H35
(4)
H40
(4)
F43
(7)
Notes to Table 1–5:
(1) Device packages in the same column and marked under the same arrow sign have vertical migration capability.
(2) Use the Pin Migration Viewer in the Pin Planner to verify the pin migration compatibility when migrating devices. For more information, refer to
I/O Management in the Quartus II Handbook, Volume 2.
(3) The 780-pin EP4SE360 device is available only in the 33 mm x 33 mm Hybrid flip chip package.
(4) The 1152-pin and 1517-pin for EP4SE530 and EP4SE820 devices are available only in the 42.5 mm x 42.5 mm Hybrid flip chip package.
(5) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Package
Information Datasheet for Altera Devices.
(6) Devices listed in this column do not have on-package decoupling capacitors.
(7) Devices listed in this column have on-package decoupling capacitors. For more information about on-package decoupling capacitor value for
each device, refer to Table 1–6.
Table 1–6 lists the Stratix IV E on-package decoupling information.
Table 1–6. Stratix IV E Device On-Package Decoupling Information (1)
Ordering Information
EP4SE360
F35
VCC
VCCIO
41 uF + 4470 nF
10 nF per bank
41 uF + 4470 nF
10 nF per bank
41 uF + 4470 nF
10 nF per bank
H35
EP4SE530
H40
F43
H35
EP4SE820
H40
F43
Note to Table 1–6:
(1) Table 1–6 refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
devices, contact Altera Technical Support.
Table 1–7 lists the Stratix IV GT device features.
Table 1–7. Stratix IV GT Device Features (Part 1 of 2)
Feature
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
1517
1517
1517
1932
1932
ALMs
91,200
212,480
91,200
116,480
141,440
212,480
LEs
228,000
531,200
228,000
291,200
353,600
531,200
36
36
36
48
48
Package Pin Count
Total Transceiver
Channels
Stratix IV Device Handbook
Volume 1
EP4S40G2
EP4S100G5
1517
36
1932
48
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
1–17
Table 1–7. Stratix IV GT Device Features (Part 2 of 2)
Feature
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
10G Transceiver
Channels
(600 Mbps - 11.3 Gbps
with PMA + PCS)
12
12
24
24
24
24
32
8G Transceiver
Channels
(600 Mbps - 8.5 Gbps
with PMA + PCS) (1)
12
12
0
8
8
0
0
PMA-only CMU
Channels
(600 Mbps- 6.5 Gbps)
12
12
12
16
16
12
16
PCIe hard IP Blocks
2
2
2
4
4
2
4
High-Speed LVDS
SERDES
(up to 1.6 Gbps) (2)
46
46
46
47
47
46
47
SP1-4.2 Links
2
2
2
2
2
2
2
M9K Blocks
(256 x 36 bits)
1,235
1,280
1,235
936
1,248
1,280
M144K Blocks
(2048 x 72 bits)
22
64
22
36
48
64
Total Memory (MLAB +
M9K + M144K) Kb
17,133
27,376
17,133
17,248
22,564
27,376
Embedded Multipliers
18 x 18 (3)
1,288
1,024
1,288
832
1,024
1,024
8
8
8
12
12
8
12
654
654
654
781
781
654
781
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
PLLs
User I/Os
(4), (5)
Speed Grade
(fastest to slowest)
Notes to Table 1–7:
(1) You can configure all 10G transceiver channels as 8G transceiver channels. For example, the EP4S40G2F40 device has twenty-four 8G
transceiver channels and the EP4S100G5F45 device has thirty-two 8G transceiver channels.
(2) Total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.
(3) Four multiplier adder mode.
(4) The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
(5) This data is preliminary.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–18
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
Table 1–8 lists the resource counts for the Stratix IV GT devices.
Table 1–8. Stratix IV GT Device Package Options
(1), (2)
1517 Pin
(40 mm x 40 mm)
Device
1932 Pin
(45 mm x 45 mm)
(3)
Stratix IV GT 40 G Devices
EP4S40G2
F40
EP4S40G5
—
(4), (5)
H40
—
Stratix IV GT 100 G Devices
EP4S100G2
F40
—
EP4S100G3
—
F45
EP4S100G4
—
F45
EP4S100G5
H40
(4), (5)
F45
Notes to Table 1–8:
(1) This table represents pin compatability; however, it does not include hard IP block placement compatability.
(2) Devices under the same arrow sign have vertical migration capability.
(3) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information,
refer to the Altera Device Package Information Data Sheet.
(4) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm x 42.5-mm Hybrid flip chip
packages.
(5) If you are using the hard IP block, migration is not possible.
Table 1–9 lists the Stratix IV GT on-package decoupling information.
Table 1–9. Stratix IV GT Device On-Package Decoupling Information (1)
Ordering
Information
EP4S40G2F40
EP4S100G2F40
VCC
VCCIO
VCCL_GXB
VCCA_L/R
VCCT_L/R
VCCR_L/R
21 uF + 2470 nF
10 nF per bank
(2)
100 nF per
transceiver block
100 nF
100 nF
100 nF
41 uF + 4470 nF
10 nF per bank
(2)
100 nF per
transceiver block
100 nF
100 nF
100 nF
EP4S100G3F45
EP4S100G4F45
EP4S40G5H40
EP4S100G5H40
EP4S100G5F45
Notes to Table 1–9:
(1) Table 1–9 refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
devices, contact Altera Technical Support.
(2) For I/O banks 3(*), 4(*), 7(*), and 8(*) only. There is no OPD for I/O bank 1(*), 2(*), 5(*), and 6(*).
Stratix IV Device Handbook
Volume 1
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Integrated Software Platform
1–19
Integrated Software Platform
The Quartus II software provides an integrated environment for HDL and schematic
design entry, compilation and logic synthesis, full simulation and advanced timing
analysis, SignalTap II Logic Analyzer, and device configuration of Stratix IV designs.
The Quartus II software provides the MegaWizard Plug-In Manager user interface to
generate different functional blocks, such as memory, PLL, and digital signal
processing logic. For transceivers, the Quartus II software provides the ALTGX
MegaWizard Plug-In Manager interface that guides you through configuration of the
transceiver based on your application requirements.
The Stratix IV GX and GT transceivers allow you to implement low-power and
reliable high-speed serial interface applications with its fully reconfigurable
hardware, optimal signal integrity, and integrated Quartus II software platform.
f For more information about the QuarJanuary2016tus II software features, refer to the
Quartus II Handbook.
Ordering Information
This section describes the Stratix IV E, GT, and GX devices ordering information.
Figure 1–4 shows the ordering codes for Stratix IV GX and E devices.
Figure 1–4. Stratix IV GX and E Device Packaging Ordering Information
EP4SGX
230
K
F
40
C
2
G
ES
Family Signature
Optional Suffix
EP4SGX: Stratix IV Transceiver
EP4SE: Stratix IV Logic/Memory
N: RoHS5
G: RoHS6
Leaded
Device Density
70
110
180
230
290
360
530
820
Contact Altera for availability
Transceiver Count
Speed Grade
D: 8
F: 16
H: 24
K: 36
N: 48
Package Type
F: FineLine BGA (FBGA)
H: Hybrid FineLine BGA
January 2016
Indicates specific device
options or shipment method
ES: Engineering sample
RoHS
Altera Corporation
2, 2x, 3, or 4, with 2 being the fastest
Operating Temperature
Ball Array Dimension
Corresponds to pin count
29 = 780 pins
35 = 1152 pins
40 = 1517 pins
43 = 1760 pins
45 = 1932 pins
C: Commercial Temperature (tJ=0° C to 85° C)
I: Industrial Temperature (tJ=–40° C to 100° C)
M: Military Temperature (tJ=–55° C to 125° C)
Stratix IV Device Handbook
Volume 1
1–20
Chapter 1: Overview for the Stratix IV Device Family
Ordering Information
Figure 1–5 shows the ordering codes for Stratix IV GT devices.
Figure 1–5. Stratix IV GT Device Packaging Ordering Information
EP4SEP4S
40G
2
230
40
F
C
2
ES
Family Signature
Optional Suffix
Aggregate Bandwidth
Indicates specific device options
ES: Engineering sample
N: Lead-free devices
40G
100G
Device Density
Speed Grade
2 = 230k LEs
3 = 290k LEs
4 = 360k LEs
5 = 530k LEs
1, 2, 3 with 1 being the fastest
Operating Temperature
Package Type
C: Commercial temperature (t J = 0 C to 85 C)
I : Industrial temperature (t J = 0°C to 100°C)
F: FineLine BGA (FBGA)
H: Hybrid FineLine BGA
Ball Array Dimension
Corresponds to pin count
40 = 1517 pins
45 = 1932 pins
o
Document Revision History
Table 1–10 lists the revision history for this chapter.
Table 1–10. Document Revision History (Part 1 of 2)
Date
Version
January 2016
3.5
September 2012
3.4
June 2011
3.3
February 2011
3.2
March 2010
Stratix IV Device Handbook
Volume 1
3.1
Changes
■
Updated Figure 1–4 with new RoHS information
■
Updated Table 1–1 to close FB #30986.
■
Updated Table 1–2 and Table 1–5 to close FB #31127.
■
Added military temperature to Figure 1–4.
■
Updated Table 1–7 and Table 1–8.
■
Applied new template.
■
Minor text edits.
■
Updated Table 1–1, Table 1–2, and Table 1–7.
■
Updated Figure 1–3.
■
Updated the “Stratix IV GT Devices” section.
■
Added two new references to the Introduction section.
■
Minor text edits.
January 2016 Altera Corporation
Chapter 1: Overview for the Stratix IV Device Family
Ordering Information
1–21
Table 1–10. Document Revision History (Part 2 of 2)
Date
Version
November 2009
June 2009
3.0
2.4
April 2009
2.3
March 2009
2.2
March 2009
2.1
November 2008
2.0
Changes
■
Updated the “Stratix IV Device Family Overview”, “Feature Summary”, “Stratix IV GT
Devices”, “High-Speed Transceiver Features”, “FPGA Fabric and I/O Features”, “Highest
Aggregate Data Bandwidth”, “System Integration”, and “Integrated Software Platform”
sections.
■
Added Table 1–3, Table 1–6, and Table 1–9.
■
Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, Table 1–7, and Table 1–8.
■
Updated Figure 1–3, Figure 1–4, and Figure 1–5.
■
Minor text edits.
■
Updated Table 1–1.
■
Minor text edits.
■
Added Table 1–5, Table 1–6, and Figure 1–3.
■
Updated Figure 1–5.
■
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
■
Updated “Introduction”, “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV GT
Devices”, “Architecture Features”, and “FPGA Fabric and I/O Features”
■
Updated “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV E Device”, “Stratix IV
GT Devices”, “Signal Integrity”
■
Removed Tables 1-5 and 1-6
■
Updated Figure 1–4
■
Updated “Introduction”, “Feature Summary”, “Stratix IV Device Diagnostic Features”,
“Signal Integrity”, “Clock Networks”,“High-Speed Differential I/O with DPA and SoftCDR”, “System Integration”, and “Ordering Information” sections.
■
Added “Stratix IV GT 100G Devices” and “Stratix IV GT 100G Transceiver Bandwidth”
sections.
■
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
■
Added Table 1–5 and Table 1–6.
■
Updated Figure 1–3 and Figure 1–4.
■
Added Figure 1–5.
■
Removed “Referenced Documents” section.
■
Updated “Feature Summary” on page 1–1.
■
Updated “Stratix IV Device Diagnostic Features” on page 1–7.
■
Updated “FPGA Fabric and I/O Features” on page 1–8.
■
Updated Table 1–1.
■
Updated Table 1–2.
■
Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT
Device.” on page 1–15.
July 2008
1.1
Revised “Introduction”.
May 2008
1.0
Initial release.
January 2016
Altera Corporation
Stratix IV Device Handbook
Volume 1
1–22
Stratix IV Device Handbook
Volume 1
Chapter 1: Overview for the Stratix IV Device Family
Ordering Information
January 2016 Altera Corporation
2. Logic Array Blocks and Adaptive Logic
Modules in Stratix IV Devices
February 2011
SIV51002-3.1
SIV51002-3.1
This chapter describes the features of the logic array blocks (LABs) in the Stratix® IV
core fabric. LABs are made up of adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
LABs and ALMs are the basic building blocks of the Stratix IV device. Use these to
configure logic, arithmetic, and register functions. The ALM provides advanced
features with efficient logic usage and is completely backward-compatible.
This chapter contains the following sections:
■
“Logic Array Blocks”
■
“Adaptive Logic Modules” on page 2–5
Logic Array Blocks
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus® II Compiler places associated logic in
the LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 1
February 2011
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2–2
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Logic Array Blocks
Figure 2–1 shows the Stratix IV LAB structure and interconnects.
Figure 2–1. Stratix IV LAB Structure and Interconnects
C4
C12
Row Interconnects of
Variable Speed & Length
R20
R4
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB
MLAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB, as shown in Figure 2–2.
The MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix IV
families. MLAB is a superset of the LAB and includes all LAB features.
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Logic Array Blocks
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f For more information about the MLAB, refer to the chapter.
Figure 2–2. Stratix IV LAB and MLAB Structure
LUT-based-64 x 1
Simple dual-port SRAM
(1)
ALM
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
ALM
LAB Control Block
(1)
ALM
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
LUT-based-64 x 1
Simple dual-port SRAM
(1)
MLAB
ALM
ALM
LAB Control Block
LUT-based-64 x 1
Simple dual-port SRAM
ALM
ALM
ALM
ALM
ALM
LAB
Note to Figure 2–2:
(1) You can use the MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown.
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Logic Array Blocks
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven by column
and row interconnects and ALM outputs in the same LAB. Neighboring
LABs/MLABs, M9K RAM blocks, M144K blocks, or digital signal processing (DSP)
blocks from the left or right can also drive the LAB’s local interconnect through the
direct link connection. The direct link connection feature minimizes the use of row
and column interconnects, providing higher performance and flexibility. Each LAB
can drive 30 ALMs through fast-local and direct-link interconnects.
Figure 2–3 shows the direct-link connection.
Figure 2–3. Direct-Link Connection
Direct-link interconnect from the
left LAB, TriMatrix memory
block, DSP block, or IOE output
Direct-link interconnect from the
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
ALMs
Direct-link
interconnect
to right
Direct-link
interconnect
to left
Local
Interconnect
MLAB
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. Control
signals include three clocks, three clock enables, two asynchronous clears, a
synchronous clear, and synchronous load control signals. This gives a maximum of 10
control signals at a time. Although you generally use synchronous-load and clear
signals when implementing counters, you can also use them with other functions.
Each LAB has two unique clock sources and three clock enable signals, as shown in
Figure 2–4. The LAB control block can generate up to three clocks using two clock
sources and three clock enable signals. Each LAB’s clock and clock enable signals are
linked. For example, any ALM in a particular LAB using the labclk1 signal also uses
the labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it
also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off
the corresponding LAB-wide clock.
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Adaptive Logic Modules
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The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. The MultiTrack interconnect’s inherent low skew allows clock and control
signal distribution in addition to data.
Figure 2–4. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk2
labclk1
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr1
syncload
labclr0
synclr
Adaptive Logic Modules
The ALM is the basic building block of logic in the Stratix IV architecture. It provides
advanced features with efficient logic usage. Each ALM contains a variety of
LUT-based resources that can be divided between two combinational adaptive LUTs
(ALUTs) and two registers. With up to eight inputs for the two combinational ALUTs,
one ALM can implement various combinations of two functions. This adaptability
allows an ALM to be completely backward-compatible with four-input LUT
architectures. One ALM can also implement any function with up to six inputs and
certain seven-input functions.
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Adaptive Logic Modules
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can efficiently
implement various arithmetic functions and shift registers. Each ALM drives all types
of interconnects: local, row, column, carry chain, shared arithmetic chain, register
chain, and direct link. Figure 2–5 shows a high-level block diagram of the Stratix IV
ALM.
Figure 2–5. High-Level Block Diagram of the Stratix IV ALM
shared_arith_in
carry_in
Combinational/Memory ALUT0
reg_chain_in
labclk
To general or
local routing
dataf0
datae0
6-Input LUT
adder0
D
Q
dataa
To general or
local routing
reg0
datab
datac
datad
datae1
adder1
D
Q
6-Input LUT
To general or
local routing
reg1
dataf1
To general or
local routing
Combinational/Memory ALUT1
reg_chain_out
shared_arith_out
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
2–7
Figure 2–6 shows a detailed view of all the connections in an ALM.
Figure 2–6. Stratix IV ALM Connection Details
syncload
aclr[1:0]
shared_arith_in
carry_in
clk[2:0]
sclr
reg_chain_in
dataf0
datae0
dataa
datab
GND
4-INPUT
LUT
datac0
+
CLR
D
Q
3-INPUT
LUT
local
interconnect
row, column
direct link routing
row, column
direct link routing
3-INPUT
LUT
4-INPUT
LUT
datac1
+
CLR
D
Q
3-INPUT
LUT
local
interconnect
row, column
direct link routing
row, column
direct link routing
3-INPUT
LUT
VCC
datae1
dataf1
shared_arith_out
carry_out
reg_chain_out
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, and synchronous load and clear inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register’s
clock and clear-control signals. Either general-purpose I/O pins or internal logic can
drive the clock enable. For combinational functions, the register is bypassed and the
output of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register outputs can drive these output drivers (refer to
Figure 2–6). For each set of output drivers, two ALM outputs can drive column, row,
or direct-link routing connections. One of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
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This feature, called register packing, improves device utilization because the device
can use the register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The ALM can also drive out registered and
unregistered versions of the LUT or adder output.
ALM Operating Modes
The Stratix IV ALM operates in one of the following modes:
■
Normal
■
Extended LUT
■
Arithmetic
■
Shared Arithmetic
■
LUT-Register
Each mode uses ALM resources differently. In each mode, eleven available inputs to
an ALM—the eight data inputs from the LAB local interconnect, carry-in from the
previous ALM or LAB, the shared arithmetic chain connection from the previous
ALM or LAB, and the register chain connection—are directed to different destinations
to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all ALM modes.
For more information about the LAB-wide control signals, refer to “LAB Control
Signals” on page 2–4.
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as the library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions.
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
2–9
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the
combinational logic. Normal mode allows two functions to be implemented in one
Stratix IV ALM, or a single function of up to six inputs. The ALM can support certain
combinations of completely independent functions and various combinations of
functions that have common inputs.
Figure 2–7 shows the supported LUT combinations in normal mode.
Figure 2–7. ALM in Normal Mode
dataf0
datae0
datac
dataa
(1)
4-Input
LUT
combout0
datab
datad
datae1
dataf1
4-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
datad
datae1
dataf1
3-Input
LUT
dataf0
datae0
datac
dataa
datab
5-Input
LUT
4-Input
LUT
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
6-Input
LUT
combout1
datad
datae1
dataf1
combout1
combout0
combout1
datae1
dataf1
Note to Figure 2–7:
(1) Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following
number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, and 5 and 2.
Normal mode provides complete backward-compatibility with four-input LUT
architectures.
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Adaptive Logic Modules
For the packing of 2 five-input functions into one ALM, the functions must have at
least two common inputs. The common inputs are dataa and datab. The combination
of a four-input function with a five-input function requires one common input (either
dataa or datab).
In the case of implementing 2 six-input functions in one ALM, four inputs must be
shared and the combinational function must be the same. In a sparsely used device,
functions that could be placed in one ALM may be implemented in separate ALMs by
the Quartus II software to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically uses the full potential of the Stratix IV
ALM. The Quartus II Compiler automatically searches for functions using common
inputs or completely independent functions to be placed in one ALM to make efficient
use of device resources. In addition, you can manually control resource usage by
setting location assignments.
You can implement any six-input function using inputs dataa, datab, datac, datad,
and either datae0 and dataf0 or datae1 and dataf1. If you use datae0 and dataf0, the
output is driven to register0, and/or register0 is bypassed and the data drives out
to the interconnect using the top set of output drivers (refer to Figure 2–8). If you use
datae1 and dataf1, the output either drives to register1 or bypasses register1 and
drives to the interconnect using the bottom set of output drivers. The Quartus II
Compiler automatically selects the inputs to the LUT. ALMs in normal mode support
register packing.
Figure 2–8. Input Function in Normal Mode
dataf0
datae0
dataa
datab
datac
datad
(1)
To general or
local routing
6-Input
LUT
D
Q
To general or
local routing
reg0
datae1
dataf1
(2)
D
labclk
Q
To general or
local routing
reg1
These inputs are available for register packing.
Notes to Figure 2–8:
(1) If you use datae1 and dataf1 as inputs to a six-input function, datae0 and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is unregistered.
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Adaptive Logic Modules
2–11
Extended LUT Mode
Use extended LUT mode to implement a specific set of seven-input functions. The set
must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs. Figure 2–9 shows the template of supported seven-input functions using
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–9 occur naturally in designs.
These functions often appear in designs as “if-else” statements in Verilog HDL or
VHDL code.
Figure 2–9. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
5-Input
LUT
To general or
local routing
combout0
D
5-Input
LUT
Q
To general or
local routing
reg0
datae1
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–9:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is
not available.
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Adaptive Logic Modules
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of
2 four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of 2 four-input functions.
The four LUTs share dataa and datab inputs. As shown in Figure 2–10, the carry-in
signal feeds to adder0 and the carry-out from adder0 feeds to the carry-in of adder1.
The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in
arithmetic mode can drive out registered and/or unregistered versions of the adder
outputs.
Figure 2–10. ALM in Arithmetic Mode
carry_in
datae0
adder0
4-Input
LUT
To general or
local routing
D
dataf0
datac
datab
dataa
datad
datae1
Q
To general or
local routing
reg0
4-Input
LUT
adder1
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
dataf1
carry_out
While operating in arithmetic mode, the ALM can support simultaneous use of the
adder’s carry output along with combinational logic outputs. In this operation, adder
output is ignored. Using the adder with combinational logic output provides resource
savings of up to 50% for functions that can use this ability.
Arithmetic mode also offers clock enable, counter enable, synchronous up/down
control, add/subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up/down, and add/subtract control signals. These control signals are good
candidates for the inputs that are shared between the four LUTs in the ALM. The
synchronous clear and synchronous load options are LAB-wide signals that affect all
registers in the LAB. These signals can also be individually disabled or enabled per
register. The Quartus II software automatically places any registers that are not used
by the counter into other LABs.
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Adaptive Logic Modules
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Carry Chain
The carry chain provides a fast carry function between the dedicated adders in
arithmetic or shared-arithmetic mode. The two-bit carry select feature in Stratix IV
devices halves the propagation delay of carry chains within the ALM. Carry chains
can begin in either the first ALM or the fifth ALM in the LAB. The final carry-out
signal is routed to the ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry-chain logic during design
processing, or you can create it manually during design entry. Parameterized
functions such as LPM functions automatically take advantage of carry chains for the
appropriate functions.
The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. For enhanced
fitting, a long carry chain runs vertically, allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high fan-in
arithmetic function is implemented, the LAB can support carry chains that only use
either the top half or bottom half of the LAB before connecting to the next LAB. This
leaves the other half of the ALMs in the LAB available for implementing narrower
fan-in functions in normal mode. Carry chains that use the top five ALMs in the first
LAB carry into the top half of the ALMs in the next LAB within the column. Carry
chains that use the bottom five ALMs in the first LAB carry into the bottom half of the
ALMs in the next LAB within the column. In every alternate LAB column, the top half
can be bypassed; in the other MLAB columns, the bottom half can be bypassed.
For more information about carry-chain interconnects, refer to “ALM Interconnects”
on page 2–18.
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Adaptive Logic Modules
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add within the
ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either
computes the sum of three inputs or the carry of three inputs. The output of the carry
computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of
the next ALM in the LAB) using a dedicated connection called the shared arithmetic
chain. This shared arithmetic chain can significantly improve the performance of an
adder tree by reducing the number of summation stages required to implement an
adder tree. Figure 2–11 shows the ALM using this feature.
Figure 2–11. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
labclk
4-Input
LUT
To general or
local routing
D
datae0
datac
datab
dataa
datad
datae1
Q
To general or
local routing
reg0
4-Input
LUT
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
carry_out
shared_arith_out
You can find adder trees in many different applications. For example, the summation
of the partial products in a logic-based multiplier can be implemented in a tree
structure. Another example is a correlator function that can use a large adder tree to
sum filtered data samples in a given time frame to recover or de-spread data that was
transmitted using spread-spectrum technology.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM
to implement a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
Shared arithmetic chains can begin in either the first or sixth ALM in the LAB. The
Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long shared arithmetic chain runs vertically, allowing fast
horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic
chain can continue as far as a full column.
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Adaptive Logic Modules
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Similar to the carry chains, the top and bottom halves of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in an LAB while leaving the other half
available for narrower fan-in functionality. Every other LAB column is top-half
by-passable, while the other LAB columns are bottom-half by-passable.
For more information about the shared arithmetic chain interconnect, refer to “ALM
Interconnects” on page 2–18.
LUT-Register Mode
LUT-register mode allows third-register capability within an ALM. Two internal
feedback loops allow combinational ALUT1 to implement the master latch and
combinational ALUT0 to implement the slave latch needed for the third register. The
LUT register shares its clock, clock enable, and asynchronous clear sources with the
top dedicated register. Figure 2–12 shows the register constructed using two
combinational blocks within the ALM.
Figure 2–12. LUT Register from Two Combinational Blocks
sumout
clk
aclr
LUT regout
4-input
LUT
combout
5-input
LUT
combout
sumout
datain(datac)
sclr
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Adaptive Logic Modules
Figure 2–13 shows the ALM in LUT-register mode.
Figure 2–13. ALM in LUT-Register Mode with Three-Register Capability
clk [2:0]
DC1
aclr [1:0]
reg_chain_in
datain
lelocal 0
aclr
aclr
sclr
regout
datain
latchout
sdata
leout 0 a
regout
leout 0 b
E0
F1
lelocal 1
aclr
datain
E1
sdata
F0
leout 1 a
regout
leout 1 b
reg_chain_out
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Adaptive Logic Modules
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Register Chain
In addition to general routing outputs, ALMs in the LAB have register-chain outputs.
Register-chain routing allows registers in the same LAB to be cascaded together. The
register-chain interconnect allows the LAB to use LUTs for a single combinational
function and the registers to be used for an unrelated shift-register implementation.
These resources speed up connections between ALMs while saving local interconnect
resources (refer to Figure 2–14). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
Figure 2–14. Register Chain within the LAB
(1)
From previous ALM
within the LAB
reg_chain_in
labclk
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
reg_chain_out
To next ALM
within the LAB
Note to Figure 2–14:
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
For more information about the register chain interconnect, refer to “ALM
Interconnects” on page 2–18.
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Adaptive Logic Modules
ALM Interconnects
There are three dedicated paths between the ALMs—register cascade, carry chain,
and shared arithmetic chain. Stratix IV devices include an enhanced interconnect
structure in LABs for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect. The
Quartus II Compiler automatically takes advantage of these resources to improve
utilization and performance. Figure 2–15 shows the shared arithmetic chain, carry
chain, and register chain interconnects.
Figure 2–15. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
Local interconnect
routing among ALMs
in the LAB
Carry chain & shared
arithmetic chain
routing to adjacent ALM
ALM 1
Register chain
routing to adjacent
ALM's register input
ALM 2
Local
interconnect
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
ALM 10
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear signal. The ALM directly
supports an asynchronous clear function. You can achieve the register preset through
the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to
two clears.
Stratix IV devices provide a device-wide reset pin (DEV_CLRn) that resets all the
registers in the device. An option set before compilation in the Quartus II software
controls this pin. This device-wide reset overrides all other control signals.
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Adaptive Logic Modules
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LAB Power Management Techniques
The following techniques are used to manage static and dynamic power consumption
within the LAB:
■
To save AC power, the Quartus II software forces all adder inputs low when ALM
adders are not in use.
■
Stratix IV LABs operate in high-performance mode or low-power mode. The
Quartus II software automatically chooses the appropriate mode for the LAB,
based on the design, to optimize speed versus leakage trade-offs.
■
Clocks represent a significant portion of dynamic power consumption due to their
high switching activity and long paths. The LAB clock that distributes a clock
signal to registers within an LAB is a significant contributor to overall clock power
consumption. Each LAB’s clock and clock enable signal are linked. For example, a
combinational ALUT or register in a particular LAB using the labclk1 signal also
uses the labclkena1 signal. To disable LAB-wide clock power consumption
without disabling the entire clock tree, use LAB-wide clock enable to gate the
LAB-wide clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within the LAB that share a
common clock and clock enable are controlled by a shared, gated clock. To take
advantage of these clock enables, use a clock-enable construct in your HDL code
for the registered logic.
f For more information about implementing static and dynamic power consumption
within the LAB, refer to the Power Optimization chapter in volume 2 of the Quartus II
Handbook.
Document Revision History
Table 2–1 lists the revision history for this chapter.
Table 2–1. Document Revision History
Date
Version
February 2011
3.1
November 2009
3.0
June 2009
2.2
March 2009
2.1
November 2008
2.0
May 2008
1.0
February 2011
Altera Corporation
Changes
■
Updated Figure 2–6.
■
Applied new template.
■
Minor text edits.
■
Updated graphics.
■
Minor text edits.
■
Removed the Conclusion section.
■
Added introductory sentences to improve search ability.
■
Minor text edits.
Removed “Referenced Documents” section.
■
Updated Figure 2–6.
■
Made minor editorial changes.
Initial release.
Stratix IV Device Handbook
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Stratix IV Device Handbook
Volume 1
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
February 2011 Altera Corporation
3. TriMatrix Embedded Memory Blocks in
Stratix IV Devices
December 2011
SIV51003-3.3
SIV51003-3.3
This chapter describes the TriMatrix embedded memory blocks in Stratix® IV devices.
TriMatrix embedded memory blocks provide three different sizes of embedded
SRAM to efficiently address the needs of Stratix IV FPGA designs. TriMatrix memory
includes 640-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and
144-Kbit M144K blocks. MLABs have been optimized to implement filter delay lines,
small FIFO buffers, and shift registers. You can use the M9K blocks for general
purpose memory applications and the M144K blocks for processor code storage,
packet buffering, and video frame buffering.
You can independently configure each embedded memory block to be a single- or
dual-port RAM, FIFO buffer, ROM, or shift register using the Quartus® II
MegaWizard™ Plug-In Manager. You can stitch together multiple blocks of the same
type to produce larger memories with minimal timing penalty. TriMatrix memory
provides up to 31,491 Kbits of embedded SRAM at up to 600 MHz operation.
This chapter contains the following sections:
■
“Overview”
■
“Memory Modes” on page 3–9
■
“Clocking Modes” on page 3–17
■
“Design Considerations” on page 3–18
Overview
Table 3–1 lists the features supported by the three sizes of TriMatrix memory.
Table 3–1. Summary of TriMatrix Memory Features (Part 1 of 2)
Feature
Maximum performance
Total RAM bits
(including parity bits)
MLABs
M9K Blocks
M144K Blocks
600 MHz
600 MHz
540 MHz
640
9216
147,456
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
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3–2
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Table 3–1. Summary of TriMatrix Memory Features (Part 2 of 2)
Feature
MLABs
M9K Blocks
8K × 1
4K × 2
64 × 8
2K × 4
64 × 9
Configurations
(depth × width)
1K × 8
64 × 10
1K × 9
32 × 16
512 × 16
32 × 18
512 × 18
32 × 20
256 × 32
256 × 36
M144K Blocks
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
Parity bits
Supported
Supported
Supported
Byte enable
Supported
Supported
Supported
—
Supported
Supported
Address clock enable
Supported
Supported
Supported
Single-port memory
Supported
Supported
Supported
Simple dual-port memory
Supported
Supported
Supported
True dual-port memory
—
Supported
Supported
Embedded shift register
Supported
Supported
Supported
ROM
Supported
Supported
Supported
FIFO buffer
Packed mode
Supported
Supported
Supported
Simple dual-port mixed
width support
—
Supported
Supported
True dual-port mixed width
support
—
Supported
Supported
Memory Initialization File
(.mif)
Supported
Supported
Supported
Mixed clock mode
Supported
Supported
Supported
Power-up condition
Outputs cleared if
registered, otherwise reads
memory contents
Outputs cleared
Outputs cleared
Register clears
Output registers
Output registers
Output registers
Write/Read operation
triggering
Write: Falling clock edges
Write and Read: Rising clock
edges
Write and Read: Rising clock
edges
Same-port read-during-write
Outputs set to don’t care
Outputs set to old data or
new data
Outputs set to old data or
new data
Mixed-port read-during-write
Outputs set to old data,
new data, or don’t care
Outputs set to old data or
don’t care
Outputs set to old data or
don’t care
ECC Support
Soft IP support using the
Quartus II software
Soft IP support using the
Quartus II software
Built-in support in ×64-wide
SDP mode or soft IP support
using the Quartus II software
Read: Rising clock edges
(1)
Note to Table 3–1:
(1) The mixed-port read-during-write options of new data or old data are only supported for MLABs when you use both the read address registers
and the output registers.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
3–3
Table 3–2 lists the capacity and distribution of the TriMatrix memory blocks in each
Stratix IV family member.
Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices
MLABs
M9K Blocks
M144K
Blocks
Total Dedicated RAM Bits
(Dedicated Memory Blocks Only)
(Kb)
Total RAM Bits
(Including MLABs)
(Kb)
EP4SE230
4,560
1,235
22
14,283
17,133
EP4SE360
7,072
1,248
48
18,144
22,564
EP4SE530
10,624
1,280
64
20,736
27,376
EP4SE820
16,261
1,610
60
23,130
33,294
EP4SGX70
1,452
462
16
6,462
7,370
EP4SGX110
2,112
660
16
8,244
9,564
Device
EP4SGX180
3,515
950
20
11,430
13,627
EP4SGX230
4,560
1,235
22
14,283
17,133
EP4SGX290
5,824
936
36
13,608
17,248
EP4SGX360
7,072
1,248
48
18,144
22,564
EP4SGX530
10,624
1,280
64
20,736
27,376
EP4S40G2
4,560
1,235
22
14,283
17,133
EP4S40G5
10,624
1280
64
20,736
27,376
EP4S100G2
4,560
1,235
22
14,283
17,133
EP4S100G3
5,824
936
36
13,608
17,248
EP4S100G4
7,072
1,248
48
18,144
22,564
EP4S100G5
10,624
1,280
64
20,736
27,376
TriMatrix Memory Block Types
While the M9K and M144K memory blocks are dedicated resources, the MLABs are
dual-purpose blocks. They can be configured as regular logic array blocks (LABs) or
as MLABs. Ten adaptive logic modules (ALMs) make up one MLAB. You can
configure each ALM in an MLAB as either a 64 × 1 or a 32 × 2 block, resulting in a
64 × 10 or 32 × 20 simple dual-port SRAM block in a single MLAB.
Parity Bit Support
All TriMatrix memory blocks have built-in parity-bit support. The ninth bit associated
with each byte can store a parity bit or serve as an additional data bit. No parity
function is actually performed on the ninth bit.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input data so that
only specific bytes of data are written. The unwritten bytes retain the previously
written values. The write enable (wren) signals, along with the byte enable (byteena)
signals, control the RAM blocks’ write operations.
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Stratix IV Device Handbook
Volume 1
3–4
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers have no clear
port. When using parity bits on the M9K and M144K blocks, the byte enable controls
all nine bits (eight bits of data plus one parity bit). When using parity bits on the
MLAB, the byte-enable controls all 10 bits in the widest mode.
The MSB for the byteena signal corresponds to the MSB of the data bus and the LSB of
the byteena signal corresponds to the LSB of the data bus. For example, if you use a
RAM block in ×18 mode, with byteena = 01, data[8..0] is enabled, and data[17..9]
id disabled. Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled.
Byte enables are active high.
1
You cannot use the byte enable feature when using the error correction coding (ECC)
feature on M144K blocks.
1
Byte enables are only supported for true dual-port memory configurations when both
the PortA and PortB data widtByths of the individual M9K memory blocks are
multiples of 8 or 9 bits. For example, if you implement a mixed data width memory
configured with portA = 32 and portB = 8 as two separate 16 x 4 bit memories, you
cannot use the byte enable feature.
Figure 3–1 shows how the write enable (wren) and byte enable (byteena) signals
control the operations of the RAM blocks.
When a byte-enable bit is de-asserted during a write cycle, the corresponding data
byte output can appear as either a “don’t care” value or the current data at that
location. The output value for the masked byte is controllable using the Quartus II
software. When a byte-enable bit is asserted during a write cycle, the corresponding
data byte output also depends on the setting chosen in the Quartus II software.
Figure 3–1. Byte Enable Functional Waveform
inclock
wren
address
data
byteena
contents at a0
contents at a1
a0
an
a1
a2
a0
a1
ABCD
XXXX
10
XX
a2
XXXX
01
11
FFFF
XX
ABFF
FFFF
FFCD
FFFF
contents at a2
ABCD
don't care: q (asynch)
doutn
ABXX
XXCD
ABCD
ABFF
FFCD
ABCD
current data: q (asynch)
doutn
ABFF
FFCD
ABCD
ABFF
FFCD
ABCD
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
3–5
Packed Mode Support
Stratix IV M9K and M144K blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements packed mode where appropriate by placing the
physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
December 2011
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Stratix IV Device Handbook
Volume 1
3–6
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Address Clock Enable Support
All Stratix IV memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When the
memory blocks are configured in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signals is low
(disabled).
Figure 3–2 shows an address clock enable block diagram. The address clock enable is
referred to by the port name addressstall.
Figure 3–2. Address Clock Enable
address[0]
1
0
address[N]
1
0
address[0]
register
address[0]
address[N]
register
address[N]
addressstall
clock
Figure 3–3 shows the address clock enable waveform during the read cycle.
Figure 3–3. Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory)
an
q (synch) doutn-1
q (asynch)
Stratix IV Device Handbook
Volume 1
doutn
a1
a0
doutn
dout0
dout0
a4
dout4
dout1
dout1
a5
dout4
dout5
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
3–7
Figure 3–4 shows the address clock enable waveform during the write cycle.
Figure 3–4. Address Clock Enable During the Write Cycle Waveform
inclock
wraddress
a0
a1
a2
a3
a4
a5
a6
00
01
02
03
04
05
06
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
an
a1
a0
a4
a5
00
XX
XX
01
02
contents at a2
XX
contents at a3
XX
contents at a4
contents at a5
03
04
XX
XX
05
Mixed Width Support
M9K and M144K memory blocks support mixed data widths inherently. MLABs can
support mixed data widths through emulation using the Quartus II software. When
using simple dual-port, true dual-port, or FIFO modes, mixed width support allows
you to read and write different data widths to a memory block. For more information
about the different widths supported per memory mode, refer to “Memory Modes”
on page 3–9.
1
MLABs do not support mixed-width FIFO mode.
Asynchronous Clear
Stratix IV TriMatrix memory blocks support asynchronous clears on output latches
and output registers. Therefore, if your RAM is not using output registers, you can
still clear the RAM outputs using the output latch asynchronous clear. Figure 3–5
shows a waveform of the output latch asynchronous clear function.
Figure 3–5. Output Latch Asynchronous Clear Waveform
outclk
aclr
aclr at latch
q
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard Plug-In Manager.
f For more information, refer to the Internal Memory (RAM and ROM) User Guide.
December 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
3–8
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Error Correction Code (ECC) Support
Stratix IV M144K blocks have built-in support for error correction code (ECC) when in
×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in
the memory array. The M144K blocks have a single-error-correction
double-error-detection (SECDED) implementation. SECDED can detect and fix a
single bit error in a 64-bit word, or detect two bit errors in a 64-bit word. It cannot
detect three or more errors.
The M144K ECC status is communicated using a three-bit status flag
eccstatus[2..0]. The status flag can be either registered or unregistered. When
registered, it uses the same clock and asynchronous clear signals as the output
registers. When unregistered, it cannot be asynchronously cleared.
Table 3–3 lists the truth table for the ECC status flags.
Table 3–3. Truth Table for ECC Status Flags
Status
eccstatus[2]
eccstatus[1]
eccstatus[0]
No error
0
0
0
Single error and fixed
0
1
1
Double error and no fix
1
0
1
Illegal
0
0
1
Illegal
0
1
0
Illegal
1
0
0
Illegal
1
1
X
1
You cannot use the byte enable feature when ECC is engaged.
1
Read-during-write “old data mode” is not supported when ECC is engaged.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–9
Figure 3–6 shows a diagram of the ECC block of the M144K block.
Figure 3–6. ECC Block Diagram of the M144K Block
8
64
64
SECDED
Encoder
Data Input
8
72
RAM
Array
72
64
SECDED
Encoder
Comparator
8
64
8
8
64
Error
Locator
64
Error
Correction
Block
Flag
Generator
3
Status Flags
64
Data Output
Memory Modes
Stratix IV TriMatrix memory blocks allow you to implement fully synchronous SRAM
memory in multiple modes of operation. M9K and M144K blocks do not support
asynchronous memory (unregistered inputs). MLABs support asynchronous
(flow-through) read operations.
Depending on which TriMatrix memory block you target, you can use the following:
■
“Single-Port RAM Mode” on page 3–10
■
“Simple Dual-Port Mode” on page 3–11
■
“True Dual-Port Mode” on page 3–14
■
“Shift-Register Mode” on page 3–16
■
“ROM Mode” on page 3–17
■
“FIFO Mode” on page 3–17
c When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or
hold-time on any of the memory block input registers. This applies to both read and
write operations.
December 2011
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Stratix IV Device Handbook
Volume 1
3–10
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
Single-Port RAM Mode
All TriMatrix memory blocks support single-port mode. Single-port mode allows you
to do either one-read or one-write operation at a time. Simultaneous reads and writes
are not supported in single-port mode. Figure 3–7 shows the single-port RAM
configuration.
Figure 3–7. Single-Port RAM
(1)
data[ ]
address[ ]
wren
byteena[]
addressstall
inclock
clockena
rden
aclr
q[]
outclock
Note to Figure 3–7:
(1) You can implement two single-port memory blocks in a single M9K or M144K block. For more information, refer to
“Packed Mode Support” on page 3–5.
During a write operation, RAM output behavior is configurable. If you use the
read-enable signal and perform a write operation with read enable de-activated, the
RAM outputs retain the values they held during the most recent active read enable. If
you activate read enable during a write operation, or if you are not using the
read-enable signal at all, the RAM outputs either show the “new data” being written,
the “old data” at that address, or a “don’t care” value. To choose the desired behavior,
set the read-during-write behavior to either new data, old data, or don’t care in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to “Read-During-Write Behavior” on page 3–19.
Table 3–4 lists the possible port width configurations for TriMatrix memory blocks in
single-port mode.
Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode)
MLABs
M9K Blocks
8K × 1
64 × 8
64 × 9
Port Width
Configurations
64 × 10
32 × 16
32 × 18
32 × 20
4K × 2
2K × 4
1K × 8
1K × 9
512 × 16
512 × 18
256 × 32
256 × 36
Stratix IV Device Handbook
Volume 1
M144K Blocks
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–11
Figure 3–8 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs. Registering the RAM’s outputs simply delays the
q output by one clock cycle.
Figure 3–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
clk_a
A0
address
A1
rdena
wrena
bytenna
data_a
01
10
00
A123
B456
C789
A0 (old data) DoldDold23
q_a (asyn)
11
DDDD
B423
EEEE
A1(old data)
FFFF
DDDD
EEEE
Simple Dual-Port Mode
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode
allows you to perform one read and one write operation to different locations at the
same time. Write operation happens on port A; read operation happens on port B.
Figure 3–9 shows a simple dual-port configuration.
Figure 3–9. Stratix IV Simple Dual-Port Memory
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
(1)
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
ecc_status
Note to Figure 3–9:
(1) Simple dual-port RAM supports input/output clock mode in addition to read/write clock mode.
Simple dual-port mode supports different read and write data widths (mixed-width
support). Table 3–5 lists the mixed width configurations for M9K blocks in simple
dual-port mode. MLABs do not have native support for mixed-width operation. The
Quartus II software implements mixed-width memories in MLABs by using more
than one MLAB.
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Write Port
Read Port
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
256 × 32
1K × 9
512 × 18
256 × 36
8K × 1
Y
Y
Y
Y
Y
Y
—
—
—
4K × 2
Y
Y
Y
Y
Y
Y
—
—
—
2K × 4
Y
Y
Y
Y
Y
Y
—
—
—
December 2011
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Stratix IV Device Handbook
Volume 1
3–12
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Write Port
Read Port
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
256 × 32
1K × 9
512 × 18
256 × 36
1K × 8
Y
Y
Y
Y
Y
Y
—
—
—
512 × 16
Y
Y
Y
Y
Y
Y
—
—
—
256 × 32
Y
Y
Y
Y
Y
Y
—
—
—
1K × 9
—
—
—
—
—
—
Y
Y
Y
512 × 18
—
—
—
—
—
—
Y
Y
Y
256 × 36
—
—
—
—
—
—
Y
Y
Y
Table 3–6 lists the mixed-width configurations for M144K blocks in simple dual-port
mode.
Table 3–6. M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Write Port
Read Port
16K × 8
8K × 16
4K × 32
2K × 64
16K × 9
8K × 18
4K × 36
2K × 72
16K × 8
Y
Y
Y
Y
—
—
—
—
8K × 16
Y
Y
Y
Y
—
—
—
—
4K × 32
Y
Y
Y
Y
—
—
—
—
2K × 64
Y
Y
Y
Y
—
—
—
—
16K × 9
—
—
—
—
Y
Y
Y
Y
8K × 18
—
—
—
—
Y
Y
Y
Y
4K × 36
—
—
—
—
Y
Y
Y
Y
2K × 72
—
—
—
—
Y
Y
Y
Y
In simple dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output a “don’t care” value or “old data” value. To choose the desired behavior,
set the read-during-write behavior to either don’t care or old data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information, refer
to “Read-During-Write Behavior” on page 3–19.
MLABs only support a write-enable signal. For MLABs, you can set the same-port
read-during-write behavior to don’t care and the mixed-port read-during-write
behavior to either don’t care or old data. The available choices depend on the
configuration of the MLAB. There is no “new data” option for MLABs.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–13
Figure 3–10 shows timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the RAM outputs simply
delays the q output by one clock cycle.
Figure 3–10. Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress
an-1
data
din-1
a0
an
a1
a2
a3
din
a4
a5
din4
din5
a6
din6
rdclock
rden
rdaddress
q (asynch)
bn
b1
b0
doutn-1
b2
b3
dout0
doutn
Figure 3–11 shows timing waveforms for read and write operations in mixed-port
mode with unregistered outputs.
Figure 3–11. Mixed-Port Read-During-Write Timing Waveforms
wrclock
wren
wraddress
an-1
data
din-1
a0
an
a1
a2
din
a3
a4
a5
din4
din5
a6
din6
rdclock
rden
rdaddress
q (asynch)
December 2011
bn
doutn-1
Altera Corporation
b0
doutn
b1
b2
b3
dout0
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
True Dual-Port Mode
Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called
bi-directional dual-port, this mode allows you to perform any combination of two
port operations: two reads, two writes, or one read and one write at two different
clock frequencies.
Figure 3–12 shows the true dual-port RAM configuration.
Figure 3–12. Stratix IV True Dual-Port Memory
(1)
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
rden_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
rden_b
aclr_b
q_b[]
Note to Figure 3–12:
(1) True dual-port memory supports input/output clock mode in addition to independent clock mode.
The widest bit configuration of the M9K and M144K blocks in true dual-port mode is
as follows:
■
M9K: 512 × 16-bit (or 512 ×18-bit with parity)
■
M144K: 4K × 32-bit (or 4K ×36-bit with parity)
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers. Table 3–7 lists the possible M9K block mixed-port width
configurations in true dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True Dual-Port Mode)
Write Port
Read Port
Stratix IV Device Handbook
Volume 1
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9 512 × 18
8K × 1
Y
Y
Y
Y
Y
—
—
4K × 2
Y
Y
Y
Y
Y
—
—
2K × 4
Y
Y
Y
Y
Y
—
—
1K × 8
Y
Y
Y
Y
Y
—
—
512 × 16
Y
Y
Y
Y
Y
—
—
1K × 9
—
—
—
—
—
Y
Y
512 × 18
—
—
—
—
—
Y
Y
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
3–15
Table 3–8 lists the possible M144K block mixed-port width configurations in true
dual-port mode.
Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode)
Write Port
Read Port
16K × 8
8K × 16
4K × 32
16K × 9
8K × 18
4K × 36
16K × 8
Y
Y
Y
—
—
—
8K × 16
Y
Y
Y
—
—
—
4K × 32
Y
Y
Y
—
—
—
16K × 9
—
—
—
Y
Y
Y
8K × 18
—
—
—
Y
Y
Y
4K × 36
—
—
—
Y
Y
Y
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”. To choose the desired
behavior, set the read-during-write behavior to either new data or old data in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to “Read-During-Write Behavior” on page 3–19.
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. No conflict resolution circuitry is built into the
Stratix IV TriMatrix memory blocks. You must handle address conflicts external to the
RAM block.
Figure 3–13 shows true dual-port timing waveforms for the write operation at port A
and the read operation at port B, with the read-during-write behavior set to new data.
Registering the RAM’s outputs simply delays the q outputs by one clock cycle.
Figure 3–13. True Dual-Port Timing Waveform
clk_a
wren_a
address_a
an-1
an
data_a
din-1
din
q_a (asynch)
din-1
a0
din
a1
dout0
a2
dout1
a3
dout2
a4
a5
a6
din4
din5
din6
dout3
din4
din5
clk_b
wren_b
address_b
q_b (asynch)
December 2011
bn
doutn-1
Altera Corporation
b0
b1
b2
b3
doutn
dout0
dout1
dout2
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
Shift-Register Mode
All Stratix IV memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for digital signal processing (DSP)
applications, such as finite impulse response (FIR) filters, pseudo-random number
generators, multi-channel filtering, and auto- and cross-correlation functions. These
and other DSP applications require local data storage, traditionally implemented with
standard flipflops that quickly exhaust many logic cells for large shift registers. A
more efficient alternative is to use embedded memory as a shift-register block, which
saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data width (w), the
length of the taps (m), and the number of taps (n). You can cascade memory blocks to
implement larger shift registers.
Figure 3–14 shows the TriMatrix memory block in shift-register mode.
Figure 3–14. Shift-Register Memory Configuration
w x m x n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
n Number of Taps
m-Bit Shift Register
W
W
m-Bit Shift Register
W
Stratix IV Device Handbook
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December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Clocking Modes
3–17
ROM Mode
All Stratix IV TriMatrix memory blocks support ROM mode. A .mif file initializes the
ROM contents of these blocks. The address lines of the ROM are registered on M9K
and M144K blocks, but can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
FIFO Mode
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with
many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the
Quartus II software FIFO MegaWizard Plug-In Manager. Both single- and dual-clock
(asynchronous) FIFO buffers are supported.
f For more information about implementing FIFO buffers, refer to the SCFIFO and
DCFIFO Megafunctions User Guide.
1
MLABs do not support mixed-width FIFO mode.
Clocking Modes
Stratix IV TriMatrix memory blocks support the following clocking modes:
■
“Independent Clock Mode” on page 3–18
■
“Input/Output Clock Mode” on page 3–18
■
“Read/Write Clock Mode” on page 3–18
■
“Single Clock Mode” on page 3–18
c Violating the setup or hold time on the memory block address registers could corrupt
memory contents. This applies to both read and write operations.
Table 3–9 lists which clocking mode/memory mode combinations are supported.
Table 3–9. TriMatrix Memory Clock Modes
True
Dual-Port Mode
Simple
Dual-Port Mode
Single-Port Mode
ROM Mode
FIFO Mode
Independent
Y
—
—
Y
—
Input/output
Y
Y
Y
Y
—
Read/write
—
Y
—
—
Y
Single clock
Y
Y
Y
Y
Y
Clocking Mode
December 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
3–18
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Independent Clock Mode
Stratix IV TriMatrix memory blocks can implement independent clock mode for true
dual-port memories. In this mode, a separate clock is available for each port (clock A
and clock B). Clock A controls all registers on the port A side; clock B controls all
registers on the port B side. Each port also supports independent clock enables for
both port A and port B registers, respectively. Asynchronous clears are supported
only for output latches and output registers on both ports.
Input/Output Clock Mode
Stratix IV TriMatrix memory blocks can implement input/output clock mode for true
dual-port and simple dual-port memories. In this mode, an input clock controls all
registers related to the data input to the memory block including data, address, byte
enables, read enables, and write enables. An output clock controls the data output
registers. Asynchronous clears are available on output latches and output registers
only.
Read/Write Clock Mode
Stratix IV TriMatrix memory blocks can implement read/write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both read and write clocks. Asynchronous clears are
available on data output latches and registers only.
When using read/write clock mode, if you perform a simultaneous read/write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or input/output clock mode
and choose the appropriate read-during-write behavior in the MegaWizard Plug-In
Manager.
Single Clock Mode
Stratix IV TriMatrix memory blocks can implement single-clock mode for true
dual-port, simple dual-port, and single-port memories. In this mode, a single clock,
together with a clock enable, is used to control all registers of the memory block.
Asynchronous clears are available on output latches and output registers only.
Design Considerations
This section describes guidelines for designing with TriMatrix memory blocks.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread memory out
across multiple memory blocks when resources are available to increase the
performance of the design. You can manually assign memory to a specific block size
using the RAM MegaWizard Plug-In Manager.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
3–19
MLABs can implement single-port SRAM through emulation using the Quartus II
software. Emulation results in minimal additional logic resources being used. Because
of the dual-purpose architecture of the MLAB, it only has data input registers and
output registers in the block. MLABs gain input address registers and additional data
output registers from ALMs.
f For more information about register packing, refer to the Logic Array Blocks and
Adaptive Logic Modules in Stratix IV Devices chapter.
Conflict Resolution
When using memory blocks in true dual-port mode, it is possible to attempt two write
operations to the same memory location (address). Because no conflict resolution
circuitry is built into the memory blocks, this results in unknown data being written to
that location. Therefore, you must implement conflict resolution logic external to the
memory block to avoid address conflicts.
Read-During-Write Behavior
You can customize the read-during-write behavior of the Stratix IV TriMatrix memory
blocks to suit your design needs. Two types of read-during-write operations are
available: same port and mixed port. Figure 3–15 shows the difference between the
two types.
Figure 3–15. Stratix IV Read-During-Write Data Flow
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true dual-port
RAM. For MLABs, the output of the MLABs can only be set to don’t care in same-port
read-during-write mode. In this mode, the output of the MLABs is unknown during a
write cycle. There is a window near the falling edge of the clock during which the
output is unknown. Prior to that window, “old data” is read out; after that window,
“new data” is seen at the output.
December 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Figure 3–16 shows sample functional waveforms of same-port read-during-write
behavior in don’t care mode for MLABs.
Figure 3–16. MLABs Same-Port Read-During Write: Don’t Care Mode
clk_a
address
XX
A0
data_in
XX
FFFF
A1
A2
AAAA
XXXX
wrena
q(unregistered)
q(registered)
XX
FFFF
A0(old data)
AAAA
A1(old data)
XX
FFFF
A2(old data)
AAAA
For M9K and M144K memory blocks, three output choices are available in same-port
read-during-write mode: “new data” (or flow-through) or “old data”. In new data
mode, the “new data” is available on the rising edge of the same clock cycle on which
it was written. In old data mode, the RAM outputs reflect the “old data” at that
address before the write operation proceeds. In don’t care mode, the RAM outputs
“unknown values” for a read-during-write operation.
Figure 3–17 shows sample functional waveforms of same-port read-during-write
behavior in new data mode for M9K and M144K blocks.
Figure 3–17. M9K and M144K Blocks Same-Port Read-During-Write: New Data Mode
clk_a
0A
address
0B
rdena
wrena
bytenna
data_a
q_a (asyn)
Stratix IV Device Handbook
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01
10
00
A123
B456
C789
XX23
B423
11
B423
DDDD
EEEE
DDDD
EEEE
FFFF
FFFF
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
3–21
Figure 3–18 shows sample functional waveforms of same-port read-during-write
behavior in old data mode for M9K and M144K blocks.
Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode
clk_a
A0
address
A1
rdena
wrena
01
10
00
A123
B456
C789
bytenna
data_a
A0 (old data) DoldDold23
q_a (asyn)
11
DDDD
B423
EEEE
A1(old data)
FFFF
DDDD
EEEE
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock.
In this mode, you have two output choices if you use the output register: “old data,”
or “don’t care”. With MLABs, you also have the output register “new data.” In old
data mode, a read-during-write operation to different ports causes the RAM outputs
to reflect the “old data” at that address location. In don’t care mode, the same
operation results in a “don’t care” or “unknown” value on the RAM outputs.
f Read-during-write behavior is controlled with the RAM MegaWizard Plug-In
Manager. For more information, refer to the Internal Memory (RAM and ROM) User
Guide.
Figure 3–19 shows a sample functional waveform of mixed-port read-during-write
behavior for old data mode in MLABs.
Figure 3–19. MLABs Mixed-Port Read-During-Write: Old Data Mode
clk_a
wraddress
A0
A1
rdaddress
A0
A1
data_in
AAAA
BBBB
CCCC
DDDD
EEEE
FFFF
01
10
11
01
10
AAAA
AABB
A1(old data)
DDDD
wrena
byteena_a
q_b(registered)
December 2011
Altera Corporation
11
A0 (old data)
DDEE
Stratix IV Device Handbook
Volume 1
3–22
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Figure 3–20 shows a sample functional waveform of mixed-port read-during-write
behavior for don’t care mode in MLABs.
Figure 3–20. MLABs Mixed-Port Read-During-Write: Don’t Care Mode
clk_a
wraddress
A0
A1
rdaddress
A0
A1
data_in
AAAA
BBBB
CCCC
DDDD
EEEE
FFFF
01
10
11
01
10
AAAA
AABB
CCBB
DDDD
DDEE
wrena
byteena_a
11
q_b(registered)
FFEE
Figure 3–21 shows a sample functional waveform of mixed-port read-during-write
behavior for old data mode in M9K and M144K blocks.
Figure 3–21. M9K and M144K Blocks Mixed-Port Read-During Write: Old Data Mode
clk_a&b
wrena
address_a
A1
A0
data_a
AAAA
BBBB
CCCC
bytenna
11
01
10
DDDD
EEEE
FFFF
11
rdenb
address_b
q_b_(asyn)
Stratix IV Device Handbook
Volume 1
A1
A0
A0 (old data)
AAAA
AABB
A1(old data)
DDDD
EEEE
December 2011 Altera Corporation
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
3–23
Figure 3–22 shows a sample functional waveform of mixed-port read-during-write
behavior for don’t care mode in M9K and M144K blocks.
Figure 3–22. M9K and M144K Blocks Mixed-Port Read-During Write: Don’t Care Mode
clk_a&b
wrena
A0
address_a
A1
data_a
AAAA
BBBB
CCCC
bytenna
11
01
10
DDDD
EEEE
FFFF
11
rdenb
address_b
q_b_(asyn)
A0
A1
XXXX (unknown data)
Mixed-port read-during-write is not supported when two different clocks are used in
a dual-port RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
Power-Up Conditions and Memory Initialization
M9K memory cells are initialized to all zeros through a default .mif file in the
Quartus II software. However, you may specify your own initialization of the
memory cells through a defined .mif file. M144K memory cells are not initialized and;
therefore, come up in an undefined state. This is to prevent the programming file from
being too large. Again, you may specify your own initialization of the memory cells
through a defined .mif file.
MLABs power up to zero if output registers are used and power up reading the
memory contents if output registers are not used. You must take this into
consideration when designing logic that might evaluate the initial power-up values of
the MLAB memory block. For Stratix IV devices, the Quartus II software initializes
the RAM cells to zero unless there is a .mif file specified.
As mentioned, all memory blocks support initialization using a .mif file. You can
create .mif files in the Quartus II software and specify their use with the RAM
MegaWizard Plug-In Manager when instantiating a memory in your design. Even if a
memory is pre-initialized (for example, using a .mif file), it still powers up with its
outputs cleared.
f For more information about .mif files, refer to the Internal Memory (RAM and ROM)
User Guide and the Quartus II Handbook.
December 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
3–24
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Power Management
Stratix IV memory block clock-enables allow you to control clocking of each memory
block to reduce AC power consumption. Use the read-enable signal to ensure that
read operations only occur when you need them to. If your design does not need
read-during-write, you can reduce your power consumption by de-asserting the
read-enable signal during write operations, or any period when no memory
operations occur.
The Quartus II software automatically places any unused memory blocks in
low-power mode to reduce static power.
Document Revision History
Table 3–10 lists the revision history for this chapter.
Table 3–10. Document Revision History
Date
Version
December 2011
February 2011
March 2010
November 2009
June 2009
April 2009
3.3
3.2
3.1
3.0
Changes
■
Updated the “Byte Enable Support” and “Mixed-Port Read-During-Write Mode” sections.
■
Updated Table 3–1.
■
Updated the “Byte Enable Support” and “Power-Up Conditions and Memory Initialization”
sections.
■
Applied new template.
■
Minor text edits.
■
Updated the “Simple Dual-Port Mode”, “Same-Port Read-During-Write Mode”, and
“Mixed-Port Read-During-Write Mode” sections.
■
Updated Figure 3–14.
■
Minor text edits.
■
Updated Table 3–2.
■
Updated the “Simple Dual-Port Mode” section.
■
Minor text edits.
■
Updated graphics.
■
Updated Table 3–1 and Figure 3–2.
■
Updated the “Introduction”, “Byte Enable Support”, “Mixed Width Support”,
“Asynchronous Clear”, “Single-Port RAM”, “Simple Dual-Port Mode”, “True Dual-Port
Mode”, “FIFO Mode”, and “Read/Write Clock Mode” sections.
■
Added introductory sentences to improve search ability.
■
Removed the Conclusion section.
■
Minor text edits.
■
Updated Table 3–2.
■
Updated Table 3–2.
■
Removed “Referenced Documents” section.
2.3
2.2
March 2009
2.1
November 2008
2.0
Updated “Power-Up Conditions and Memory Initialization” on page 3–20
May 2008
1.0
Initial release.
Stratix IV Device Handbook
Volume 1
December 2011 Altera Corporation
4. DSP Blocks in Stratix IV Devices
February 2011
SIV51004-3.1
SIV51004-3.1
This chapter describes how the Stratix® IV device digital signal processing (DSP)
blocks are optimized to support DSP applications requiring high data throughput,
such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, and encoders. You can configure the DSP blocks to
implement one of several operational modes to suit your application. The built-in
shift register chain, multipliers, and adders/subtractors minimize the amount of
external logic to implement these functions, resulting in efficient resource usage and
improved performance and data throughput for DSP applications.
Many complex systems, such as WiMAX, 3GPP WCDMA, high-performance
computing (HPC), voice over Internet protocol (VoIP), H.264 video compression,
medical imaging, and HDTV use sophisticated digital signal processing techniques,
which typically require a large number of mathematical computations. Stratix IV
devices are ideally suited for these tasks because the DSP blocks consist of a
combination of dedicated elements that perform multiplication, addition, subtraction,
accumulation, summation, and dynamic shift operations.
Along with the high-performance Stratix IV soft logic fabric and TriMatrix memory
structures, you can configure DSP blocks to build sophisticated fixed-point and
floating-point arithmetic functions. These can be manipulated easily to implement
common, larger computationally intensive subsystems such as FIR filters, complex
FIR filters, IIR filters, FFT functions, and discrete cosine transform (DCT) functions.
This chapter contains the following sections:
■
“Stratix IV DSP Block Overview” on page 4–2
■
“Stratix IV Simplified DSP Operation” on page 4–4
■
“Stratix IV Operational Modes Overview” on page 4–8
■
“Stratix IV DSP Block Resource Descriptions” on page 4–9
■
“Stratix IV Operational Mode Descriptions” on page 4–15
■
“Software Support” on page 4–36
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
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February 2011
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4–2
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Overview
Stratix IV DSP Block Overview
Each Stratix IV device has two to seven columns of DSP blocks that implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions efficiently. Architectural highlights of the Stratix IV DSP block include:
■
High-performance, power optimized, fully registered, and pipelined
multiplication operations
■
Natively supported 9-, 12-, 18-, and 36-bit wordlengths
■
Natively supported 18-bit complex multiplications
■
Efficiently supported floating-point arithmetic formats (24-bit for single precision
and 53-bit for double precision)
■
Signed and unsigned input support
■
Built-in addition, subtraction, and accumulation units to combine multiplication
results efficiently
■
Cascading 18-bit input bus to form the tap-delay line for filtering applications
■
Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
■
Rich and flexible arithmetic rounding and saturation units
■
Efficient barrel shifter support
■
Loopback capability to support adaptive filtering
Table 4–1 lists the number of DSP blocks for the Stratix IV device family.
Family
Stratix IV E
Stratix IV GX
DSP Blocks
Table 4–1. Number of DSP Blocks in Stratix IV Devices (Part 1 of 2)
Device
Independent Input and Output Multiplication Operators
High-Precision
Multiplier
Adder Mode
Four
Multiplier
Adder
Mode
9×9
Multipliers
12 × 12
Multipliers
18 × 18
Multipliers
18 × 18
Complex
36 × 36
Multipliers
18 × 36
Multipliers
18 × 18
Multipliers
EP4SE230
161
1,288
966
644
322
322
644
1288
EP4SE360
130
1,040
780
520
260
260
520
1040
EP4SE530
128
1,024
768
512
256
256
512
1024
EP4SE820
120
960
720
480
240
240
480
960
EP4SGX70
48
384
288
192
96
96
192
384
EP4SGX110
64
512
384
256
128
128
256
512
EP4SGX180
115
920
690
460
230
230
460
920
EP4SGX230
161
1,288
966
644
322
322
644
1288
EP4SGX290
104
832
624
416
208
208
416
832
EP4SGX360
(1)
130
1,040
780
520
260
260
520
1,040
EP4SGX360
(2)
128
1,024
768
512
256
256
512
1,024
128
1,024
768
512
256
256
512
1,024
EP4SGX530
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Overview
4–3
Family
DSP Blocks
Table 4–1. Number of DSP Blocks in Stratix IV Devices (Part 2 of 2)
Device
Stratix IV GT
Independent Input and Output Multiplication Operators
High-Precision
Multiplier
Adder Mode
Four
Multiplier
Adder
Mode
9×9
Multipliers
12 × 12
Multipliers
18 × 18
Multipliers
18 × 18
Complex
36 × 36
Multipliers
18 × 36
Multipliers
18 × 18
Multipliers
EP4S40G2
161
1,288
966
644
322
322
644
1,288
EP4S40G5
128
1,024
768
512
256
256
512
1,024
EP4S100G2
161
1,288
966
644
322
322
644
1,288
EP4S100G3
104
832
624
416
208
208
416
832
EP4S100G4
128
1,024
768
512
256
256
512
1,024
EP4S100G5
128
1,024
768
512
256
256
512
1,024
Notes to Table 4–1:
(1) This is applicable for all packages in EP4SGX360 except F1932.
(2) This is applicable for EP4SGX360F1932 only.
Table 4–1 shows that the largest Stratix IV DSP-centric device provides up to 1288
18 × 18 multiplier functionality in the 36 × 36, complex 18 × 18, and summation
modes.
Each DSP block occupies four LABs in height and can be divided further into two half
blocks that share some common clock signals, but are for all common purposes
identical in functionality. Figure 4–1 shows the layout of each DSP block.
Figure 4–1. Overview of DSP Block Signals
34
Control
144
Input
Data
Half-DSP Block
72
Output
Data
72
Output
Data
288
144
Half-DSP Block
Full DSP Block
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
Stratix IV Simplified DSP Operation
In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit
multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in
Equation 4–1 and Figure 4–2.
1
All signed numbers, input, and output data are represented in 2’s-complement format
only.
Equation 4–1. Multiplier Equation
P[36..0] = A0[17..0] × B0[17..0] ± A1[17..0] × B1[17..0]
Figure 4–2. Basic Two-Multiplier Adder Building Block
A0[17..0]
B0[17..0]
+/A1[17..0]
D
Q
B1[17..0]
D
Q
P[36..0]
The structure shown in Figure 4–2 is useful for building more complex structures,
such as complex multipliers and 36 × 36 multipliers, as described in later sections.
Each Stratix IV DSP block contains four two-multiplier adder units (2 two-multiplier
adder units per half block). Therefore, there are eight 18 × 18 multiplier functionalities
per DSP block.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
4–5
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions per half block, as shown in Equation 4–2 and
Equation 4–3.
Equation 4–2. Four-Multiplier Adder Equation
Z[37..0] = P0[36..0] + P1[36..0]
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
Wn[43..0] = Wn-1[43..0] ± Zn[37..0]
In these equations, n denotes sample time and P[36..0] denotes the result from the
two-multiplier adder units.
Equation 4–2 provides a sum of four 18 × 18-bit multiplication operations
(four-multiplier adder). Equation 4–3 provides a four 18 × 18-bit multiplication
operation but with a maximum 44-bit accumulation capability by feeding the output
of the unit back to itself, as shown in Figure 4–3.
Depending on the mode you select, you can bypass all register stages except
accumulation and loopback mode. In these two modes, one set of registers must be
enabled. If the register set is not enabled, an infinite loop occurs.
Output Register Bank
Adder/
Accumulator
144
Pipeline Register Bank
Input
Data
Input Register Bank
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
44
Result[]
Half-DSP Block
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
To support commonly found FIR-like structures efficiently, a major addition to the
DSP block in Stratix IV devices is the ability to propagate the result of one half block
to the next half block completely within the DSP block without additional soft logic
overhead. This is achieved by the inclusion of a dedicated addition unit and routing
that adds the 44-bit result of a previous half block with the 44-bit result of the current
block. The 44-bit result is either fed to the next half block or out of the DSP block using
the output register stage, as shown in Figure 4–4. Detailed examples are described in
later sections.
The combination of a fast, low-latency four-multiplier adder unit and the “chained
cascade” capability of the output chaining adder provides the optimal FIR and vector
multiplication capability.
To support single-channel type FIR filters efficiently, you can configure one of the
multiplier input’s registers to form a tap delay line input, saving resources and
providing higher system performance.
Figure 4–4. Output Cascading Feature for FIR Structures
From Previous Half DSP Block
Half DSP Block
Output Register Bank
Round/Saturate
Adder/
Accumulator
144
Pipeline Register Bank
Input
Data
Input Register Bank
44
44
Result[]
44
To Next
Half DSP Block
Also shown in Figure 4–4 is the optional rounding and saturation unit (RSU). This
unit provides a rich set of commonly found arithmetic rounding and saturation
functions used in signal processing.
In addition to the independent multipliers and sum modes, you can use DSP blocks to
perform shift operations. DSP blocks can dynamically switch between logical shift
left/right, arithmetic shift left/right, and rotation operation in one clock cycle.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
4–7
Figure 4–5 shows a top-level view of the Stratix IV DSP block.
Figure 4–6 on page 4–9 shows a more detailed top-level view of the DSP block.
Figure 4–5. Stratix IV Full DSP Block
From Previous
Half DSP Block
Output Multiplexer
Round/Saturate
Output Register Bank
Output Multiplexter
Round/Saturate
Output Register Bank
Adder/Accumulator
144
Pipeline Register Bank
Input
Data
Input Register Bank
44
Result[]
Top Half DSP Block
Adder/Accumulator
144
Pipeline Register Bank
Input
Data
Input Register Bank
44
Result[]
Bottom Half DSP Block
To Next Half DSP Block
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Modes Overview
Stratix IV Operational Modes Overview
You can use each Stratix IV DSP block in one of five basic operational modes.
Table 4–2 lists the five basic operational modes and the number of multipliers that you
can implement within a single DSP block, depending on the mode.
Table 4–2. Stratix IV DSP Block Operation Modes
Multiplier
in Width
# of
Mults
# per
Block
Signed or
Unsigned
RND,
SAT
In Shift
Register
Chainout
Adder
1st Stage
Add/Sub
2nd
Stage
Add/Acc
9 bits
1
8
Both
No
No
No
—
—
12 bits
1
6
Both
No
No
No
—
—
18 bits
1
4
Both
Yes
Yes
No
—
—
36 bits
1
2
Both
No
No
No
—
—
Double
1
2
Both
No
No
No
—
—
Two-Multiplier
Adder (1)
18 bits
2
4
Signed
Yes
No
No
Both
—
Four-Multiplier
Adder
18 bits
4
2
Both
Yes
Yes
Yes
Both
Add Only
Multiply
Accumulate
18 bits
4
2
Both
Yes
Yes
Yes
Both
Both
1
2
Both
No
No
—
—
—
2
2
Both
No
No
No
—
Add Only
Mode
Independent
Multiplier
Shift
(2)
High Precision
Multiplier Adder
36 bits
(3)
1836
(4)
Notes to Table 4–2:
(1) This mode also supports loopback mode. In loopback mode, the number of loopback multipliers per DSP block is two. You can use the
remaining multipliers in regular two-multiplier adder mode.
(2) Dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, and rotation operation.
(3) Dynamic shift mode operates on a 32-bit input vector but the multiplier width is configured as 36 bits.
(4) Unsigned value is also supported but you must ensure that the result can be contained within 36 bits.
The DSP block consists of two identical halves (the top half and bottom half). Each
half has four 18 × 18 multipliers.
The Quartus® II software includes megafunctions used to control the mode of
operation of the multipliers. After making the appropriate parameter settings using
the megafunction’s MegaWizard Plug-In Manager, the Quartus II software
automatically configures the DSP block.
Stratix IV DSP blocks can operate in different modes simultaneously. Each half block
is fully independent except for the sharing of the three clock, ena, and aclr signals.
For example, you can break down a single DSP block to operate a 9 × 9 multiplier in
one half block and an 18 × 18 two-multiplier adder in the other half block. This
increases DSP block resource efficiency and allows you to implement more
multipliers within a Stratix IV device. The Quartus II software automatically places
multipliers that can share the same DSP block resources within the same block.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
4–9
Stratix IV DSP Block Resource Descriptions
The DSP block consists of the following elements:
■
Input register bank
■
Four two-multiplier adders
■
Pipeline register bank
■
Two second-stage adders
■
Four rounding and saturation logic units
■
Second adder register and output register bank
Figure 4–6 shows a detailed overall architecture of the top half of the DSP block.
Table 4–9 on page 4–35 shows a list of DSP block dynamic signals.
Figure 4–6. Half DSP Block Architecture
clock[3..0]
ena[3..0]
alcr[3..0]
chainin[ ] (3)
signa
signb
output_round
output_saturate
rotate
shift_right
zero_loopback
accum_sload
zero_chainout
chainout_round
chainout_saturate
overflow (1)
chainout_sat_overflow (2)
scanina[ ]
datab_3[ ]
Multiplexer
Shift/Rotate
Output Register Bank
Second Round/Saturate
Chainout Adder
Second Adder Register Bank
dataa_3[ ]
First Round/Saturate
datab_2[ ]
Second Stage Adder/Accumulator
dataa_2[ ]
Pipeline Register Bank
datab_1[ ]
Input Register Bank
datab_0[ ]
dataa_1[ ]
First Stage Adder
loopback
First Stage Adder
dataa_0[ ]
result[ ]
Half-DSP Block
scanouta
chainout
Notes to Figure 4–6:
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) The chainin port must only be connected to chainout of the previous DSP blocks and must not be connected to general routings.
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Stratix IV DSP Block Resource Descriptions
Input Registers
All of the DSP block registers are triggered by the positive edge of the clock signal and
are cleared after power up. Each multiplier operand can feed an input register or go
directly to the multiplier, bypassing the input registers. The following DSP block
signals control the input registers within the DSP block:
■
clock[3..0]
■
ena[3..0]
■
aclr[3..0]
Every DSP block has nine 18-bit data input register banks per half DSP block. Every
half DSP block has the option to use the eight data register banks as inputs to the four
multipliers. The special ninth register bank is a delay register required by modes that
use both the cascade and chainout features of the DSP block. Use the ninth register
bank to balance the latency requirements when using the chained cascade feature.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
4–11
A feature of the input register bank is to support a tap delay line. Therefore, the top
leg of the multiplier input (A) can be driven from general routing or from the cascade
chain, as shown in Figure 4–7. Table 4–9 on page 4–35 lists the DSP block dynamic
signals.
Figure 4–7. Input Register of a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
scanina[17..0]
dataa_0[17..0]
loopback
datab_0[17..0]
+/-
dataa_1[17..0]
datab_1[17..0]
dataa_2[17..0]
datab_2[17..0]
+/-
dataa_3[17..0]
datab_3[17..0]
Delay
Register
scanouta
At compile time, you must select whether the A-input comes from general routing or
from the cascade chain. In cascade mode, the dedicated shift outputs from one
multiplier block and directly feeds the input registers of the adjacent multiplier below
it (within the same half DSP block) or the first multiplier in the next half DSP block, to
form an 8-tap shift register chain per DSP Block. The DSP block can increase the
length of the shift register chain by cascading to the lower DSP blocks. The dedicated
shift register chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing resources.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
Shift registers are useful in DSP functions such as FIR filters. When implementing
18 × 18 or smaller width multipliers, you do not need external logic to create the shift
register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in Stratix IV
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to
select between general routing and loopback, as shown in Figure 4–6 on page 4–9. In
loopback mode, the most significant 18-bit registered outputs are connected as
feedback to the multiplier input of the first top multiplier in each half DSP block.
Loopback modes are used by recursive filters where the previous output is needed to
compute the current output.
Loopback mode is described in “Two-Multiplier Adder Sum Mode” on page 4–23.
Table 4–3 lists input register modes for the DSP block.
Table 4–3. Input Register Modes
Register Input Mode
(1)
Parallel input
Shift register input
Loopback input
(2)
(3)
9×9
12 × 12
18 × 18
36 × 36
Double
Y
Y
Y
Y
Y
—
—
Y
—
—
—
—
Y
—
—
Notes to Table 4–3:
(1) Multiplier operand input wordlengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per half block. For more information, refer to Figure 4–15 on page 4–25.
Multiplier and First-Stage Adder
The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers.
Other wordlengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 would be padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page 4–15. Depending on the data width of the
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number. Table 4–4 lists the sign of the
multiplication result for the various operand sign representations. The result of the
multiplication is signed if any one of the operands is a signed value.
Table 4–4. Multiplier Sign Representation
Stratix IV Device Handbook
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Data A (signa Value)
Data B (signb Value)
Result
Unsigned (logic 0)
Unsigned (logic 0)
Unsigned
Unsigned (logic 0)
Signed (logic 1)
Signed
Signed (logic 1)
Unsigned (logic 0)
Signed
Signed (logic 1)
Signed (logic 1)
Signed
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Stratix IV DSP Block Resource Descriptions
4–13
Each half block has its own signa and signb signal. Therefore, all of the data A inputs
feeding the same half DSP block must have the same sign representation. Similarly, all
of the data B inputs feeding the same half DSP block must have the same sign
representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 × 18 loopback and
two-multiplier adder modes. For more information, refer to “Two-Multiplier Adder
Sum Mode” on page 4–23.
1
By default, when the signa and signb signals are unused, the Quartus II software sets
the multiplier to perform unsigned multiplication.
Figure 4–6 on page 4–9 shows that the outputs of the multipliers are the only outputs
that can feed into the first-stage adder. There are four first-stage adders in a DSP block
(two adders per half DSP block). The first-stage adder block has the ability to perform
addition and subtraction. The control signal for addition or subtraction is static and
has to be configured after compile time. The first-stage adders are used by the sum
modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operations.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, rounding and saturation unit, or
output registers.
Pipeline Register Stage
Figure 4–6 on page 4–9 shows that the output from the first-stage adder can either
feed or bypass the pipeline registers. Pipeline registers increase the DSP block’s
maximum performance (at the expense of extra cycles of latency), especially when
using the subsequent DSP block stages. Pipeline registers split up the long signal path
between the input registers/multiplier/first-stage adder and the second-stage adder/
round-and-saturation/output registers, creating two shorter paths.
Second-Stage Adder
There are four individual 44-bit second-stage adders per DSP block (two adders
per half DSP block). You can configure the second-stage adders as follows:
1
■
The final stage of a 36-bit multiplier
■
A sum of four (18 × 18)
■
An accumulator (44-bits maximum)
■
A chained output summation (44-bits maximum)
You can use the chained-output adder at the same time as a second-level adder in
chained output summation mode.
The output of the second-stage adder has the option to go into the rounding and
saturation logic unit or the output register.
1
February 2011
You cannot use the second-stage adder independently from the multiplier and
first-stage adder.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
Rounding and Saturation Stage
The rounding and saturation logic units are located at the output of the 44-bit
second-stage adder (the rounding logic unit followed by the saturation logic unit).
There are two rounding and saturation logic units per half DSP block. The input to the
rounding and saturation logic unit can come from one of the following stages:
■
Output of the multiplier (independent multiply mode in 18 × 18)
■
Output of the first-stage adder (two-multiplier adder)
■
Output of the pipeline registers
■
Output of the second-stage adder (four-multiplier adder and multiply-accumulate
mode in 18 × 18)
These stages are described in “Stratix IV Operational Mode Descriptions” on
page 4–15.
The rounding and saturation logic unit is controlled by the dynamic rounding and
saturate signals, respectively. A logic 1 value on the rounding and/or saturate
signals enables the rounding and/or saturate logic unit, respectively.
1
You can use the rounding and saturation logic units together or independently.
Second Adder and Output Registers
The second adder register and output register banks are two banks of 44-bit registers
that you can combine to form larger 72-bit banks to support 36 × 36 output results.
The outputs of the different stages in the Stratix IV devices are routed to the output
registers through an output selection unit. Depending on the operational mode of the
DSP block, the output selection unit selects whether the outputs of the DSP blocks
comes from the outputs of the multiplier block, first-stage adder, pipeline registers,
second-stage adder, or the rounding and saturation logic unit. The output selection
unit is set automatically by the software, based on the DSP block operational mode
you specified, and has the option to either drive or bypass the output registers. The
exception is when you use the block in shift mode, in which case you dynamically
control the output-select multiplexer directly.
When the DSP block is configured in chained cascaded output mode, both of the
second-stage adders are used. Use the first one for performing a four-multiplier
adder; use the second for the chainout adder.
The outputs of the four-multiplier adder are routed to the second-stage adder
registers before they enter the chainout adder. The output of the chainout adder goes
to the regular output register bank. Depending on the configuration, you can route
the chainout results to the input of the next half block’s chainout adder input or to the
general fabric (functioning as regular output registers). For more information, refer to
“Stratix IV Operational Mode Descriptions” on page 4–15.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–15
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared after power up. The following DSP block signals control the
output registers within the DSP block:
■
clock[3..0]
■
ena[3..0]
■
aclr[3..0]
Stratix IV Operational Mode Descriptions
This section contains an explanation of different operational modes in Stratix IV
devices.
Independent Multiplier Modes
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers.
9-, 12-, and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A
single DSP block can support up to eight individual 9 × 9 multipliers, six individual
12 × 12 multipliers, or four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs. Figure 4–8, Figure 4–9, and Figure 4–10 show the DSP block in
the independent multiplier operation. Table 4–9 on page 4–35 lists the dynamic
signals for the DSP block.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–8. 18-Bit Independent Multiplier Mode Shown for a Half DSP Block
signa
clock[3..0]
signb
overflow (1)
Pipeline Register Bank
18
dataa_1[17..0]
Input Register Bank
18
datab_0[17..0]
18
datab_1[17..0]
36
result_0[ ]
Output Register Bank
18
dataa_0[17..0]
Round/Saturate
output_round
output_saturate
Round/Saturate
ena[3..0]
aclr[3..0]
36
result_1[ ]
Half-DSP Block
Note to Figure 4–8:
(1) Block output for accumulator overflow and saturate overflow.
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–17
Figure 4–9. 12-Bit Independent Multiplier Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
12
dataa_0[11..0]
24
result_0[ ]
12
Output Register Bank
12
datab_1[11..0]
Pipeline Register Bank
12
dataa_1[11..0]
Input Register Bank
datab_0[11..0]
24
result_1[ ]
12
dataa_2[11..0]
24
result_2[ ]
12
datab_2[11..0]
Half-DSP Block
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–10. 9-Bit Independent Multiplier Mode Shown for a Half Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
9
dataa_0[8..0]
18
result_0[ ]
9
datab_0[8..0]
9
dataa_1[8..0]
Output Register Bank
9
dataa_2[8..0]
Pipeline Register Bank
9
datab_1[8..0]
Input Register Bank
18
result_1[ ]
18
result_2[ ]
9
datab_2[8..0]
9
dataa_3[8..0]
18
result_3[ ]
9
datab_3[8..0]
Half-DSP Block
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
can register the signals in the DSP block. Additionally, the multiplier inputs and
results can be registered independently. You can use the pipeline registers within the
DSP block to pipeline the multiplier result, increasing the performance of the DSP
block.
1
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The rounding and saturation logic unit is supported for 18-bit independent multiplier
mode only.
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–19
36-Bit Multiplier
You can efficiently construct a 36 × 36 multiplier using four 18 × 18 multipliers. This
simplification fits conveniently into one half DSP block and is implemented in the
DSP block automatically by selecting 36 × 36 mode. Stratix IV devices can have up to
two 36-bit multipliers per DSP block (one 36-bit multiplier per half DSP block). The
36-bit multiplier is also under the independent multiplier mode but uses the entire
half DSP block, including the dedicated hardware logic after the pipeline registers to
implement the 36 × 36 bit multiplication operation, as shown in Figure 4–11.
The 36-bit multiplier is useful for applications requiring more than 18-bit precision;
for example, for the mantissa multiplication portion of single precision and extended
single precision floating-point arithmetic applications.
Figure 4–11. 36-Bit Independent Multiplier Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
dataa_0[35..18]
datab_0[35..18]
datab_0[17..0]
+
Output Register Bank
dataa_0[35..18]
Input Register Bank
datab_0[35..18]
Pipeline Register Bank
+
dataa_0[17..0]
72
result[ ]
+
dataa_0[17..0]
datab_0[17..0]
Half-DSP Block
February 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
4–20
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Double Multiplier
You can configure the Stratix IV DSP block to efficiently support a signed or unsigned
54 × 54-bit multiplier that is required to compute the mantissa portion of an IEEE
double-precision floating point multiplication. You can build a 54 × 54-bit multiplier
using basic 18 × 18 multipliers, shifters, and adders. In order to efficiently use the
Stratix IV DSP block’s built-in shifters and adders, a special double mode (partial
54 × 54 multiplier) is available that is a slight modification to the basic 36 × 36
multiplier mode, as shown in Figure 4–12 and Figure 4–13.
Figure 4–12. Double Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
dataa_0[35..18]
datab_0[35..18]
datab_0[17..0]
+
Output Register Bank
dataa_0[35..18]
Input Register Bank
datab_0[35..18]
Pipeline Register Bank
+
dataa_0[17..0]
72
result[ ]
+
dataa_0[17..0]
datab_0[17..0]
Half-DSP Block
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–21
Figure 4–13. Unsigned 54 × 54 Multiplier for a Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
"0"
"0"
dataa[53..36]
signa
signb
Two Multiplier
Adder Mode
+
36
datab[53..36]
dataa[35..18]
Double Mode
55
datab[35..18]
dataa[53..36]
datab[17..0]
dataa[35..18]
Final Adder (implemented with ALUT logic)
datab[53..36]
dataa[53..36]
Shifters and Adders
datab[53..36]
dataa[17..0]
108
result[ ]
36 x 36 Mode
datab[35..18]
dataa[35..18]
Shifters and Adders
datab[35..18]
dataa[17..0]
72
datab[17..0]
dataa[17..0]
datab[17..0]
Unsigned 54 X 54 Multiplier
February 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
4–22
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Two-Multiplier Adder Sum Mode
In a two-multiplier adder configuration, the DSP block can implement four 18-bit
two-multiplier adders (2 two-multiplier adders per half DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs. You must
select summation or subtraction at compile time. The two-multiplier adder function
is useful for applications such as FFTs, complex FIR, and IIR filters. Figure 4–14 on
page 4–24 shows the DSP block configured in two-multiplier adder mode.
Loopback mode is the other sub-feature of the two-multiplier adder mode.
Figure 4–15 on page 4–25 shows the DSP block configured in the loopback mode. This
mode takes the 36-bit summation result of the two multipliers and feeds back the
most significant 18-bits to the input. The lower 18-bits are discarded. You have the
option to disable or zero-out the loopback data by using the dynamic zero_loopback
signal. A logic 1 value on the zero_loopback signal selects the zeroed data or
disables the looped back data, while a logic 0 selects the looped back data.
1
You must select the option to use loopback mode or the general two-multiplier adder
mode at compile time.
For two-multiplier adder mode, if all the inputs are full 18-bit and unsigned, the result
requires 37 bits. As the output data width in two-multiplier adder mode is limited to
36 bits, this 37-bit output requirement is not allowed. Any other combination that
does not violate the 36-bit maximum result is permitted; for example, two 16 × 16
signed two-multiplier adders is valid.
Two-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–23
Figure 4–14. Two-Multiplier Adder Mode Shown for a Half DSP Block
signa
clock[3..0]
ena[3..0]
aclr[3..0]
signb
output_round
output_saturate
overflow (1)
Output Register Bank
Round/Saturate
dataa_1[17..0]
+
Pipeline Register Bank
datab_0[17..0]
Input Register Bank
dataa_0[17..0]
result[ ]
datab_1[17..0]
Half-DSP Block
Note to Figure 4–14:
(1) Block output for accumulator overflow and saturate overflow.
February 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
4–24
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–15. Loopback Mode for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
zero_loopback
overflow (1)
Output Register Bank
dataa_1[17..0]
+
Round/Saturate
datab_0[17..0]
Pipeline Register Bank
loopback
Input Register Bank
dataa_0[17..0]
result[ ]
datab_1[17..0]
Half-DSP Block
Note to Figure 4–15:
(1) Block output for accumulator overflow and saturate overflow.
18 x 18 Complex Multiply
You can configure the DSP block to implement complex multipliers using
two-multiplier adder mode. A single half DSP block can implement one 18-bit
complex multiplier.
Equation 4–4 shows a complex multiplication.
Equation 4–4. Complex Multiplication Equation
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j((a × d) + (b × c))
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–25
To implement this complex multiplication within the DSP block, the real part
((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block
while the imaginary part ((a × d) + (b × c)) is implemented using another two
multipliers feeding an adder block. Figure 4–16 shows an 18-bit complex
multiplication. This mode automatically assumes all inputs are using signed
numbers.
Figure 4–16. Complex Multiplier Using Two-Multiplier Adder Mode
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
A
C
36
AxC BxD
Real Part
Output Register Bank
Pipeline Register Bank
D
Input Register Bank
B
36
AxD
BxC
Imaginary Part
Half-DSP Block
February 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Four-Multiplier Adder
In the four-multiplier adder configuration shown in Figure 4–17, the DSP block can
implement two four-multiplier adders (one four-multiplier adder per half DSP block).
These modes are useful for implementing one-dimensional and two-dimensional
filtering applications. The four-multiplier adder is performed in two addition stages.
The outputs of two of the four multipliers are initially summed in the two first-stage
adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown
by Equation 4–2 on page 4–5 and Equation 4–3 on page 4–5.
Figure 4–17. Four-Multiplier Adder Mode Shown for a Half DSP Block
signa
signb
clock[3..0]
ena[3..0]
aclr[3..0]
output_round
output_saturate
overflow (1)
dataa_0[ ]
datab_0[ ]
+
Output Register Bank
+
Round/Saturate
dataa_2[ ]
Input Register Bank
datab_1[ ]
Pipeline Register Bank
dataa_1[ ]
result[ ]
datab_2[ ]
+
dataa_3[ ]
datab_3[ ]
Half-DSP Block
Note to Figure 4–17:
(1) Block output for accumulator overflow and saturate overflow.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
4–27
Four-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
High-Precision Multiplier Adder Mode
In a high-precision multiplier adder configuration, shown in Figure 4–18 on
page 4–29, the DSP block can implement 2 two-multiplier adders, with multiplier
precision of 18 x 36 (one two-multiplier adder per half DSP block). This mode is useful
in filtering or FFT applications where a data path greater than 18 bits is required, yet
18 bits is sufficient for the coefficient precision. This can occur where the data has a
high dynamic range. If the coefficients are fixed, as in FFT and most filter applications,
the precision of 18 bits provide a dynamic range over 100 dB, if the largest coefficient
is normalized to the maximum 18-bit representation.
In these situations, the data path can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision. This mode is
also extremely useful in single precision block floating point applications.
The high-precision multiplier adder is performed in two stages. The 18 × 36 multiply
is divided into two 18 × 18 multipliers. The multiplier with the LSB of the data source
is performed unsigned, while the multiplier with the MSB of the data source can be
signed or unsigned. The latter multiplier has its result left shifted by 18 bits prior to
the first adder stage, creating an effective 18 x 36 multiplier. The results of these two
adder blocks are then summed in the second stage adder block to produce the final
result:
Z[54..0] = P0[53..0] + P1[53..0]
where:
P0 = A[17..0] × B[35..0]
P1 = C[17..0] × D[35..0]
February 2011
Altera Corporation
Stratix IV Device Handbook
Volume 1
4–28
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–18. High-Precision Multiplier Adder Configuration
signa
signb
clock[3..0]
ena[3..0]
aclr[3..0]
overflow (1)
dataA[0:17]
dataB[0:17]
Pipeline Register Bank
dataC[0:17]
Input Register Bank
dataB[18:35]
P0
). For example, and
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