Cyclone® III Development Kit
User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
P25-36208-01
Document Date:
October 2007
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Part Number UG-01027-1.0
ii
Cyclone III Development Kit
User Guide0
Altera Corporation
October 2007
Contents
Chapter 1. About This Kit
Introduction ............................................................................................................................................ 1–1
Kit Features ............................................................................................................................................. 1–1
Documentation ....................................................................................................................................... 1–3
Chapter 2. Getting Started
Introduction ............................................................................................................................................
Before You Begin ...................................................................................................................................
Check the Kit Contents ....................................................................................................................
Inspect the Board ..............................................................................................................................
Hardware Requirements .................................................................................................................
Software Requirements ...................................................................................................................
Further Information ..............................................................................................................................
2–1
2–1
2–1
2–2
2–2
2–3
2–3
Chapter 3. Software Installation
Installing the Development Kit CD-ROM ..........................................................................................
Installing the Quartus II DVD ..............................................................................................................
Installing the USB-Blaster™ Driver ....................................................................................................
Licensing Considerations .....................................................................................................................
3–1
3–2
3–3
3–4
Chapter 4. Development Board Setup
Introduction ............................................................................................................................................
Requirements .........................................................................................................................................
Powering Up the Board ........................................................................................................................
Configuring the FPGA ..........................................................................................................................
4–1
4–1
4–1
4–4
Chapter 5. Design Tutorials
My First FPGA Tutorial ........................................................................................................................ 5–1
My First Nios Software Tutorial .......................................................................................................... 5–1
Chapter 6. Measuring Power
Introduction ............................................................................................................................................
Power Design Example .........................................................................................................................
Measuring Power ...................................................................................................................................
A/D Measurements .........................................................................................................................
Measuring Voltage with a DMM ...................................................................................................
Calculating Power ............................................................................................................................
Changing the Design Example ............................................................................................................
Altera Corporation
6–1
6–1
6–3
6–3
6–5
6–5
6–6
iii
Preliminary
Contents
Cyclone III Development Kit
Appendix A. Programming the Flash Device
Overview ................................................................................................................................................ A–1
Creating a Flash File ............................................................................................................................. A–1
Parallel Flash Loader Instantiation .................................................................................................... A–3
Programming the Flash Device .......................................................................................................... A–4
Restoring the Factory Design to the Flash Device ........................................................................... A–6
Additional Information
Revision History ............................................................................................................................... Info–i
How to Contact Altera ..................................................................................................................... Info–i
Typographic Conventions ............................................................................................................... Info–i
iv
Preliminary
Altera Corporation
1. About This Kit
Introduction
Welcome to the Altera® Cyclone® III Development Kit, which includes a
full-featured field-programmable gate array (FPGA) development board,
hardware and software development tools, documentation, and
accessories needed to begin FPGA development.
The kit provides an integrated control environment that includes a USB
command controller, a multi-port SRAM/DDR SDRAM/flash memory
controller, Ethernet, an on-board current meter, and an example design
with demonstration circuitry specified in Verilog code to help you get
started quickly with your own designs.
The development board includes an Altera Cyclone III FPGA configured
with a hardware reference design stored in flash memory. Hardware
designers can use the development board, along with example designs
included in the kit, as a platform to prototype complex embedded
systems.
The development kit includes these kit features and documentation:
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■
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Kit Features
This section briefly describes the Cyclone III Development Kit features.
■
f
Altera Corporation
October 2007
The Cyclone III development board
Altera Complete Design Suite DVD containing:
●
Quartus® II Web Edition Software
●
MegaCore® IP Library
●
Nios® II Embedded Software Design Tools
Cyclone III Development Kit CD-ROM
Design examples
Accessory daughter cards
Power supply, cables, and documentation
The Cyclone III Development Board—a prototyping platform that
allows you to develop and prototype high-speed bus interfaces as
well as evaluate Cyclone III transceiver performance.
For specific information about board components and interfaces, refer to
the Cyclone III Development Board Reference Manual.
User Guide
1–1
Cyclone III Development Kit
Kit Features
■
f
Quartus II Web Edition Software—The Quartus II software
(available on the DVD) integrates into nearly any design
environment, with interfaces to industry-standard EDA tools. The
kit includes:
●
The SOPC Builder system development tool
●
Free Quartus II Web Edition software license, Windows
platform only
For more information, refer to the Altera website at
http://www.altera.com/products/software/products/quartus2web/
sof-quarwebmain.html.
■
MegaCore IP Library—This library (available on the DVD) contains
Altera IP MegaCore functions. You can evaluate MegaCore functions
by using the OpenCore® Plus feature to do the following:
●
Simulate behavior of a MegaCore function within your system
●
Verify functionality of your design, and quickly and easily
evaluate its size and speed
●
Generate time-limited device programming files for designs that
include MegaCore functions
●
Program a device and verify your design in hardware
■
Nios II Embedded Software Design Tools—This full-featured set of
tools (available on the DVD) allows you to develop embedded
software on the Nios II processor running on Altera FPGAs.
■
Cyclone III Development Kit Application & Drivers—The
application and drivers (available on the CD-ROM) allow you to
execute memory read and write transactions to the board.
■
Design Examples—The design examples (available on the
CD-ROM) are useful for a variety of hardware applications and let
you quickly begin board prototyping and device verification.
You only need to purchase a license for a MegaCore function when you
are completely satisfied with its functionality and performance, and want
to take your design to production.
1
1–2
Cyclone III Development Kit
The OpenCore Plus hardware evaluation feature is an
evaluation tool for prototyping only. You must purchase a
license to use a MegaCore function in production.
User Guide
Preliminary
Altera Corporation
October 2007
About This Kit
Documentation
The Cyclone III Development Kit CD-ROM contains the following
documents:
■
■
■
Altera Corporation
October 2007
Readme file—Contains special instructions and refers to the kit
documentation.
Cyclone III Development Kit User Guide (this document) —
Describes how to use the kit.
Cyclone III Development Board Reference Manual—Provides
specific information about the board components and interfaces,
steps for using the board, and pin-outs and signal specifications.
User Guide
1–3
Documentation
1–4
Cyclone III Development Kit
User Guide
Preliminary
Altera Corporation
October 2007
2. Getting Started
Introduction
This user guide familiarizes you with the contents of the kit and guides
you through the Cyclone III development board setup. Using this guide,
you can do the following:
■
■
■
■
■
■
■
■
f
Before You
Begin
Inspect the contents of the kit
Install the Altera Development Suite Tools
Set up licensing
Install the Cyclone III Development Kit CD-ROM
Set up, power up, and verify correct operation of the development
board
Configure the Cyclone III FPGA
Find and use the tutorials
Set up and run included application examples and demonstrations.
For complete details on the development board, refer to the
Cyclone III Development Board Reference Manual.
Before using the kit or installing the software, check the kit contents and
inspect the board to verify that you received all of the items listed in this
section. If any of the items are missing, contact Altera before you proceed.
Check the Kit Contents
The Cyclone III Development Kit (ordering code: DK-DEV-3C120N)
contains the following items:
■
■
■
Altera Corporation
October 2007
Cyclone III development board with an EP3C120F780C7N
Cyclone III device
Altera Complete Design Suite DVD containing:
●
Quartus II Web Edition Software
●
MegaCore IP Library
●
Nios II Embedded Software Design Tools
Cyclone III Development Kit CD-ROM, which includes:
●
References design and demonstrations
●
Cyclone III development kit application and device drivers
●
Design examples
●
Cyclone III Development Board Reference Manual
●
Cyclone III Development Kit User Guide (this document)
●
Device datasheets and tutorials
●
Schematic and board design files
User Guide
2–1
Cyclone III Development Kit
Before You Begin
■
■
■
1
USB cable
Accessory daughter cards:
●
Two loopback high-speed mezzanine connector (HSMC) cards
●
Debug HSMC card
●
One 16 character x 2 line Liquid Crystal Display (LCD)
●
One 2.8 in. thin-film transistor (TFT) LCD module
16 V DC Power supply and adapters for North America, Europe, the
United Kingdom, and Japan.
To ensure that you have the most up-to-date information on this
product, go to the Altera website at www.altera.com/products
/devkits/altera/kit-cyc3-Development.html
Inspect the Board
Place the board on an anti-static surface and inspect it to ensure that it has
not been damaged during shipment.
w
Without proper anti-static handling, the Cyclone III
development board can be damaged.
Verify that all components are on the board and appear intact.
1
f
In typical applications with the Cyclone III development board,
a heatsink is not necessary. However, under extreme conditions
the board may require additional cooling to stay within
operating temperature guidelines. You may wish to perform
power consumption and thermal modeling to determine
whether your application requires additional cooling.
For more information on power consumption and thermal modeling,
refer to AN 358: Thermal Management for FPGAs at the Altera website
at http://www.altera.com/literature/an/an358.pdf
Hardware Requirements
The Quartus II software has some minimum system requirements.
Otherwise, the Cyclone III development kit provides all of the hardware
needed to use the board.
f
2–2
Cyclone III Development Kit
For the Quartus II requirements, refer to the Altera website at
http://www.altera.com/products/software/products/quartus2web/
sof-quarwebmain.html for details.
User Guide
Altera Corporation
October 2007
Getting Started
Software Requirements
This kit requires the following software:
■
■
Windows XP operating system
Quartus II Web Edition software version 7.2 or later.
1
f
Refer to the Quartus II Installation & Licensing for Windows document for
further information on the Quartus II system software requirements,
especially heeding the following:
1
Further
Information
Although it is already available on the DVD included in the kit,
you can also download the Quartus II software from the Altera
website at http://www.altera.com/products/software/
products/quartus2web/sof-quarwebmain.html.
●
A web browser, Microsoft Internet Explorer version 5.0 or later
or Firefox version 2.0 or later. You need a web browser to register
the Quartus II software and request license files. Refer to
“Licensing Considerations” on page 3–4.
●
Version 2.0 or later of the .NET framework.
If you receive an “Application Error” message when
launching the demo application, please install version 2.0 or
later versions of the .NET framework. Some Windows versions
do not have runtime DLL for the .NET application. The .NET
framework application can be downloaded from the following
location: http://www.microsoft.com/download.
For other related information, refer to the following websites:
■
For additional daughter cards available for purchase:
www.altera.com/products/devkits/kit-daughter_boards.jsp
■
For the Cyclone III handbook:
www.altera.com/literature/lit-cyc3.jsp
■
For the Cyclone III reference designs:
www.altera.com/
endmarkets/refdesigns/device/cyclone3/cyclone3-index.jsp
■
Altera Corporation
October 2007
For eStore if you want to purchase devices:
User Guide
2–3
Cyclone III Development Kit
Further Information
www.altera.com/buy/devices/buy-devices.html
■
For Cyclone III Orcad symbols:
www.altera.com/support/software/download/pcb/
pcb-pcb_index.html
■
For Nios II 32-bit embedded processor solutions:
www.altera.com/technology/embedded/emb-index.html
2–4
Cyclone III Development Kit
User Guide
Altera Corporation
October 2007
3. Software Installation
The instructions in this section explain how to install the following:
■
■
■
1
Installing the
Development Kit
CD-ROM
Cyclone III Development Kit CD-ROM
Cyclone III Development Kit demo application and drivers
The Quartus II Web Edition Software DVD, including MegaCore
functions from the MegaCore IP Library
Before starting the installation, verify that you have complied
with the conditions described in “Software Requirements” on
page 2–3.
The Cyclone III Development Kit CD-ROM contains the following items:
■
■
■
■
■
■
The sample design and board design files
Quick Start Guide
My First FPGA Tutorial
My First Nios Tutorial
Cyclone III Development Kit User Guide (this document)
Cyclone III Development Board Reference Manual
To install the Cyclone III Development Kit CD-ROM, perform the
following steps:
1.
Insert the Cyclone III Development Kit CD-ROM into the CD-ROM
drive.
1
2.
The CD-ROM should start an auto-install process. If it does
not, browse to the CD-ROM drive and double-click on the
setup.exe file.
Follow the online instructions to complete the installation process.
The installation program copies the Cyclone III development kit files to
the computer hard disk and creates an icon labeled Programs > Altera >
Cyclone III Development Kit accessible from the Windows
Start menu. Use this icon to launch the development kit graphical user
interface (GUI).
Altera Corporation
October 2007
User Guide
3–1
Cyclone III Development Kit
Installing the Quartus II DVD
When the installation is complete, the Cyclone III Development Kit
installation program creates the directory structure shown in Figure 3–1,
where is the Cyclone III Development Kit installation directory.
Figure 3–1. Cyclone III Development Kit Installed Directory Structure
The default Windows installation directory is C:\altera\\kits.
cycloneIII_3c120_dev
board_design_files
documents
examples
Table 3–1 lists the file directory names and a description of their contents.
Table 3–1. Installed Directory Contents
Directory Name
Description of Contents
board_design_files
Contains schematic, layout, assembly, and bill of material board design files. Use
these files as a starting point for a new prototype board design.
documents
Contains the development kit documentation
examples
Contains the sample design files for the Cyclone III Development Kit
Installing the
Quartus II DVD
The Quartus II software is the primary FPGA development tool used to
create the reference designs used in this development kit.
Additionally, you may want to install the Nios II Embedded Design Suite
found in the Altera Complete Design Suite at
https://www.altera.com/support/software/download/nios2/dnlnios2.jsp. The Nios II soft-core embedded processor runs on Altera
FPGAs. Some of the reference designs included in this development kit
use the Nios II processor.
Load the Altera Complete Design Suite DVD into the DVD player, and
click on Install free package on the startup screen (Figure 3–2). Follow
the on-screen instructions and accept all defaults. After installing the
software, request and install a license to enable it.
3–2
Cyclone III Development Kit
User Guide
Altera Corporation
October 2007
Software Installation
f
For information on obtaining a license file, refer to “Licensing
Considerations” on page 3–4.
1
During installation of the Quartus II software, choose to install
the MegaCore IP Library when presented the option and follow
the on-screen instructions.
Figure 3–2. Quartus II Installation from DVD
Installing the
USB-Blaster™
Driver
Altera Corporation
October 2007
The Cyclone III development board includes integrated USB-Blaster
circuitry for FPGA programming. However, for the host computer and
development board to communicate, you must install the USB-Blaster
driver on the host computer.
User Guide
3–3
Cyclone III Development Kit
Licensing Considerations
f
Licensing
Considerations
To download the USB-Blaster driver, refer to the Altera support site at
http://www.altera.com/support/software/drivers/dri-index.html.
To install it, refer to the USB-Blaster Driver for Windows XP site at
http://www.altera.com/support/software/drivers/usb-blaster/driusb-blaster-xp.html.
Before using the Quartus II software, you must request a license file from
the Altera web site at www.altera.com/licensing and install it on your
computer. When you request a license file, Altera emails you a license.dat
file that enables the software.
1
3–4
Cyclone III Development Kit
To license the Quartus II software, you need your network
interface card (NIC) ID, a 12-digit hexadecimal number that
identifies your computer. Networked (or floating-node)
licensing requires a NIC ID or server host ID. When obtaining a
license file for network licensing, use the NIC ID from the
computer that will issue the Quartus II licenses to distributed
users over a network. You can find the NIC ID for your card by
typing "ipconfig /all" at a command prompt. Your NIC ID
is the number on the physical address line, without the dashes.
User Guide
Altera Corporation
October 2007
4. Development Board Setup
Introduction
The instructions in this section explain how to install the development
board and configure the FPGA.
Requirements
Before starting the installation, verify that you have complied with the
conditions described in “Hardware Requirements” on page 2–2 and have
completed the following requirements:
■
■
1
Powering Up the
Board
Altera Corporation
October 2007
Quartus II software installed on the host computer
USB-Blaster driver software installed on the host computer.
The Cyclone III development board includes integrated
USB-Blaster circuitry for FPGA programming. Host computer
and development board can not communicate without the
USB-Blaster driver software installed. For installation
information, refer to “Installing the USB-Blaster™ Driver” on
page 3–3.
Figure 4–1 shows the Cyclone III development board and its components.
User Guide
4–1
Cyclone III Development Kit
Powering Up the Board
Figure 4–1. Cyclone III Development Board Layout and Components
DDR2TOP_ACTIVE
LED (D11)
Cyclone III FPGA (U20)
Power
LED (D5)
DC Power
Power
Switch (SW2) Jack (J2)
DDR2 SDRAM Device Interface
Four x16 and one x8
(U11, U12, U25, U26, U13)
(Three on Top and Two on Bottom)
MAX II CPLD (U7)
MAX II Device
Control DIP
Switch (SW1)
24 MHz Crystal (Y1)
Ethernet PHY
LEDs (D1, D3, D4)
6 MHz
Crystal (Y2)
JTAG Control
DIP Switch (SW3)
Ethernet PHY
Duplex LED (D6)
Device Select
Jumper (J6)
Ethernet PHY TX/RX
Activity LEDS (D7, D8)
24 MHz USBBlaster Clock (Y3)
Speaker Header (J5)
125 MHz
Clock (Y4)
50 MHz
Clock (Y5)
HSMC Port B (J9)
(Debug Header Shown)
HSMC Port A (J8)
(Loopback Board Shown)
SRAM Active
LED (D17)
Clock Out SMA (J11)
Clock In SMA (J10)
HSMC Port A
Present LED (D18)
HSMC Port B
Present LED (D19)
Power Select
Rotary Switch (SW4)
PGM Config Select
Rotary Switch (SW5)
Board-Specific LEDs
(D20 through D24)
User DIP
Switch (SW6)
User Push Buttons
(S1 through S4)
Power Display (U28)
Configuration
Done LED (D25)
Graphics
LCD (J13)
User LEDs
(D26 through D33)
Flash Active
LED (D23)
Reset and
Factory
Configuration
Push Buttons
(S6 and S7)
User Defined
7-Segment
Display (U30)
CPU Reset Push
Button Switch (S5)
DDR2BOT_ACTIVE
LED (D16)
Before powering up, prepare the board as follows:
4–2
Cyclone III Development Kit
1.
If cards are plugged into the HSMC ports, remove them (Figure 4–1
shows a daughter card plugged into both port A and port B.)
2.
Ensure that the POWER switch SW2 is in the OFF (or DOWN)
position.
User Guide
Altera Corporation
October 2007
Development Board Setup
3.
Configure the 8-position SW1 DIP switch to the default settings in
Table 4–1.
Table 4–1. Switch SW1 Settings
Function
Switch
Name
Position 0
Default
Position
Position 1
1
mW/mA
2
V/W
mW
mA
0
V
W
1
3
RSV0
MAX_RESERVE0
X
4
RSV1
MAX_RESERVE1
X
5
MAX0
PFL Disable PFL Enable
1
6
MAX1
MAX_DIP1
X
7
MAX2
MAX_DIP2
X
8
MAX3
MAX_DIP3
X
Note to Table 4–1:
(1)
X = don’t care
4.
Ensure that the 4-position SW3 mini-DIP switches and the two
jumpers are set to the default positions shown in Table 4–2.
Table 4–2. Initial Switch and Jumper Settings
DEV_SEL-J6 JTAG_SEL-J7 SW3.1 SW3.2 SW3.3 SW3.4
ON
5.
ON
ON
OFF
OFF
OFF
Verify that the PGM CONFIG SELECT rotary switch SW5 is set to 0.
At power up, the development board uses a preloaded configuration to
demonstrate that the board is operating correctly.
Power up the development board by performing the following steps:
1.
w
2.
Altera Corporation
October 2007
Connect the 16 V DC adapter to the development board and to a
power source.
Only use the supplied 16 V power supply. Power regulation
circuitry on the board could be damaged by supplies greater
than 16 V.
Slide the POWER switch to ON. The nearby blue POWER
light-emitting diode (LED) lights up.
User Guide
4–3
Cyclone III Development Kit
Configuring the FPGA
3.
Confirm that user LEDs 0-7 flash in a scrolling, side-to-side pattern.
For customized configurations, the pattern depends on the
application.
f
For information about custom configurations, refer to “Programming the
Flash Device” on page A–4
Configuring the
FPGA
Before configuring the FPGA, ensure that the Quartus II software and the
USB-Blaster driver software are installed on the host computer and the
development board is powered on.
f
For USB-Blaster driver installation information, refer to “Installing the
USB-Blaster™ Driver” on page 3–3.
To configure the Cyclone III FPGA, perform the following steps:
4–4
Cyclone III Development Kit
1.
Verify that the 4-position SW3 mini-DIP switches and the two
jumpers are set to the default positions shown in Table 4–2.
2.
Connect the USB cable to the development board USB port.
3.
Cycle the POWER switch OFF then ON.
4.
Start the Quartus II software.
5.
On the Tools menu, click Programmer. The Quartus II Programmer
appears (Figure 4–2).
User Guide
Altera Corporation
October 2007
Development Board Setup
Figure 4–2. Quartus II Programmer
Altera Corporation
October 2007
6.
Click Add File and select
\...\examples\cycloneIII_3c120_dev_my_first_fpga
\cycloneIII_3c120_dev_my_first_fpga.sof.
7.
Click the Program/Configure box to select the added file.
8.
Click Start to download the selected file to the FPGA. The FPGA is
configured when the progress bar reaches 100%.
9.
Confirm that user LEDs 0-3 flash in a slow binary counting pattern.
User Guide
4–5
Cyclone III Development Kit
Configuring the FPGA
4–6
Cyclone III Development Kit
User Guide
Altera Corporation
October 2007
5. Design Tutorials
The example designs and tutorials included in the Cyclone III
Development Kit help familiarize new users with development board
features. My First FPGA Tutorial and My First Nios Tutorial provide
step-by-step guidance for the first-time user.
My First FPGA
Tutorial
My First FPGA Tutorial describes how to create a simple Altera FPGA
design. The tutorial takes less than an hour to complete and provides an
overview of the design flow using Quartus II to build a simple logic
counter which drives LEDs to flash on the development board.
After installing the Cyclone III Development Kit CD-ROM, the My First
FPGA Tutorial design and documentation can be found at path>\...
\documents\tutorials\hardware_tutorials\my_first_fpga_tutorial.pdf.
My First Nios
Software
Tutorial
My First Nios Tutorial introduces the basic system development flow for
the Nios II processor. This tutorial provides a good starting point if you
are new to the Nios II processor or to the general concept of using an
embedded processor in an FPGA. In this tutorial, you use a standard,
existing Nios II hardware system and create a software program to
run on it.
After installing the Cyclone III Development Kit CD-ROM, the My First
Nios SW Tutorial design and documentation can be found at
path>\...\documents\tutorials\software_tutorials
\my_first_nios2_software_tutorial.pdf.
Altera Corporation
October 2007
User Guide
5–1
Cyclone III Development Kit
My First Nios Software Tutorial
5–2
Cyclone III Development Kit
User Guide
Altera Corporation
October 2007
6. Measuring Power
Introduction
One of the main features of the Cyclone III FPGA device is its low power
consumption. You can measure the power used by the 3C120 FPGA
device on the Cyclone III development board for various conditions with
a power design example provided with the kit.
With the power design example you can control the amount of logic
utilized in the FPGA, the clock frequency, and the number of I/Os used,
and measure the effect on power use by the Cyclone III device.
Power Design
Example
The power design example uses a replicated module, stamp.v, that
contains combinational logic, randomly filled ROMs, multiplier blocks,
and shift registers that change with every clock cycle. The frequency and
resource states indicated in Table 6–2 and Table 6–3 on page 6–2 represent
the percent of full design used. As compiled, the full example design uses
the following FPGA resources:
■
■
■
■
■
■
■
■
Logic elements: 113,849 / 119,088 (96%)
Combinational functions: 14,422 / 119,088 (12%)
Dedicated logic registers: 104,192 / 119,088 (87%)
Total registers: 104,192
Total pins: 165 / 532 (31%)
Total memory bits: 2,490,368 / 3,981,312 (63%)
Embedded Multiplier 9-bit elements: 576 / 576 (100%)
Total PLLs: 1/4 (25%)
Table 6–1 describes the functionality of the four user push buttons that
control the power design example. The on-board 50 MHz oscillator
provides the input clock (i_clk, PIN_AH15).
Table 6–1. Four Input Button Functionality
User Push
Button
FPGA Pin
Type
Description
User_PB0
AD7
Reset
Resets the demo to the beginning, i_nrst
User_PB1
AC12
Toggle
Advances the design example to the next higher frequency,
i_nfreq_next
User_PB2
AH3
Toggle
Advances the design example to the next higher resource
utilization, i_nperc_next
User_PB3
AA12
Toggle
Enables the outputs to toggle, i_noutput_ena
Altera Corporation
October 2007
User Guide
6–1
Cyclone III Development Kit
Power Design Example
The LEDs in Table 6–2 indicate the power-state values of the design
example as User_PB1 advances frequency.
Table 6–2. Power State Indicators for Frequency
LED1 (AE20)
LED0 (AD15)
Frequency (MHz)
0
0
0
0
1
33
1
0
67
1
1
100
The LEDs in Table 6–3 indicate the power-state values of the design
example (and number of output pins, when enabled by User_PB3) as
User_PB2 advances resource utilization.
Table 6–3. Power State Indicators for Resources
LED6 LED5 LED4 LED3 LED2 Resources Number of
(AG19) (AC17 (AE15) (AD19 (AF18)
(%)
Outputs
6–2
Cyclone III Development Kit
0
0
0
0
0
5
8
0
0
0
0
1
10
16
0
0
0
1
0
15
24
0
0
0
1
1
20
32
0
0
1
0
0
25
40
0
0
1
0
1
30
48
0
0
1
1
0
35
56
0
0
1
1
1
40
64
0
1
0
0
0
45
72
0
1
0
0
1
50
80
0
1
0
1
0
55
88
0
1
0
1
1
60
96
0
1
1
0
0
65
104
0
1
1
0
1
70
112
0
1
1
1
0
75
120
0
1
1
1
1
80
128
1
0
0
0
0
85
136
1
0
0
0
1
90
144
1
0
0
1
0
95
152
User Guide
Altera Corporation
October 2007
Measuring Power
The resource state (Table 6–3) controls the number of I/O pins used. Each
resource increment adds 8 additional I/O pins (Table 6–3). Similarly, the
overall design frequency (Table 6–2) sets the toggle frequency of these
I/O pins.
Measuring
Power
You can measure power by using the analog-to-digital (A/D) circuitry on
the development board or by using a digital multimeter (DMM) across
on-board sense resistors. However, note that, depending on the DMM
accuracy, the on-board A/D measurements tend to produce considerably
more accurate results.
A/D Measurements
The POWER SELECT rotary switch SW4 sets the development board to
measure and display FPGA core power or I/O output power (Table 6–4).
Table 6–4. Switch SW4 Power Selection
Switch Position
FPGA Power
I/O Banks
0
Core: VCC_INT, 1.2 V
5
I/O: 2.5 V
1 and 2
6
I/O: 2.5 V
5 and 6
—
Measuring Core Power
To measure FPGA core power at VCC_INT=1.2 V for various power
states, perform the following steps:
Altera Corporation
October 2007
1.
Ensure that the 8-position SW1 DIP switch is configured to the
default settings shown in Table 4–1 on page 4–3.
2.
Download the cycloneIII_dev_powerdemo.sof file as described in
“Configuring the FPGA” on page 4–4. You can find the power
design example in the
path>\...\examples\cycloneIII_3c120_dev_powerdemo directory.
3.
Set the POWER SELECT rotary switch SW4 to 0 to measure the
internal VCC_INT power in watts.
4.
Observe the power on the 4-digit hexadecimal power display.
5.
Using the user input push buttons (Table 6–1 on page 6–1), advance
through the power states in Table 6–2 and Table 6–3 on page 6–2.
Notice how power increases as frequency and resources increase.
User Guide
6–3
Cyclone III Development Kit
Measuring Power
Measuring I/O Power
This example uses FPGA I/O banks 1, 2, 5, and 6. Using the SW4 settings
(Table 6–4), measure the power for I/O banks 1 and 2, then for I/O banks
5 and 6, by performing the following steps:
1.
Ensure that the 8-position SW1 DIP switch is configured to the
default settings shown in Table 4–1 on page 4–3.
2.
Download the cycloneIII_dev_powerdemo.sof file as described in
“Configuring the FPGA” on page 4–4. You can find the power
design example in the
path>\...\examples\cycloneIII_3c120_dev_powerdemo directory.
3.
Set the POWER SELECT rotary switch SW4 to 5.
4.
Observe the 4-digit hexadecimal display for the I/O output power
in watts on banks 1 and 2.
5.
Using the user input push buttons (Table 6–1 on page 6–1), advance
through the power states in Table 6–2 and Table 6–3 on page 6–2.
Notice how power increases as frequency and resources increase.
6.
Press the User_PB3 button to enable the output pins on the HSMC
connectors J8 and J9. LED7 (AF19), signal o_noutput_ena_state,
lights to indicate that the outputs are enabled and toggling.
Enabling the outputs further increases power for each resource
utilization percentage used by the Cyclone III FPGA.
7.
Press the User_PB3 button again to disable the outputs. LED7 turns
off.
8.
Set the POWER SELECT rotary switch SW4 to 6.
9.
Repeat steps 4 through 7 to observe the I/O output power in watts
on banks 5 and 6.
The sum of power results from the two sets of I/O banks provides the
total FPGA I/O power.
f
6–4
Cyclone III Development Kit
For specific information about on-board measurements and the POWER
SELECT rotary switch, refer to the Cyclone III Development Board Reference
Manual located in the documents directory (refer to Figure 3–1 on
page 3–2).
User Guide
Altera Corporation
October 2007
Measuring Power
Measuring Voltage with a DMM
To obtain power values by using a DMM, measure voltage across the
sense-resistors, R49, R48, and R51on the board, then use the voltage
measurements to calculate power.
1
For best results, use a DMM with six-digit or greater accuracy.
FPGA I/O power is distributed by banks (Table 6–5), for which the sense
resistors are components R48 and R51. For the I/O power calculation, use
the sum of voltage measurements across these resistors while outputs are
enabled. For the FPGA core power calculation, measure the sense resistor
voltage across R49.
Table 6–5. Sense Resistors
FPGA Power
I/O
Voltage
Sense Resistor
Resistor Value
Banks 1 and 2
2.5 V
R48
0.009 Ω
Banks 5 and 6
2.5 V
R51
0.009 Ω
1.2 V
R49
0.009 Ω
Core: VCC_INT
Calculating Power
To obtain the power P in watts, measure the voltage across the sense
resistors, VSENSE, and calculate the nominal power as follows:
If
VSENSE
ISENSE
VSUPPLY
RSENSE
= Voltage measured across the sense resistor
= Current through the sense resistor
= FPGA supply voltage
= Sense resistor value in Table 6–5.
then
V SUPPLY × V SENSE
P = VI = V SUPPLY × I SENSE = ------------------------------------------------R SENSE
where
VSUPPLY is 1.2 V for the FPGA core and 2.5 V for FPGA I/O.
Voltage measurements on the DMM should increase as frequency and
resource utilization increases according to Table 6–2 and Table 6–3 on
page 6–2.
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October 2007
User Guide
6–5
Cyclone III Development Kit
Changing the Design Example
Changing the
Design Example
The development kit includes source code for the Cyclone III power
design example so you can use it as a starting point for your own
measurements.
The design example uses 19 stamp.v modules, each with 8 outputs, for
a total of 152 output pins. It assigns the pins selected as outputs to the
HSMC connectors J8 and J9.
To change the number of outputs, modify the design example and assign
the pins appropriately.
1
6–6
Cyclone III Development Kit
Power should track linearly with frequency and percentage
resources. If you observe superlinear power measurements,
some temperature issue may be the cause.
User Guide
Altera Corporation
October 2007
Appendix A. Programming the
Flash Device
Overview
There is a Common Flash Interface (CFI) type flash memory device on the
Cyclone III development board. When you first receive the kit, this CFI
flash device arrives programmed with a default factory configuration
that was loaded from a Programmer Object File (POF).
When you power up the board, the CFI flash device configures the FPGA
with the default factory configuration using Passive Serial (PS)
programming. If the configuration loaded correctly, the user LEDs on the
board flash sequentially from side to side.
As you develop your own project using the Altera tools, you may wish to
program the flash device so that, upon power up, it loads the FPGA with
your own design. Or you may wish to restore the default factory
configuration to your board.
This appendix describes how to program the flash device. You can load
an existing design from a POF, but if your design exists on an SRAM
Object File (SOF), then first you must convert the SOF to a POF.
Programming the flash device also requires the use of the Altera Parallel
Flash Loader (PFL). Using this appendix, you can do the following:
■
■
■
■
Creating a Flash
File
Create a flash file by converting an SOF to POF
Install the PFL
Use the Quartus II programmer to write a POF to the flash device
Restore the default factory configuration
To create a flash-programmable configuration POF, perform the
following steps:
1.
From the main Quartus II menu, choose Convert Programming
Files... in the File menu.
2.
In the Convert Programming Files... window, select the parameter
values as shown:
Programming File Type: Programmer Object File (.pof)
Configuration Device: CFI_512MB
Mode: 1-bit Passive Serial
File Name:
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October 2007
User Guide
A–1
Cyclone III Development Kit
Creating a Flash File
1
(This is the default file name. Change this to the file name you
wish to use for your application. Save the file in the
< path>\...\examples\cycloneIII_3c120_dev_pfl directory)
Memory Map File: selected (default)
3.
f
For more information regarding option bits and Page Mode
Implementation of memory, refer to AN 386: Using the Parallel Flash
Loader with the Quartus II Software.
4.
1
A–2
Cyclone III Development Kit
Click Options… In the Options window, enter 0x3FE0000 then
select OK. This sets the option bit base address for the development
kit to the required default, 0x3FE0000. The option bit sector stores
the start address for each page of memory and also stores the Page
Valid bits. The Page Valid bits indicate whether each page is
successfully programmed.
Choose the SOF file you want to convert by selecting the row
labeled SOF Data in the Input files to convert area, click the Add
File... button, browse to and select the file you wish to convert, and
click OK. Figure A–1 shows the Convert Programming Files
window updated with the factory image your_design_name.sof.
If you choose to overwrite an existing POF file, you will receive
a warning message.
User Guide
Altera Corporation
October 2007
Figure A–1. Convert Programming Files Settings
5.
Click Generate. Generation takes about 15 seconds confirmed by a
“Generated… pof successfully” message.
You now have a successfully generated POF that can be programmed to
the flash device to automatically configure the FPGA on your Cyclone III
development board.
Parallel Flash
Loader
Instantiation
The development kit includes a PFL megafunction design,
cycloneIII_3c120_dev_pfl, in the < path>\...\examples directory.
Quartus use the PFL to write programming files to the flash device, which
then loads the FPGA at power up.
To write to a flash device, you must first program the PFL into the FPGA
by using the Quartus II software as described in “Programming the Flash
Device” on page A–4, steps 1 through 8.
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October 2007
User Guide
A–3
Cyclone III Development Kit
Programming the Flash Device
f
Programming
the Flash Device
For more information about the PFL megafunction, refer to AN 386:
Using the Parallel Flash Loader with the Quartus II Software.
To program the flash device on the development board, you must have
first created a POF flash file as described in “Creating a Flash File” on
page A–1. In the following procedure, you first program the PFL into the
FPGA, then use the PFL to write the POF flash file into the flash device.
To download a configuration bit stream into the flash device, perform the
following steps:
A–4
Cyclone III Development Kit
1.
Ensure that the POWER switch SW2 is in the OFF (or DOWN)
position.
2.
Verify the switch SW3 and jumper settings shown in Table 4–2 on
page 4–3.
3.
Connect the USB cable to the USB port on the board.
4.
Cycle the POWER switch OFF then ON.
5.
From the Quartus II menu, choose Tools >Programmer.
6.
Click Add File and select <
path>\...\examples\cycloneIII_3C120_dev_pfl\cycloneIII_3C120
_dev_pfl.sof.
7.
Click the Program/Configure box to select the added file.
8.
Click Start to download the selected configuration file to FPGA
(Figure A–2). Configured when the progress bar reaches 100%, the
FPGA is ready to access and program the flash device.
User Guide
Altera Corporation
October 2007
Figure A–2. PFL Programming
9.
Click Auto Detect. The EP3C120 device and a child CFI_512MB
device appear in the list of devices to be programmed.
10. Double-click the File> field of the CFI_512MB row. This
opens a Select New programming File window. Choose the desired
POF, in this example the .pof flash file you created
earlier, and click Open.
11. Select the Program/Configure checkboxes that correspond to the
CFI_512MB device for Page_0 and OPTION_BITS (Figure A–3). This
results in writes only to the flash page zero and the option bit
register.
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October 2007
User Guide
A–5
Cyclone III Development Kit
Restoring the Factory Design to the Flash Device
Figure A–3. Program/Configure Checkboxes
12. Click Start. The message window details the flash writing progress
to successful completion. Flash writing to one page, as in this case,
can take five to six minutes.
You have now successfully programmed the flash device with a
configuration for your board. To configure the board from the flash
device, power cycle the board as described in “Powering Up the Board”
on page 4–1.
Powering on the board causes the flash device to load a new
configuration into the FPGA device. The CONF DONE LED lights up and
the hardware functions associated with the design take effect.
Restoring the
Factory Design
to the Flash
Device
A–6
Cyclone III Development Kit
To restore the development board to factory conditions, repeat the steps
for writing a new POF to the flash device as described in “Programming
the Flash Device” on page A–4, except select the
cycloneIII_3c120_dev_factory_recovery.pof file.
User Guide
Altera Corporation
October 2007
Additional Information
Revision History
Chapter
All
Date
October 2007
How to Contact
Altera
The table below displays the revision history for the chapters in this user
guide.
Version
1.0.0
Changes Made
First publication
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
custrain@altera.com
Product literature
Website
www.altera.com/literature
Altera literature services
Email
literature@altera.com
Non-technical support (General)
Email
nacomp@altera.com
(Software Licensing) Email
authorization@altera.com
Note to table:
(1)
Typographic
Conventions
Visual Cue
You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
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Typographic Conventions Stratix II GX EP2GX90 Signal Integrity Development Board Reference Manual
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Italic type
Meaning
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: , .pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
w
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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