Data SheeT
Intel® Enpirion® Power Solutions
ED8401 Digital Multi-Phase Controller
Multi Phase, Single Output, Fully Digital Step-down Controller with PMBusTM
v1.2 Compliant Interface
Description
Features
The ED8401 is a true digital multi-phase step-down
controller for non-isolated, high current DC/DC
applications. A PMBus version 1.2 compliant
interface provides setup, control, and telemetry.
•
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•
•
Differential remote sensing and ±0.5% set-point
accuracy provides precise regulation over line, load
and temperature variation to provide excellent
static regulation for today’s FPGAs, ASICs,
processors, and DDR memory devices.
The ED8401 can be configured and controlled in
any application by two methods, either in pin-strap
mode using onboard resistors, or using the PMBUS
interface. The customer can also configure the
device during engineering evaluation using the
PMBUS interface, which offers a high degree of
flexibility and programmability, and then use the pin
strap mode when devices are deployed in
production. The Intel Enpirion Digital Power
Configurator provides a user-friendly and easy-touse interface for communicating with and
configuring the device.
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The ED8401 offers a scalable solution by operating
in 4, 3, or 2 phase mode. Combined with the Intel
Enpirion ET6160LI power stage, this enables an
optimized load current range to greater than 200A.
•
•
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Programmable digital control loops
All Phases actively current balanced
Tracking pin for complex power sequencing
Vin Feed-forward
Individual Tmon input for each Phase
Meets all high-performance FPGA requirements
o Digital loop for excellent transient response
o 0.5% set-point over line, load, temperature
o Differential remote sensing
o Monotonic startup into pre-bias output
o Optimized FPGA configs stored in NVM
Programmable through PMBus
o VOUT margining, startup and shutdown delays
o Programmable warnings, faults and response
Operational without PMBus
o RVSET resistor for setting VOUT
o RTUNE resistor for single resistor-based
compensation
Programmable Overcurrent Response
o Latch Off (default)
o Hiccup
Protection features
o Over-Current Protection
o Over Voltage protection VIN VOUT
o Under Voltage protection VIN VOUT
o Over Temperature
o Restart and delay times
Fuse-Based NVM for improved reliability
RoHS compliant, MSL level 3, 260°C reflow
Small 5mmx5mmx0.9mm QFN Package
Applications
• High performance FPGA Core Supply
• ASIC and processor supply rails
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Rev B
Data Sheet | Intel Enpirion Power Solutions: ED8401
Ordering Information
Part Number
Configuration*
Package
Markings
Package Description
ED8401P01QI
4-Phase
500kHz
84011
5 mm x 5 mm x 0.9mm QFN40
ED8401P03QI
3-Phase
500kHz
84013
5 mm x 5 mm x 0.9mm QFN40
ED8401P05QI
2-Phase
500kHz
84015
5 mm x 5 mm x 0.9mm QFN40
EVB-ED8401P01
Evaluation board; 4-Phase, 500kHz
EVB-ED8401P03
Evaluation board; 3-Phase, 500kHz
EVB-ED8401P05
Evaluation board; 2-Phase, 500kHz
EVI-EM2COMIF
GUI interface dongle
* For alternative configurations contact Sales
Packing and Marking Information: www.intel.com/content/www/us/en/programmable/support/qualityand-reliability/packing.html
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Data Sheet | Intel Enpirion Power Solutions: ED8401
CONTROL
SALRT
SDA
SCL
DGND
VDD18
VDD33
VDD50
AVDD18
ADCVREF
Pin Assignments
40 39 38 37 36 35 34 33 32 31
AGND 1
30 POK
VREFP 2
29 SYNC
VFBP 3
28 GPIO
VFBN 4
27 GPIO
26 PWM0
ISNSN0 5
PAD
ISNSP0 6
25 PWM1
ISNSN1 7
24 PWM2
ISNSP1 8
23 PWM3
ISNSN2 9
22 TEMP3
ISNSP2 10
21 TEMP2
RVSET
RTUNE
VINSEN
ADDR1
ADDR0
TEMP1
TEMP0
VTRACK
ISNSP3
ISNSN3
11 12 13 14 15 16 17 18 19 20
Figure 1: Pin Out Diagram (Top side)
For 2 & 3 Phase derivatives the now unrequired ISNSxx, Tempx and PWMx pins maybe left floating
Pin Description
PIN
NAME
I/O
FUNCTION
1
AGND
Input
Analog ground. Connect to system ground plane.
2
VREFP
Output
Reference terminal
3
VFBP
Input
Differential output voltage sense input (positive).
4
VFBN
Input
Differential output voltage sense input (negative).
5
ISNSN0
Input
Negative input of differential current sensing Phase 0
6
ISNSP0
Input
Positive input of differential current sensing Phase 0
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Data Sheet | Intel Enpirion Power Solutions: ED8401
PIN
NAME
I/O
FUNCTION
7
ISNSN1
Input
Negative input of differential current sensing Phase 1
8
ISNSP1
Input
Positive input of differential current sensing Phase 1
9
ISNSN2
Input
Negative input of differential current sensing Phase 2
10
ISNSP2
Input
Positive input of differential current sensing Phase 2
11
ISNSN3
Input
Negative input of differential current sensing Phase 3
12
ISNSP3
Input
Positive input of differential current sensing Phase 3
13
VTRACK
Input
External voltage tracking input
14
TEMP0
Input
Temp0 Channel (with PTOK & Fault Detection)
15
TEMP1
Input
Temp1 Channel (with PTOK & Fault Detection)
16
ADDR0
Input
PMBus address selection 0
17
ADDR1
Input
PMBus address selection 1
18
VINSEN
Input
PVIN supply input voltage sensing
19
RVSET
Input
A resistor from RVSET to AGND; can be used to set the
Output Voltage
RTUNE
Input
A resistor from RTUNE to AGND; can be used to scale the
compensator coefficients
21
TEMP2
Input
Temp2 Channel (with PTOK & Fault Detection)
22
TEMP3
Input
Temp3 Channel (with PTOK & Fault Detection)
23
PWM3
Output
PWM control signal phase 3
24
PWM2
Output
PWM control signal phase 2
25
PWM1
Output
PWM control signal phase 1
26
PWM0
Output
PWM control signal phase 0
27
GPIO
Input/Output
General Purpose Input/Output
28
GPIO
Input/Output
General Purpose Input/Output
29
SYNC
Input/Output
PWM synchronization signal
30
POK
Output
Output status flag (open drain)
31
CONTROL
Input
Control input (configurable – default high = Enable output))
32
SALRT
Output
PMBus alert output
33
SDA
Input/Output
PMBus shift data I/O
34
SCL
Input
PMBus shift clock input (slave-only)
35
DGND
Ground
Digital ground. Connect to system ground plane.
36
VDD18
Output
Internal 1.8V digital supply terminal
37
VDD33
Input/Output
3.3 V supply voltage terminal
38
VDD50
Input
5.0V supply voltage terminal
39
AVDD18
Output
Internal 1.8V analog supply terminal
40
ADCVREF
Input
Analog-to-digital converter (ADC) reference terminal
PAD
Input
Exposed pad, digital ground. (Connect to Pins 1 & 35)
20
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Data Sheet | Intel Enpirion Power Solutions: ED8401
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Voltage measurements are referenced to PGND.
Absolute Maximum Pin Ratings
Table 1
PARAMETER
SYMBOL
MIN
MAX
UNITS
5V supply voltage
VDD50
-0.3
5.5
V
Maximum slew rate
VDD50
0.15
V/µs
3.3V supply voltage
VDD33
Maximum slew rate
VDD33 = VDD50
1.8V supply voltage
VDD18
AVDD18
-0.3
3.9
0.15
V/µs
-0.3
2.0
V
SCL, SDA, CTRL, SALRT, POK
SYNC, PWMx
-0.3
3.9
V
TEMPx
-0.3
3.9
V
ADCREF, VREFP, VINSEN, ADDRx,
RVSET, RTUNE, VTRACK
-0.3
3.9
V
Voltage feedback, positive
VFBP
-0.3
2.0
V
Voltage feedback, negative
VFBN
-0.3
0.3
V
ISNSPx
ISNSNx
-0.3
5.0
V
MIN
MAX
UNITS
+125
°C
+150
°C
+260
°C
MAX
UNITS
Digital I/O pins
Analog/Digital I/O pins
Analog pins
Current sensing
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
Operating junction
temperature
Storage temperature range
Reflow peak body
temperature
-65
(10 Sec) MSL3
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM
All pins;
1000
V
CDM
All pins;
500
V
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Data Sheet | Intel Enpirion Power Solutions: ED8401
Recommended Operating Conditions
Table 2
PARAMETER
Supply voltage VDD50
Supply voltage VDD33 (VDD50 tied to VDD33)
PINS
MIN
MAX
UNITS
VDD50
4.75
5.25
V
VDD33 =
VDD50
3.00
3.6
V
-40
125
°C
0
50
°C
Operation junction temperature
Non-Volatile Memory programming
Thermal Characteristics
Table 3
PARAMETER
PINS
TYPICAL
UNITS
Thermal shutdown default [programmable]
TSD
120
°C
Thermal shutdown Hysteresis [programmable]
TSDH
18
°C
Thermal resistance: junction to case bottom (0
LFM)
θJC
1.5
°C/W
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Data Sheet | Intel Enpirion Power Solutions: ED8401
Electrical Characteristics
PVIN = 12V and VDD50 = 5.0V. The minimum and maximum values are over the ambient temperature range
(-40°C to 85°C) unless otherwise noted. Typical values are at TA = 25°C.
Table 4
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5.0
5.25
V
3.0
3.3
3.6
V
Normal operation; switching
fsw = 500kHz
70
125(2)
mA
Idle; communication and
telemetry but not switching
45
mA
1.25
mA
INPUT SUPPLY CHARACTERISTICS
VDD50
Input supply voltage
range
VDD33
Input supply current
Disabled (VCC ≤ 2.8V) (2)
Supply for both the VDD33
and VDD50 pins if the
internal 3.3V regulator is not
used.
Disabled (VCC ≤ 2.8V)
INTERNALLY GENERATED SUPPLY VOLTAGES
3.3V voltage range
VDD33
3.3V output current(2)
-400C to +1250C
3.0V to 3.6V
1.8V voltage range
VDD18
AVDD18
1.8V output current(2)
AVDD18
VDD50=5.0V
-400C to +1250C
Minimum Capacitance
Minimum Capacitance
1.72V to 1.98V
VREF
ADCREF
3.3
-400C to +1250C
Power On Reset (POR)
threshold for VDD33
pin – Low
From VDD33 valid, to start
of output voltage ramp, if
configured to regulate from
power on reset, and
TON_DELAY is set to 0.
3.6
V
2
mA
0.7
1.72
µF
1.8
0.7
VDD50=5.0V
Power On Reset (POR)
threshold for VDD33
pin – High
Output voltage startup
delay upon exceeding
POR(2)
3.0
VDD50=5.0V
Minimum Capacitance
Internal References
VDD50=5.0V
1.98
V
1
mA
µF
1.44
0.1
µF
2.8
V
2.6
V
6
ms
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Rev B
Data Sheet | Intel Enpirion Power Solutions: ED8401
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL I/O PIN ( SYNC)
Input high voltage
Configured for input Clk
2.0
3.6
V
Input low voltage
Configured for input Clk
-0.3
0.8
V
Output high voltage
Configured as Output Clk
2.4
VDD
33
V
Output low voltage
Configured as Output Clk
0.4
V
Input leakage current
±1
µA
Output current - source
2.0
mA
Output current - sink
2.0
mA
±12.5
%
SYNC frequency range
(1)
Percent of nominal
switching frequency
SYNC pulse width(1)
25
ns
Open Drain PIN (POK)
Low voltage
0
0.8
V
Input leakage current
±1
µA
Output current - sink
2.0
mA
POK Delay(2)
Normal mode & VTRACK
mode. Propagation delay
from detection of stable
output until PG asserts.
42
µs
POK De-Assertion
Delay(2)
Normal mode & VTRACK
mode. Propagation delay
from detection of out-ofband, or major fault, until PG
de-asserts.
31
µs
DIGITAL I/O PIN (CTRL)
Input high voltage
2.0
3.6
V
Input low voltage
-0.3
0.8
V
CTRL response delay
(stop) (2)
Configurable polarity; extra
turn-off delay configurable
(assumes 0 s turn-off delay)
120
µs
CTRL response delay
(start) (2)
Configurable polarity; extra
turn-on delay configurable
(assumes 0 s turn-on delay)
160
µs
DIGITAL I/O PINs ( GPIO0 & GPIO1)
Input high voltage
VDD33=3.3V
2.0
3.6
V
Input low voltage
VDD33=3.3V
-0.3
0.8
V
Output Sink Current
Configured for open drain
2
mA
Output high voltage
VDD33=3.3V
2.4
3.6
V
Output low voltage
VDD33=3.3V
-0.3
0.4
V
2
mA
Output Drive Current
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Data Sheet | Intel Enpirion Power Solutions: ED8401
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM Output pins
PWM output voltage high
VDD33=3.3V
PWM output voltage low
VDD33=3.3V
2.4
V
PWM tristate leakage
Frequency accuracy
0.4
V
±1
µA
2.0
PWM pulse width(2)
%
25
Resolution(2)
ns
163
ps
Current Measurement
Common mode
voltage(2)
ISNSP
ISNSN
Differential voltage
range(2)
ISNSP ISNSN
Accuracy
0
ET6160 = 1µA/A x 2700Ω x
66.67A
Controller reporting
5.25
V
180
mV
3
%
OUTPUT VOLTAGE SENSE, REPORTING, AND MANAGEMENT
Output voltage
adjustment range
Output voltage setpoint accuracy
0.5
1.3
V
0˚C < TA < 85˚C
-0.5
+0.5
%
-40˚C < TA < 85˚C
-1
+1
%
Output set-point
resolution
Output voltage startup
delay upon exceeding
POR(2)
From VDD33 valid, to start
of output voltage ramp, if
configured to regulate from
power on reset, and
TON_DELAY is set to 0.
Output voltage ramp
delay (TON_DELAY &
TOFF_DELAY) (2)
Configurable, no VOUT prebias condition.
1.4
mV
6
ms
0
500
ms
2.0
V/ms
1.4
V
VTRACK
VTRACK ramp rate(2)
VTRACK range
0
VTRACK offset voltage
±100
mV
TEMPERATURE SENSE, REPORTING, AND MANAGEMENT
Temperature reporting
accuracy
Resolution
Offset @ 250C
(Reprogrammable)
Assuming 8mV/0C
5
°C
0.22
°C
800
mV
FAULT MANAGEMENT PROTECTION FEATURES
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Data Sheet | Intel Enpirion Power Solutions: ED8401
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1.58
V
Over-Voltage Protection & Under-Voltage Protection
Set-point voltage
Reference DAC
Resolution
Reference DAC
0
12.5
mV
1.4V)
V
VTRACK
VOUT
t
Figure 14: Ratiometric Sequencing Using VTRACK
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Rev B
V
VTRACK
VOUT
t
Figure 15: Simultaneous Sequencing Using VTRACK
TEMPERATURE MEASUREMENT
The ED8401 temperature sense block provides the device and the system with precision temperature
information over a wide range of temperatures (-40°C to +150°C). The temperature sense block measures
both the digital controller’s temperature and up to four external Power Train temperatures. The ED8401
supports temperature telemetry and reporting through the standardized PMBus commands,
READ_TEMPERATURE_1 is mapped to the Power Trains die temperatures and READ_TEMPERATURE_2 is
mapped to the controller die temperature.
SMBAlert Pin
The SMBAlert pin is intended to operate using an external pull-up voltage of 3.3V and contains a weak
internal pull-up.
If operating in applications with a lower voltage pull-up voltage, it is recommended that an external low Vf
Schottky diode be placed at the input to localise this voltage.
VPull-Up
SMBAlert
ED8401
Figure 16: SMBAlert Pin Low Voltage Pull-up Option
Table 14: Schottky Diode Options
Description
Manufacturer
P/N
40V, 300mA, Schottky, SOD523
ST
BAT54KFILM
40V, 250mA, Schottky, SOD523
Diode Inc
BAT64T5Q
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Rev B
PMBus Functionality
INTRODUCTION
The ED8401 supports the PMBus protocol (version 1.2) to enable the use of configuration, monitoring, and
fault management features during run-time.
The PMBus host controller is connected to the ED8401 via the PMBus pins (SDA, SCL). A dedicated
SMBALERT pin is provided to notify the host that new status information is present.
The ED8401 supports packet error correction (PEC) according to the PMBus™ specification.
The ED8401 supports more than 60 PMBus commands in addition to several manufacturer specific
commands related to output voltage, faults, telemetry, and more.
The ED8401 provides a PMBus set of synchronous communication lines, with serial clock input (SCL), serial
data I/O (SDA), and serial alarm output (SALRT) pins.
The communication lines provide 1.8V I/O compatibility and open-drain outputs (SDA, SCL and SALRT).
The communication lines require external pull-up resistors; typical applications require pull-up resistors
on each end of the communication lines (typically values of 10 kΩ each), connected to VDD33 or an
alternative termination voltage. Please refer to the PMBus specification (www.pmbus.org) for full details.
The ED8401 provides configurable behavior for the SALRT pin to allow users to determine which fault or
warning conditions to communicate over the SALRT line. The default behavior of the controller ensures
that any fault or warning results in the ED8401 SALRT pin going low; the alert behavior is enabled for all
faults and warnings. You can deselect any of the faults or warnings so when one of these conditions occur,
the SALRT pin is not pulled low.
Remote measurement and reporting of telemetry information at the power supply level provides feedback
on key parameters such as voltages, current levels, temperature, and energy, and allows reporting of
information such as faults and warning flags. With this information, data is collected and analyzed while
the power supply is in development, such as in the qualification or verification phases, or in the field, and
system level interaction such as power capping is implemented. Several telemetry parameters are
supported by standard PMBus commands.
The ED8401 supports the LINEAR data format according to the PMBus specification. Note that in
accordance with the PMBus specification, all commands related to the output voltage are subject to the
VOUT_MODE settings.
A detailed description of the supported PMBus commands supported by the ED8401 can be found in
ED8401 Application Note – PMBus Commands Guide.
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Rev B
TIMING AND BUS SPECIFICATION
tLOW
tR
SCL
tBUF
tHIGH
tF
tHD:DAT
tSU:STA
tSU:STO
tHD:STA
SDA
S
P
tSU:DAT
P
S
Figure 17: PMBus Timing Diagram
Table 15: ED8401 PMBus Parameters
Parameter
Symbol
PMBus operation frequency
Conditions
Min
Typ
Max
Units
fSMB
10
100
400
kHz
Bus free time between start and
stop
tBUF
1.3
μs
Hold time after start condition
tHD:STA
0.6
μs
Repeat start condition setup time
tSU:STA
0.6
μs
Stop condition setup time
tSU:STO
0.6
μs
Data hold time
tHD:DAT
300
ns
Data setup time
tSU:DAT
100
ns
Clock low time-out
tTIMEOUT
Clock low period
tLOW
1.3
μs
Clock high period
tHIGH
0.6
μs
Cumulative clock low extend time
tLOW:SEXT
25
ms
Clock or data fall time
tF
300
ns
Clock or data rise time
tR
300
ns
25
35
ms
ADDRESS SELECTION VIA EXTERNAL RESISTORS
The PMBus protocol uses a 7-bit device address to identify different devices connected to the bus. This
address can be selected via external resistors connected to the ADDRx pins.
The resistor values are sensed using the internal ADC during the initialization phase and the appropriate
PMBus address is selected. Note that the respective circuitry is only active during the initialization phase;
hence no DC voltage can be measured at the pins. The supported PMBus addresses and the values of the
respective required resistors are listed in Table 16.
Table 16: Supported Resistor Values For PMBus Address Selection
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
0x40
0
0
0x2B
1.2 k
12 k
0x56
3.9 k
4.7 k
0x01*
0
680
0x2C
1.2 k
15 k
0x57
3.9 k
5.6 k
Page 39
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Rev B
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
0x02*
0
1.2 k
0x2D
1.2 k
18 k
0x58
3.9 k
6.8 k
0x03*
0
1.8 k
0x2E
1.2 k
22 k
0x59
3.9 k
8.2 k
0x04*
0
2.7 k
0x2F
1.2 k
27 k
0x5A
3.9 k
10 k
0x05*
0
3.9 k
0x30
1.8 k
0
0x5B
3.9 k
12 k
0x06*
0
4.7 k
0x31
1.8 k
680
0x5C
3.9 k
15 k
0x07*
0
5.6 k
0x32
1.8 k
1.2 k
0x5D
3.9 k
18 k
0x08*
0
6.8 k
0x33
1.8 k
1.8 k
0x5E
3.9 k
22 k
0x09
0
8.2 k
0x34
1.8 k
2.7 k
0x5F
3.9 k
27 k
0x0A
0
10 k
0x35
1.8 k
3.9 k
0x60
4.7 k
0
0x0B
0
12 k
0x36
1.8 k
4.7 k
0x61*
4.7 k
680
0x0C*
0
15 k
0x37*
1.8 k
5.6 k
0x62
4.7 k
1.2 k
0x0D
0
18 k
0x38
1.8 k
6.8 k
0x63
4.7 k
1.8 k
0x0E
0
22 k
0x39
1.8 k
8.2 k
0x64
4.7 k
2.7 k
0x0F
0
27 k
0x3A
1.8 k
10 k
0x65
4.7 k
3.9 k
0x10
680
0
0x3B
1.8 k
12 k
0x66
4.7 k
4.7 k
0x11
680
680
0x3C
1.8 k
15 k
0x67
4.7 k
5.6 k
0x12
680
1.2 k
0x3D
1.8 k
18 k
0x68
4.7 k
6.8 k
0x13
680
1.8 k
0x3E
1.8 k
22 k
0x69
4.7 k
8.2 k
0x14
680
2.7 k
0x3F
1.8 k
27 k
0x6A
4.7 k
10 k
0x15
680
3.9 k
0x40
2.7 k
0
0x6B
4.7 k
12 k
0x16
680
4.7 k
0x41
2.7 k
680
0x6C
4.7 k
15 k
0x17
680
5.6 k
0x42
2.7 k
1.2 k
0x6D
4.7 k
18 k
0x18
680
6.8 k
0x43
2.7 k
1.8 k
0x6E
4.7 k
22 k
0x19
680
8.2 k
0x44
2.7 k
2.7 k
0x6F
4.7 k
27 k
0x1A
680
10 k
0x45
2.7 k
3.9 k
0x70
5.6 k
0
0x1B
680
12 k
0x46
2.7 k
4.7 k
0x71
5.6 k
680
0x1C
680
15 k
0x47
2.7 k
5.6 k
0x72
5.6 k
1.2 k
0x1D
680
18 k
0x48
2.7 k
6.8 k
0x73
5.6 k
1.8 k
0x1E
680
22 k
0x49
2.7 k
8.2 k
0x74
5.6 k
2.7 k
0x1F
680
27 k
0x4A
2.7 k
10 k
0x75
5.6 k
3.9 k
0x20
1.2 k
0
0x4B
2.7 k
12 k
0x76
5.6 k
4.7 k
0x21
1.2 k
680
0x4C
2.7 k
15 k
0x77
5.6 k
5.6 k
0x22
1.2 k
1.2 k
0x4D
2.7 k
18 k
0x78*
5.6 k
6.8 k
0x23
1.2 k
1.8 k
0x4E
2.7 k
22 k
0x79*
5.6 k
8.2 k
0x24
1.2 k
2.7 k
0x4F
2.7 k
27 k
0x7A*
5.6 k
10 k
0x25
1.2 k
3.9 k
0x50
3.9 k
0
0x7B*
5.6 k
12 k
0x26
1.2 k
4.7 k
0x51
3.9 k
680
0x7C*
5.6 k
15 k
Page 40
15612
April 2, 2020
Rev B
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
0x27
1.2 k
5.6 k
0x52
3.9 k
1.2 k
0x7D*
5.6 k
18 k
0x28*
1.2 k
6.8 k
0x53
3.9 k
1.8 k
0x7E*
5.6 k
22 k
0x29
1.2 k
8.2 k
0x54
3.9 k
2.7 k
0x7F*
5.6 k
27 k
0x2A
1.2 k
10 k
0x55
3.9 k
3.9 k
Note 2: The gray-highlighted addresses with an asterisk are reserved by the SMBus specification.
Clock Stretching
The SMBus specification allows devices to slow down the bus by periodically extending the clock low
interval which then allows devices of different speeds to co-exist on the same bus.
The ED8401 family utilizes clock stretching for communications and with this the PMBus master must
support clock stretching.
Internal clock in Master
SCL-MASTER
1
2
7
8
9
SCL - BUS
1
2
7
8
9
Data
Data
Data
Data
ACK
SDA
S
SCL - Clock stretching by the slave –
Shown in Green
Figure 18: Example of Periodic & Random Clock Stretching
After every byte is received by our module, the module will acknowledge receiving the byte and if required
will then hold the SCL line low (Clock stretch) while it processes the received data. Upon completion it will
then release the clock signaling to the Master it is ready to receive the next Byte.
Only after issuing the acknowledge bit will our module clock Stretch. The duration of the clock stretch
interval will vary in length dependent on the command received and what other activities the controller is
performing at that time.
As per the SMBus specification if the SCL is detected to be low for a duration longer than the “Clock low
time-out” period then the module will reset its SMBus interface thereby releasing the BUS and be ready for
fresh communications. Upon this event occurring the Module will also assert its SMBalert pin to signal the
Master an event was occurred. This functionality is not required by the I2C specification, so user should be
aware of this difference.
For greater detail on Clock Stretching, please refer to “SMBus Version 2.0” specifications, available at
www.smbus.org.
Page 41
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PMBUS COMMANDS
A detailed description of the PMBus commands supported by the ED8401 can be found in a separate
document - ED8401 PMBus Commands Guide. Below, Table 17 lists of all supported PMBus commands.
Table 17 : List Of Supported PMBus Commands
Command
Code
PMBus Parameter
Description
01HEX
OPERATION
On/off command
02HEX
ON_OFF_CONFIG
On/off configuration
03HEX
CLEAR_FAULTS
Clear status information
04HEX
PHASE
Configure, control, and monitor phases
10HEX
WRITE_PROTECT
Protect against changes
11HEX
STORE_DEFAULT_ALL
Copy entire memory into OTP
12HEX
RESTORE_DEFAULT_ALL
Copy entire memory from OTP
13HEX
STORE_DEFAULT_CODE
Copy single parameter into OTP
14HEX
RESTORE_DEFAULT_CODE
Copy single parameter from OTP
19HEX
CAPABILITY
PMBus Capabilities
20HEX
VOUT_MODE (Note 3)
Exponent of the VOUT_COMMAND value
21HEX
VOUT_COMMAND
Set output voltage
22HEX
VOUT_TRIM
Apply a fixed offset voltage
23HEX
VOUT_CAL_OFFSET
Apply a fixed offset voltage
24HEX
VOUT_MAX
Sets maximum VOUT
25HEX
VOUT_MARGIN_HIGH
Sets maximum value
26HEX
VOUT_MARGIN_LOW
Sets minimum value
29HEX
VOUT_SCALE_LOOP
Scalar for output voltage divider
2AHEX
VOUT_SCALE_MONITOR
Scalar for read-back with output voltage
divider
2BHEX
VOUT_MAX
Sets minimum VOUT
35HEX
VIN_ON
Input voltage turn on threshold
36HEX
VIN_OFF
Input voltage turn off threshold
40HEX
VOUT_OV_FAULT_LIMIT
Over-voltage fault limit
41HEX
VOUT_OV_FAULT_RESPONSE
Over-voltage fault response
42HEX
VOUT_OV_WARN_LIMIT
Over-voltage warning level
43HEX
VOUT_UV_WARN_LIMIT
Under-voltage warning level
44HEX
VOUT_UV_FAULT_LIMIT
Under-voltage fault level
45HEX
VOUT_UV_FAULT_RESPONSE
Under-voltage fault response
46HEX
IOUT_OC_FAULT_LIMIT
Over-current fault limit
47HEX
IOUT_OC_FAULT_RESPONSE
Over-current fault response
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Rev B
Command
Code
PMBus Parameter
Description
4AHEX
IOUT_OC_WARN_LIMIT
Over-current warning level
4FHEX
OT_FAULT_LIMIT
Power Train Over-temperature fault level
50HEX
OT_FAULT_RESPONSE
Power Train Over-temperature fault
response
51HEX
OT_WARN_LIMIT
Power Train Over-temperature warning level
55HEX
VIN_OV_FAULT_LIMIT
Over-voltage fault limit
56HEX
VIN_OV_FAULT_RESPONSE
Over-voltage fault response
57HEX
VIN_OV_WARN_LIMIT
Over-voltage warning level
58HEX
VIN_UV_WARN_LIMIT
Under-voltage warning level
59HEX
VIN_UV_FAULT_LIMIT
Under-voltage fault level
5AHEX
VIN_UV_FAULT_RESPONSE
Under-voltage fault response
5EHEX
POWER_GOOD_ON
Power good on threshold
5FHEX
POWER_GOOD_OFF
Power good off threshold
60HEX
TON_DELAY
Turn-on delay
61HEX
TON_RISE
Turn-on rise time
62HEX
TON_MAX_FAULT_LIMIT
Turn-on maximum fault time
64HEX
TOFF_DELAY
Turn-off delay
65HEX
TOFF_FALL
Turn-off fall time
66HEX
TOFF_MAX_WARN_LIMIT
Turn-off maximum warning time
78HEX
STATUS_BYTE
Unit status byte
79HEX
STATUS_WORD
Unit status word
7AHEX
STATUS_VOUT
Output voltage status
7BHEX
STATUS_IOUT
Output current status
7CHEX
STATUS_INPUT
Input status
7DHEX
STATUS_TEMPERATURE
Temperature status
7EHEX
STATUS_CML
Communication and memory status
80HEX
STATUS_MFR_SPECIFIC
Manufacturer specific status
88HEX
READ_VIN
Reads input voltage
8BHEX
READ_VOUT
Reads output voltage
8CHEX
READ_IOUT
Reads output current
8DHEX
READ_TEMPERATURE_1
Power Train Temperature read back
8EHEX
READ_TEMPERATURE_2
Controller Temperature read back
94HEX
READ_DUTY_CYCLE
Current Duty Cycle read back
95HEX
READ_FREQUENCY
Reads switching frequency
Page 43
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Rev B
Command
Code
PMBus Parameter
Description
96HEX
READ_POUT
Reads output power
98HEX
PMBUS™_REVISION
PMBus™ revision
99HEX
MFR_ID
Manufacturer ID
9AHEX
MFR_MODEL
Manufacturer model identifier
9BHEX
MFR_REVISION
Manufacturer product revision
9EHEX
MFR_SERIAL
Serial number
A0HEX
MFR_VIN_MIN
Minimum input voltage
A1HEX
MFR_VIN_MAX
Maximum input voltage
A4HEX
MFR_VOUT_MIN
Minimum output voltage
A5HEX
MFR_VOUT_MAX
Maximum output voltage
ADHEX
IC_DEVICE_ID
Product Family’s model Number
AEHEX
IC_DEVICE_REV
Silicon Hardware Revision
C4HEX
MFR_TEMP0_FAULT_RESPONSE
Phase0 fault response
C5HEX
MFR_TEMP1_FAULT_RESPONSE
Phase1 fault response
C6HEX
MFR_TEMP2_FAULT_RESPONSE
Phase2 fault response
C7HEX
MFR_TEMP3_FAULT_RESPONSE
Phase3 fault response
C9HEX
MFR_CBC_LIM_FAULT_RESPONSE
CBC LIM fault response
CAHEX
MFR_CBC_POS_LIMIT
CBC positive correction limit
D0HEX
MFR_SPECIFIC_00
Write word (once) / Read word – 2 bytes
D1HEX
MFR_SPECIFIC_01
Write word / read word – 12 bytes
D2HEX
MFR_READ_VCC
Reads VCC voltage
D7HEX
MFR_STATUS_EXT1
External Power Train Fault status Flags 1
D8HEX
MFR_STATUS_EXT2
External Power Train Fault status Flags 2
D9HEX
MFR_FAULT_RESPONSE_EXT_READ
Returns additional Fault response settings
DAHEX
MFR_FAULT_RESPONSE_EXT_WRITE
Sets additional Fault response settings
DBHEX
MFR_RTUNE_CONFIG
Gets/sets RTUNE settings
DDHEX
MFR_RTUNE_INDEX
Returns index derived from resistor
detected on RTUNE pin
DEHEX
MFR_RVSET_INDEX
Returns index derived from resistor
detected on RVSET pin
E0HEX
MFR_VOUT_OFF
Sets the target turn-off voltage
E1HEX
MFR_EXT_TEMP_CAL_OFFSET
Calibrate with external Temp Sensors
E2HEX
MFR_IOT_FAULT_LIMIT
Controller Over-temperature fault level
E3HEX
MFR_IOT_WARN_LIMIT
Controller Over-temperature warning level
E5HEX
MFR_IOT_FAULT_RESPONSE
Controller Over-temperature fault response
Page 44
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Rev B
Command
Code
PMBus Parameter
Description
E6HEX
MFR_TEMP_ON
Over-temperature on level
E7HEX
MFR_PIN_CONFIG
Enable/disable – RTUNE, RVSET, VTRACK
and SYNC
E9HEX
MFR_STORE_CONFIG_ADDR_READ
Reads a configuration value
EAHEX
MFR_STORE_PARAMS_REMAINING
Number of STORE_DEFAULT_ALL
commands remaining
EBHEX
MFR_STORE_CONFIGS_REMAINING
Number of full configurations remaining
ECHEX
MFR_STORE_CONFIG_BEGIN
Commence programming of OTP
EDHEX
MFR_STORE_CONFIG_ADDR_DATA
Program a configuration value
EEHEX
MFR_STORE_CONFIG_END
Completed programming of OTP
EFh
MFR_OTP_STATUS
NVM Status
Note 3: VOUT_ MODE is read only for the ED8401
Page 45
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April 2, 2020
Rev B
Package Dimensions
Figure 19: Package Dimensions (ED8401P01 Shown)
Page 46
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April 2, 2020
Rev B
Revision History
Rev
Date
Change(s)
A
29th Apr 19
First Release
A1
31st Oct 19
Minor updates
B
6 Apr 20
Release Update
th
Where to Get More Information
For more information about Intel and Intel Enpirion PowerSoCs, visit https://www.altera.com/enpirion
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
* Other marks and brands may be claimed as the property of others.
Page 47
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