DataSheeT
Intel® Enpirion® Power Solutions
EM2120x01QI 20A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor, Featuring
Digital Control with PMBusTM v1.2 Compliant Interface
Description
Features
The EM2120 is a fully integrated 20A PowerSoC
synchronous buck converter. It features an advanced
digital controller, gate drivers, synchronous MOSFET
switches, and a high-performance inductor. Only
input and output filter capacitors and a few small
signal components are required for a complete
solution. A PMBus version 1.2 compliant interface
provides setup, control, and telemetry.
•
•
•
•
•
Differential remote sensing and ±0.5% set-point
accuracy provides precise regulation over line, load
and temperature variation. Very low ripple further
reduces accuracy uncertainty to provide best in class
static regulation for today’s FPGAs, ASICs, processors,
and DDR memory devices.
The EM2120 may be used in standalone mode or
utilizing the PMBus interface for a high degree of
flexibility and programmability. Advanced digital
control techniques ensure stability and excellent
dynamic performance, and eliminate the need for
external compensation components. The PC-based
Intel Enpirion Digital Power Configurator provides a
user-friendly and easy-to-use interface to the device
for communication and configuration.
The EM2120 features high conversion efficiency and
superior thermal performance to minimize thermal
de-rating limitations, which is key to product
reliability and longevity.
•
•
•
•
•
•
Integrated inductor, FETs, and digital controller
Wide 4.5V to 16V VIN range
0.7V to 5V VOUT range
20A continuous current with no thermal de-rating
High efficiency in 11mm x 17mm x 6.76mm QFN
package
o 95% efficiency at VIN = 5V, VOUT = 3.3V
o 90% efficiency at VIN = 12V, VOUT = 1.2V
Optimized total solution size of only 365 mm2
Meets all high-performance FPGA requirements
o Digital loop for best in class transient response
o 0.5% set-point over line, load, and temperature
o Output ripple as low as 10 mV peak-peak
o Differential remote sensing
o Monotonic startup into pre-bias output
o Optimized FPGA configs stored in NVM
Programmable through PMBus™
o VOUT margining, startup and shutdown delays
o Programmable warnings, faults and response
Ability to operate without PMBus™
o RVSET resistor for programmable VOUT
o RTUNE resistor for single resistor compensation
Tracking pin for complex sequencing
RoHS compliant, MSL level 3, 260°C reflow
Applications
• High performance FPGA supply rails
• ASIC and processor supply rails
• High density double data rate (DDR) memory
VDDQ rails
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Ordering Information
Table 1
Part Number
Supported VOUT
Range
Package
Markings
Package Description
EM2120L01QI
0.7V to 1.325V
M2120L
17 mm x 11 mm x 6.76 mm QFN104 provided in 112
units per tray
EM2120H01QI
1.35V to 5V
M2120H
17 mm x 11 mm x 6.76 mm QFN104 provided in 112
units per tray
EVB-EM2120L01
0.7V to 1.325V
Evaluation board; 20A single phase
EVB-EM2120H01
1.35V to 5V
Evaluation board; 20A single phase
EVI-EM2COMIF
GUI interface dongle
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-andmarking.html
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Pin Assignments
91
82
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
100
PIN
1 VOUT
VOUT
VOUT
RVSET
RTUNE
VINSEN
ADDR1
ADDR0
PWM
SYNC
POK
CTRL
SALRT
SDA
SCL
16 VDD33
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
31 PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VOUT 81
VOUT
VOUT
VCCSEN
VTRACK
NC
NC
NC
NC
VSENN
VSENP
AGND
DGND
NC
NC
VCC 66
PVCC
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND 51
32
41
100
82
101
VOUT
102
AGND
103
PVIN
104
PGND
50
32
50
Figure 1: Pin Out Diagram
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Pin Description
Table 2
PIN
NAME
I/O
FUNCTION
1,2,3,
79-101
VOUT
Regulated
Output
Regulated output voltage. Decouple to PGND with appropriate filter capacitors
4
RVSET
Analog
I/O
5
RTUNE
Analog
I/O
A resistor from RTUNE to AGND; and can be used to tune the transient
compensator for the amount of output capacitance. Using 1% tolerance or better
resistor. See Table 11 and Table 12 for more information.
6
VINSEN
Analog
Input
Single-ended input voltage sense (relative to AGND).
7
ADDR1
Analog
I/O
A resistor from ADDR1 to AGND; and can be used to set the PMBus™ address. Use
a 1% tolerance or better resistor.
8
ADDR0
Analog
I/O
A resistor from ADDR0 to AGND; and can be used to set the PMBus™ address. Use
a 1% tolerance or better resistor.
9
PWM
PWM
PWM signal test pin.
10
SYNC
Digital I/O
PWM synchronization signal
11
POK
Digital I/O
Power OK is selectable as a push-pull output or an open drain transistor for
power system state indication. See the Power OK description for details
12
CTRL
Digital
Input
PMBus-compatible control pin with programmable functionality. CTRL should
never be left floating if enabled in Configuration. The default configuration is for
VOUT to be on with CTRL high (positive edge)
13
SALRT
Digital
Output
PMBus™ alert line.
14
SDA
Digital I/O
PMBus™ serial data I/O.
15
SCL
Digital
Input
PMBus™ serial clock input.
16
VDD33
Output
3.3V output of the internal LDO. May be used as pull-up supply for PMBus™ pins
and CTRL pin.
17-21,
61-64,
103
PVIN
Input
Supply
Input supply for MOSFET switches. Decouple to PGND with appropriate filter
capacitors. Refer to Recommended Application Circuit section for more details.
22-60,
104
PGND
Ground
Power ground. Ground for MOSFET switches.
65
PVCC
Input
Supply
5.0V supply voltage for driver circuitry. Decouple to PGND using a 2.2µF MLCC
high quality ceramic capacitor.
66
VCC
Input
Supply
5.0V supply voltage for analog circuitry.
67,68,
73-76
NC
NC
No connect. Do not connect to any signal, supply, or ground.
69
DGND
Ground
Digital ground. Connect to AGND pin directly.
A resistor from RVSET to AGND; and can be used to program the VOUT set-point.
Using 1% tolerance or better resistor. See
Table 8 and Table 9 for more information.
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PIN
NAME
I/O
FUNCTION
70, 102
AGND
Ground
Analog ground. Connect to system ground plane. Refer to layout section for more
details on grounding.
71
VSENP
Analog
Input
Differential output voltage sense input (positive).
72
VSENN
Analog
Input
Differential output voltage sense input (negative).
77
VTRACK
Analog
Input
Voltage tracking reference input if EM2120 is configured for voltage tracking
mode. May remain floating if not used. If enabled but not used, connect to
VDD33 using a 10kΩ resistor. VTRACK is not enabled in the default
configuration.
78
VCCSEN
Analog
Input
Single-ended VCC voltage sense (relative to AGND)
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Voltage
measurements are referenced to AGND.
Absolute Maximum Pin Ratings
Table 3
PARAMETER
SYMBOL
MIN
MAX
UNITS
Supply voltage PVIN
PVIN
-0.3
18
V
Supply voltage VCC
VCC
-0.3
5.5
V
VCC ramp time
VCC
20
ms
VDD33
VDD33
-0.3
3.6
V
Digital ground
DGND
-0.3
0.1
V
Power ground
PGND
-0.3
0.3
V
Digital I/O pins
SALRT, POK, SYNC,
-0.3
5.5
V
Digital I/O pins
SCL, SDA, CTRL
-0.3
3.6
V
Analog I/O pins
VINSEN, VCCSEN, ADDR0, ADDR1,
RVSET, RTUNE, VTRACK
-0.3
2.0
V
VSENP, VSENN
-0.3
2.0
V
PWM pin
PWM
-0.3
5.5
V
Output voltage pins
VOUT
-0.3
5.5
V
DC current on VOUT
VOUT
23
A
MAX
UNITS
+125
°C
+150
°C
+260
°C
MAX
UNITS
Voltage feedback
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
MIN
Operating junction
temperature
Storage temperature range
-65
Reflow peak body temperature
(10 Sec) MSL3
Absolute Maximum ESD Ratings
PARAMETER
HBD
CONDITION
MIN
All pins; Except VINSEN 1000 V
Max
2000
V
500
V
CDM; all pins
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Recommended Operating Conditions
Table 4
PARAMETER
PINS
MIN
MAX
UNITS
PVIN supply voltage range
PVIN
4.5
16
V
Supply voltage VCC & PVCC
VCC, PVCC
4.75
5.25
V
20
A
125
°C
Continuous load current
VOUT
Junction Temperature (Note 1)
-40
(Note 1): OTP default is set to 120°C for safety margin
Thermal Characteristics
Table 5
PARAMETER
PINS
TYPICAL
UNITS
Thermal shutdown [programmable]
TSD
120
°C
Thermal shutdown Hysteresis
TSDH
18
°C
θJA
8
θJC
1.5
Thermal resistance: junction to ambient (0 LFM)
((Note 2)
Thermal resistance: junction to case bottom (0 LFM)
°C/W
°C/W
(Note 2): Based on 2 oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51 standards for high thermal
conductivity boards. No top side cooling required.
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Electrical Characteristics
PVIN = 12V and VCC = 5.0V. The minimum and maximum values are over the ambient temperature range (-40°C
to 85°C) unless otherwise noted. Typical values are at TA = 25°C.
Table 6
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
16
V
SUPPLY CHARACTERISTICS
PVIN supply voltage
range
PVIN
Device switching; no load; fsw
= 800 kHz; VOUT = 1.0V
PVIN supply quiescent
current
VCC supply voltage
range
4.5
40
Device not switching
VCC
mA
1
4.75
5.0
5.25
V
VCC UVLO rising
4.4
V
VCC UVLO falling
4.2
V
PVCC & VCC supply
current
Normal operation; no load;
fsw = 800 kHz
80
100
mA
Normal operation; no load;
fsw = 1.33 MHz
120
150(1)
mA
Idle; communication and
telemetry only; no switching
30
mA
Disabled (VCC ≤ 2.8V)
900
µA
INTERNALLY GENERATED SUPPLY VOLTAGE
VDD33 voltage range
VDD33
3.0
VDD33 output current
3.3
3.6
2
mA
DIGITAL I/O PINS (POK, SYNC)
Input high voltage
2.0
5.5
V
Input low voltage
0
0.8
V
2.4
VDD33
V
Output low voltage
0.4
V
Input leakage current
±1
µA
Output current - source
2.0
mA
Output current - sink
2.0
mA
Output high voltage
DIGITAL I/O PIN (CTRL)
Input high voltage
2.0
3.6
V
Input low voltage
-0.3
0.8
V
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CTRL response delay
(stop)
Configurable polarity; extra
turn-off delay configurable
(assumes 0 s turn-off delay)
150
µs
CTRL response delay
(start)
Configurable polarity; extra
turn-on delay configurable
(assumes 0 s turn-on delay)
250
µs
HKADC INPUT PINS (VINSEN, VCCSEN, ADDR0 AND ADDR1)
Input voltage
0
1.44
V
PWM AND SYNCHRONIZATION
PWM output voltage high
2.4
V
PWM output voltage low
0.4
V
PWM tristate leakage
±1
µA
PWM pulse width
30
Resolution
ns
163
ps
Switching frequency –
EM2120L
fSW
With internal oscillator
800
kHz
Switching frequency –
EM2120H
fSW
With internal oscillator
1333
kHz
Percent of nominal switching
frequency
SYNC frequency range
SYNC pulse width
±12.5
25
%
ns
OUTPUT VOLTAGE SENSE, REPORTING, AND MANAGEMENT
Output voltage
adjustment range
EM2120L
0.7
1.325
V
EM2120H
1.35
5
V
-0.5
+0.5
%
Output voltage setpoint accuracy
EM2120L
0˚C < TA < 85˚C
EM2120L
-40˚C < TA < 85˚C
-1
+1
%
EM2120H
-40˚C < TA < 85˚C
-1
+1
%
Output set-point
resolution
EM2120L
1.5
mV
Line regulation
0.007
mV/V
Load regulation
0.07
mV/A
5
ms
Output voltage startup
delay
From VCC valid, to start of
output voltage ramp, if
configured to regulate from
power on reset, and
TON_DELAY is set to 0.
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PARAMETER
SYMBOL
Output voltage ramp
delay (TON_DELAY &
TOFF_DELAY)
TEST CONDITIONS
Configurable, no VOUT prebias condition.
MIN
TYP
0
Vout slew rate
MAX
UNITS
500
ms
0.5
VTRACK ramp rate
VTRACK range
Without resistor divider
0
VTRACK offset voltage
V/ms
2.0
V/ms
1.4
V
±100
mV
OUTPUT CURRENT SENSE, REPORTING, AND MANAGEMENT
±1.5
A
±1
A
±5
°C
0.22
°C
PVIN UV threshold
3.96
V
PVIN OV threshold
16.5
V
Current sense reporting
accuracy
IOUT > 5A, 25°C < TA < 85°C
IOUT > 5A, TA = 25°C
TEMPERATURE SENSE, REPORTING, AND MANAGEMENT
Temperature reporting
accuracy
Resolution
FAULT MANAGEMENT PROTECTION FEATURES
VOUT OV threshold
Percentage of output voltage
115
%
VOUT UV threshold
Percentage of output voltage
85
%
IOUT OCP
DC Current Value
25
OTP threshold
30
35
A
120
°C
OTP hysteresis
Fixed.
85
%
POK threshold
On level
95
%
POK threshold
Off level
90
%
Watchdog Timer
Interval
3
ms
SERIAL COMMUNICATION PMBUS DC CHARACTERISTICS
Input voltage – high
(VIH)
SCL and SDA
Input voltage – low
(VIL)
SCL and SDA
Rise & Fall Time
SCL and SDA >0.8V 1.4V)
V
VTRACK
VOUT
t
Figure 13: Ratiometric Sequencing Using VTRACK
V
VTRACK
VOUT
t
Figure 14: Simultaneous Sequencing Using VTRACK
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CLOCK SYNCHRONIZATION
The EM2120’s PWM synchronization feature allows the user to synchronize the switching frequency of
multiple devices. The SYNC pin can be configured as an input or an output.
When the SYNC pin is configured as input clock, the external clock need to be available before the EM2120 is
enabled. The EM2120 will only lock to the external clock within 1ms after the device is enabled. After 1 ms the
device can be re-synchronized to the external clock signal by toggling VOUT or via PMBus MFR_RESYNC
command.
When the SYNC pin is configured as an output clock (sync out), there is no requirement to provide an external
clock to allow synchronization.
The EM2120 SYNC functionality maybe configured as an input or an output using Intel’s GUI software or via
the manufacturer-specific PMBus command, MFR_PIN_CONFIG. The default configuration for synchronization
control is OFF.
TEMPERATURE AND OUTPUT CURRENT MEASUREMENT
The EM2120 temperature sense block provides the device and the system with precision temperature
information over a wide range of temperatures (-40°C to +150°C). The temperature sense block measures the
digital controller temperature, which will be slightly lower than the powertrain junction temperature.
The EM2120 monitors output current by real-time, temperature compensated DCR current sensing across the
inductor. This real-time current waveform is then digitally filtered and averaged for accurate telemetry, fault
warning, and management.
Factory calibration has been performed for every EM2120 device to improve measurement accuracy over the
full output current range. This allows the EM2120 to correct for DCR manufacturing variations.
For over-current protection, an unfiltered ADC is used in order to minimize delays in protecting the device.
Because this measurement is unfiltered, the accuracy of the protection threshold is less than that of the
average current reading.
PROTECTION AND FAULT RESPONSE
The EM2120 monitors various signals during operation in order to detect fault conditions. Measured and
filtered signals are compared to a configurable set of warnings and fault thresholds. In typical usage, a warning
sets a status flag, but does not trigger a response; whereas a fault sets a status flag and generates a response.
The assertion of the SMBALERT signal can be configured to individual application requirements.
The EM2120 supports a number of different response types depending on the fault detected.
In the default configuration, the EM2120 responds to an over temperature event by ramping down VOUT in a
controlled manner at a slew rate defined by the TOFF_FALL value. This response type is termed “Soft-Off”. The
final state of the output signals depends on the value selected for VOFFnom.
For all other faults the EM2120 will respond by immediately turning off both the top-side MOSFET and lowside MOSFET. This response type is termed “High-Impedance”.
For each fault response, a delay and a retry setting can be configured. If the delay-to-fault value is set to nonzero, the EM2120 will not respond to a fault immediately. Instead it will delay the response by the configured
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value and then reassesses the signal. If the fault remains present during the delay time, the appropriate
response will be triggered. If the fault is no longer present, the previous detection will be disregarded.
If the delay-to-retry value is set to non-zero, the EM2120 will not attempt to restart immediately after fault
detection. Instead it will delay the restart by the configured value. If the fault is still present when attempting
to restart, the appropriate response will be triggered. If the fault is no longer present, the previous detection
will be disregarded. If the delay-to-fault is a non-zero value, then the delay-to-retry value will be a factor of
100 times greater than the delay-to-fault value.
The retry setting, i.e. the number of EM2120 restarts after a fault event, can be configured. This number can
be between zero and six. A setting of seven represents infinite retry operation. This setting is commonly known
as “Hiccup Mode.”
Watchdog Timer
General house-keeping operations are managed by an internal microcontroller (MCU). To ensure reliable
MCU operation in all environments a watchdog timer has been incorporated. The purpose of the watchdog
timer is to reset the MCU as a last resort in the unlikely event of it entering an unknown state.
In the exceptional event of a reset the MCU will shutdown the controller into a safe state and will then reload
its memory, restarting the controller and output into its known good default operating condition.
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PMBus Functionality
INTRODUCTION
The EM2120 supports the PMBus protocol (version 1.2) to enable the use of configuration, monitoring, and
fault management features during run-time.
The PMBus host controller is connected to the EM2120 via the PMBus pins (SDA, SCL). A dedicated SMBALERT
pin is provided to notify the host that new status information is present.
The EM2120 supports packet correction (PEC) according to the PMBus™ specification.
The EM2120 supports clock stretching according to the SMBus specification.
The EM2120 communications utilizes clock stretching as required and this requires the PMBus master to
support clock stretching.
The EM2120 supports more than 60 PMBus commands in addition to several manufacturer specific
commands related to output voltage, faults, telemetry, and more.
The EM2120 provides a PMBus set of synchronous communication lines, with serial clock input (SCL), serial
data I/O (SDA), and serial alarm output (SALRT) pins.
The communication lines provide 3.6V-tolerance, 1.8V I/O compatibility and open-drain outputs (SDA, SCL
and SALRT). The communication lines require external pull-up resistors; typical applications require pull-up
resistors on each end of the communication lines (typically values of 10 kΩ each), connected to VDD33 or an
alternative termination voltage. Please refer to the PMBus specification (www.pmbus.org) for full details.
The EM2120 provides configurable behavior for the SALRT pin to allow users to determine which fault or
warning conditions to communicate over the SALRT line. The default behavior of the controller ensures that
any fault or warning results in the EM2120 SALRT pin going low; the alert behavior is enabled for all faults and
warnings. You can deselect any of the faults or warnings so when one of these conditions occur, the SALRT
pin is not pulled low.
The EM2120 provides a PMBus compliant power conversion control signal through input CTRL. You can
configure input CTRL through the standard PMBus command ON_OFF_CONFIG.
By default configuration, the CTRL pin must be pulled high to enable operation and the PMBus command
OPERATION is ignored. You can override this function with the ON_OFF_CONFIG PMBus command.
Remote measurement and reporting of telemetry information at the power supply level provides feedback on
key parameters such as voltages, current levels, temperature, and energy, and allows reporting of information
such as faults and warning flags. With this information, data is collected and analyzed while the power supply
is in development, such as in the qualification or verification phases, or in the field, and system level interaction
such as power capping is implemented. Several telemetry parameters are supported by standard PMBus
commands.
The EM2120 supports PMBus output current telemetry through the READ_IOUT command and reports the
low-pass filtered, or DC, output current.
The standard PMBus command READ_VOUT supports output voltage telemetry.
The standard PMBus command READ_VIN supports input voltage telemetry.
The EM2120 supports temperature telemetry and reporting through standardized PMBus commands.
READ_TEMPERATURE_2 is mapped to the controller die temperature.
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The standard PMBus command READ_FREQUENCY supports switching frequency monitoring. This command
returns the scaled frequency of the PWM output in kHz.
The EM2120 supports the LINEAR data format according to the PMBus specification. Note that in accordance
with the PMBus specification, all commands related to the output voltage are subject to the VOUT_MODE
settings.
A detailed description of the supported PMBus commands supported by the EM2120 can be found in EM21xx
Application Note – PMBus Commands Guide.
TIMING AND BUS SPECIFICATION
tLOW
SCL
tR
tBUF
tHIGH
tF
tHD:DAT
tSU:STA
tSU:STO
tHD:STA
SDA
P
S
tSU:DAT
P
S
Figure 15: PMBus Timing Diagram
Table 15: EM2120 PMBus Parameters
Parameter
Symbol
PMBus operation frequency
Conditions
Min
Typ
Max
Units
fSMB
10
100
400
kHz
Bus free time between start and stop
tBUF
1.3
μs
Hold time after start condition
tHD:STA
0.6
μs
Repeat start condition setup time
tSU:STA
0.6
μs
Stop condition setup time
tSU:STO
0.6
μs
Data hold time
tHD:DAT
300
ns
Data setup time
tSU:DAT
150*
ns
Clock low time-out
tTIMEOUT
Clock low period
tLOW
1.3
μs
Clock high period
tHIGH
0.6
μs
Cumulative clock low extend time
tLOW:SEXT
25
ms
Clock or data fall time
tF
300
ns
Clock or data rise time
tR
300
ns
25
35
ms
Note: The EM2120 fully complies with PMBus 1.2 specifications for operation up to 100kHz on SCL. The EM2120
may be operated at frequencies up to at least 400kHz on SCL if tSU:DAT is maintained greater than 150ns.
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ADDRESS SELECTION VIA EXTERNAL RESISTORS
The PMBus protocol uses a 7-bit device address to identify different devices connected to the bus. This
address can be selected via external resistors connected to the ADDRx pins.
The resistor values are sensed using the internal ADC during the initialization phase and the appropriate
PMBus address is selected. Note that the respective circuitry is only active during the initialization phase; hence
no DC voltage can be measured at the pins. The supported PMBus addresses and the values of the respective
required resistors are listed in Table 16.
Table 16: Supported Resistor Values For PMBus Address Selection
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
0x40
0
0
0x2B
1.2 k
12 k
0x56
3.9 k
4.7 k
0x01*
0
680
0x2C
1.2 k
15 k
0x57
3.9 k
5.6 k
0x02*
0
1.2 k
0x2D
1.2 k
18 k
0x58
3.9 k
6.8 k
0x03*
0
1.8 k
0x2E
1.2 k
22 k
0x59
3.9 k
8.2 k
0x04*
0
2.7 k
0x2F
1.2 k
27 k
0x5A
3.9 k
10 k
0x05*
0
3.9 k
0x30
1.8 k
0
0x5B
3.9 k
12 k
0x06*
0
4.7 k
0x31
1.8 k
680
0x5C
3.9 k
15 k
0x07*
0
5.6 k
0x32
1.8 k
1.2 k
0x5D
3.9 k
18 k
0x08*
0
6.8 k
0x33
1.8 k
1.8 k
0x5E
3.9 k
22 k
0x09
0
8.2 k
0x34
1.8 k
2.7 k
0x5F
3.9 k
27 k
0x0A
0
10 k
0x35
1.8 k
3.9 k
0x60
4.7 k
0
0x0B
0
12 k
0x36
1.8 k
4.7 k
0x61*
4.7 k
680
0x0C*
0
15 k
0x37*
1.8 k
5.6 k
0x62
4.7 k
1.2 k
0x0D
0
18 k
0x38
1.8 k
6.8 k
0x63
4.7 k
1.8 k
0x0E
0
22 k
0x39
1.8 k
8.2 k
0x64
4.7 k
2.7 k
0x0F
0
27 k
0x3A
1.8 k
10 k
0x65
4.7 k
3.9 k
0x10
680
0
0x3B
1.8 k
12 k
0x66
4.7 k
4.7 k
0x11
680
680
0x3C
1.8 k
15 k
0x67
4.7 k
5.6 k
0x12
680
1.2 k
0x3D
1.8 k
18 k
0x68
4.7 k
6.8 k
0x13
680
1.8 k
0x3E
1.8 k
22 k
0x69
4.7 k
8.2 k
0x14
680
2.7 k
0x3F
1.8 k
27 k
0x6A
4.7 k
10 k
0x15
680
3.9 k
0x40
2.7 k
0
0x6B
4.7 k
12 k
0x16
680
4.7 k
0x41
2.7 k
680
0x6C
4.7 k
15 k
0x17
680
5.6 k
0x42
2.7 k
1.2 k
0x6D
4.7 k
18 k
0x18
680
6.8 k
0x43
2.7 k
1.8 k
0x6E
4.7 k
22 k
0x19
680
8.2 k
0x44
2.7 k
2.7 k
0x6F
4.7 k
27 k
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Data Sheet | Intel Enpirion Power Solutions: EM2120
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
Address
(hex)
ADDR1
Ω
ADDR0
Ω
0x1A
680
10 k
0x45
2.7 k
3.9 k
0x70
5.6 k
0
0x1B
680
12 k
0x46
2.7 k
4.7 k
0x71
5.6 k
680
0x1C
680
15 k
0x47
2.7 k
5.6 k
0x72
5.6 k
1.2 k
0x1D
680
18 k
0x48
2.7 k
6.8 k
0x73
5.6 k
1.8 k
0x1E
680
22 k
0x49
2.7 k
8.2 k
0x74
5.6 k
2.7 k
0x1F
680
27 k
0x4A
2.7 k
10 k
0x75
5.6 k
3.9 k
0x20
1.2 k
0
0x4B
2.7 k
12 k
0x76
5.6 k
4.7 k
0x21
1.2 k
680
0x4C
2.7 k
15 k
0x77
5.6 k
5.6 k
0x22
1.2 k
1.2 k
0x4D
2.7 k
18 k
0x78*
5.6 k
6.8 k
0x23
1.2 k
1.8 k
0x4E
2.7 k
22 k
0x79*
5.6 k
8.2 k
0x24
1.2 k
2.7 k
0x4F
2.7 k
27 k
0x7A*
5.6 k
10 k
0x25
1.2 k
3.9 k
0x50
3.9 k
0
0x7B*
5.6 k
12 k
0x26
1.2 k
4.7 k
0x51
3.9 k
680
0x7C*
5.6 k
15 k
0x27
1.2 k
5.6 k
0x52
3.9 k
1.2 k
0x7D*
5.6 k
18 k
0x28*
1.2 k
6.8 k
0x53
3.9 k
1.8 k
0x7E*
5.6 k
22 k
0x29
1.2 k
8.2 k
0x54
3.9 k
2.7 k
0x7F*
5.6 k
27 k
0x2A
1.2 k
10 k
0x55
3.9 k
3.9 k
Note2: The gray-highlighted addresses with an asterisks are reserved by the SMBus specification.
PMBUS COMMANDS
A detailed description of the PMBus commands supported by the EM2120 can be found in a separate
document - EM2120 PMBus Commands Guide. Below, Table 16 lists of all supported PMBus commands.
Table 17: List Of Supported PMBus Commands
Command
Code
PMBus Parameter
Description
01HEX
OPERATION
On/off command
02HEX
ON_OFF_CONFIG
On/off configuration
03HEX
CLEAR_FAULTS
Clear status information
10HEX
WRITE_PROTECT
Protect against changes
11HEX
STORE_DEFAULT_ALL
Copy entire memory into OTP
12HEX
RESTORE_DEFAULT_ALL
Copy entire memory from OTP
13HEX
STORE_DEFAULT_CODE
Copy single parameter into OTP
14HEX
RESTORE_DEFAULT_CODE
Copy single parameter from OTP
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Command
Code
PMBus Parameter
Description
20HEX
VOUT_MODE (Note4)
Exponent of the VOUT_COMMAND value
21HEX
VOUT_COMMAND
Set output voltage
22HEX
VOUT_TRIM
Apply a fixed offset voltage
23HEX
VOUT_CAL_OFFSET
Apply a fixed offset voltage
25HEX
VOUT_MARGIN_HIGH
Sets maximum value
26HEX
VOUT_MARGIN_LOW
Sets minimum value
29HEX
VOUT_SCALE_LOOP
Scalar for output voltage divider
2AHEX
VOUT_SCALE_MONITOR
Scalar for read-back with output voltage divider
35HEX
VIN_ON
Input voltage turn on threshold
36HEX
VIN_OFF
Input voltage turn off threshold
40HEX
VOUT_OV_FAULT_LIMIT
Over-voltage fault limit
41HEX
VOUT_OV_FAULT_RESPONSE
Over-voltage fault response
42HEX
VOUT_OV_WARN_LIMIT
Over-voltage warning level
43HEX
VOUT_UV_WARN_LIMIT
Under-voltage warning level
44HEX
VOUT_UV_FAULT_LIMIT
Under-voltage fault level
45HEX
VOUT_UV_FAULT_RESPONSE
Under-voltage fault response
55HEX
VIN_OV_FAULT_LIMIT
Over-voltage fault limit
56HEX
VIN_OV_FAULT_RESPONSE
Over-voltage fault response
57HEX
VIN_OV_WARN_LIMIT
Over-voltage warning level
58HEX
VIN_UV_WARN_LIMIT
Under-voltage warning level
59HEX
VIN_UV_FAULT_LIMIT
Under-voltage fault level
5AHEX
VIN_UV_FAULT_RESPONSE
Under-voltage fault response
5EHEX
POWER_GOOD_ON
Power good on threshold
5FHEX
POWER_GOOD_OFF
Power good off threshold
60HEX
TON_DELAY
Turn-on delay
61HEX
TON_RISE
Turn-on rise time
62HEX
TON_MAX_FAULT_LIMIT
Turn-on maximum fault time
64HEX
TOFF_DELAY
Turn-off delay
65HEX
TOFF_FALL
Turn-off fall time
66HEX
TOFF_MAX_WARN_LIMIT
Turn-off maximum warning time
78HEX
STATUS_BYTE
Unit status byte
79HEX
STATUS_WORD
Unit status word
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Command
Code
PMBus Parameter
Description
7AHEX
STATUS_VOUT
Output voltage status
7BHEX
STATUS_IOUT
Output current status
7CHEX
STATUS_INPUT
Input status
7EHEX
STATUS_CML
Communication and memory status
80HEX
STATUS_MFR_SPECIFIC
Manufacturer specific status
88HEX
READ_VIN
Reads input voltage
8BHEX
READ_VOUT
Reads output voltage
8CHEX
READ_IOUT
Reads output current
8EHEX
READ_TEMPERATURE
Reads temperature
95HEX
READ_FREQUENCY
Reads switching frequency
96HEX
READ_POUT
Reads output power
98HEX
PMBUS™_REVISION
PMBus™ revision
99HEX
MFR_ID
Manufacturer ID
9AHEX
MFR_MODEL
Manufacturer model identifier
9BHEX
MFR_REVISION
Manufacturer product revision
9EHEX
MFR_SERIAL
Serial number
A0HEX
MFR_VIN_MIN
Minimum input voltage
A4HEX
MFR_VOUT_MIN
Minimum output voltage
D0HEX
MFR_SPECIFIC_00
Write word (once) / Read word – 2 bytes
D1HEX
MFR_SPECIFIC_01
Write word / read word – 12 bytes
D2HEX
MFR_READ_VCC
Reads VCC voltage
D3HEX
MFR_RESYNC
Active RESYNC
DAHEX
MFR_RTUNE_CONFIG
Gets/sets RTUNE settings
DBHEX
MFR_VOUT_MARGIN_HIGH
Gets/sets Margin High
DCHEX
MFR_VOUT_MARGIN_LOW
Gets/sets Margin Low
DDHEX
MFR_RTUNE_INDEX
Returns index derived from resistor detected on
RTUNE pin
DEHEX
MFR_RVSET_INDEX
Returns index derived from resistor detected on
RVSET pin
E0HEX
MFR_VOUT_OFF
Sets the target turn-off voltage
E2HEX
MFR_OT_FAULT_LIMIT
Over-temperature fault level
E3HEX
MFR_OT_WARN_LIMIT
Over-temperature warning level
E5HEX
MFR_OT_FAULT_RESPONSE
Over-temperature fault response
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Command
Code
PMBus Parameter
Description
E6HEX
MFR_TEMP_ON
Over-temperature on level
E7HEX
MFR_PIN_CONFIG
Enable/disable – RTUNE, RVSET, VTRACK and
SYNC
E9HEX
MFR_STORE_CONFIG_ADDR_READ
Reads a configuration value
EAHEX
MFR_STORE_PARAMS_REMAINING
Number of STORE_DEFAULT_ALL commands
remaining
EBHEX
MFR_STORE_CONFIGS_REMAINING
Number of full configurations remaining
ECHEX
MFR_STORE_CONFIG_BEGIN
Commence programming of OTP
EDHEX
MFR_STORE_CONFIG_ADDR_DATA
Program a configuration value
EEHEX
MFR_STORE_CONFIG_END
Completed programming of OTP
Note4: VOUT_ MODE is read only for the EM2120
VIN
EM2120
LOCAL CIN
PVIN
4X22µF
1206
VOUT
LOCAL COUT
Load
Decoupling
R1VIN
Outpu t Voltage
Sense Point
VINSEN
R2VIN
5V
PVCC
FB
VCC
VCCSEN
R1DIV
VSENP
R2DIV
VSENN
CTRL
SYNC
VTRACK
VDD33
POK
SALERT
SDA
SCL
ADDR0
ADDR1
0R
RTUN E
RVSET
DGND AGND PGND
Figure 16: Recommended Application Circuit
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Data Sheet | Intel Enpirion Power Solutions: EM2120
Layout Recommendations
Recommendation 1: It is highly recommended to use separate nets for AGND and PGND and connecting them
through a 0Ω resistor or a short. This method helps with ground management and prevents the noise from the
Power Ground disturbing the more sensitive Analog (“Signal”) Ground.
Recommendation 2: It is good practice to minimize the PGND loop. Whenever possible the input and output
loops should close to the same point, which is the ground of the EM2120 module. Module decoupling ceramic
capacitors are to be placed as close as possible to the module in order to contain the switching noise in the
smallest possible loops and to improve PVIN decoupling by minimizing the series parasitic inductance of the
PVIN traces. For achieving this goal, it helps to place decoupling capacitors on the same side as the module
since VIAs are generally more inductive, thus reducing the effectiveness of the decoupling. Of course, bulk and
load high frequency decoupling should be placed closer to the load.
Figure 17: Top Layer Layout With Critical Components Only
Recommendation 3: It is good practice to place the other small components needed by the EM2120 on the
opposite side of the board, in order to avoid cutting the power planes on the module side. Since the EM2120
heat is evacuated mostly through the PCB, this will also help with heat dissipation; wide copper planes under
the module can also help with cooling. The PVIN copper plane should not be neglected as it helps spread the
heat from the high side FET.
Recommendation 4: It is recommended that at least below the EM2120 module, the next layers to the surface
(2 and n-1) be solid ground planes, which provides shielding and lower the ground impedance at the module
level. AGND should be also routed as a copper plane, in order to reduce the ground impedance and reduce
noise injection.
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Figure 18: VIAs in The Power Pads
Recommendation 5: In order to better spread the current and the heat through the inner layers, arrays of VIAs
should be placed in the power pads. 10mils diameter is a good size for the plated in-pad VIAs. It is critical that
through VIAs should not be placed by any means elsewhere under the module; the non-pad area around AGND
is VIA keep out area.
Recommendation 6: All other signal and LDO decoupling capacitors should be placed as close as possible to
the terminal they are decoupling, while the AGND connection should be done through VIAs to the AGND plane.
Figure 19: Backside Decoupling
All Signal Decoupling Go To The Bottom AGND Plane And Get Connected To The EM2120 Module AGND
Through The AGND In-PAD VIAs (Again, No Other VIAs Are Allowed In That Area)
Recommendation 7: Figure 20 also shows the 0Ω resistor that connects AGND to PGND. The recommended
connecting point, as shown, is to a quiet PGND the output capacitors PGND.
Recommendation 8: Differential remote sense should be routed as much as possible as a differential pair, on
an inner layer, preferably shielded by a ground plane.
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Figure 20: Remote Sense Routing On An Inner Layer (Highlighted, Yellow)
Recommendation 9: If the design allows it, stitching VIAs can be used on the power planes, close to the module
in order to help with cooling. This is a thermal consideration and does not matter much for the electrical
design.
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Recommended PCB Footprint
Figure 21: Recommended PCB Footprint
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Data Sheet | Intel Enpirion Power Solutions: EM2120
30% Solder Stencil Aperture (see note below)
Figure 22: 30% Solder Stencil Aperture Dimensions
Notes:
•
•
The solder stencil for each pad under the device is recommended to be up to 30% of the total pad
size.
The aperture dimensions are based on a 4mil stencil thickness.
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Data Sheet | Intel Enpirion Power Solutions: EM2120
Package Dimensions
Figure 23: Package Dimensions
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Tray Information
Figure 24: Tray Information 1/2
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Data Sheet | Intel Enpirion Power Solutions: EM2120
Tray Information (Continued)
Figure 25: Tray Information 2/2
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Data Sheet | Intel Enpirion Power Solutions: EM2120
Revision History
Rev
A
Date
Change(s)
Mar - 17
Initial Release
B
May - 17
Added Rtune table for EM2120H
Removed old Table 12 and Figure 7, updated the Output Capacitor
Recommendation section.
Updated for new POK functionality.
C
Sept - 17
Updated RVSET Table
Corrected some text errors
D
Nov - 17
Updated POK description
Corrected some text errors
E
Jun - 18
No Change
F
Jun - 18
Updated POK description, PMBus Introduction and note on Watchdog Timer
G
Jul - 18
Added the solder stencil options for 30% & 45% opening
H
Mar - 20
Added information relating to SMBALERT, removed stencil option for 45%
opening
Where to Get More Information
For more information about Intel and Intel Enpirion PowerSoCs, visit https://www.altera.com/enpirion
© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
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