EN5311QI

Enpirion® Power Datasheet EN5311QI 1A PowerSoC Synchronous Buck Regulator With Integrated Inductor Product Overview Featuring Integrated Inductor Technology The Ultra-Low-Profile EN5311QI is targeted to applications where board area and profile are critical. EN5311QI is a complete power conversion solution requiring only two low cost ceramic MLCC caps. Inductor, MOSFETS, PWM, and compensation are integrated into a tiny 5mm x 4mm x 1.1mm QFN package. The EN5311QI is engineered to simplify design and to minimize layout constraints. 4 MHz switching frequency and internal type III compensation provides superior transient response. With a 1.1 mm profile, the EN5311QI is ideal for space and height constrained applications. VIN UVLO Thermal Limit Current Limit ENABLE Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive GND VSENSE Sawtooth Generator Compensation Network (-) Switch Error Amp VFB (+) DAC VREF A 3-pin VID output voltage selector provides seven pre-programmed output voltages along with an option for external resistor divider. Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling. Voltage Select Package Boundry VS0 VS1 VS2 Product Highlights Typical Application Circuit • Revolutionary Integrated Inductor • 5mm x 4mm x1.1mm QFN package • Very small total solution foot print* • 4 MHz switching frequency • Only two low cost MLCC caps required • Designed for low noise/low EMI • Very low ripple voltage; 5mV p-p Typical • High efficiency, up to 95% • Wide 2.4V to 6.6V input range • 1000mA continuous output current • Less than 1 µA standby current. • Excellent transient performance • 3 Pin VID Output Voltage select • External divider: 0.6V to V IN -V dropout • 100% duty cycle capable • Short circuit and over current protection • UVLO and thermal protection • RoHS compliant; MSL 3 260°C reflow VIN 4.7µF VOLTAGE SELECT VOUT VOUT EN5311QI VS0 VS1 VS2 COUT VFB GND Figure 1. Typical application circuit. Applications • • • • • • • Area constrained applications Noise Sensitive Applications such as A/V and RF LDO replacement for improved thermals Set top box/home gateway Smart phones, PDAs VoIP and Video phones Personal Media Players 1 03799 ENABLE VSENSE VIN December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Pin Description other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. VSENSE (Pin 15): Sense pin for output voltage regulation. Connect V SENSE to the output voltage rail as close to the terminal of the output filter capacitor as possible. VFB (Pin 16): Feedback pin for external divider option. When using the external divider option (VS0=VS1=VS2= high) connect this pin to the center of the external divider. Set the divider such that V FB = 0.603V. VS0,VS1,VS2 (Pin 17,18,19): Output voltage select. VS0=pin19, VS1=pin18, VS2=pin17. Selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. Logic low is defined as V LOW ≤ 0.4V. Logic high is defined as V HIGH ≥ 1.4V. Any level between these two values is indeterminate. Figure 2. Pin description, top view. VIN (Pin 1,2): Input voltage pin. power to the IC. Supplies Input GND: (Pin 3): Input power ground. Connect this pin to the ground terminal of the input capacitor. Refer to Layout Recommendations for further details. ENABLE (Pin 20): Output enable. Enable = logic high, disable = logic low. Logic low is defined as V LOW ≤ 0.2V. Logic high is defined as V HIGH ≥ 1.4V. Any level between these two values is indeterminate. Output GND: (Pin 4): Power ground. The output filter capacitor should be connected between this pin and V OUT . Refer to Layout recommendations for further detail. Bottom Thermal Pad: Device thermal pad to remove heat from package. Connect to PCB surface ground pad and PCB internal ground plane (see layout recommendations). VOUT (Pin 5,6,7): Regulated output voltage. NC (Pin 8,9,10,11,12,13,14): These pins should not be electrically connected to each 2 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Functional Block Diagram VIN UVLO Thermal Limit Current Limit ENABLE Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive GND VSENSE Sawtooth Generator Compensation Network (-) Switch Error Amp VFB (+) DAC Voltage Select VREF Package Boundry VS0 VS1 VS2 Figure 3. Functional Block Diagram. 3 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER Input Supply Voltage Voltages on: ENABLE, V SENSE , V S0 -V S2 Voltage on: V FB Storage Temperature Range Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A ESD Rating (based on Human Body Model) SYMBOL MIN MAX UNITS V IN -0.3 -0.3 -0.3 -65 7.0 V IN + 0.3 2.7 150 260 2000 V V V °C °C V T STG Recommended Operating Conditions PARAMETER SYMBOL Input Voltage Range (VID) V IN 1 Input Voltage Range (External Divider (VFB)) V IN Output Voltage Range V OUT Output Current I OUT Operating Ambient Temperature TA Operating Junction Temperature TJ 1. See Section “Application Information” for specific circuit requirements MIN MAX UNITS 2.4 2.4 0.6 0 -40 -40 5.5 6.6 V IN -0.6 1000 +85 +125 V V V mA °C °C Thermal Characteristics PARAMETER Thermal Resistance: Junction to Ambient (0 LFM) Thermal Resistance: Junction to Case (0 LFM) Thermal Shutdown Thermal Shutdown Hysteresis 4 03799 December 14, 2015 SYMBOL TYP UNITS θ JA θ JC T J-TP 65 15 +150 15 °C/W °C/W °C °C www.altera.com/enpirion Rev G EN5311QI Electrical Characteristics NOTE: T A = 25°C unless otherwise noted. Typical values are at V IN = 3.6V, C IN = 4.7µF, C OUT =10µF. NOTE: V IN must be greater than V OUT + 0.6V. PARAMETER Operating Input Voltage SYMBOL Under Voltage Lockout UVLO Hysteresis V UVLO V OUT Initial Accuracy (VID) V IN V OUT V OUT Variation for all Causes (VID) V OUT Feedback Pin Voltage V FB Feedback Pin Voltage V FB Feedback Pin Input Current Dynamic Voltage Slew † Rate Output Current Shut-Down Current Quiescent Current I FB TEST CONDITIONS Using VID 1 Using External Divider (VFB) VIN going low to high 2.4V ≤ V IN ≤ 5.5V, I LOAD = 100mA; T A = 25C 2.4V ≤ VIN ≤ 5.5V, ILOAD = 0 - 1A, T A = -40°C to +85°C 2.4V ≤ V IN ≤ 6.6V, I LOAD = 100mA TA = 25C; VSO=VS1=VS2=1 2.4V ≤ VIN ≤ 6.6V, ILOAD = 0 - 1A, T A = -40°C to +85°C; VSO=VS1=VS2=1 PFET OCP Threshold I LIM VS0-VS1 Thresholds V TH VS0-VS2 Pin Input Current I VSX Enable Voltage Threshold TYP 2.2 0.145 MAX 5.5 6.6 2.3 -2.0 +2.0 % -3.0 +3.0 % 0.591 0.603 0.615 0.585 0.603 0.621 1.24 1.65 1.4 2.1 V/ms mA µA µA 2 A 0.0 1.4 0.4 V IN 0.0 1.4 Enable Pin Input Current I EN Operating Frequency F OSC PFET On Resistance R DS(ON) NFET On Resistance R DS(ON) Typical inductor DCR Soft-Start Operation † 2 V OUT Soft Start Slew Rate VID Mode 1.24 ∆V SS 2 Soft Start Rise Time VFB mode 0.80 ∆T SS 1. See Section “Application Information” for specific circuit requirements 2. Measured from when V IN ≥ V UVLO & ENABLE pin crosses its logic High threshold V 0.75 800 1 Logic Low Logic High V IN = 3.6V V nA 1000 Enable = Low No switching 2.4V ≤ V IN ≤ 6.6V, 0.6V ≤ V OUT ≤ V IN – 0.6V Pin = Low Pin = High UNITS V V V V 1 V slew I OUT I SD MIN 2.4 2.4 nA 0.2 V IN µA MHz mΩ mΩ Ω 2 4 340 270 .110 1.65 1.10 V 2.1 1.40 V/ms ms † Parameter guaranteed by design. 5 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Typical Performance Characteristics Efficiency Vs. Load Current (Vin = 3.3V) 95 100 90 95 Efficency (%) Efficency (%) Efficiency Vs. Load Current (Vin = 5.0V) 85 80 75 70 65 60 55 90 85 80 75 70 65 60 55 50 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 Load Current (A) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Load Current (A) Top to Bottom: V OUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V Top to Bottom: V OUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V Output Ripple: V IN = 5.0 V Output Ripple: V IN = 3.3 V V OUT = 1.2V, I LOAD = 1A, C OUT = 1 x 10µF 0805 V OUT = 1.2V, I LOAD = 1A, C OUT = 1 x 10µF 0805 6 03799 0.1 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Detailed Description short circuit protection, and thermal overload protection. Functional Overview The EN5311QI is a complete DCDC converter solution requiring only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency, low ripple, and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a high switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The high switching frequency enables the use of very small components making possible this unprecedented level of integration. Integrated Inductor Altera has introduced the world’s first product family featuring integrated inductors. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. Soft Start Altera Enpirion’s proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. Unique magnetic design allows for integration of the inductor into the very low profile 1.1mm package. Integration of the inductor virtually eliminates the design/layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster integration into various applications to meet demanding EMI requirements. Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The EN5311QI operates in a constant slew rate when the output voltage is programmed with an internal VID code. The EN5311QI, when in external resistor divider mode, has a constant start up time. Please refer to the Electrical Characteristics table for soft-start slew rates and soft-start time Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in the 0.6V to V IN 0.6V range. This reduces the number of components that must be qualified and reduces inventory burden. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling. Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Assuming no-load at startup, the maximum total capacitance on the output, including the output filter capacitor, bulk and decoupling capacitance, at the load, is given as: In VID Mode: Protection features include under-voltage lockout (UVLO), over-current protection (OCP), C OUT_TOTAL_MAX = C OUT_Filter + C OUT_BULK = 700µF 7 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. In external divider mode: C OUT_TOTAL_MAX = 1.22x10-3/V OUT Farads See the applications section for more details. Enable Startup into Pre-Bias The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. In shutdown mode, the device quiescent current will be less than 1 µA. The EN5311QI supports startup into a prebiased output of up to VOUT. The output of the EN5311QI can be pre-biased with a voltage up to VOUT when it is first enabled. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense PMOSFET which is compared to a reference current. When this level is exceeded the PFET is turned off and the N-FET is turned on, pulling V OUT low. This condition is maintained for a period of 1ms and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat in a “hick-up” mode. NOTE: This pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 15C°, the device will go through the normal startup process. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching Application Information Output Voltage Select control loop that causes the device to behave abnormally and damage may occur. To provide the highest degree of flexibility in choosing output voltage, the EN5311QI uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. Since VFB is a sensitive node, do not touch the VFB node while the device is in operation as doing so may introduce parasitic capacitance into the Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to V IN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to V IN or GND or alternatively can be driven by standard logic levels. Logic low is defined as V LOW ≤ 0.4V. Logic high is defined as V HIGH ≥ 1.4V. Any level between these two values is indeterminate. These pins must not be left floating. The External Voltage Divider pin, V FB, may be left floating for all VID settings other than the VS0=VS1=VS2= ”1”. 8 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI V OUT can be programmed over the range of 0.6V to V IN – 0.6V (0.6 is the nominal full load dropout voltage including margin). Table 1. VID voltage select settings. VS1 0 0 1 1 0 0 1 1 VS0 0 1 0 1 0 1 0 1 V OUT 3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V User Selectable VS0 VS1 VS2 VS0 VS1 VS2 EN5311QI 4.7uF Rb GND > 5.5V). Dynamic transitioning between internal VID settings and the external divider is not allowed. Vout COUT Input and Output Capacitors VFB The input capacitance requirement is 4.7µF. Altera recommends that a low ESR MLCC capacitor be used. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input and output filter applications. Rb GND Figure 4. External Divider (V IN ≤ 5.5V). The output voltage is selected by the following formula: ) VOUT = 0.603V (1 + Ra Rb R a must be chosen as 200KΩ to maintain loop gain. Then R b is given as: Rb = VFB The EN5311QI is designed to allow for dynamic switching between the predefined VID voltage levels. The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the softstart slew rate of 1.65V/ms. VOUT Ra COUT Dynamically Adjustable Output Figure 5 indicates the required connections for V IN > 5.5V. Vin Ca Ra 27pF For applications where V IN > 5.5V, the V SENSE connection is not necessary, but the addition of C A = 27pF is required. For applications with V IN ≤ 5.5V, VSENSE must be connected to VOUT as indicated in Figure 4. VSense VOUT Vout Figure 5. External Divider (V IN As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to V IN or logic “high”. The EN5311QI uses a separate feedback pin, VFB, when using the external divider. ENABLE Vin 4.7uF External Voltage Divider VIN VSense ENABLE VIN EN5311QI VS2 0 0 0 0 1 1 1 1 The output capacitance minimum requirement depends on the output voltage setting. The following table shows the recommended minimum output capacitance for a given output voltage. 1.2 x10 5 Ω VOUT − 0.603 Table 2. Recommended Output Capacitance VOUT 9 03799 December 14, 2015 C OUT Size (EIA) www.altera.com/enpirion Rev G 1V 1.8V 3.3V 10 µF 10 µF 47 µF EN5311QI mode DC-DC converter input and output filter applications. 0805 0805 0805 Table 3. Input Capacitor Recommendations The control loop is designed to be stable with up to 60µF of total output capacitance next to the output pins of the device without requiring modification to the compensation network. V OUT has to be sensed at the last output filter capacitor next to the device. Altera recommends a low ESR MLCC type capacitor be used. Additional capacitance may be added to improve load transient response. Description 4.7µF, 10V, X5R, 0805 10µF, 10V, X5R, 0805 MFG Taiyo Yuden Murata Taiyo Yuden Murata P/N LMK107BJ475KA-T GRM185R61A475KE11# LMK212ABJ106KG GRM21BR61A106KE19 Table 4. Output Capacitor Recommendations Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the V OUT Sense point and the bulk capacitance. The separation provides an inductance that isolates the control loop from the bulk capacitance. Description 10µF, 10V, X5R, 0805 22µF, 10V, X5R, 0805 Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup. Refer to the section on Soft-Start for the maximum total capacitance on the output. 47µF, 6.3V, X5R, 0805 MFG Taiyo Yuden Murata Taiyo Yuden Murata Taiyo Yuden Murata P/N LMK212ABJ106KG GRM21BR61A106KE19 LMK212BBJ226MG-T GRM21BR61A226ME51 JMK212BBJ476MG-T GRM21BR60J476ME15 Power-Up Sequencing The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch- During power-up, ENABLE should not be asserted before VIN. Tying these pins together meets these requirements. LAYOUT CONSIDERATIONS* *Optimized PCB Layout file downloadable from the Altera Enpirion Website to assure first pass design success. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN5311QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN5311QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground pad for the input and output filter capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5. 10 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect ground terminals of the Input capacitor and the output capacitor to the system ground plane. This provides a low inductance path for the high-frequency AC currents; thereby reducing ripple and suppressing EMI (see Fig. 6, Fig. 7, and Fig. 8). Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for heat dissipation from the converter. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (PCB layer 2). This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the EN5311QI and its input and output capacitors. The vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as well. Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package. Recommendation 7: The VOUT sense point should be just after the last output filter capacitor next to the device. Keep the sense trace short in order to avoid noise coupling into the node. Recommendation 8: Keep R a , C a , and R b close to the VFB pin (see Figures 4 and 5). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R b directly to the GND pin instead of going through the GND plane. Figure 6 shows an example schematic for the EN5311QI using the internal voltage select. In this example, the device is set to a VOUT of 1.5V (VS2=0, VS1=1, VS0=1). VFB VSENSE NC NC NC NC 15 14 13 12 11 NC 7 VOUT Rb=60K Ra=200K 6 VOUT VOUT VOUT VOUT 5 8 20 4 19 3 VS0 ENABLE GND NC 6 NC 9 GND NC 11 16 NC 12 5 VOUT 10 18 2 NC 13 VOUT NC 17 VS1 1 NC 14 4 7 3 8 20 GND 19 GND VS0 ENABLE VS2 VIN VFB VSENSE 15 NC 2 VS1 1 NC 9 VIN 10 18 VIN 17 VIN VS2 16 Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The resistor values are chosen to give an output voltage of 2.6V. VOUT VIN VIN 4.7uF 10µF (see layout recommendation 3) Figure 6. Example application, Vout=1.5V. 4.7uF 10µF (see layout recommendation 3) Figure 7. Example Application, external divider, Vout = 2.6V. Figure 8 shows an example board layout. The left side of the figure demonstrates construction of the PCB top layer. Note the placement of the vias from the input and output filter capacitor grounds, and 11 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI the thermal pad, to the PCB ground on layer 2 (1 layer below PCB surface). The right side of the figure shows the layout with the components populated. Note the placement of the vias per recommendation 3. st Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to PCB system ground. Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom of Package Altera has developed a break-through in package technology that utilizes the lead frame as part of the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, it does require some special considerations. As part of the package assembly process, lead frame construction requires that for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the large thermal pad and the perimeter pin pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN5311QI should be clear of any metal except for the large thermal pad. The “grayed-out” area in Figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10. 12 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Thermal Pad. Connect to Ground plane Figure 9. Exposed metal and mechanical dimensions of the package. Gray area represents bottom metal noconnect and area that should be clear of any traces, planes, or vias, on the top layer of the PCB. Figure 10. Exposed pad clearances; the Altera Enpirion lead frame package complies with JEDEC requirements. 13 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Figure 11. Recommended solder mask opening. 14 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Figure 12. Package mechanical dimensions. 15 03799 December 14, 2015 www.altera.com/enpirion Rev G EN5311QI Ordering Information Part Number Temp Range EN5311QI EVB-EN5311QI -40°C to +85°C Package QFN20 Evaluation Board Tape & Reel Contact Information Altera Corporation 101 Innovation Drive San Jose, CA 95134 Phone : 408-544-7000 www.altera.com © 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 16 03799 December 14, 2015 www.altera.com/enpirion Rev G