EN5319QI

DataSheeT – enpirion® power solutions EN5319QI 1.5A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION FEATURES The EN5319QI is an Intel® Enpirion® Power System on a Chip (PowerSoC) DC-DC converter. The device features an advance integrated inductor, integrated MOSFETs, a PWM voltage-mode controller, and internal compensation providing the smallest possible solution size. • Integrated Inductor The EN5319QI is a member of the EN53x9QI family of pin compatible and interchangeable devices. The pin compatibility enables an easy to use scalable family of products covering the load range from 1.5A up to 3A in a low profile 4mm x 6mm x 1.1mm QFN package. • Low Output Ripple Voltage; 3.3V 6.8 Ra (kΩ) Cout (µF) 348 1x22uF/0805 348 2x22uF/0603 348 2x22uF/0805 Note: Follow Layout Recommendations Page 17 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI THERMAL CONSIDERATIONS Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated needs to be accounted for. Intel’s Enpirion PowerSoCTM helps alleviate some of those concerns. Intel’s Enpirion EN5319QI DC-DC converter is packaged in a 4x6x1.1mm 24-pin QFN package. The QFN package is constructed with exposed thermal pads on the bottom of the package. The exposed thermal pad should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150°C. The EN5319QI is guaranteed to support the full 1.5A output current up to 85°C ambient temperature. The following example and calculations illustrate the thermal performance of the EN5319QI. Example: VIN = 5V VOUT = 3.3V IOUT = 1.5A First calculate the output power. POUT = 3.3V x 1.5A = 4.95W Next, determine the input power based on the efficiency (η) shown in Figure 7. 100 90 EFFICIENCY (%) 80 ~94% 70 60 50 40 30 20 CONDITIONS VIN = 5V VOUT = 3.3V 10 0 0 0.25 0.5 0.75 1 1.25 1.5 OUTPUT CURRENT (A) Figure 7: Efficiency vs. Output Current Page 18 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI For VIN = 5V, VOUT = 3.3V at 1.5A, η ≈ 94% η = POUT / PIN = 94% = 0.94 PIN = POUT / η PIN ≈ 4.95W / 0.94 ≈ 5.3W The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN – POUT ≈ 5.3W – 4.95W ≈ 0.35W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN5319QI has a θJA value of 36°C/W without airflow. Determine the change in temperature (ΔT) based on PD and θJA. ΔT = PD x θJA ΔT ≈ 0.35W x 36°C/W = 12.6°C ≈ 13°C The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in temperature. We assume the initial ambient temperature to be 25°C. TJ = TA + ΔT TJ ≈ 25°C + 13°C ≈ 38°C The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated. TAMAX = TJMAX – PD x θJA ≈ 125°C – 13°C ≈ 112°C The ambient temperature can actually rise by another 87°C, bringing it to 112°C before the device will reach TJMAX. This indicates that the EN5319QI can support the full 1.5A output current range up to approximately 112°C ambient temperature given the input and output voltage conditions. Note that the efficiency will be slightly lower at higher temperatures and these calculations are estimates. Page 19 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI ENGINEERING SCHEMATIC Figure 8. Engineering Schematic with Critical Components Page 20 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI LAYOUT RECOMMENDATIONS This layout only shows the critical components and top layer traces for minimum footprint with ENABLE as a separate signal. Alternate ENABLE configurations & the POK pin need to be connected and routed according to customer application. Please see the Gerber files on EN5319QI’s product page at www.altera.com/powersoc for details on all layers. Figure 9: Optimized Layout Rommendations Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN5319QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The Voltage and GND traces between the capacitors and the EN5319QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Recommendation 3: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 9 this connection is made at the input capacitor. Place a 1µF capacitor from the AVIN pin to AGND right next to device pins. Page 21 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 8. See the section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. Recommendation 8: Keep RA, CA, RB close to the VFB pin (See Figures 6). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R B directly to the AGND pin instead of going through the GND plane. Page 22 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES Exposed Metal on Bottom of Package QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the package that provide improved thermal dissipation, lower package thermal resistance, smaller package footprint and thickness, larger lead size and pitch, and excellent lead co-planarity. As the EN5319QI package is a fully integrated module consisting of multiple internal devices, the lead-frame provides circuit interconnection and mechanical support of these devices resulting in multiple exposed metal pads on the package bottom. Only the two large thermal pads and the perimeter leads are to be mechanically/electrically connected to the PCB through a SMT soldering process. All other exposed metal is to remain free of any interconnection to the PCB. Figure 10 shows the recommended PCB metal layout for the EN5319QI package. A GND pad with a solder mask "bridge" to separate into two pads and 24 signal pads are to be used to match the metal on the package. The PCB should be clear of any other metal, including traces, vias, etc., under the package to avoid electrical shorting. The Solder Stencil Aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Please consult EN5319QI Soldering Guidelines for more details and recommendations. Figure 10: Lead-Frame exposed metal (Top View) Note: Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. Page 23 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI RECOMMENDE PCB FOOTPRINT Figure 11: Landing Pattern with Solder Stencil (Top View) The solder stencil aperture for the thermal pads (shown in blue) is based on Intel Enpirion’s manufacturing recommendations Page 24 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI PACKAGE DIMENSIONS Figure 12: EN5319QI Package Dimensions (Bottom View) Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html Page 25 08325 September 24, 2018 Rev E Datasheet | Intel® Enpirion® Power Solutions: EN5319QI REVISION HISTORY Rev E Date August 2018 Change(s) • Changed datasheet into Intel format. WHERE TO GET MORE INFORMATION For more information about Intel® and Enpirion® PowerSoCs, visit: www.altera.com/enpirion © 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. Page 26 08325 September 24, 2018 Rev E