DataSheeT – enpirion® power solutions
EN5337QI 3A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
FEATURES
The EN5337QI is a Power Supply on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, all small-signal circuits, compensation, and
the inductor in an advanced 4mm x 7mm QFN
package.
•
•
•
•
•
The EN5337QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards, and system
level applications in distributed power architectures.
Advanced circuit techniques, ultra high switching
frequency, and very advanced, high-density,
integrated circuit and proprietary inductor
technology deliver high-quality, ultra compact, nonisolated DC-DC conversion.
Intel Enpirion solution significantly helps in system
design and productivity by offering greatly simplified
board
design,
layout
and
manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
Intel Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
•
•
•
•
•
•
Integrated INDUCTOR, MOSFETS, Controller
Total Power Solution ≈ 75mm2
Minimal external components.
3A Continuous Output Current Capability
5MHz operating frequency. Switching frequency
can be phase locked to an external clock.
High efficiency, up to 92%.
Wide input voltage range of 2.375V to 5.5V.
Output Enable pin and Power OK signal.
Programmable soft-start time.
Under Voltage Lockout, Over Current, Short
Circuit and Thermal Protection.
RoHS compliant, MSL level 3, 260C reflow.
APPLICATIONS
•
•
•
•
•
•
POL for low-power processors, network
processors, DSPs, FPGAs, and ASICs
Noise sensitive applications such as A/V, RF and
Gbit I/O
Low voltage, distributed power architectures.
Computing, Networking, DSL, STB, DVR, DTV, iPC
Ripple sensitive applications
Beat frequency sensitive applications
ENA
22µF
1206
AVIN
PGND
SS
AGND
VOUT
XFB
VOUT
90
85
RA
80
CA
47µF
1206
PGND
RB
EFFICIENCY (%)
PVIN
EN5337QI
Efficiency vs. Output Current
VIN
75
70
65
60
VOUT= 2.5V
55
50
Figure 1. Typical Application Schematic
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
2.5
3
Figure 2. Efficincy at VIN =5V
Page 1
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
ORDERING INFORMATION
Part Number
Package Markings
TJ Rating
Package Description
EN5337QI
EN5337QI
-40°C to +125°C
38-pin (4mm x 7mm x 1.85mm) QFN
EN5337QI-E
EN5337QI
QFN Evaluation Board
Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html
NC(SW)
NC(SW)
NC(SW)
NC(SW)
NC(SW)
AVIN
AGND
XFB
SS
EAOUT
POK
ENABLE
SYNC
PIN FUNCTIONS
38
37
36
35
34
33
32
31
30
29
28
27
26
NC(SW)
1
25
NC
NC(SW)
2
24
NC
NC
3
23
NC
NC
4
22
NC
VOUT
5
21
PVIN
VOUT
6
20
PVIN
7
8
9
10
11
12
13
14
15
16
17
18
19
VOUT
VOUT
VOUT
VOUT
VOUT
NC(SW)
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
EN5337QI
Figure 3. Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Black ‘dot’ on top left is pin 1 indicator on top of the device package.
Page 2
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
PIN DESCRIPTIONS
PIN
1-2,
12, 3438
NAME
NC(SW)
TYPE
FUNCTION
-
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. They are not to be electrically
connected to any external signal, ground, or voltage. Failure to follow this
guideline may result in damage to the device.
3-4,
22-25
NC
-
NO CONNECT – These pins may be internally connected. Do not connect
them to each other or to any other electrical signal. Failure to follow this
guideline may result in device damage.
5-11
VOUT
Power
Regulated converter output. Connect these pins to the load and place
output capacitor from these pins the PGND pins 17-18
13-18
PGND
Power
Input/Output power ground. Connect these pins to the ground electrode
of the Input and output filter capacitors. See VOUT and PVIN pin
descriptions for more details.
19-21
PVIN
Power
Input power supply. Connect to input power supply. Decouple with input
capacitor to PGND (pins 16-18).
26
SYNC
Digital
External Clock Input to synchronize internal switching clock to an
external signal
27
ENABLE
Analog
Input Enable. Applying logic high enables the output and initiates a softstart. Applying a logic low disables the output.
28
POK
Analog
Power OK is an open drain transistor for power system state indication.
POK is a logic high when VOUT is with -10% to +20% of VOUT nominal.
29
EAOUT
Analog
Optional Error Amplifier output. Allows for customization of the control
loop.
30
SS
Analog
Soft-Start node. The soft-start capacitor is connected between this pin
and AGND. The value of this resistor determines the startup timing.
31
XFB
Analog
External Feedback Input. The feedback loop is closed through this pin. A
voltage divider at VOUT is used to set the output voltage. The mid point
of the divider is connected to XFB. A phase lead capacitor from this pin to
VOUT is also required to stabilize the loop.
32
AGND
Power
Analog Ground. This is the Ground return for the controller. Needs to be
connected to a quiet ground.
33
AVIN
Power
Input power supply for the controller. Needs to be connected to input
voltage at a quiet point.
Page 3
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
PVIN, AVIN, VOUT
-0.5
6.0
V
ENABLE, POK
-0.5
VIN
V
XFB, EAOUT, SYNC, SS
-0.5
2.5
V
MIN
MAX
UNITS
+150
°C
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
Maximum Operating Junction
Temperature
Storage Temperature Range
-65
+150
°C
Ambient Temperature Range
-40
+85
°C
+260
°C
MAX
UNITS
Reflow Peak Body Temperature
(10 Sec) MSL3 JEDEC J-STD-020A
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.375
5.5
V
Output Voltage Range
VOUT
0.60
VIN – VDO (1)
V
Output Current Range
IOUT
3
A
Operating Ambient Temperature Range
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Input Voltage Range
(1) VDO (drop-out voltage) is defined as (ILOAD x Dropout Resistance). Please see Electrical Characteristics table.
Page 4
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
TSD
150
°C
TSDHYS
20
°C
Thermal Resistance: Junction to Ambient (0 LFM) (2)
θJA
30
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
3
°C/W
Thermal Shutdown
Thermal Shutdown Hysteresis
(2) Based on a four layer copper board and proper thermal design in line with JEDEC EIJ/JESD51 standards.
ELECTRICAL CHARACTERISTICS
NOTE: VIN = 5.5V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.
PARAMETER
Operating Input Voltage
SYMBOL
TEST CONDITIONS
VIN
MIN
TYP
2.375
MAX
UNITS
5.5
V
Under Voltage Lock-out –
VIN Rising
VUVLOR
Voltage above which UVLO
is not asserted
2.2
V
Under Voltage Lock-out –
VIN Falling
VUVLOF
Voltage below which UVLO
is asserted
2.1
V
ENABLE=0V
100
µA
Shut-Down Supply
Current
IS
Feedback Pin Voltage
VXFB
Feedback node voltage –
factory setting – TA = 25°C
Feedback pin Input
Leakage Current (3)
IXFB
XFB pin input leakage
current
0.735
0.75
-5
0.765
V
5
nA
Line Regulation
∆VOUT_LINE
2.375V ≤ VIN ≤ 5.5V
0.02
%/V
Load Regulation
∆VOUT_LOAD
0A ≤ ILOAD ≤ 3A
-0.03
%/A
Temperature Regulation
∆VOUT_TEMP
-40°C ≤ TEMP ≤ 85°C
0.003
%/°C
VOUT Rise Time
Rise Time Accuracy (3)
Output Drop Out Voltage
Resistance (3)
tRISE
∆TRISE
VDO
RDO
Measured from when VIN ≥
VUVLOR & ENABLE pin voltage
crosses logic high threshold.
(4.7nF ≤ CSS ≤ 100nF)
4.7nF ≤ CSS ≤ 100nF
VINMIN - VOUT at Full load
Input to Output Resistance
CSS X 67
kΩ
-25
250
83
+25
%
500
167
mV
mΩ
Page 5
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
PARAMETER
Maximum Continuous
Output Current
Over Current Trip Level
SYMBOL
IOCP
VDISABLE
ENABLE Threshold
VENABLE
ENABLE pin Input Current
(3)
Switching Frequency
(Free Running)
MIN
TYP
MAX
3
IOUT_Max
Disable Threshold
ENABLE Lock-out time
TEST CONDITIONS
A
4.5
ENABLE pin logic low.
ENABLE pin logic high
2.375V ≤ VIN ≤ 5.5V
TENLO
Time for device to re-enable
after a falling edge on
ENABLE pin
IENABLE
ENABLE pin has ~80kΩ pull
down
FSW
Free Running frequency of
oscillator
UNITS
A
0.0
0.8
V
1.8
VIN
V
700
µS
70
5
µA
MHz
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock
frequency
SYNC Input Threshold –
Low
VSYNC_LO
SYNC Clock Logic Level
SYNC Input Threshold –
High
VSYNC_HI
SYNC Clock Logic Level
POK Threshold
POKTH
Output voltage as a fraction
of expected output voltage
POK Output Low Voltage
VPOKL
With 4mA current sink into
POK
0.4
V
POK Output Hi Voltage
VPOKH
2.375V ≤ VIN ≤ 5.5V
VIN
V
POK pin VOH Leakage
Current (3)
IPOKL
POK high
1
µA
4.5
1.8
5.5
MHz
0.8
V
2.5
V
90
%
(3) Parameter guaranteed by design.
Page 6
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
TYPICAL PERFORMANCE CURVES
Efficiency VIN = 3.3V
VOUT (From top to bottom) = 2.5, 1.8, 1.2, 1.0, 0.75V
Efficiency VIN = 5.0V
VOUT (From top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0, 0.75V
Drop-Out Voltage
Page 7
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
TYPICAL PERFORMANCE CHARACTERISTICS
Note: CIN = 22µF, COUT = 47µF/1206 + 10µF/0805, Slew Rate ≥ 10A/µS, 15nF Soft-Start Capacitor
500 MHz BW
20 MHz BW limit
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Iout = 3A
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Iout = 3A
500 MHz BW
20 MHz BW limit
Output Ripple: VIN = 5V, VOUT = 1.2V, Iout = 3A
Output Ripple: VIN = 5V, VOUT = 1.2V, Iout = 3A
Page 8
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
VOUT
VOUT
ILOAD
ILOAD
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load Transient: VIN = 3.3V, VOUT = 1.2V
VOUT
VOUT
ENABLE
ENABLE
POK
POK
Power Up/Down at No Load: VIN/VOUT = 5.0V, 1.2V
Power Up/Down into 0.4Ω load: VIN/VOUT = 5.0V, 1.2V
Enable Lock-out Time
Page 9
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
FUNCTIONAL BLOCK DIAGRAM
PVIN
EN5337QI
UVLO
Thermal Limit
Current Limit
Over Voltage
NC(SW)
P-Drive
VOUT
(-)
N-Drive
PWM
Comp
(+)
SYNC
PGND
Compensation
Network
PLL / Sawtooth
Generator
(-)
EAOUT
XFB
Error
Amp
(+)
ENABLE
power
Good
Logic
POK
AVIN
SS
Soft Start
Voltage
Reference
EAOUT
Regulated
Voltage
AGND
Figure 4. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN5337QI is a synchronous, programmable power supply with integrated power MOSFET switches and
integrated inductor. The nominal input voltage range is 2.375V to 5.5V. The output voltage is programmed
using an external resistor divider network. The control loop is voltage-mode with a type III compensation
network. Much of the compensation circuitry is internal to the device. However, a phase lead capacitor is
required along with the output voltage feedback resistor divider to complete the type III compensation
network. The device uses a low-noise PWM topology. Up to 3A of continuous output current can be drawn
from this converter. The 5MHz switching frequency allows the use of small size input / output capacitors, and
realizes a wide loop bandwidth within a small foot print.
Page 10
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
The power supply has the following protection features:
•
•
•
•
Over-current protection (to protect the IC from excessive load current)
Thermal shutdown with hysteresis
Over-voltage protection
Under-voltage lockout circuit to disable the converter output when the input voltage is less than
approximately 2.2V
Additional features include:
•
•
•
The switching frequency can be phase-locked to an external clock to eliminate or move beat
frequency tones out of band.
Soft-start circuit, limiting the in-rush current when the converter is initially powered up. The soft start
time is programmable with appropriate choice of soft start capacitor value.
Power good circuit indicating the output voltage is between 90% and 120% of programmed value as
long as the feedback loop is closed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN.
The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered
down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up
or power down meets these requirements.
Enable Operation
The ENABLE pin provides a means to enable normal operation or to shut down the device. Applying logic high
will enable the converter into normal operation. When the ENABLE pin is asserted (high) the device will
undergo a normal soft start. A logic low will disable the converter. A logic low will power down the device in a
controlled manner and the device is subsequently shut down. The device will remain shut-down for the
duration of the ENABLE lockout time (see Electrical Characteristics Table). If the ENABLE signal is re-asserted
during this time, the device will power up with a normal soft-start at the end of the ENABLE lockout time.
Pre-Bias Start-up
The EN5337QI supports startup into a pre-biased output of up to 1.5V. The output of the EN5337QI can be
pre-biased with a voltage up to 1.5V when it is first enabled.
Frequency Synchronization
The switching frequency of the DC-DC converter can be phase-locked to an external clock source to move
unwanted beat frequencies out of band. To avail this feature, the clock source should be connected to the
SYNC pin. An activity detector recognizes the presence of an external clock signal and automatically phaselocks the internal oscillator to this external clock. Phase-lock will occur as long as the input clock frequency
is in the range
of 4.5 to 5.5 MHz. When no clock signal is present, the device reverts to the free running frequency of the
internal oscillator.
Spread Spectrum Mode
The external clock frequency may be swept between 4.5 MHz and 5.5 MHz at repetition rates of up to 10 kHz
in order to reduce EMI frequency components.
Page 11
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
Soft-Start Operation
Soft start is a means to reduce the in-rush current when the device is enabled. The output voltage is ramped
up gradually upon start-up. The output rise time is controlled by the choice of soft-start capacitor, which is
placed between the SS pin (pin 30) and the AGND pin (pin 32).
Rise Time: TR ≈ (Css* 67kΩ) ± 25%
During start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final
level by an internal current source of approximately 10uA. The soft start capacitor should be between 4.7nF
and 100nf. Typical soft-start rise time is ~1mS with SS capacitor value of 15nF. The rise time is measured from
when VIN ≥ VUVLOR and ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its
programmed value.
POK Operation
The POK signal is an open drain signal (requires a pull up resistor to VIN or similar voltage) from the converter
indicating the output voltage is within the specified range. The POK signal will be logic high (VIN) when the
output voltage is above 90% of programmed VOUT. If the output voltage goes below this threshold, the POK
signal will be at logic low.
Over-Current Protection
The current limit function is achieved by sensing the current flowing through the Power PFET. When the
sensed current exceeds the over current trip point, both power FETs are turned off for the remainder of the
switching cycle. If the over-current condition is removed, the over-current protection circuit will enable normal
PWM operation. If the over-current condition persists, the soft start capacitor will gradually discharge causing
the output voltage to fall. When the OCP fault is removed, the output voltage will ramp back up to the desired
voltage. This circuit is designed to provide high noise immunity.
Thermal Overload Protection
Thermal shutdown circuit will disable device operation when the Junction temperature exceeds approximately
150°C. After a thermal shutdown event, when the junction temperature drops by approx 20°C, the converter
will re-start with a normal soft-start.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will not start switching until the input voltage is above the
specified minimum voltage. Hysteresis, input de-glitch, and output leading edge blanking ensure high noise
immunity and prevent false UVLO triggers.
Compensation
The EN5337QI uses a type 3 compensation network. A piece of the compensation circuit is the phase lead
capacitor CA in Figure 5 This network will provide wide loop bandwidth and excellent transient performance
for most applications. It is optimized for use with about 50μF of output filter capacitance at the voltage sensing
point. Additional load decoupling capacitance may be placed beyond the voltage sensing point outside the
control loop. Voltage mode operation provides high noise immunity at light load, and low output impedance.
Page 12
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
APPLICATION INFORMATION
Output Voltage Programming
The EN5337QI output voltage is determined by the voltage presented at the XFB pin. This voltage is set by
way of a resistor divider between VOUT and AGND with the midpoint going to XFB. A phase lead capacitor CA is
also required for stabilizing the loop. Figure 5 shows the required components and the equations to calculate
the values.
VOUT
RA
CA
XFB
RB
RA = 150 kΩ , CA = 22 pF
RB =
0.75 * RA
(VOUT − 0.75V )
Figure 5. VOUT Resistor Divider Network and Compensation Capacitor CA
Input Capacitor Selection
The EN5337QI requires between 10μF and 20μF of input capacitance. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this converter. The dielectric must be X5R or X7R rated. Y5V or
equivalent dielectric formulations must not be used as these lose too much capacitance with frequency,
temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the
larger, capacitors in order to provide high frequency decoupling.
Table 1. Recommended Input Capacitors
Description
MFG
P/N
10μF, 10V, 10%, X7R, 1206
Murata
GRM31CR71A106KA01L
(1-2 capacitors needed)
Taiyo Yuden
LMK316B7106KL-T
22μF, 10V, 20%, X5R, 1206
Murata
GRM31CR61A226ME19L
(1 capacitor needed)
Taiyo Yuden
LMK316BJ226ML-T
Page 13
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
Output Capacitor Selection
The EN5337QI has been optimized for use with approximately 50μF of output filter capacitance at the voltage
sensing point Additional load decoupling capacitance may be placed beyond the voltage sensing point outside
the control loop. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency,
temperature and bias voltage.
Table 2. Recommended Output Capacitors
Description
MFG
P/N
47μF, 6.3V, 20%, X5R, 1206
Murata
GRM31CR60J476ME19L
(1 capacitor needed)
Taiyo Yuden
JMK212BJ476ML-T
10μF, 6.3V, 10%, X5R, 0805
(Optional 1 capacitor in
parallel with 47μF above)
Murata
GRM21BR60J106KE19L
Taiyo Yuden
JMK212BJ106KG-T
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage.
1
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Table 3. Typical Ripple Voltages
Output Capacitor
Configuration
Typical Output Ripple (mVp-p) (as measured
on EN5335QI Evaluation Board)
1 x 47μF
30
47μF + 10μF
15
Power-Up Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before
AVIN. Tying all three pins together meets these requirements.
Page 14
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
THERMAL CONSIDERATIONS
EN5337QI DC-DC converter is packaged in a 7 x 4 x 1.85mm 38-pin QFN package. The QFN package is
constructed with copper lead frames that have exposed thermal pads. The recommended maximum junction
temperature for continuous operation is 125°C. Continuous operation above 125°C will reduce long-term
reliability. The device has a thermal overload protection circuit designed to shut it off at an approximate
junction temperature value of 150°C.
The silicon is mounted on a copper thermal pad that is exposed at the bottom of the package. The thermal
resistance from the silicon to the exposed thermal pad is very low. In order to take advantage of this low
resistance, the exposed thermal pad on the package should be soldered directly on to a copper ground pad
on the printed circuit board (PCB). The PCB then acts as a heat sink. In order for the PCB to be an effective heat
sink, the device thermal pad should be coupled to copper ground planes or special heat sink structures
designed into the PCB (refer to the recommendations at the end of this note).
The junction temperature, TJ, is calculated from the ambient temperature, TA, the device power dissipation, PD,
and the device junction-to-ambient thermal resistance, θJA in °C/W::
TJ = TA + (PD)(θJA)
The junction temperature, TJ, can also be expressed in terms of the device case temperature, TC, and the device
junction-to-case thermal resistance, θJC in °C/W, as follows:
TJ = TC + (PD)(θJC)
The device case temperature, TC, is the temperature at the center of the exposed thermal pad at the bottom
of the package.
The device junction-to-ambient and junction-to-case thermal resistances, θJA and θJC, are shown in the
Thermal Characteristics table . The θJC is a function of the device and the 38-pin QFN package design. The
θJA is a function of θJC and the user’s system design parameters that include the thermal effectiveness of the
customer PCB and airflow.
The θJA value shown in the Thermal Characteristics table is for free convection with the device heat sunk
(through the thermal pad) to a copper plated four-layer PC board with a full ground and a full power plane
following JEDEC EIJ/JESD 51 Standards. The θJA can be reduced with the use of forced air convection.
Because of the strong dependence on the thermal effectiveness of the PCB and the system design, the actual
θJA value will be a function of the specific application.
Page 15
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
LAYOUT RECOMMENDATIONS
Figure 6 shows critical components and layer 1 traces of a recommended minimum footprint EN5337QI layout.
Alternate ENABLE configurations and other small signal pins need to be connected and routed according to
specific customer application. Please see the Gerber files on the Intel website www.intel.com/enpirion for exact
dimensions and other layers. Please refer to Figure 6 while reading the layout recommendations in this section.
Figure 6. Optimized Layout Recommendations
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN5337QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EN5337QI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Three PGND pins are dedicated to the input circuit, and two to the output circuit. The slit
in Figure 4 separating the input and output GND circuits helps minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors. Please see the Gerber files on the Intel website www.intel.com/enpirion.
Recommendation 4: The large thermal pad underneath the component must be connected to the system
ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias
must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figures: 5, 6, and 7.
Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the
+V copper. Please see Figure 4. These vias connect the input/output filter capacitors to the GND plane, and
help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN
and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not
use thermal reliefs or spokes to connect these vias to the ground plane.
Page 16
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
Recommendation 6: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 4 this connection is made at the input capacitor close
to the VIN connection.
Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 4. See the
section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to
run sensitive signal or control lines underneath the converter package on other layers.
Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense
trace as short as possible in order to avoid noise coupling into the control loop.
Recommendation 9: Keep RA, CA, and RB close to the VFB pin (see Figures 6 and 7). The VFB pin is a highimpedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB
directly to the AGND pin instead of going through the GND plane.
Page 17
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC
board. The PCB top layer under the EN5337QI should be clear of any metal except for the large thermal pad.
The “grayed-out” area in Figure 7 represents the area that should be clear of any metal (traces, vias, or planes),
on the top layer of the PCB. Figure 6 shows the recommended PCB footprint for this device.
Figure 7. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or
electrically connected to the PCB.
Page 18
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
RECOMMENDED PCB FOOTPRINT
Figure 8. EN5337QI PCB Footprint (Top View)
Page 19
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
PACKAGE DIMENSIONS
Figure 9. EN5337QI Package Dimensions (Bottom View)
Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html
Page 20
02638
March 29, 2019
Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5337QI
REVISION HISTORY
Rev
I
Date
Change(s)
March, 2019
Changed datasheet into Intel format.
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.intel.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 21
02638
March 29, 2019
Rev I
工商网监
湘ICP备2023018690号
