DataSheeT – enpirion® power solutions
EN6337QI 3A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EN6337QI is an Intel® Enpirion® Power System on
a Chip (PowerSoC) DC-DC converter. It integrates the
inductor, MOSFET switches, small-signal circuits and
compensation in an advanced 4mm x 7mm x 1.85mm
38-pin QFN package.
FEATURES
• Integrated Inductor, MOSFETs, Controller
• Up to 3A Continuous Operating Current
• High Efficiency (Up to 95%)
• Frequency Synchronization to External Clock
The EN6337QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
The device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
• Input Voltage Range (2.5V to 6.6V)
Intel Enpirion Power Solutions significantly help in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of components required for the complete power
solution helps to enable an overall system cost
saving.
APPLICATIONS
All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
EN6337QI
AVIN
• Programmable Soft-Start
• Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
• RoHS Compliant, MSL Level 3, 260°C Reflow
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• Beat Frequency/Noise Sensitive Applications
RA
VFB
CA
47F
1206
PGND
• Output Enable Pin and Power OK
VOUT
ENABLE
22F
• Optimized Total Solution Size (75mm2)
VOUT
VIN
PVIN
• Programmable Light Load Mode
1206
PGND
LLM/
SS
AGND SYNC
RB
CSS
Figure 1: Simplified Applications Circuit
Figure 2: Highest Efficiency in Smallest Solution Size
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
ORDERING INFORMATION
Part Number
Package Markings
TJ (°C)
Package Description
EN6337QI
EN6337QI
-40°C to +125°C
38-pin (4mm x 7mm x 1.85mm) QFN
EVB-EN6337QI
EN6337QI
QFN Evaluation Board
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
NC(SW)
NC(SW)
NC(SW)
NC(SW)
AVIN
AGND
VFB
SS
RLLM
POK
ENABLE
LLM / SYNC
37
36
35
34
33
32
31
30
29
28
27
26
KEEP OUT
NC(SW)
12
13
14
15
16
17
18
19
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
6
NC(SW)
VOUT
11
5
VOUT
VOUT
10
4
VOUT
NC
39
PGND
KEEP OUT
9
3
VOUT
NC
8
2
VOUT
NC(SW)
7
1
VOUT
NC(SW)
38
PIN FUNCTIONS
25
NC
24
NC
23
NC
22
NC
21
PVIN
20
PVIN
Figure 3: Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected
to the PCB. Refer to Figure 11 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
PIN DESCRIPTIONS
PIN
1, 2,
12, 3438
NAME
NC(SW)
TYPE
FUNCTION
-
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. They are not to be electrically
connected to any external signal, ground, or voltage. Failure to follow this
guideline may result in damage to the device.
3-4,
22-25
NC
-
NO CONNECT – These pins may be internally connected. Do not connect
to each other or to any other electrical signal. Failure to follow this
guideline may result in device damage.
5-11
VOUT
Power
Regulated converter output. Connect to the load and place output filter
capacitor(s) between these pins and PGND pins. Refer to the Layout
Recommendation section.
13-18
PGND
Ground
Input/Output power ground. Connect these pins to the ground electrode
of the input and output filter capacitors. See VOUT and PVIN pin
descriptions for more details.
19-21
PVIN
Power
Input power supply. Connect to input power supply. Decouple with input
capacitor to PGND pins 16-18.
26
LLM/SYNC
Analog
Dual function pin providing LLM Enable and External Clock
Synchronization (see Application Section). At static Logic HIGH, device
will allow automatic engagement of light load mode. At static logic LOW,
the device is forced into PWM only. A clocked input to this pin will
synchronize the internal switching frequency to the external signal. If this
pin is left floating, it will pull to a static logic high, enabling LLM.
27
ENABLE
Analog
Input Enable. Applying logic high enables the output and initiates a softstart. Applying logic low disables the output.
28
POK
Digital
Power OK is an open drain transistor used for power system state
indication. POK is logic high when VOUT is within -10% of VOUT nominal.
29
RLLM
Analog
Programmable LLM engage resistor to AGND allows for adjustment of
load current at which Light-Load Mode engages. Can be left open for
PWM only operation.
30
SS
Analog
A soft-start capacitor is connected between this pin and AGND. The value
of the capacitor controls the soft-start interval. Refer to Soft-Start
Operation in the Functional Description section for more details.
31
VFB
Analog
External Feedback Input. The feedback loop is closed through this pin. A
voltage divider at VOUT is used to set the output voltage. The midpoint
of the divider is connected to VFB. A phase lead capacitor from this pin to
VOUT is also required to stabilize the loop.
32
AGND
Power
Ground for internal control circuits. Connect to the power ground plane
with a via right next to the pin.
33
AVIN
Power
Input power supply for the controller. Connect to input voltage at a quiet
point. Refer to the Layout Recommendation section.
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
PIN
39
NAME
PGND
TYPE
Ground
FUNCTION
Power ground thermal pad. Not a perimeter pin. Connect thermal pad to
the system GND plane for heat-sinking purposes. Refer to the Layout
Recommendation section.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
PVIN, AVIN, VOUT
-0.3
7.0
V
ENABLE, POK, LLM/SYNC
-0.3
VIN+0.3
V
VFB, SS,RLLM
-0.3
2.5
V
MIN
MAX
UNITS
+150
°C
+150
°C
+260
°C
MAX
UNITS
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
Maximum Operating Junction
Temperature
Storage Temperature Range
Reflow Peak Body Temperature
-65
(10 Sec) MSL3 JEDEC J-STD-020A
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
VIN
2.5
6.6
Output Voltage Range
VOUT
0.6
Output Current Range
IOUT
Operating Ambient Temperature Range
TA
Operating Junction Temperature
TJ
Input Voltage Range
VIN – VDO
UNITS
V
V
(1)
3
A
-40
+85
°C
-40
+125
°C
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
TSD
160
°C
TSDHYS
35
°C
Thermal Resistance: Junction to Ambient (0 LFM) (2)
JA
30
°C/W
Thermal Resistance: Junction to Case (0 LFM)
JC
3
°C/W
Thermal Shutdown
Thermal Shutdown Hysteresis
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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ELECTRICAL CHARACTERISTICS
NOTE: VIN = 6.6V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PVIN = AVIN
2.5
TYP
MAX
UNITS
6.6
V
Operating Input Voltage
VIN
Under Voltage Lock-Out
– VIN Rising
VUVLOR
Voltage above which UVLO is
not asserted
2.3
V
Under Voltage Lock-Out
– VIN Falling
VUVLOF
Voltage below which UVLO is
asserted
2.075
V
Shut-Down Supply
Current
IS
ENABLE = 0V
100
A
Operating Quiescent
Current
IQ
LLM/SYNC = High
650
A
Feedback Pin Voltage (3)
VFB Pin Voltage (Load
and Temperature
VFB
VIN = 5V, ILOAD = 0, TA =
25°C
0.7425
0.75
0.7575
V
0.739
0.75
0.761
V
0.735
0.75
0.765
V
5
nA
1.5
ms
68
nF
0A ≤ ILOAD ≤ 3A
VVFB
Starting Date Code: X501 or
higher
Feedback node voltage at:
Feedback Pin Voltage
(Line, Load,
Temperature)
VFB
Feedback pin Input
Leakage Current (4)
IFB
VFB pin input leakage current
-5
tRISE
Measured from when VIN >
VUVLOR & ENABLE pin voltage
crosses
its
logic
high
threshold to when VOUT
reaches its final value. CSS =
15 nF
0.9
VOUT Rise Time (4)
2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 3A
1.2
Soft Start Capacitor
Range
CSS_RANGE
Output Drop Out (4)
VDO
VINMIN - VOUT at Full load
210
315
mV
Voltage Resistance (4)
RDO
Input to Output Resistance
70
105
m
Continuous Output
Current
IOUT
3
3
A
10
PWM mode
LLM mode (5)
0
0.002
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PARAMETER
Over Current Trip Level
SYMBOL
TEST CONDITIONS
IOCP
VIN = 5V, VOUT = 1.2V
Precision Disable
Threshold
VDISABLE
Precision ENABLE
Threshold
VENABLE
ENABLE Lockout Time
ENABLE pin Input
Current (4)
Switching Frequency
(Free Running)
MIN
TYP
MAX
5
ENABLE pin logic low.
ENABLE pin logic high
2.5V ≤ VIN ≤ 6.6V
UNITS
A
0.0
0.6
V
1.8
VIN
V
TENLOCKOUT
4.2
ms
IENABLE
ENABLE pin has ~180k pull
down
40
A
FSW
Free Running frequency of
oscillator
1.9
MHz
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range
of
frequency
SYNC Input Threshold –
Low (LLM/SYNC PIN)
VSYNC_LO
SYNC Clock Logic Level
SYNC Input Threshold –
High (LLM/SYNC PIN) (6)
VSYNC_HI
SYNC Clock Logic Level
POK Lower Threshold
POKLT
Output voltage as a fraction
of expected output voltage
POK Output low Voltage
VPOKL
With 4mA current sink into
POK
0.4
V
POK Output High Voltage
VPOKH
2.5V ≤ VIN ≤ 6.6V
VIN
V
POK pin VOH leakage
current (4)
IPOKL
POK high
1
µA
SYNC
1.5
1.8
LLM Logic Low
(LLM/SYNC PIN)
VLLM_LO
LLM Static Logic Level
LLM Logic High
(LLM/SYNC PIN)
VLLM_HI
LLM Static Logic Level
2.3
MHz
0.8
V
2.5
V
90
Minimum
VIN-VOUT
to
ensure proper LLM operation
LLM Engage Headroom
LLM/SYNC Pin Current
clock
%
800
mV
0.3
1.5
LLM/SYNC Pin is 4
1000
56
>4
Power-Up
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN.
Tying all three pins together meets these requirements.
Pre-Bias Start-up
The EN6337QI supports startup into a pre-biased output of up to 1.5V. The output of the EN6337QI can be
pre-biased with a voltage up to 1.5V when it is first enabled.
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THERMAL CONSIDERATIONS
Thermal considerations are important power supply design facts that cannot be avoided in the real world.
Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be
accounted for. The Enpirion PowerSoC helps alleviate some of those concerns.
The Enpirion EN6337QI DC-DC converter is packaged in a 4x7x3mm 38-pin QFN package. The QFN package
is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the
package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a
heat sink. The recommended maximum junction temperature for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit
designed to turn off the device at an approximate junction temperature value of 160°C.
The following example and calculations illustrate the thermal performance of the EN6337QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 3A
First calculate the output power.
POUT = 3.3V x 3A = 9.9W
Next, determine the input power based on the efficiency (η) shown in Figure 8.
Efficiency vs. IOUT (VOUT = 3.3V)
100
90
80
LLM
EFFICIENCY (%)
70
60
50
40
PWM
CONDITIONS
VIN = 5V
30
VOUT = 3.3V LLM
20
VOUT = 3.3V PWM
10
0
0.01
0.1
1
OUTPUT CURRENT (A)
10
Figure 8: Efficiency vs. Output Current
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For VIN = 5V, VOUT = 3.3V at 3A, η ≈ 92.5%
η = POUT / PIN = 92.5% = 0.925
PIN = POUT / η
PIN ≈ 9.9W / 0.94 ≈ 10.7W
The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
≈ 10.7W – 9.9W ≈ 0.8W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EN63437QI has a θJA value of 30°C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.8W x 30°C/W = 24.08°C ≈ 24°C
The junction temperature (TJ) of the device is approximately the ambient temperature (T A) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 24°C ≈ 49°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 24°C ≈ 101°C
The maximum ambient temperature the device can reach is 101°C given the input and output conditions. Note
that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate.
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ENGINEERING SCHEMATIC
Figure 9: Engineering Schematic with Engineering Notes
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LAYOUT RECOMMENDATIONS
Figure 10 shows critical components and layer 1 traces of a recommended minimum footprint EN6337QI
layout with ENABLE tied to VIN in PWM mode. Alternate ENABLE configurations, and other small signal pins
need to be connected and routed according to specific customer application. Visit the Enpirion Power
Solutions website at www.altera.com/powersoc for more information regarding layout. Please refer to this
Figure 10 while reading the layout recommendations in this section.
Figure 10: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN6337QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EN6337QI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Three PGND pins are dedicated to the input circuit, and three to the output circuit. The
slit in Figure 10 separating the input and output GND circuits helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors.
Recommendation 4: The large thermal pad underneath the component must be connected to the system
ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias
must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figures: 7, 8, and 9.
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Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the
+V copper. Please see Figure 10. These vias connect the input/output filter capacitors to the GND plane, and
help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under C IN
and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not
use thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 6: : AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 10 this connection is made at the input capacitor
close to the VIN connection.
Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 10. See the
section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to
run sensitive signal or control lines underneath the converter package on other layers.
Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense
trace as short as possible in order to avoid noise coupling into the control loop.
Recommendation 9: Keep RA, CA, and RB close to the VFB pin (see Figures 6 and 7). The VFB pin is a highimpedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R B
directly to the AGND pin instead of going through the GND plane.
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DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance such as in reduced electrical lead resistance and
in overall footprint; however, they do require some special considerations.
In the assembly process lead frame construction requires some of the lead-frame cantilevers be exposed at
the point where wire-bond or internal passives are attached for mechanical support. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 11.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the board.
The PCB top layer under the EN6337QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 11 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by solder mask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. See Figure 11 for details.
Figure 11: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
Figure 12: EN6337QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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PACKAGE DIMENSIONS
Figure 13: EN6337QI Package Dimensions
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
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Datasheet | Intel® Enpirion® Power Solutions: EN6337QI
REVISION HISTORY
Rev
Date
Change(s)
F
April, 2018
Changed datasheet into Intel format.
G
August, 2018
Corrected some typos
H
Oct, 2019
Corrected package top marking typo.
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
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