DataSheeT – enpirion® power solutions
EN6340QI 4A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EN6340QI is an Intel® Enpirion® Power System on
a Chip (PowerSoC) DC-DC converter. It integrates the
inductor, MOSFET switches, small-signal circuits and
compensation in an advanced 4mm x 6mm x 2.5mm
34-pin QFN package.
FEATURES
• High Efficiency (Up to 95%)
• Excellent Ripple and EMI Performance
• Up to 4A Continuous Operating Current
• 2.7V to 6.6V Input Voltage Range
The EN6340QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architectures.
The device’s advanced circuit techniques, high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
• 0.5% VFB Initial Accuracy
Intel Enpirion Power Solutions significantly help in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of components required for the complete power
solution helps to enable an overall system cost
saving.
• Pin Compatible with EN6363QI (6A)
All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
• Space Constrained Applications Needing High
Power Density
• 1.5% VOUT Accuracy (Line, Load, Temp)
• 2MHz Switching Frequency
• 60mm2 Optimized Total Solution Size
• Programmable Soft-Start
• Power OK Indicator
• Thermal, Over-Current, Short Circuit, UnderVoltage and Pre-Bias Protections
• RoHS Compliant, MSL Level 3, 260°C Reflow
APPLICATIONS
• Point of Load Regulation for FPGAs, Distributed
Power Architectures, Low-Power ASICs, MultiCore, Communication Processors and DSPs
• 5V/3.3V Bus Architectures Needing High Efficiency
Efficiency vs. Output Current
VOUT
VIN
10Ω
2x
22µF
0805
VOUT
EN6340QI
AVIN
PGND
2x
47µF
0805
95
RA
CA
RC
ENABLE
POK
VFB
PGND
85
80
VOUT = 3.3V
75
VOUT = 2.5V
70
VOUT = 1.8V
65
VOUT = 1.5V
60
SS
15nF
90
EFFICIENCY (%)
PVIN
100
AGND
RB
CONDITIONS
VIN = 5.0V
55
VOUT = 1.2V
VOUT = 1.0V
50
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Figure 1: Simplified Applications Circuit
Figure 2: Efficiency at VIN = 5V
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
ORDERING INFORMATION
Part Number
Package Markings
TA Rating
Package Description
EN6340QI
EN6340QI
-40°C to +85°C
34-pin (4mm x 6mm x 2.5mm) QFN
EVB-EN6340QI
EN6340QI
QFN Evaluation Board
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
PIN FUNCTIONS
NC(SW)
NC(SW)
NC(SW)
NC(SW)
NC(SW)
AGND
POK
AGND
AVIN
SS
VFB
34
33
32
31
30
29
28
27
26
25
24
23 NC
NC(SW) 1
KEEP-OUT
NC(SW) 2
4
VOUT
5
VOUT
6
KEEP-OUT
18 NC
13
14
15
16
17
PVIN
PVIN
PVIN
VOUT
12
PGND
VOUT
11
PGND
VOUT
10
NC(SW)
9
19 NC
VOUT
8
20 ENABLE
VOUT
7
KEEP-OUT
NC
21 NC
35
PGND
3
KEEP-OUT
NC
22 NC
Figure 3: Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
NOTE C: Keep-Out are No Connect pads that should not to be electrically connected to each other or to any external
signal, ground or voltage. They do not need to be soldered to the PCB.
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
PIN DESCRIPTIONS
PIN
1, 2,
12, 30,
31, 32,
33, 34
3, 4,
18, 19,
21, 22,
23
5, 6, 7,
8, 9,
10, 11
NAME
NC(SW)
NC
VOUT
TYPE
FUNCTION
-
No Connect. These pins are internally connected to the common
switching node of the internal MOSFETs. They must be soldered to PCB
but not be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in device damage.
-
No Connect. These pins must be soldered to PCB but not electrically
connected to each other or to any external signal, voltage, or ground.
These pins may be connected internally. Failure to follow this guideline
may result in device damage.
Power
Regulated converter output. Connect to the load and place output filter
capacitor(s) between these pins and PGND pins. Refer to the Layout
Recommendation section.
13, 14
PGND
Ground
Input/Output power ground. Connect to the ground electrode of the
input and output filter capacitors. See VOUT and PVIN pin descriptions
for more details.
15, 16,
17
PVIN
Power
Input power supply. Connect to input power supply. Decouple with input
capacitor to PGND pin. Refer to the Layout Recommendation section.
Analog
Input Enable. Applying logic high or floating the ENABLE pin will enable
the device and initiate a soft-start. Applying logic low disables the output
and switching stops.
Analog
External feedback input pin. A resistor divider connects from the output
to AGND. The mid-point of the resistor divider is connected to VFB. A
feed-forward capacitor (CA) and resistor (RC) are required in parallel to the
upper feedback resistor (RA). The output voltage regulation is based on
the VFB node voltage being equal to 0.6V.
20
24
ENABLE
VFB
25
SS
Analog
A soft-start capacitor is connected between this pin and AGND. The value
of the capacitor controls the soft-start interval. Refer to Soft-Start
Operation in the Functional Description section for more details.
26
AVIN
Power
Input power supply for the controller. Connect to input voltage at a quiet
point. Refer to the Layout Recommendation section.
27, 29
AGND
Power
Ground for internal control circuits. Connect to the power ground plane
with a via right next to the pin.
28
POK
Digital
Power OK is an open drain transistor used for power system state
indication. POK is logic high when VOUT is within ±10% of VOUT nominal
and has an internal 100kΩ pull-up resistance to AVIN.
Ground
Power ground thermal pad. Not a perimeter pin. Connect thermal pad to
the system GND plane for heat-sinking purposes. Refer to the Layout
Recommendation section.
35
PGND
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
PVIN, AVIN, VOUT
-0.3
7.0
V
ENABLE, POK
-0.3
VIN+0.3
V
VFB, SS
-0.3
2.5
V
7.0
V
NC(SW) Voltage DC
VSW
NC(SW) Voltage Peak < 5ns
VSW_PEAK
-2.0
10.5
V
CONDITION
MIN
MAX
UNITS
+150
°C
+150
°C
+260
°C
MAX
UNITS
Absolute Maximum Thermal Ratings
PARAMETER
Maximum Operating Junction
Temperature
Storage Temperature Range
Reflow Peak Body
Temperature
-65
(10 Sec) MSL3 JEDEC J-STD-020A
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.7
6.6
V
Output Voltage Range
VOUT
0.75
VIN – VDO (1)
V
Output Current Range
IOUT
4
A
Operating Ambient Temperature Range
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Input Voltage Range
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
TSD
160
°C
TSDHYS
25
°C
Thermal Resistance: Junction to Ambient (0 LFM) (2)
JA
12.5
°C/W
Thermal Resistance: Junction to Case (0 LFM)
JC
1
°C/W
Thermal Shutdown
Thermal Shutdown Hysteresis
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
ELECTRICAL CHARACTERISTICS
NOTE: VIN = PVIN = AVIN = 5V, Minimum and Maximum values are over operating ambient temperature range
unless otherwise noted. Typical values are at TA = TJ = 25°C.
PARAMETER
Operating Input
Voltage
SYMBOL
VIN
TEST CONDITIONS
MIN
PVIN = AVIN
2.7
TYP
MAX
UNITS
6.6
V
Under Voltage LockOut – VIN Rising
VUVLOR
Voltage above which UVLO is
not asserted
2.2
2.3
2.4
V
Under Voltage LockOut – VIN Falling
VUVLOF
Voltage below which UVLO is
asserted
1.7
2.075
2.2
V
Under Voltage LockOut Hysteresis
VUVLOHYS
Shut-Down Supply
Current
IS
AVIN Quiescent Current
IAVINQ
No Load Quiescent
Current
IVINQ
Feedback Pin Voltage (3)
VFB
Feedback Pin Voltage
(Line, Load, Temp.)
225
mV
ENABLE = 0V
500
700
A
AVIN only
3.5
10
mA
PVIN and AVIN
40
VOUT = 1.2V
VOUT = 0.6V, ILOAD = 0,
TA =25°C
mA
0.597
0.6
0.603
V
0.591
0.6
0.609
V
2.7V ≤ VIN ≤ 6.6V
VFB
0A ≤ ILOAD ≤ 4A
-40°C ≤ TA ≤ 85°C
Feedback pin Input
Leakage Current (4)
VFB pin input leakage current
-10
10
nA
Capacitor programmable
0.2
20
ms
CSS_RANGE
10
100
nF
Soft-Start Charging
Current
ISS
3.5
5
6.5
µA
Drop-Out Voltage (4)
VDO
VINMIN - VOUT at full load
200
320
mV
Drop-Out Resistance (4)
RDO
Input to output resistance
50
80
m
Continuous Output
Current
IOUT
4
A
Over Current Trip Level
IOCP
VOUT Rise Time Range (4)
Soft Start Capacitance
Range (4)
IFB
tRISE
0
VIN = 5V, VOUT = 1.2V
4.5
6.5
A
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Limit Retry
Time (4)
TCL_TRY
Precision Disable
Threshold
VDISABLE
ENABLE pin logic going low
0.95
1.01
1.07
V
Precision Enable
Threshold
VEN
ENABLE pin logic going high
1.08
1.12
1.16
V
ENABLE Hysteresis
ENHYS
ENABLE Pin Input
Current
IEN
ENABLE Pull-Up
Resistance
17
ms
110
mV
Device not switching;
40
ENABLE pin has ~110k pull
down
90
A
REN_UP
Not a passive element and
changes with VIN
190
kΩ
REN_DOWN
Not a passive element and
changes with VIN
110
kΩ
FSW
Free running frequency of
oscillator
POK High Range
POKRANGE
Typical percentage range
within VOUT nominal when
POK is asserted high
POK Low Voltage
VPOKL
With 4mA current sink into
POK
0.4
V
POK High Voltage
VPOKH
2.7V ≤ VIN ≤ 6.6V
VIN
V
POK Pin Leakage
Current (4)
IPOKH
POK is high
1
µA
ENABLE Pull-Down
Resistance
Switching Frequency
1.8
2.0
2.2
±10
MHz
%
(3) The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
(4) Parameter not production tested but is guaranteed by design.
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CURVES
Efficiency vs. Output Current
100
100
95
95
90
90
85
85
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
VOUT = 3.3V
75
VOUT = 2.5V
70
VOUT = 1.8V
65
VOUT = 1.5V
CONDITIONS
VIN = 5.0V
60
55
80
VOUT = 1.8V
70
VOUT = 1.5V
65
VOUT = 1.2V
60
VOUT = 1.0V
55
50
VOUT = 2.5V
75
CONDITIONS
VIN = 3.3V
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.006
1.006
CONDITIONS
VIN = 3.3V
1.004
VOUT = 1.0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.0V
50
0
1.002
1
0.998
0.996
0.994
CONDITIONS
VIN = 5.0V
1.004
VOUT = 1.0V
1.002
1
0.998
0.996
0.994
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.806
1.806
CONDITIONS
VIN = 3.3V
1.804
VOUT = 1.8V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.2V
1.802
1.8
1.798
1.796
CONDITIONS
VIN = 5.0V
1.804
VOUT = 1.8V
1.802
1.8
1.798
1.796
1.794
1.794
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
3.306
CONDITIONS
VIN = 3.3V
2.504
VOUT = 2.5V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.506
2.502
2.5
2.498
2.496
2.494
CONDITIONS
VIN = 5.0V
3.304
3.302
3.3
3.298
3.296
3.294
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
OUTPUT CURRENT (A)
Output Voltage vs. Temperature
2
2.5
3
3.5
4
Output Voltage vs. Temperature
1.806
1.804
LOAD = 2A
LOAD = 0.01A
VOUT = 1.8V
LOAD = 4A
1.802
CONDITIONS
VIN = 2.7V
OUTPUT VOLTAGE (V)
LOAD = 0.01A
OUTPUT VOLTAGE (V)
1.5
OUTPUT CURRENT (A)
1.806
1.8
1.798
1.796
1.794
1.804
LOAD = 2A
VOUT = 1.8V
LOAD = 4A
1.802
CONDITIONS
VIN = 3.3V
1.8
1.798
1.796
1.794
-40
-20
0
20
40
60
80
100
-40
AMBIENT TEMPERATURE ( C)
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE ( C)
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.806
1.806
1.804
LOAD = 2A
LOAD = 0.01A
VOUT = 1.8V
LOAD = 4A
1.802
CONDITIONS
VIN = 5.0V
OUTPUT VOLTAGE (V)
LOAD = 0.01A
OUTPUT VOLTAGE (V)
VOUT = 3.3V
1.8
1.798
1.796
1.794
1.804
LOAD = 2A
VOUT = 1.8V
LOAD = 4A
1.802
CONDITIONS
VIN = 6.6V
1.8
1.798
1.796
1.794
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE ( C)
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE ( C)
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
Input Voltage vs. Output Voltage
Input Voltage vs. Output Voltage
1.81
CONDITIONS
VOUT = 1.8V
TA = 25°C
1.804
1.802
LOAD = 0.01A
1.808
TA = -40°C
TA = 0°C
LOAD = 2A
1.806
TA = 25°C
TA = 85°C
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.806
LOAD = 4A
1.8
1.798
1.796
1.804
1.802
1.8
1.798
1.796
CONDITIONS
VOUT = 1.8V
LOAD = 2A
1.794
1.792
1.79
1.794
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2.5
7
3
No Thermal Derating
4.5
5
5.5
6
6.5
7
No Thermal Derating
5
5
4.5
4.5
MAX LOAD
4
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.5
3
2.5
2
1.5
CONDITIONS
VIN = 5.0V
1
0.5
MAX LOAD
4
3.5
3
2.5
2
1.5
CONDITIONS
VIN = 5.0V
1
0.5
VOUT = 3.3V
0
VOUT = 1.0V
0
-40
-20
0
20
40
60
80
100
-40
AMBIENT TEMPERATURE ( C)
60.0
40.0
HORIZONTAL
VERTICAL
CISPR 22 Class B 3m
30.0
20
40
60
CONDITIONS
VIN = 5.0V
VOUT_NOM = 3.3V
LOAD = 1Ω
50.0
LEVEL (dBµV/m)
50.0
0
80
100
EMI Performance
60.0
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.2V
LOAD = 0.33Ω
-20
AMBIENT TEMPERATURE ( C)
EMI Performance
LEVEL (dBµV/m)
3.5
20.0
10.0
40.0
HORIZONTAL
VERTICAL
CISPR 22 Class B 3m
30.0
20.0
10.0
0.0
0.0
10
100
1000
FREQUENCY (MHz)
10
100
1000
FREQUENCY (MHz)
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CHARACTERISTICS
Output Ripple at 20MHz Bandwidth
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
COUT = 2x47µF
No Load
VOUT = 1.0V
(AC Coupled)
10mV / DIV
VOUT = 1.8V
(AC Coupled)
10mV / DIV
VOUT = 1.8V
(AC Coupled)
10mV / DIV
VOUT = 3.3V
(AC Coupled)
10mV / DIV
VOUT = 3.3V
(AC Coupled)
10mV / DIV
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 5V
COUT = 2x47µF
4A Load
VOUT = 1.0V
(AC Coupled)
10mV / DIV
Output Ripple at 500MHz Bandwidth
VOUT = 1.0V
VOUT = 3.3V
(AC Coupled at 2mV / DIV)
VOUT = 1.8V
(AC Coupled at 2mV / DIV)
VOUT = 1.8V
VOUT = 3.3V
VOUT = 1.0V
(AC Coupled at 2mV / DIV)
CONDITIONS
VIN = 5V, 4A Load
COUT = 2 x 47µF + 0.1µF
CONDITIONS
VIN = 5V
COUT = 2 x (47µF, 22µF,10µF, 4.7µF, 2.2µF, 1µF, 0.1µF)
Improved Load Transient 0 to 4A
Load Transient 0 to 4A
VOUT
(AC Coupled)
VOUT
(AC Coupled)
4A
CONDITIONS
VIN = 3.3V
VOUT = 1.2V
CA = 47pF
COUT = 2x47µF + 3x100µF
CONDITIONS
VIN = 3.3V
VOUT = 1.2V
CA = 15pF
COUT = 2x47µF
4A
LOAD = 0A
LOAD = 0A
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Improved Load Transient 0 to 4A
Load Transient 0 to 4A
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1.2V
CA = 47pF
COUT = 2x47µF + 3x100µF
CONDITIONS
VIN = 5V
VOUT = 1.2V
CA = 15pF
COUT = 2x47µF
4A
4A
LOAD = 0A
LOAD = 0A
Improved Load Transient 0 to 4A
Load Transient 0 to 4A
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 33pF
COUT = 2x47µF + 3x100µF
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2x47µF
4A
4A
LOAD = 0A
LOAD = 0A
Startup and Shutdown at 4A Load
Startup and Shutdown at No Load
EN
VOUT
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
No Load
VOUT Floats
EN
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
VOUT
POK
POK
SS
SS
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Datasheet | Intel® Enpirion® Power Solutions: EN6340QI
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
VIN Startup at No Load
VIN Shutdown at No Load
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
PVIN
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
VOUT
PVIN
POK
VOUT
SS
POK
SS
VIN Startup at 4A Load
VIN Shutdown at 4A Load
PVIN
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
VOUT
PVIN
POK
VOUT
LOAD
POK
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 10pF
COUT = 2 x 47µF
LOAD
Pre-Bias Startup
Pre-Bias Startup
EN
EN
90% Pre-Bias
90% Pre-Bias
VOUT 50% Pre-Bias
VOUT 50% Pre-Bias
10% Pre-Bias
POK
10% Pre-Bias
CONDITIONS
VIN = 5V
VOUT = 1V
POK
CONDITIONS
VIN = 5V
VOUT = 3.3V
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Short Circuit and Recovery
Short Circuit and Recovery
CONDITIONS
VIN = 6.6V, VOUT = 3.3V
POK
POK
“Re-Try”
VOUT
VOUT
VSW
VSW
LOAD
SS
CONDITIONS
VIN = 6.6V, VOUT = 3.3V
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FUNCTIONAL BLOCK DIAGRAM
PVIN
UVLO
Thermal Limit
LDO
Current Limit
NC(SW)
P-Drive
(-)
Logic
PWM
Comp
(+)
VOUT
N-Drive
PGND
PLL/Sawtooth
Generator
Compensation
Network
AVIN
Prebias Sense
(-)
Error
Amp
(+)
AVIN
Power
OK
100k
POK
ENABLE
Soft-Start
Internal
Reference
VFB
Internal
Regulator
AGND
AVIN
SS
Figure 4: Functional Block Diagram
FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN6340QI is a synchronous DC-DC PowerSoC with integrated power MOSFET switches and integrated
inductor. The nominal input voltage range is 2.7V to 6.6V. The output voltage is programmed using an external
resistor divider network. The control loop is voltage-mode with a type III compensation network. Much of the
compensation circuitry is internal to the device, but a phase-lead capacitor and resistor are required to
complete the compensation network. The type III voltage mode architecture with integrated compensation
maximizes loop bandwidth without increasing complexity. This architecture is designed to maintain stability
with excellent gain and phase margin and improve transient response. The enhanced voltage mode
architecture also provides high noise immunity at light load and maintains excellent line and load regulation.
Up to 4A of continuous output current can be drawn from this converter. The 2MHz switching frequency allows
the use of smaller case size input and output capacitors within a small footprint.
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The EN6340QI architecture includes the following features.
Operational Features:
•
Precision enable circuit with tight threshold range
•
Soft-start circuit allowing controlled startup when the converter is initially powered up
•
Power OK circuit indicating the output voltage is greater than 90% of programmed value
Protection Features:
•
Over-current protection from short circuit or excessive load current
•
Thermal shutdown with hysteresis to prevent over temperature stress
•
Output voltage pre-bias startup protection for smooth monotonic startup
•
Under-voltage lockout protection to prevent under-voltage operation
Precision Enable Operation
The enable (ENABLE) pin provides a mean to startup or to shutdown the device. When the ENABLE pin is
asserted high, the device will undergo a normal soft-start where the output will rise monotonically into
regulation. Asserting a logic low on this pin will deactivate the device by turning off the internal power switches
and the POK flag will also be pulled low. The ENABLE pin is connected through an internal divider network to
AVIN and AGND. If left floating, the ENABLE voltage will be equal to the AVIN voltage and the value set by the
divider network ratio (~2.5):
VEN (FLOATING) ≈ AVIN / 2.5
The precision enable circuit ensures the device will enable or disable within a tight voltage range for both high
or low logic. In order to ensure a known state the ENABLE pin should be pulled high or low. See the Electrical
Characteristics Table for technical specifications for the ENABLE pin.
Soft-Start Operation
The soft-start circuitry will reduce inrush current during startup as the regulator charges the output voltage up
to nominal level gradually. The output rise time is controlled by the soft-start capacitor, which is placed
between the SS pin and the AGND pin. When the part is enabled, the soft-start (SS) current generator charges
the SS capacitor in a linear manner. Once the voltage on the SS capacitor reaches 0.6V, the controller selects
the intenral bandgap voltage as the reference. The voltage across the SS capacitor will continue ramping up
until it reaches around 1.27V. The rise time is defined as the time needed by the output voltage to go from
zero to the programmed value. The rise time (tRISE) is given by the following equation:
tRISE [ms] = Css [nF] x 0.13
With a 10nF soft-start capacitance on the SS pin, the soft-start rise time will be set to 1.3ms. The recommended
range for the value of the SS capacitor is between 10nF and 100nF. Note that excessive bulk capacitance on
the output can cause an over current event on startup if the soft-start time is too low. Refer to the
Compensation and Transient Response section for details on proper bulk capacitance usage.
POK Operation
The Power OK (POK) is an open drain signal (with internal 100kΩ pull-up to AVIN) to indicate if the output
voltage is within the specified range. POK is asserted high when the rising output voltage exceeds 90% of the
programmed output voltage. For a stronger pull-up, an external resistor may be connected to AVIN. If the
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nominal output voltage falls outside the set range (typically 90% to 110% of nominal) the POK signal will be
asserted low by an internal 4mA pull-down transistor.
Over-Current Protection (OCP)
The current limit function is achieved by sensing the current flowing through the topside power PFET. When
the sensed current exceeds the over current trip point (see Electrical Characteristics Table), both power FETs
are turned off for the remainder of the switching cycle. If the over-current condition is removed, the overcurrent protection circuit will enable normal PWM operation. In the event the OCP circuit trips at least 7
consecutive PWM cycles, the device enters a retry mode; the device is disabled for about 17ms and restarted
with a normal soft-start. This cycle can continue indefinitely as long as the over current condition persists. The
OCP circuit will disable operation and protect the device from excessive current during operation without
compromising the full load capability of the device.
Thermal Protection
The thermal shutdown circuit disables the device operation (switching stops) when the junction temperature
exceeds 160°C. When the junction temperature drops by approximately 25°C, the converter will re-start with
a normal soft-start. By preventing operation at excessive temperatures, the thermal shutdown circuit will
protect the device from overstress.
Pre-Bias Startup Protection
The EN6340QI supports startup into a pre-biased output. A proprietary circuit ensures the output voltage rises
from the pre-bias voltage level to the programmed output voltage on startup. During this soft-start period, the
voltage rise is monotonic for output voltage range from 0% to 90% of nominal. If the pre-bias voltage is above
90% on startup, there might be a slight dip (~3%) in output voltage before it rises monotonically. If the prebias voltage is above 100% of nominal during startup, the device will not switch until the soft-start period is
over. Note that when the device begins switching and the pre-bias output voltage is higher than nominal, the
bottomside NFET will discharge the output quickly (but limited to 2-cycles to prevent excessive current) to
bring the voltage back into regulation. The pre-bias protection circuit is designed to prevent improper behavior
on startup regardless of the pre-bias output voltage during soft-start.
Input Under-Voltage Lock-Out (UVLO)
When the device input voltage falls below UVLO, switching is disabled to prevent operation at insufficient
voltage levels. During startup, the UVLO circuit ensures that the converter will not start switching until the
input voltage is above the specified minimum voltage. Hysteresis and input de-glitch circuits are incorporated
in order to ensure high noise immunity and prevent a false trigger in the UVLO voltage region.
APPLICATION INFORMATION
Output Voltage Setting
The EN6340QI output voltage is programmed using a simple resistor divider network (RA and RB). Figure 5
shows the resistor divider configuration.
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EN6340QI
VOUT
VOUT
PGND
VFB
COUT
(100µF to 400µF)
RA
249k
CA
(10pF to 47pF)
RC
10k
VFB = 0.6V
RB =
VFB x RA
VOUT - VFB
AGND
Figure 5: VOUT Resistor Divider & Compensation Capacitor
The recommended RA resistor value is 249kΩ and the feedback voltage is typically 0.6V. Depending on the
output voltage (VOUT), the RB resistor value may be calculated as shown in Figure 5. Since the accuracy of the
output voltage setting is dependent upon the feedback voltage and the external ressitors, 1% or better
resistors are recommended. The external compensation capacitor (CA) and resistor (RC) is also required in
parallel with RA. Depending on input and output voltage, the recommended external compensation values are
shown in Table 1.
Table 1: External Compensation Recommendations
VIN
3.3V
VOUT
RB
CA
1.0V
374kΩ
18pF
1.2V
249kΩ
15pF
1.5V
165kΩ
15pF
1.8V
124kΩ
15pF
2.5V
78.7kΩ
12pF
1.0V
374kΩ
15pF
1.2V
249kΩ
15pF
1.5V
165kΩ
15pF
1.8V
124kΩ
12pF
2.5V
78.7kΩ
12pF
3.3V
54.9kΩ
10pF
5V
RA
RC
COUT (0805)
249kΩ
10kΩ
2 x 47µF
249kΩ
10kΩ
2 x 47µF
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Compensation and Transient Response
The EN6340QI uses an enhanced type III voltage mode control architecture. Most of the compensation is
internal, which simplifies the design. In some applications, improved transient performance may be desired
with additional output capacitors (COUT). In such an instance, the phase-lead capacitor (CA) can be adjusted
depending on the total output capacitance. Using Table 1 as the reference for CA, if COUT is increased, then the
CA should also be increased. The relationship is linearly shown below:
ΔCOUT ≈ +100µF ΔCA ≈ +10pF
As COUT increases and the CA value is adjusted, the device bandwidth will reach its optimization level (at around
1/10th of the switching frequency). As shown in Table 1, the recommended CA value is lower for the 5V input
than 3.3V input. This is to ensure that the loop bandwidth is not over extended due to the increased gain at
the higher input voltage range. The CA value may be extrapolated for other input voltages. The limitation for
adjusting the compensation is based on diminished return. Further adjustments by increasing COUT and
increasing CA may not yield better transient response or in some situations cause lower gain and phase margin.
Over compensating with excessive output capacitance may also cause the device to trigger current limit on
startup due to the energy required to charge the output up to regulation level. Due to such limitations, the
recommended maximum output capacitance (COUT_MAX) is 400µF and the recommended maximum phase-lead
capacitance (CA_MAX) is 47pF.
Input Capacitor Selection
The input of synchronous buck regulators can be very noisy and should be decoupled properly in order to
ensure stable operation. In addition, input parasitic line inductance can attribute to higher input voltage ripple.
The EN6340QI requires a minimum of 2 x 22µF 0805 input capacitors. As the distance of the input power
source to the input of the EN6340QI is increased, it is recommended to increase input capacitance in order to
mitigate the line inductance from the source. Low-ESR ceramic capacitors should be used. The dielectric must
be X5R or X7R rated and the size must be at least 0805 (EIA) due to derating. Y5V or equivalent dielectric
formulations must not be used as these lose too much capacitance with frequency, temperature and bias
voltage. In some applications, lower value capacitors are needed in parallel with the larger capacitors in order
to provide high frequency decoupling. Larger electrolytic or tantalum bulk capacitors may be used in
conjunction to increase total input capacitance but should not be used solely as a replacement for the ceramic
capacitors.
Table 2: Recommended Input Capacitors
DESCRIPTION
MFG
Taiyo Yuden
22µF ±20%, 10V
X5R, 0805
Murata
TDK
P/N
LMK212BBJ226MG-T
GRM21BR61A226ME51
C2012X5R1A226M125AB
Output Capacitor Selection
The output ripple of a synchronous buck converter can be attributed to its inductance, switching frequency
and output decoupling. The EN6340QI requires a minimum of 2 x 47µF 0805 output capacitors. Low ESR
ceramic capacitors should be used. The dielectric must be X5R or X7R rated and the size must be at least 0805
(EIA) due to derating. Y5V or equivalent dielectric formulations must not be used as these lose too much
capacitance with frequency, temperature and bias voltage.
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Table 3: Recommended Output Capacitors
DESCRIPTION
MFG
Taiyo Yuden
47µF ±20%, 6.3V,
Murata
X5R, 0805
TDK
P/N
JMK212BBJ476MG-T
GRM21BR60J476ME15
C2012X5R0J476M125AC
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance (ESR) and effective series inductance (ESL):
Z = ESR + ESL
The resonant frequency of a ceramic capacitor is inversely proportional to the capacitance. Lower capacitance
corresponds to higher resonant frequency. When two capacitors are placed in parallel, the benefit of both are
combined. It is beneficial to decouple the output with capacitors of various capacitance and size. Placing them
all in parallel reduces the impedance and will hence result in lower output ripple.
1
Z Total
1
1
1
...
Z1 Z 2
Zn
THERMAL CONSIDERATIONS
Thermal considerations are important elements of power supply design. Whenever there are power losses in
a system, the heat that is generated by the power dissipation needs to be taken into account. The Intel Enpirion
PowerSoC technology helps alleviate some of those concerns.
The EN6340QI DC-DC converter is packaged in a 4mm x 6mm x 2.5mm 34-pin QFN package. The QFN package
is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the
package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a
heat sink. The recommended maximum junction temperature for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit
designed to turn off the device at an approximate junction temperature value of 160°C.
The following example and calculations illustrate the thermal performance of the EN6340QI with the following
parameters:
VIN = 5V
VOUT = 3.3V
IOUT = 4A
First, calculate the output power.
POUT = VOUT x IOUT = 3.3V x 4A = 13.2W
Next, determine the input power based on the efficiency (η) shown in Figure 6.
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Efficiency vs. Output Current
100
95
EFFICIENCY (%)
90
85
80
75
70
65
60
CONDITIONS
VIN = 5.0V
55
VOUT = 3.3V
50
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Figure 6: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 4A, η ≈ 94%
η = POUT / PIN = 94% = 0.94
PIN = POUT / η
PIN ≈ 13.2W / 0.94 ≈ 14W
The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
= 14W – 13.2W ≈ 0.8W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EN6340QI has a θJA value of 12.5°C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.8W x 12.5°C/W ≈ 10°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 10°C ≈ 35°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 10°C ≈ 115°C
The maximum ambient temperature the device can reach is 115°C given the input and output conditions. Note
that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate.
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APPLICATION CIRCUITS
5V
1.8V @ 4A
PVIN
10Ω
VOUT
EN6340QI
2x
22µF
0805
AVIN
PGND
2x
47µF
0805
249k
12pF
10k
ENABLE
POK
VFB
PGND
SS
15nF
124k
AGND
Figure 7: Smallest Solution Size Application Circuit for VOUT = 1.8V
1.8V @ 4A
5V
PVIN
10Ω
2x
22µF
0805
VOUT
EN6340QI
AVIN
PGND
2x
47µF
0805
249k
3x
100µF
10k
ENABLE
POK
47pF
VFB
PGND
SS
15nF
124k
AGND
Figure 8: Improved Transient Response Application Circuit for VOUT = 1.8V
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LAYOUT RECOMMENDATIONS
Figure 9 shows critical components and layer 1 traces of a recommended minimum footprint EN6340QI layout.
ENABLE and other small signal pins need to be connected and routed according to specific customer
application. Visit the Enpirion Power Solutions website at www.altera.com/powersoc for more information
regarding layout. Please refer to this Figure 9 while reading the layout recommendations in this section.
Figure 9: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN6340QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
Voltage and GND traces between the capacitors and the EN6340QI should be as close to each other as possible
so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Half of the PGND pins are dedicated to the input circuit and the other half to the output
circuit. The slit shown in Figure 9 separating the input and output GND circuits helps minimize noise coupling
between the converter input and output switching loops.
Recommendation 3: The system ground plane should be on the 2nd layer (below the surface layer). This
ground plane should be continuous and un-interrupted.
Recommendation 4: The large thermal pad underneath the device must be connected to the system ground
plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must
have at least 1-oz. copper plating on the inside wall, making the finished hole size around 0.2mm to 0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figure 9.
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Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. Put the vias under the capacitors along the edge of the GND copper closest to the Voltage copper.
Please see Figure 9. These vias connect the input/output filter capacitors to the GND plane, and help reduce
parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT,
then put them just outside the capacitors along the GND slit separating the two components. Do not use
thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 6: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 9 this connection is made at the input capacitor
furthest from the PVIN pin and on the input source side. Avoid connecting AVIN near the PVIN pin even though
it is the same node as the input ripple is higher there.
Recommendation 7: The VOUT sense point should be connected at the last output filter capacitor furthest from
the VOUT pins. Keep the sense trace as short as possible in order to avoid noise coupling into the control loop.
Recommendation 8: Keep RA, CA, RC and RB close to the VFB pin (see Figure 9). The VFB pin is a high-impedance,
sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the
AGND pin instead of going through the GND plane. The AGND should connect to the PGND at a single point
from the AGND pin to the PGND plane on the 2nd layer.
Recommendation 9: The layer 1 metal under the device must not be more than shown in Figure 9. See the
following section regarding Exposed Metal on Bottom of Package. As with any switch-mode DC-DC
converter, try not to run sensitive signal or control lines underneath the converter package on other layers.
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DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance such as in reduced electrical lead resistance and
in overall footprint; however, they do require some special considerations.
In the assembly process lead frame construction requires some of the lead-frame cantilevers be exposed at
the point where wire-bond or internal passives are attached for mechanical support. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 10.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the board.
The PCB top layer under the EN6340QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 10 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by solder mask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. See Figure 11 for details.
Figure 10: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Figure 11: Landing Pattern with Solder Stencil (Top View)
The solder stencil aperture for the thermal PGND pad is shown in Figure 11 and is based on Enpirion power product
manufacturing specifications.
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PACKAGE DIMENSIONS
Figure 12: EN6340QI Package Dimensions
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
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REVISION HISTORY
Rev
A
Date
Change(s)
July, 2017
Initial Release
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
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