DataSheeT – enpirion® power solutions
EN6382QI 8A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
FEATURES
The EN6382QI is an Intel® Enpirion® Power System on
a Chip (PowerSoC) DC-DC converter with an
integrated inductor, PWM controller, MOSFETsF and
compensation to provide the smallest solution size in
an 8x8x3mm 56 pin QFN module. It offers very high
efficiency and is able to provide 8A continuous output
current with no de-rating. The EN6382QI also
provides excellent line and load regulation over
temperature. The EN6382QI is specifically designed
to meet the precise voltage and fast transient
requirements of high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
• High Efficiency (Up to 96%)
Other features include precision enable threshold,
pre-bias monotonic start-up, and programmable
soft-start. The device’s advanced circuit techniques,
ultra-high switching frequency, and proprietary
integrated inductor technology deliver high-quality,
ultra-compact DC-DC conversion.
• RoHS Compliant, MSL Level 3, 260°C Reflow
Intel Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Enpirion products
are RoHS compliant and lead-free manufacturing
environment compatible.
• Industrial automation, servers, storage, adapter
cards, wireless base stations, test and
measurement, and embedded computing.
• Space constrained applications that require the
highest power density.
• Noise sensitive applications.
VOUT
VIN
EN
AVIN
2x
47µF
1206
EN6382QI
RA
VFB
PGND
PGND
SS
AGND
FQADJ
CA
R1
ENABLE
15nF
• Input Voltage Range (3.0V to 6.5V)
• 1.5% VFB Accuracy
• Optimized Total Solution Size (160 mm2)
• Precision Enable Threshold for Sequencing
• Programmable Soft-Start
• Pin compatible with the EN6362QI (6A)
• Thermal, Over-Current, Short Circuit, Reverse
Current Limit and Under-Voltage Protections
APPLICATIONS
• Point of Load Regulation for FPGAs, ASICs
Processors, DSPs, and Distributed Power
Architectures
Efficieny vs. Output Current
100
VOUT
10Ω
2x
22µF
1206
• Up to 8A Continuous Operating Current
RB
RFQADJ
90
EFFICIENCY (%)
PVIN
• Excellent Ripple and EMI Performance
80
70
60
50
40
0
Figure 1: Simplified Applications Circuit
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
Figure 2: Efficiency at VIN = 5V, VOUT = 3.3V
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Rev B
Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
ORDERING INFORMATION
Part Number
Package Markings
TJ Rating
Package Description
EN6382QI
EN6382QI
-40°C to +125°C
56-pin (8mm x 8mm x 3mm) QFN
EVB-EN6382QI
EN6382QI
QFN Evaluation Board
Packing and Marking Information:
https://www.intel.com/content/www/us/en/programmable/support/quality-and-reliability/packing.html
NC
NC
NC
NC
NC(SW)
NC(SW)
NC(SW)
NC(SW)
PGOOD
VSENSE
SS
FQADJ
AGND
AVIN
56
55
54
53
52
51
50
49
48
47
46
45
44
43
PIN FUNCTIONS
NC
1
42
VFB
NC
2
41
ENABLE
NC
3
40
BGND
NC
4
39
VDDB
NC
5
38
NC
NC
6
37
NC
36
PVIN
35
PVIN
34
PVIN
33
PVIN
32
PVIN
31
PVIN
30
PVIN
29
PVIN
22
23
24
25
26
27
28
NC(SW)
PGND
PGND
PGND
PGND
PGND
14
NC
NC
21
13
NC
NC
58
DNC
(VOUT)
20
12
NC
NC
19
11
NC
NC
18
10
VOUT
NC
59
DNC
(VIN)
17
9
VOUT
NC
16
8
VOUT
NC
57
PGND
15
7
VOUT
NC
60
NC
Figure 3: Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
NOTE C: Grayed-out pins are not to be soldered to the PCB. Refer to Figure for the keepout diagram.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
PIN DESCRIPTIONS
PIN
NAME
TYPE
FUNCTION
1-14,
19-22,
37-38,
53-56
NC
-
NO CONNECT: They must be soldered to PCB but not be electrically
connected to any external signal, ground, or voltage. Failure to follow this
guideline may result in device damage. (1)
15-18
VOUT
Power
Regulated converter output. Connect to the load and place output filter
capacitor(s) between these pins and PGND pins.
23
NC(SW)
-
NO CONNECT (1)
24-28
PGND
Power
Input and output power ground. Connect these pins to the ground
electrode of the input and output filter capacitors. Refer to VOUT, PVIN
descriptions and Layout Recommendation for more details.
29-36
PVIN
Power
Input power supply. Connect to input power supply and place input filter
capacitor(s) between these pins and PGND pins.
39
VDDB
Power
Internal regulated voltage used for the internal control circuitry. No
external connection needed.
40
BGND
Power
Ground for VDDB. Refer to the pin 39 description.
Analog
Device enable pin. A high level or floating this pin enables the device while
a low level disables the device. A voltage ramp from another power
converter may be applied for precision enable. Refer to Power Up
Sequencing.
41
ENABLE
42
VFB
Analog
This is the external feedback input pin. A resistor divider connects from the
output to AGND. The mid-point of the resistor divider is connected to VFB.
A feed-forward capacitor (CA) and resistor (RC) are required parallel to the
upper feedback resistor (RA). The output voltage regulation is based on the
VFB node voltage equal to 0.600V.
43
AVIN
Power
Analog input voltage for the control circuits. Connect this pin to the input
power supply (PVIN) at a quiet point, through a 10Ω resistor.
44
AGND
Power
The quiet ground for the control circuits. Connect to the ground plane with
a via right next to the pin.
45
FQADJ
Analog
Frequency adjust pin. This pin must have a resistor to AGND, which sets the
free running frequency of the internal oscillator.
46
SS
Analog
A soft-start capacitor is connected between this pin and AGND. The value
of the capacitor controls the soft-start interval. Refer to Soft-Start in the
Functional Description for more details.
47
VSENSE
Analog
This pin senses output voltage. Connect VSENSE to VOUT.
48
PGOOD
Digital
PGOOD is a logic level high when VOUT is within -10% to +10% of the
programmed output voltage (0.9VOUT_NOM ≤ VOUT ≤ 1.1VOUT_NOM). This pin has
an internal pull-up resistor to AVIN with a nominal value of 100kΩ.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
PIN
49-52
NAME
NC (SW)
TYPE
FUNCTION
-
NO CONNECT: These pins must be soldered to PCB and can be electrically
connected to each other but not to any external signal, voltage or ground.
Failure to follow this guideline may result in device damage.
Power
Not a perimeter pin. Device thermal pad must be connected to the system
GND plane for heat-sinking purposes. Refer to Layout Recommendation
section.
57
PGND
58
DNC
(VOUT)
Power
DO NOT CONNECT: Not a perimeter pin. This pin may be internally
connected and must not be soldered to the PCB or connected to any
external signal, voltage or ground.
59
DNC (VIN)
Power
DO NOT CONNECT: Not a perimeter pin. This pin may be internally
connected and must not be soldered to the PCB or connected to any
external signal, voltage or ground.
60
NC
-
Not a perimeter pin. Device mechanical pad must be soldered to the PCB
to improve Board Level Reliability. This pin may be internally connected
and must not be connected to any external signal, voltage or ground. (1)
(1) The NC pins must be soldered to PCB but not electrically connected to each other or to any external signal, voltage,
or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
PVIN, AVIN, VOUT
-0.3
7.0
V
ENABLE, PGOOD
-0.3
VIN+0.3
V
VFB, SS, FQADJ
-0.3
2.5
V
MIN
MAX
UNITS
+150
°C
+150
°C
+260
°C
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
Maximum Operating Junction
Temperature
Storage Temperature Range
Reflow Peak Body Temperature
-65
(10 Sec) MSL3 JEDEC J-STD-020A
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
MAX
UNITS
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.5
6.5
V
Output Voltage Range
VOUT
0.6
VIN – VDO (2)
V
Output Current Range
IOUT
8
A
+125
°C
Input Voltage Range
Operating Junction Temperature
TJ
-40
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
TSD
150
°C
TSDHYS
25
°C
Thermal Resistance: Junction to Ambient (0 LFM) (3)
JA
16
°C/W
Thermal Resistance: Junction to Case (0 LFM)
JC
1
°C/W
Thermal Shutdown
Thermal Shutdown Hysteresis
(2) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(3) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
ELECTRICAL CHARACTERISTICS
NOTE: VIN = 6.5V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
VFB
VFB Pin Voltage
VUVLOR
TEST CONDITIONS
TA =-40°C to 85°C,
3V ≤ VIN ≤ 6.5V, ILOAD = 0A to 8A
TA =-40°C to 105°C,
3V ≤ VIN ≤ 6.5V, ILOAD = 0A to 8A
MIN
TYP
MAX
UNITS
0.591
0.600
0.609
V
0.588
0.600
0.612
V
+10
nA
VFB Pin Input
Leakage Current
IVFB
VFB Pin Input Leakage Current
Shut-Down Supply
Current
ISD
Power Supply Current with
ENABLE=0
0.6
mA
Under Voltage Lockout (VIN Rising)
VUVLOR
Voltage Above Which UVLO is
Not Asserted
2.3
V
Under Voltage Lockout (VIN Falling)
VUVLOF
Voltage Below Which UVLO is
Asserted
2.0
V
Drop Out Voltage
VDO
VIN = 3V, VOUT set 3.3V, ILOAD =
8A, 100% duty cycle
280
600
mV
Drop Out Resistance
RDO
Input to Output Resistance
35
75
mΩ
Over Current Trip
Level
IOCP
Sourcing Current
11
16
20
A
Switching Frequency
FSW
RFQADJ = 15kΩ, VIN = 5V
1.15
1.5
1.7
MHz
86
90
93.5
%
105
112
114.5
%
0.2
V
Power Good Low
Power Good High
Range of Output Voltage as a
Fraction of Programmed Value.
PGOOD is Asserted. (4)
Range of Output Voltage as a
Fraction of Programmed Value.
-10
PGOOD is Asserted. (4)
VPGOOD Logic Level
Low
With 4mA Current Sink into
PGOOD Pin
VPGOOD Logic Level
High
VIN
V
PGOOD Internal pullup resistor
100
k
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
PARAMETER
Soft Start Current
SYMBOL
ISS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Soft start current generator
towards GND
6.5
9
11.5
µA
3.0V ≤ VIN ≤ 6.5V;
1.08
1.12
1.16
V
0.95
1.01
1.07
V
ENABLE Logic Level
VENABLE
DISABLE Logic Level
VDISABLE
ENABLE hysteresis
VEN_Hyst
110
mV
Pull-up EN resistor
REN_UP
190
kΩ
REN_DWN
110
kΩ
TOTP
150
°C
OTPHYST
25
°C
Pull-down EN resistor
OTP level
OTP hysteresis
(4) After crossing the PGOOD threshold level, there is a 63 µs (at 1.5 MHz) delay before PGOOD is de-asserted.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
TYPICAL PERFORMANCE CURVES
Efficiency vs Output Current
100
CONDITIONS
VIN= 3.0V
98
96
96
90
88
86
92
90
88
86
82
VOUT = 1.8V
0
1
2
80
3
4
5
6
OUTPUT CURRENT (A)
7
8
0
Efficiency vs Output Current
100
VIN = 3.0V
VIN = 5.0V
VIN = 6.5V
96
94
2
3
4
5
6
OUTPUT CURRENT (A)
96
92
90
88
86
7
8
CONDITIONS
VOUT = 3.3V
98
CONDITIONS
VOUT= 1.0V
94
92
90
88
86
84
84
82
82
VIN = 4.0V
VIN = 5.0V
VIN = 6.5V
80
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
0
100
90
80
70
60
50
40
30
20
10
0
1.6
EFFICIENCY (%)
1.5
1.4
1.3
1.2
1.1
1
5
10
15
20
25
30
35
40
45
50
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
Efficiency, Power Loss vs Output
Current
Frequency vs RFQADJ
1.7
1
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
CONDITIONS
VOUT = 1.0V
VIN = 6.5V
f = 1.1MHz
0
1
2
3
4
5
6
7
POWER LOSS (W)
80
FREQUENCY (MHz)
1
Efficiency vs Output Current
100
EFFICIENCY (%)
98
VOUT = 1V
VOUT = 1.8V
VOUT = 3.3V
84
VOUT = 1V
80
EFFICIENCY (%)
94
EFFICIENCY (%)
EFFICIENCY (%)
92
82
CONDITIONS
VIN= 5.0V
98
94
84
Efficiency vs Output Current
100
8
OUTPUT CURRENT (A)
RFQADJ (kΩ)
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
CONDITIONS
VOUT = 1.0V
VIN = 6.5V
f = 1.5MHz
0
1
2
3
4
5
6
7
100
90
80
70
60
50
40
30
20
10
0
CONDITIONS
VOUT = 1.0V
VIN = 6.5V
f = 1.7MHz
0
8
1
Output voltage vs Input Voltage
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4
5
6
7
8
VIN = 3.0V
0.998
CONDITIONS
VOUT = 1.0V
fSW = 1.17MHz
VIN = 5.0V
0.998
0.997
CONDITIONS
VOUT = 1.0V
fSW = 1.17MHz
0.996
0.996
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
6.0
0
6.5
18
16
16
OCP (A)
10
6
8
14
CONDITIONS
VOUT = 1.0V
12
4
OCP vs Temperature at various VIN
20
18
14
2
OUTPUT CURRENT (A)
OCP vs Temperature at various VIN
20
OCP (A)
3
Output voltage vs Output Current
0.999
Load = 0A
Load = 4A
Load = 8A
0.997
2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
0.999
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
POWER LOSS (W)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Efficiency, Power Loss vs Output
Current
EFFICIENCY (%)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
POWER LOSS (W)
Efficiency, Power Loss vs Output
Current
8
CONDITIONS
VOUT = 1.8V
12
10
8
6
6
4
4
3
5
2
0
-40
-20
3.5
5.5
0
20
4
6
40
60
80
4
5.5
2
4.5
6.5
0
100
Temperature (⁰C)
-40
-20
4.5
6
0
20
40
5
6.5
60
80
100
Temperature (⁰C)
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
GUARANTEED LOAD (A)
No Thermal Derating
10
9
8
7
6
5
4
3
2
1
0
CONDITIONS
VIN = 3V to 6.5V
VOUT = 0.6V to 3.3V
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE(°C)
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
TYPICAL PERFORMANCE CHARACTERISTICS
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
FUNCTIONAL BLOCK DIAGRAM
VSENSE
PVIN
UVLO
VDDB
PRE-BIAS
OTP
LDO
CURRENT LIMIT
BGND
P-DRIVER
NC(SW)
VOUT
FQADJ
RAMP
PWM
COMP
+
N-DRIVER
PGND
P
COMPENSATION
NETWORK
190kΩ
AVIN
+
110kΩ
ENABLE
VFB
ERROR
AMP
EN
COMP
POWER
GOOD
100kΩ
AVIN
A
SS
PGOOD
AVIN
SOFT START
MINIMUM
DETECTOR
Bandgap
Reference
AVIN
A
AGND
Figure 4: Functional Block Diagram
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN6382QI is a synchronous buck power supply with integrated power MOSFET switches and integrated
inductor. The switching supply uses voltage mode control and a low noise PWM topology. The nominal input
voltage range is 3.0 - 6.5 volts. The output voltage is programmed using an external resistor divider network.
The feedback control loop incorporates a type IV voltage mode control design. Type IV voltage mode control
maximizes control loop bandwidth and maintains excellent phase margin to improve transient performance.
Although the EN6382QI is guaranteed to support up to 8A continuous output current operation over the full
ambient temperature range (thermal design), the peak current supported before reaching OCP is substantially
higher, exceeding 11A. The operating switching frequency can be adjusted by an external resistor between
1.1MHz and 1.7MHz. The high switching frequency enables the use of small-size input and output capacitors.
EN6382QI electrical features at a glance:
•
Precision Enable Threshold
•
Soft-Start
•
Pre-bias Start-Up
•
Resistor Programmable Switching Frequency
•
Power Good
•
Over-Current/Short Circuit Protection
•
Reverse Current Limit (RCL)
•
Thermal Shutdown (OTP) with Hysteresis
•
Under-Voltage Lockout
Precision Enable
The ENABLE threshold is a precision analog voltage rather than a digital logic threshold. A precision voltage
reference and a comparator circuit are kept powered up even when ENABLE is de-asserted. The narrow voltage
gap between ENABLE Logic Low and ENABLE Logic High (about 100mV hysteresis) allows the device to turn
on at a precise enable voltage level. The precise enable threshold, in conjunction with the proper choice of
soft-start capacitors allows accurate sequencing for multiple power supplies. ENABLE has a 2ms lockout time
that prevents the device from re-enabling immediately after it has been disabled.
Soft-Start
The SS pin, in conjunction with a small external capacitor between this pin and AGND provides the soft-start
function, designed to limit in-rush current during start-up. When the part is enabled, soft-start (SS) current
generator charges the SS capacitor in a linear manner. As long as the SS voltage level is smaller than the
feedback reference (about 0.6V) the SS voltage is used as feedback reference, ensuring a linear increase of the
output voltage. Once the voltage on the SS capacitor reaches 0.6V, the minimum detector Figure 4 will select
the bandgap reference as target, while the voltage across the SS capacitor will continue ramping up until it
reaches about 1.5V. As the SS voltage slew rate depends on the SS capacitor, so does the output voltage.
The rise time is defined as the time needed by the output voltage to go from zero to 95% of the programmed
value. The rise time (tRISE) is given by the following equation:
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
tRISE [ms] = Css [nF] x 0.065
The recommended range for the value of the SS capacitor is between 4.7nF and 100nF.
Pre-Bias Start-up
The EN6382QI supports startup into a pre-biased load. A proprietary circuit ensures the output voltage rises
up from the pre-bias value to the programmed output voltage. Start-up is guaranteed to be monotonic for
pre-bias voltages in the range of 20% to 75% of the programmed output voltage with a minimum pre-bias
voltage of 300mV. Outside of the 20% to 75% range, the output voltage rise will not be monotonic. For this
feature to work properly, the EN6382QI must be enabled after VIN ramped up.
Resistor Programmable Frequency
The operation of the EN6382QI can be optimized by a proper choice of the RFQADJ resistor.
If high efficiency is the most important factor, then a lower switching frequency should be selected. If a better
transient response is the most important factor, a higher switching frequency should be selected.
The typical Frequency vs RFQADJ relationship over the suggested range of RFQADJ is shown in the typical
performance curves.
PGOOD Operation
The PGOOD pin is used only to signal whether the output voltage is within the specified range. The PGOOD
signal is asserted high when the rising output voltage exceeds 92% of the programmed output voltage.
If the output voltage falls outside the range (roughly 90% to 110%), PGOOD remains asserted for the de-glitch
time (about 63µs at 1.5MHz switching frequency). After the de-glitch time, PGOOD is de-asserted. PGOOD is
also de-asserted if the output voltage exceeds 110% of the programmed output voltage.
Over Current Protection
The current level is sensed through the High Side Switch. The OCP trip point is nominally set around 16A
average current. When the sensed current exceeds the current limit level, both power FETs are turned off for
the rest of the switching cycle. If for the next cycle the over-current condition is removed, the PWM operation
will resume. In the event the OCP circuit trips at least 8 consecutive PWM cycles, the device enters a hiccup
mode; the device is disabled for about 23ms and restarted with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition persists.
Over Temperature Protection
Temperature sensing circuits in the controller will disable operation when the junction temperature exceeds
approximately 150°C. Once the junction temperature drops by approximatively 25°C, the converter will
resume operation with a normal soft-start.
Input Under-Voltage Lock-Out
When the rising input voltage is below the required voltage level (VUVLOR), switching is inhibited; the lock-out
threshold has hysteresis to prevent chatter, thus when the device is operating around the UVLO limit, the input
voltage has to fall below the lower threshold (VUVLOF) for the device to stop switching.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
Reverse Current Limit protection
In order to prevent excessive current buildup in the low side MOSFET, a Reverse Current Limit protection is
used; if the Low side MOSFET is kept on during two full PWM cycles, the output will be left floating for the next
three cycles. This is an effective method of protecting the low side MOSFET against Over-Current during boostback.
APPLICATION INFORMATION
Output Voltage Programming and loop Compensation
The EN6382QI output voltage is programmed using a simple resistor divider network. A phase lead capacitor
plus a resistor are required for stabilizing the loop. Figure 5 shows the required components and the equations
to calculate their values.
The EN6382QI output voltage is determined by resistor divider between VOUT and AGND with the midpoint
going to VFB. During steady state operation, the voltage presented at the VFB pin is equal to the internal
voltage reference.
Most of EN6382QI compensation network is integrated; however, a phase lead capacitor and a resistor are
required in parallel with the upper resistor of the external feedback network.
Total compensation is optimized for use with two 47μF output capacitors and will result in a wide loop
bandwidth and excellent load transient performance for most applications. Additional capacitance may be
placed beyond the voltage sensing point outside the control loop. Voltage mode operation provides high noise
immunity at light load.
In some cases, modifications to the compensation or output capacitance may be required to optimize device
performance such as transient response, ripple, or hold-up time. The EN6382QI provides the capability to
modify the control loop response to allow for customization for such applications. A simulation model is
available upon request.
VOUT
CA
RA
RC
VFB
RB
A
Figure 5: External Feedback/Compensation Network
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
The feedback and compensation network values depend on the input voltage and output voltage. The external
feedback and compensation network values can be calculated using the equations below.
𝑅𝐴 = 294𝑘𝛺
𝑅𝐵 =
𝑉𝐹𝐵 × 𝑅𝐴
𝑉𝑂𝑈𝑇 − 𝑉𝐹𝐵
where VFB = 0.6V
RA & RB value must be rounded to closest standard value
𝐶𝐴 = 15pF, 𝑅𝐶 = 10𝑘𝛺
The output voltage should be sensed close to the most distant capacitor from the local output decoupling. All
components from the compensation network must be placed as close as possible to the EN6382QI, and the
output-voltage-feedback, low-impedance trace should go directly to the controller, keeping the high
impedance VFB trace as short as possible.
In order to keep the feedback signal as clean as possible, it is recommended to connect RB directly to the AGND
pin, rather than going through the GND plane.
Compensation and Transient Response
The EN6382QI uses an enhanced type III voltage mode control architecture. Most of the compensation is
internal, which simplifies the design. In some applications, improved transient performance may be desired
with additional output capacitors (COUT2). In such an instance, the phase-lead capacitor (CA) can be adjusted
depending on the total output capacitance. Depending on the compensation values , if we adding C OUT2 , then
the CA should also be increased. The relationship is linearly shown below:
Table 1: Recommended CA Capacitor with Adding COUT2
COUT2
CA
100μF
15pF
2~3x100μF
22pF
4~5x100μF
27pF
6~7x100μF
33pF
8x100μF
47pF
As COUT2 increases and the CA value is adjusted, the device bandwidth will reach its optimization level (at
around 1/10th of the switching frequency). Further adjustments by increasing COUT2 and increasing CA may not
yield better transient response or in some situations cause lower gain and phase margin. Over compensating
with excessive output capacitance may also cause the device to trigger current limit on startup due to the
energy required to charge the output up to regulation level.
Due to such limitations, the recommended maximum output capacitance (COUT2_MAX) is 800μF and the
recommended maximum phase-lead capacitance (CA_MAX) is 47pF.
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
Input Capacitor Selection
The EN6382QI has been optimized for use with two 1206 22µF input capacitors. Low ESR ceramic capacitors
are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be
used, as these significantly lose capacitance over frequency, temperature and bias voltage.
In some applications, lower value ceramic capacitors may be needed in parallel with the larger capacitors in
order to provide high frequency decoupling. The capacitors shown in the Table 2 are typical input capacitors.
Other capacitors with similar characteristics may also be used.
Table 2: Recommended Input Capacitors
Description
MFG
P/N
22µF, 10V, 20%, X5R, 1206
Murata
GRM31CR61A226ME19L
(2 capacitors needed)
Taiyo Yuden
LMK316BJ226ML-T
Output Capacitor Selection
The EN6382QI has been optimized for use with two 1206 47µF output capacitors. Low ESR, X5R or X7R
ceramic capacitors are recommended as the primary choice. Y5V or equivalent dielectric formulations must
not be used as these significantly lose capacitance over frequency, temperature and bias voltage. The
capacitors shown in the Recommended Output Capacitors Table 3 are typical output capacitors. Other
capacitors with similar characteristics may also be used. Additional bulk capacitance from 100µF to 800µF
may be placed beyond the voltage sensing point outside the control loop. This additional capacitance should
have a minimum 6mΩ ESR to ensure stable operation. Most tantalum capacitors will have more than 6mΩ of
ESR and may be used without special care. Adding distance in layout may help increase the ESR between the
feedback sense point and the bulk capacitors.
Table 3: Recommended Output Capacitors
Description
MFG
P/N
Taiyo Yuden
LMK316BJ476ML-T
47µF, 6.3V, 20%, X5R, 1206
Murata
GRM31CR60J476ME19L
(2 capacitors needed)
Taiyo Yuden
JMK316BJ476ML-T
10µF, 6.3V, 10%, X7R, 0805
(Optional 1 capacitor in
parallel with 2x47µF)
Murata
GRM21BR70J106KE76L
Taiyo Yuden
JMK212B7106KG-T
47µF, 10V, 20%, X5R, 1206
(2 capacitors needed)
Output ripple voltage is primarily determined by the aggregate output capacitor impedance. Placing multiple
capacitors in parallel reduces the impedance and hence will result in lower ripple voltage.
1
Z Total
1
1
1
...
Z1 Z 2
Zn
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Datasheet | Intel® Enpirion® Power Solutions: EN6382QI
Table 4: Typical Ripple Voltages
†
Output Capacitor Configuration
Typical Output Ripple (mVp-p)
2 x 47 µF
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