EP1S25F672C6

Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com S5V1-3.4 Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ii Altera Corporation Contents Chapter Revision Dates .......................................................................... vii About This Handbook .............................................................................. ix How to Find Information ........................................................................................................................ ix How to Contact Altera ............................................................................................................................. ix Typographic Conventions ........................................................................................................................ x Section I. Stratix Device Family Data Sheet Revision History ............................................................................................................................ Part I–1 Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Features ................................................................................................................................................... 1–2 Chapter 2. Stratix Architecture Functional Description .......................................................................................................................... 2–1 Logic Array Blocks ................................................................................................................................ 2–3 LAB Interconnects ............................................................................................................................ 2–4 LAB Control Signals ......................................................................................................................... 2–5 Logic Elements ....................................................................................................................................... 2–6 LUT Chain & Register Chain .......................................................................................................... 2–8 addnsub Signal ................................................................................................................................. 2–8 LE Operating Modes ........................................................................................................................ 2–8 Clear & Preset Logic Control ........................................................................................................ 2–13 MultiTrack Interconnect ..................................................................................................................... 2–14 TriMatrix Memory ............................................................................................................................... 2–21 Memory Modes ............................................................................................................................... 2–22 Clear Signals .................................................................................................................................... 2–24 Parity Bit Support ........................................................................................................................... 2–24 Shift Register Support .................................................................................................................... 2–25 Memory Block Size ......................................................................................................................... 2–26 Independent Clock Mode .............................................................................................................. 2–44 Input/Output Clock Mode ........................................................................................................... 2–46 Read/Write Clock Mode ............................................................................................................... 2–49 Single-Port Mode ............................................................................................................................ 2–51 Multiplier Block .............................................................................................................................. 2–57 Adder/Output Blocks ................................................................................................................... 2–61 Modes of Operation ....................................................................................................................... 2–64 Altera Corporation iii Contents Stratix Device Handbook, Volume 1 DSP Block Interface ........................................................................................................................ 2–70 PLLs & Clock Networks ..................................................................................................................... 2–73 Global & Hierarchical Clocking ................................................................................................... 2–73 Enhanced & Fast PLLs ................................................................................................................... 2–81 Enhanced PLLs ............................................................................................................................... 2–87 Fast PLLs ........................................................................................................................................ 2–100 I/O Structure ...................................................................................................................................... 2–104 Double-Data Rate I/O Pins ......................................................................................................... 2–111 External RAM Interfacing ........................................................................................................... 2–115 Programmable Drive Strength ................................................................................................... 2–119 Open-Drain Output ...................................................................................................................... 2–120 Slew-Rate Control ........................................................................................................................ 2–120 Bus Hold ........................................................................................................................................ 2–121 Programmable Pull-Up Resistor ................................................................................................ 2–122 Advanced I/O Standard Support .............................................................................................. 2–122 Differential On-Chip Termination ............................................................................................. 2–127 MultiVolt I/O Interface ............................................................................................................... 2–129 High-Speed Differential I/O Support ............................................................................................ 2–130 Dedicated Circuitry ...................................................................................................................... 2–137 Byte Alignment ............................................................................................................................. 2–140 Power Sequencing & Hot Socketing ............................................................................................... 2–140 Chapter 3. Configuration & Testing IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1 SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5 Configuration ......................................................................................................................................... 3–5 Operating Modes .............................................................................................................................. 3–5 Configuring Stratix FPGAs with JRunner .................................................................................... 3–7 Configuration Schemes ................................................................................................................... 3–7 Partial Reconfiguration .................................................................................................................... 3–7 Remote Update Configuration Modes .......................................................................................... 3–8 Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12 Custom-Built Circuitry .................................................................................................................. 3–13 Software Interface ........................................................................................................................... 3–13 Temperature Sensing Diode ............................................................................................................... 3–13 Chapter 4. DC & Switching Characteristics Operating Conditions ........................................................................................................................... 4–1 Power Consumption ........................................................................................................................... 4–17 Timing Model ....................................................................................................................................... 4–19 Preliminary & Final Timing .......................................................................................................... 4–19 Performance .................................................................................................................................... 4–20 Internal Timing Parameters .......................................................................................................... 4–22 External Timing Parameters ......................................................................................................... 4–33 Stratix External I/O Timing .......................................................................................................... 4–36 I/O Timing Measurement Methodology .................................................................................... 4–60 External I/O Delay Parameters .................................................................................................... 4–66 iv Altera Corporation Contents Contents Maximum Input & Output Clock Rates ...................................................................................... 4–76 High-Speed I/O Specification ........................................................................................................... 4–87 PLL Specifications ................................................................................................................................ 4–94 DLL Specifications ............................................................................................................................. 4–102 Chapter 5. Reference & Ordering Information Software .................................................................................................................................................. 5–1 Device Pin-Outs ..................................................................................................................................... 5–1 Ordering Information ........................................................................................................................... 5–1 Index Altera Corporation v Contents vi Stratix Device Handbook, Volume 1 Altera Corporation Chapter Revision Dates The chapters in this book, Stratix Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Introduction Revised: Part number: July 2005 S51001-3.2 Chapter 2. Stratix Architecture Revised: July 2005 Part number: S51002-3.2 Chapter 3. Configuration & Testing Revised: July 2005 Part number: S51003-1.3 Chapter 4. DC & Switching Characteristics Revised: January 2006 Part number: S51004-3.4 Chapter 5. Reference & Ordering Information Revised: September 2004 Part number: S51005-2.1 Altera Corporation vii Chapter Revision Dates viii Stratix Device Handbook, Volume 1 Altera Corporation About This Handbook This handbook provides comprehensive information about the Altera® Stratix family of devices. How to Find Information How to Contact Altera Information Type Technical support Product literature You can find more information in the following ways: ■ The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. ■ Acrobat bookmarks, which serve as an additional table of contents in PDF documents. ■ Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. ■ Numerous links, shown in green text, which allow you to jump to related information. For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada All Other Locations www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time www.altera.com www.altera.com Altera literature services literature@altera.com literature@altera.com Non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time FTP site ftp.altera.com ftp.altera.com Altera Corporation ix Typographic Conventions Typographic Conventions Visual Cue Stratix Device Handbook, Volume 1 This document uses the typographic conventions shown below. Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Designs. Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.” Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■ Bullets are used in a list of items when the sequence of the items is not important. ● • v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. x Altera Corporation Section I. Stratix Device Family Data Sheet This section provides the data sheet specifications for Stratix® devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters: Revision History Chapter 1 ■ Chapter 1, Introduction ■ Chapter 2, Stratix Architecture ■ Chapter 3, Configuration & Testing ■ Chapter 4, DC & Switching Characteristics ■ Chapter 5, Reference & Ordering Information The table below shows the revision history for Chapters 1 through 5. Date/Version Changes Made July 2005, v3.2 ● Minor content changes. September 2004, v3.1 ● Updated Table 1–6 on page 1–5. April 2004, v3.0 ● Main section page numbers changed on first page. Changed PCI-X to PCI-X 1.0 in “Features” on page 1–2. Global change from SignalTap to SignalTap II. The DSP blocks in “Features” on page 1–2 provide dedicated implementation of multipliers that are now “faster than 300 MHz.” ● ● ● January 2004, v2.2 ● Updated -5 speed grade device information in Table 1-6. October 2003, v2.1 ● Add -8 speed grade device information. July 2003, v2.0 ● Format changes throughout chapter. Altera Corporation Section I–1 Stratix Device Family Data Sheet Chapter Date/Version 2 July 2005 v3.2 Stratix Device Handbook, Volume 1 Changes Made ● ● ● September 2004, v3.1 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● April 2004, v3.0 ● ● ● ● ● ● ● ● November 2003, v2.2 ● ● ● ● ● October 2003, v2.1 ● ● ● ● ● Section I–2 Added “Clear Signals” section. Updated “Power Sequencing & Hot Socketing” section. Format changes. Updated fast regional clock networks description on page 2–73. Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2–90. Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page 2–92. Updated notes in Figure 2–55 on page 2–93. Added information about m counter to “Clock Multiplication & Division” on page 2–101. Updated Note 1 in Table 2–58 on page 2–101. Updated description of “Clock Multiplication & Division” on page 2–88. Updated Table 2–22 on page 2–102. Added references to AN 349 and AN 329 to “External RAM Interfacing” on page 2–115. Table 2–25 on page 2–116: updated the table, updated Notes 3 and 4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively. Updated Table 2–26 on page 2–117. Added information about PCI Compliance to page 2–120. Table 2–32 on page 2–126: updated the table and deleted Note 1. Updated reference to device pin-outs now being available on the web on page 2–130. Added Notes 4 and 5 to Table 2–36 on page 2–130. Updated Note 3 in Table 2–37 on page 2–131. Updated Note 5 in Table 2–41 on page 2–135. Added note 3 to rows 11 and 12 in Table 2–18. Deleted “Stratix and Stratix GX Device PLL Availability” table. Added I/O standards row in Table 2–28 that support max and min strength. Row clk [1,3,8,10] was removed from Table 2–30. Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML, LVDS, and HyperTransport technology rows in Table 2–32. Removed the Left and Right I/O Banks row in Table 2–34. Changed RCLK values in Figures 2–50 and 2–51. External RAM Interfacing section replaced. Added 672-pin BGA package information in Table 2–37. Removed support for series and parallel on-chip termination. Termination Technology renamed differential on-chip termination. Updated the number of channels per PLL in Tables 2-38 through 242. Updated Figures 2–65 and 2–67. Updated DDR I information. Updated Table 2–22. Added Tables 2–25, 2–29, 2–30, and 2–72. Updated Figures 2–59, 2–65, and 2–67. Updated the Lock Detect section. Altera Corporation Stratix Device Family Data Sheet Chapter Date/Version 2 July 2003, v2.0 Changes Made ● ● ● ● ● ● ● ● ● ● ● ● 3 July 2005, v1.3 ● Updated “Operating Modes” section. Updated “Temperature Sensing Diode” section. Updated “IEEE Std. 1149.1 (JTAG) Boundary-Scan Support” section. Updated “Configuration” section. January 2005, v1.2 ● Updated limits for JTAG chain of devices. September 2004, v1.1 ● ● ● ● 4 Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK connections. Updated ranges for EPLL post-scale and pre-scale dividers on page 2-85. Updated PLL Reconfiguration frequency from 25 to 22 MHz on page 2-87. New requirement to assert are set signal each PLL when it has to reacquire lock on either a new clock after loss of lock (page 2-96). Updated max input frequency for CLK[1,3,8,10] from 462 to 500, Table 2-24. Renamed impedance matching to series termination throughout. Updated naming convention for DQS pins on page 2-112 to match pin tables. Added DDR SDRAM Performance Specification on page 2-117. Added external reference resistor values for terminator technology (page 2-136). Added Terminator Technology Specification on pages 2-137 and 2138. Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for high speed differential channels at full speed. Wire bond package performance specification for “high” speed channels was increased to 624 Mbps from 462 Mbps throughout chapter. ● Added new section, “Stratix Automated Single Event Upset (SEU) Detection” on page 3–12. Updated description of “Custom-Built Circuitry” on page 3–13. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. January 2006, v3.4 ● Added Table 4–135. July 2005, v3.3 ● Updated Tables 4–6 and 4–30. Updated Tables 4–103 through 4–108. Updated Tables 4–114 through 4–124. Updated Table 4–129. Added Table 4–130. ● ● ● ● Altera Corporation Section I–3 Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1 Chapter Date/Version Changes Made 4 January 2005, 3.2 ● Updated rise and fall input values. September 2004, v3.1 ● Updated Note 3 in Table 4–8 on page 4–4. Updated Table 4–10 on page 4–6. Updated Table 4–20 on page 4–12 through Table 4–23 on page 4–13. Added rows VIL(AC) and VIH(AC) to each table. Updated Table 4–26 on page 4–14 through Table 4–29 on page 4–15. Updated Table 4–31 on page 4–16. Updated description of “External Timing Parameters” on page 4–33. Updated Table 4–36 on page 4–20. Added signals tOUTCO, TXZ, and TZX to Figure 4–4 on page 4–33. Added rows tM512CLKENSU and tM512CLKENH to Table 4–40 on page 4–24. Added rows tM4CLKENSU and tM4CLKENH to Table 4–41 on page 4–24. Updated Note 2 in Table 4–54 on page 4–35. Added rows tMRAMCLKENSU and tMRAMCLKENH to Table 4–42 on page 4–25. Updated Table 4–46 on page 4–29. Updated Table 4–47 on page 4–29. ● ● ● ● ● ● ● ● ● ● ● ● ● Section I–4 Altera Corporation Stratix Device Family Data Sheet Chapter Date/Version 4 Changes Made ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Altera Corporation Table 4–48 on page 4–30: added rows tM512CLKSENSU and tM512CLKENH, and updated symbol names. Updated power-up current (ICCINT) required to power a Stratix device on page 4–17. Updated Table 4–37 on page 4–22 through Table 4–43 on page 4–27. Table 4–49 on page 4–31: added rows tM4KCLKENSU, tM4KCLKENH, tM4KBESU, and tM4KBEH, deleted rows tM4KRADDRASU and tM4KRADDRH, and updated symbol names. Table 4–50 on page 4–31: added rows tMRAMCLKENSU, tMRAMCLKENH, tMRAMBESU, and tMRAMBEH, deleted rows tMRAMADDRASU and tMRAMRADDRH, and updated symbol names. Table 4–52 on page 4–34: updated table, deleted “Conditions” column, and added rows tXZ and tZX. Table 4–52 on page 4–34: updated table, deleted “Conditions” column, and added rows tXZ and tZX. Table 4–53 on page 4–34: updated table and added rows tXZPLL and tZXPLL. Updated Note 2 in Table 4–53 on page 4–34. Table 4–54 on page 4–35: updated table, deleted “Conditions” column, and added rows tXZPLL and tZXPLL. Updated Note 2 in Table 4–54 on page 4–35. Deleted Note 2 from Table 4–55 on page 4–36 through Table 4–66 on page 4–41. Updated Table 4–55 on page 4–36 through Table 4–96 on page 4–56. Added rows TXZ, TZX, TXZPLL, and TZXPLL. Added Note 4 to Table 4–101 on page 4–62. Deleted Note 1 from Table 4–67 on page 4–42 through Table 4–84 on page 4–50. Added new section “I/O Timing Measurement Methodology” on page 4–60. Deleted Note 1 from Table 4–67 on page 4–42 through Table 4–84 on page 4–50. Deleted Note 2 from Table 4–85 on page 4–51 through Table 4–96 on page 4–56. Added Note 4 to Table 4–101 on page 4–62. Table 4–102 on page 4–64: updated table and added Note 4. Updated description of “External I/O Delay Parameters” on page 4–66. Added Note 1 to Table 4–109 on page 4–73 and Table 4–110 on page 4–74. Updated Table 4–103 on page 4–66 through Table 4–110 on page 4–74. Deleted Note 2 from Table 4–103 on page 4–66 through Table 4–106 on page 4–69. Added new paragraph about output adder delays on page 4–68. Updated Table 4–110 on page 4–74. Added Note 1 to Table 4–111 through Table 4–113 on page 4–75. Section I–5 Stratix Device Family Data Sheet Chapter Stratix Device Handbook, Volume 1 Date/Version 4 Changes Made ● ● ● ● ● ● April 2004, v3.0 ● Table 4–129 on page 4–96: updated table and added Note 10. Updated Table 4–131 and Table 4–132 on page 4–100. Updated Table 4–110 on page 4–74. Updated Table 4–123 on page 4–85. Updated Table 4–124 on page 4–87. through Table 4–126 on page 4–92. Added Note 10 to Table 4–129 on page 4–96. Moved Table 4–127 on page 4–94 to correct order in the chapter. Updated Table 4–131 on page 4–100 through Table 4–132 on page 4–100. Deleted tXZ and tZX from Figure 4–4. Waveform was added to Figure 4–6. The minimum and maximum duty cycle values in Note 3 of Table 4–8 were moved to a new Table 4–9. Changes were made to values in SSTL-3 Class I and II rows in Table 4–17. Note 1 was added to Table 4–34. Added tSU_R and tSU_C rows in Table 4–38. Changed Table 4–55 title from “EP1S10 Column Pin Fast Regional Clock External I/O Timing Parameters” to “EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks.” Changed values in Tables 4–46, 4–48 to 4–51, 4–128, and 4–131. Added tARESET row in Tables 4–127 to 4–132. Deleted -5 Speed Grade column in Tables 4–117 to 4–119 and 4–122 to 4–123. Fixed differential waveform in Figure 4–1. Added “Definition of I/O Skew” section. Added tSU and tCO_C rows and made changes to values in tPRE and tCLKHL rows in Table 4–46. Values changed in the tSU and tH rows in Table 4–47. Values changed in the tM4KCLKHL row in Table 4–49. Values changed in the tMRAMCLKHL row in Table 4–50. Added Table 4–51 to “Internal Timing Parameters” section. The timing information is preliminary in Tables 4–55 through 4–96. Table 4–111 was separated into 3 tables: Tables 4–111 to 4–113. ● Updated Tables 4–127 through 4–129. ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● November 2003, v2.2 Section I–6 Updated Table 4–123 on page 4–85 through Table 4–126 on page 4–92. Updated Note 3 in Table 4–123 on page 4–85. Table 4–125 on page 4–88: moved to correct order in chapter, and updated table. Updated Table 4–126 on page 4–92. Updated Table 4–127 on page 4–94. Updated Table 4–128 on page 4–95. Altera Corporation Stratix Device Family Data Sheet Chapter Date/Version 4 October 2003, v2.1 Changes Made ● ● ● ● ● July 2003, v2.0 ● ● ● ● ● ● ● ● ● ● ● 5 Added -8 speed grade information. Updated performance information in Table 4–36. Updated timing information in Tables 4–55 through 4–96. Updated delay information in Tables 4–103 through 4–108. Updated programmable delay information in Tables 4–100 and 4–103. Updated clock rates in Tables 4–114 through 4–123. Updated speed grade information in the introduction on page 4-1. Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD are specified. Added note 6 to Table 4-32. Updated Stratix Performance Table 4-35. Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 493. The Stratix timing models are final for all devices. Updated Stratix IOE programmable delay chains in Tables 4-100 to 4101. Added single-ended I/O standard output pin delay adders for loading in Table 4-102. Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107. Updated high-speed I/O specification for J=2 in Tables 4-114 and 4115. Updated EPLL specification and fast PLL specification in Tables 4116 to 4-120. September 2004, v2.1 ● Updated reference to device pin-outs on page 5–1 to indicate that device pin-outs are no longer included in this manual and are now available on the Altera web site. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. Altera Corporation Section I–7 Stratix Device Family Data Sheet Section I–8 Stratix Device Handbook, Volume 1 Altera Corporation 1. Introduction S51001-3.2 Introduction The Stratix® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs). The following shows the main sections in the Stratix Device Family Data Sheet: Section Page Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21 Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 2–52 PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–73 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–104 High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2–130 Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2–140 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 3–1 SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Altera Corporation July 2005 1–1 Features Features The Stratix family offers the following features: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 10,570 to 79,040 LEs; see Table 1–1 Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 22 clocking resources per device region Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps) Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4 Differential on-chip termination support for LVDS Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for remote configuration updates 1–2 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Introduction Table 1–1. Stratix Device Features — EP1S10, EP1S20, EP1S25, EP1S30 Feature EP1S10 EP1S20 EP1S25 EP1S30 10,570 18,460 25,660 32,470 M512 RAM blocks (32 × 18 bits) 94 194 224 295 M4K RAM blocks (128 × 36 bits) 60 82 138 171 LEs M-RAM blocks (4K × 144 bits) 1 2 2 4 920,448 1,669,248 1,944,576 3,317,184 DSP blocks 6 10 10 12 Embedded multipliers (1) 48 80 80 96 Total RAM bits PLLs Maximum user I/O pins 6 6 6 10 426 586 706 726 Table 1–2. Stratix Device Features — EP1S40, EP1S60, EP1S80 Feature LEs EP1S40 EP1S60 EP1S80 41,250 57,120 79,040 M512 RAM blocks (32 × 18 bits) 384 574 767 M4K RAM blocks (128 × 36 bits) 183 292 364 M-RAM blocks (4K × 144 bits) Total RAM bits 4 6 9 3,423,744 5,215,104 7,427,520 DSP blocks 14 18 22 Embedded multipliers (1) 112 144 176 PLLs 12 12 12 Maximum user I/O pins 822 1,022 1,238 Note to Tables 1–1 and 1–2: (1) This parameter lists the total number of 9 × 9-bit multipliers for each device. For the total number of 18 × 18-bit multipliers per device, divide the total number of 9 × 9-bit multipliers by 2. For the total number of 36 × 36-bit multipliers per device, divide the total number of 9 × 9-bit multipliers by 8. Altera Corporation July 2005 1–3 Stratix Device Handbook, Volume 1 Features Stratix devices are available in space-saving FineLine BGA® and ball-grid array (BGA) packages (see Tables 1–3 through 1–5). All Stratix devices support vertical migration within the same package (for example, you can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672pin BGA package). Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migrational. The Quartus® II software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. You must use the pinouts for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration. Table 1–3. Stratix Package Options & I/O Pin Counts 484-Pin FineLine BGA 672-Pin FineLine BGA 780-Pin FineLine BGA 345 335 345 426 EP1S20 426 361 EP1S25 473 Device EP1S10 672-Pin BGA 956-Pin BGA 426 586 473 597 1,020-Pin FineLine BGA 1,508-Pin FineLine BGA 706 EP1S30 683 597 726 EP1S40 683 615 773 822 EP1S60 683 773 1,022 EP1S80 683 773 1,203 Note to Table 1–3: (1) All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n) that can be used for data inputs. Table 1–4. Stratix BGA Package Sizes Dimension 672 Pin 956 Pin Pitch (mm) 1.27 1.27 (mm2) 1,225 1,600 35 × 35 40 × 40 Area Length × width (mm × mm) 1–4 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Introduction Table 1–5. Stratix FineLine BGA Package Sizes 484 Pin 672 Pin 780 Pin 1,020 Pin 1,508 Pin Pitch (mm) Dimension 1.00 1.00 1.00 1.00 1.00 (mm2) 529 729 841 1,089 1,600 23 × 23 27 × 27 29 × 29 33 × 33 40 × 40 Area Length × width (mm × mm) Stratix devices are available in up to four speed grades, -5, -6, -7, and -8, with -5 being the fastest. Table 1–6 shows Stratix device speed-grade offerings. Table 1–6. Stratix Device Speed Grades 484-Pin FineLine BGA 672-Pin FineLine BGA 780-Pin FineLine BGA -6, -7 -5, -6, -7 -6, -7 -5, -6, -7 EP1S20 -6, -7 -5, -6, -7 EP1S25 -6, -7 Device EP1S10 672-Pin BGA 956-Pin BGA -6, -7 -5, -6, -7 -6, -7, -8 -5, -6, -7 1,020-Pin FineLine BGA 1,508-Pin FineLine BGA -5, -6, -7 EP1S30 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 EP1S40 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 EP1S60 -6, -7 -5, -6, -7 -6, -7 EP1S80 -6, -7 -5, -6, -7 -5, -6, -7 Altera Corporation July 2005 -5, -6, -7 1–5 Stratix Device Handbook, Volume 1 Features 1–6 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 2. Stratix Architecture S51002-3.2 Functional Description Stratix® devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device’s logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit multipliers, or one full-precision 36 × 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with Altera Corporation July 2005 2–1 Functional Description dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 2–1 shows an overview of the Stratix device. Figure 2–1. Stratix Block Diagram M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards IOEs IOEs IOEs IOEs LABs LABs LABs LABs LABs IOEs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs IOEs LABs LABs LABs LABs M-RAM Block LABs LABs DSP Block 2–2 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 2–1 lists the resources available in Stratix devices. Table 2–1. Stratix Device Resources Device M512 RAM M4K RAM Columns/Blocks Columns/Blocks M-RAM Blocks DSP Block Columns/Blocks LAB Columns LAB Rows EP1S10 4 / 94 2 / 60 1 2/6 40 30 EP1S20 6 / 194 2 / 82 2 2 / 10 52 41 EP1S25 6 / 224 3 / 138 2 2 / 10 62 46 EP1S30 7 / 295 3 / 171 4 2 / 12 67 57 EP1S40 8 / 384 3 / 183 4 2 / 14 77 61 EP1S60 10 / 574 4 / 292 6 2 / 18 90 73 EP1S80 11 / 767 4 / 364 9 2 / 22 101 91 Logic Array Blocks Altera Corporation July 2005 Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE’s LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE’s register to the adjacent LE’s register within an LAB. The Quartus® II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–2 shows the Stratix LAB. 2–3 Stratix Device Handbook, Volume 1 Logic Array Blocks Figure 2–2. Stratix LAB Structure Row Interconnects of Variable Speed & Length Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block Local Interconnect LAB Three-Sided Architecture—Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Column Interconnects of Variable Speed & Length LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB’s local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2–3 shows the direct link connection. 2–4 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–3. Direct Link Connection Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect to right Direct link interconnect to left Local Interconnect LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. Altera Corporation July 2005 2–5 Stratix Device Handbook, Volume 1 Logic Elements With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [7..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect’s inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4 shows the LAB control signal generation circuit. Figure 2–4. LAB-Wide Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Logic Elements labclkena2 labclkena1 labclk1 labclk2 labclr2 syncload asyncload or labpre labclr1 addnsub synclr The smallest unit of logic in the Stratix architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 2–5. 2–6 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–5. Stratix LE Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear LAB Carry-In Carry-In1 addnsub Carry-In0 Programmable Register LUT chain routing to next LE data1 data2 data3 Look-Up Table (LUT) Carry Chain Synchronous Load and Clear Logic PRN/ALD D Q ADATA Row, column, and direct link routing data4 ENA CLRN labclr1 labclr2 labpre/aload Chip-Wide Reset Asynchronous Clear/Preset/ Load Logic Row, column, and direct link routing Local Routing Clock & Clock Enable Select Register Feedback Register chain output labclk1 labclk2 labclkena1 labclkena2 Carry-Out0 Carry-Out1 LAB Carry-Out Each LE’s programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register’s clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated Altera Corporation July 2005 2–7 Stratix Device Handbook, Volume 1 Logic Elements functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. LUT Chain & Register Chain In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. See “MultiTrack Interconnect” on page 2–14 for more information on LUT chain and register chain connections. addnsub Signal The LE’s dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A – B. The LUT computes addition, and subtraction is computed by adding the two’s complement of the intended subtractor. The LAB-wide signal converts to two’s complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. LE Operating Modes The Stratix LE can operate in one of the following modes: ■ ■ Normal mode Dynamic arithmetic mode Each mode uses LE resources differently. In each mode, eight available inputs to the LE—the four data inputs from the LAB local interconnect; carry-in0 and carry-in1 from the previous LE; the LAB carry-in from the previous carry-chain LAB; and the register chain connection— are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, 2–8 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture asynchronous preset load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Normal Mode The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2–6). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2–6. LE in Normal Mode sload sclear (LAB Wide) (LAB Wide) aload (LAB Wide) Register chain connection addnsub (LAB Wide) (1) data1 data2 data3 cin (from cout of previous LE) 4-Input LUT ALD/PRE ADATA Q D Row, column, and direct link routing ENA CLRN Row, column, and direct link routing clock (LAB Wide) ena (LAB Wide) data4 Local routing aclr (LAB Wide) LUT chain connection Register chain output Register Feedback Note to Figure 2–6: (1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain. Altera Corporation July 2005 2–9 Stratix Device Handbook, Volume 1 Logic Elements Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 2–7, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain’s logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1. The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals—one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LABwide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. 2–10 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–7. LE in Dynamic Arithmetic Mode LAB Carry-In sload sclear (LAB Wide) (LAB Wide) Register chain connection Carry-In0 Carry-In1 addnsub (LAB Wide) (1) data1 data2 data3 LUT LUT aload (LAB Wide) ALD/PRE ADATA Q D Row, column, and direct link routing ENA CLRN Row, column, and direct link routing clock (LAB Wide) ena (LAB Wide) LUT Local routing aclr (LAB Wide) LUT chain connection LUT Register chain output Register Feedback Carry-Out0 Carry-Out1 Note to Figure 2–7: (1) The addnsub signal is tied to the carry input for the first LE of a carry chain only. Carry-Select Chain The carry-select chain provides a very fast carry-select function between LEs in arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel precomputation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. Altera Corporation July 2005 2–11 Stratix Device Handbook, Volume 1 Logic Elements Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carryout bits. An LAB-wide carry in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix™ memory and DSP blocks. A carry chain can continue as far as a full column. 2–12 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–8. Carry Select Chain LAB Carry-In 0 1 A1 B1 LE1 A2 B2 LE2 Sum1 LAB Carry-In Carry-In0 Carry-In1 A3 B3 LE3 A4 B4 LE4 A5 B5 LE5 0 Sum2 Sum3 LUT data1 data2 Sum LUT Sum4 LUT Sum5 LUT 1 A6 B6 LE6 A7 B7 LE7 A8 B8 LE8 A9 B9 LE9 A10 B10 LE10 Sum6 Carry-Out0 Carry-Out1 Sum7 Sum8 Sum9 Sum10 LAB Carry-Out Clear & Preset Logic Control LAB-wide signals control the logic for the register’s clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Stratix devices support simultaneous preset/ Altera Corporation July 2005 2–13 Stratix Device Handbook, Volume 1 MultiTrack Interconnect asynchronous load, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Stratix devices provide a chipwide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. MultiTrack Interconnect In the Stratix architecture, connections between LEs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory within the same row. These row resources include: ■ ■ ■ ■ Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device. The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. Only one side of a M-RAM block interfaces with direct link and row interconnects. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast 2–14 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–9 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and horizontal IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 2–9. R4 Interconnect Connections Adjacent LAB can Drive onto Another LAB's R4 Interconnect C4, C8, and C16 Column Interconnects (1) R4 Interconnect Driving Right R4 Interconnect Driving Left LAB Neighbor Primary LAB (2) LAB Neighbor Notes to Figure 2–9: (1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row. The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP blocks to the right or left from a source LAB. These resources are used for fast row connections in an eight-LAB region. Every LAB has its own set of R8 interconnects to drive either left or right. R8 interconnect connections between LABs in a row are similar to the R4 connections shown in Figure 2–9, with the exception that they connect to eight LABs to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects Altera Corporation July 2005 2–15 Stratix Device Handbook, Volume 1 MultiTrack Interconnect can drive other R8 interconnects to extend their range as well as C8 interconnects for row-to-row connections. One R8 interconnect is faster than two R4 interconnects connected together. R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, TriMatrix memory and DSP blocks, and horizontal IOEs. These column resources include: ■ ■ ■ ■ ■ LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device Stratix devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2–10 shows the LUT chain and register chain interconnects. 2–16 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–10. LUT Chain & Register Chain Interconnects Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1 Register Chain Routing to Adjacent LE's Register Input LE 2 Local Interconnect LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and vertical IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation July 2005 2–17 Stratix Device Handbook, Volume 1 MultiTrack Interconnect Figure 2–11. C4 Interconnect Connections Note (1) C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnect Driving Down Note to Figure 2–11: (1) Each C4 interconnect can drive either up or down four rows. 2–18 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture C8 interconnects span eight LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in Figure 2–11 with the exception that they connect to eight LABs above and below. The C8 interconnects can drive and be driven by all types of architecture blocks similar to C4 interconnects. C8 interconnects can drive each other to extend their range as well as R8 interconnects for column-to-column connections. C8 interconnects are faster than two C4 interconnects. C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross MRAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0]. Altera Corporation July 2005 2–19 Stratix Device Handbook, Volume 1 MultiTrack Interconnect Table 2–2 shows the Stratix device’s routing scheme. Table 2–2. Stratix Device Routing Scheme Direct Link Interconnect v R4 Interconnect v R8 Interconnect v v v v R24 Interconnect v C4 Interconnect v C8 Interconnect v v v v v v v v v v v v v v v M4K RAM Block v v v v v v v v M-RAM Block v v Row IOE v 2–20 Stratix Device Handbook, Volume 1 v v v v v v v v Column IOE v v v DSP Blocks v v v v v v M512 RAM Block LE v v v C16 Interconnect v v Row IOE v Column IOE Local Interconnect DSP Blocks v M-RAM Block v Register Chain M4K RAM Block LUT Chain M512 RAM Block LE C16 Interconnect C8 Interconnect C4 Interconnect R24 Interconnect R8 Interconnect R4 Interconnect Direct Link Interconnect Local Interconnect LUT Chain Source Register Chain Destination v v v v v v v v v v v Altera Corporation July 2005 Stratix Architecture TriMatrix Memory TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2–3 shows the size and features of the different RAM blocks. Table 2–3. TriMatrix Memory Features (Part 1 of 2) Memory Feature Maximum performance M512 RAM Block M4K RAM Block (32 × 18 Bits) (128 × 36 Bits) (1) True dual-port memory (1) (1) v v Simple dual-port memory v v v Single-port memory v v v Shift register v v ROM v v (2) FIFO buffer v v v v v Parity bits v v v Mixed clock mode v v v Memory initialization v v Simple dual-port memory mixed width support v v v v v Byte enable True dual-port memory mixed width support Altera Corporation July 2005 M-RAM Block (4K × 144 Bits) Power-up conditions Outputs cleared Outputs cleared Outputs unknown Register clears Input and output registers Input and output registers Output registers Mixed-port readduring-write Unknown output/old data Unknown output/old data Unknown output 2–21 Stratix Device Handbook, Volume 1 TriMatrix Memory Table 2–3. TriMatrix Memory Features (Part 2 of 2) Memory Feature Configurations M512 RAM Block M4K RAM Block (32 × 18 Bits) (128 × 36 Bits) 512 × 1 256 × 2 128 × 4 64 × 8 64 × 9 32 × 16 32 × 18 4K × 1 2K × 2 1K × 4 512 × 8 512 × 9 256 × 16 256 × 18 128 × 32 128 × 36 M-RAM Block (4K × 144 Bits) 64K × 8 64K × 9 32K × 16 32K × 18 16K × 32 16K × 36 8K × 64 8K × 72 4K × 128 4K × 144 Notes to Table 2–3: (1) (2) See Table 4–36 for maximum performance information. The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix device must write to the dual-port memory once and then disable the write-enable ports afterwards. 1 Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Memory Modes TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K and M-RAM memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2–12 shows true dual-port memory. Figure 2–12. True Dual-Port Memory Configuration A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA 2–22 Stratix Device Handbook, Volume 1 B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB Altera Corporation July 2005 Stratix Architecture In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write occurs or just read the don’t care bits. Single-port memory supports nonsimultaneous reads and writes, but the q[] port will output the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). For more information, see Chapter 2, TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2. Figure 2–13 shows these different RAM memory port configurations for TriMatrix memory. Figure 2–13. Simple Dual-Port & Single-Port Memory Configurations Simple Dual-Port Memory data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr Single-Port Memory (1) data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr Note to Figure 2–13: (1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in ×1 mode at port A and read out in ×16 mode from port B. Altera Corporation July 2005 2–23 Stratix Device Handbook, Volume 1 TriMatrix Memory TriMatrix memory architecture can implement pipelined RAM by registering both the input and output signals to the RAM block. All TriMatrix memory block inputs are registered providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (WREN) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM WREN signal while ensuring its data and address signals meet setup and hold time specifications relative to the WREN signal. The output registers can be bypassed. Flow-through reading is possible in the simple dual-port mode of M512 and M4K RAM blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple TriMatrix memory blocks. For example, two 256 × 16-bit RAM blocks can be combined to form a 256 × 32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words available in one memory block. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic. Clear Signals When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. Parity Bit Support The memory blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. You can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations. 2–24 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Shift Register Support You can configure embedded memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multichannel filtering, auto-correlation, and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w × m × n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w × m × n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 RAM block and 4,608 bits for the M4K RAM block. The total number of shift register outputs (number of taps n × width w) must be less than the maximum data width of the RAM block (18 for M512 blocks, 36 for M4K blocks). To create larger shift registers, the memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2–14 shows the TriMatrix memory block in the shift register mode. Altera Corporation July 2005 2–25 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–14. Shift Register Memory Configuration w × m × n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Memory Block Size TriMatrix memory provides three different memory sizes for efficient application support. The large number of M512 blocks are ideal for designs with many shallow first-in first-out (FIFO) buffers. M4K blocks provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large single block of RAM ideal for data packet storage. The different-sized blocks allow Stratix devices to efficiently support variable-sized memory in designs. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes. 2–26 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture M512 RAM Block The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes: ■ ■ ■ ■ ■ Simple dual-port RAM Single-port RAM FIFO ROM Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 × 1, 256 × 2, 128 × 4, 64 × 8 (64 × 9 bits with parity), and 32 × 16 (32 × 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 2–4 summarizes the possible M512 RAM block configurations. Table 2–4. M512 RAM Block Configurations (Simple Dual-Port RAM) Write Port Read Port 512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 512 × 1 v v v v v 256 × 2 v v v v v 128 × 4 v v v 64 × 8 v v 32 × 16 v v 64 × 9 32 × 18 64 × 9 32 × 18 v v v v v v When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See “I/O Structure” on page 2–104 for details on dedicated SERDES in Stratix devices. Altera Corporation July 2005 2–27 Stratix Device Handbook, Volume 1 TriMatrix Memory M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The eight labclk signals or local interconnect can drive the inclock, outclock, wren, rden, inclr, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, LEs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–15 shows the M512 RAM block control signal generation logic. The RAM blocks within Stratix devices have local interconnects to allow LEs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Up to 10 direct link input connections to the M512 RAM block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through 10 direct link interconnects. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2–16 shows the M512 RAM block to logic array interface. 2–28 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–15. M512 RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation July 2005 outclocken inclocken inclock outclock outclr wren rden inclr 2–29 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–16. M512 RAM Block LAB Row Interface C4 and C8 Interconnects R4 and R8 Interconnects 10 Direct link interconnect to adjacent LAB Direct link interconnect to adjacent LAB dataout M512 RAM Block Direct link interconnect from adjacent LAB Direct link interconnect from adjacent LAB Control Signals datain address Clocks 2 8 Small RAM Block Local Interconnect Region LAB Row Clocks M4K RAM Blocks The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes: ■ ■ ■ ■ ■ ■ True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. 2–30 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The memory address depths and output widths can be configured as 4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2–5 and 2–6 summarize the possible M4K RAM block configurations. Table 2–5. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 4K × 1 v v v v v v 2K × 2 v v v v v v 1K × 4 v v v v v v 512 × 8 v v v v v v 256 × 16 v v v v v v 128 × 32 v v v v v v 128 × 36 512 × 9 v v v 256 × 18 v v v 128 × 36 v v v Table 2–6. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 512 × 9 256 × 18 4K × 1 v v v v v 2K × 2 v v v v v 1K × 4 v v v v v 512 × 8 v v v v v 256 × 16 v v v v v 512 × 9 v v 256 × 18 v v When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w × m × n). Altera Corporation July 2005 2–31 Stratix Device Handbook, Volume 1 TriMatrix Memory M4K RAM blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 2–7 summarizes the byte selection. Table 2–7. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0] datain ×18 datain ×36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 – [26..18] [3] = 1 – [35..27] Notes to Table 2–7: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32 modes. The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The eight labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2–17. The R4, R8, C4, C8, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 2–18 shows the M4K RAM block to logic array interface. 2–32 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–17. M4K RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect alcr_a clocken_a clock_b renwe_b Local Interconnect Local Interconnect clock_a renwe_a alcr_b clocken_b Figure 2–18. M4K RAM Block LAB Row Interface C4 and C8 Interconnects Direct link interconnect to adjacent LAB R4 and R8 Interconnects 10 Direct link interconnect to adjacent LAB dataout Direct link interconnect from adjacent LAB M4K RAM Block Direct link interconnect from adjacent LAB Byte enable Control Signals Clocks address datain 8 M4K RAM Block Local Interconnect Region Altera Corporation July 2005 LAB Row Clocks 2–33 Stratix Device Handbook, Volume 1 TriMatrix Memory M-RAM Block The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes: ■ ■ ■ ■ True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM You cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. The memory address and output width can be configured as 64K × 8 (or 64K × 9 bits), 32K × 16 (or 32K × 18 bits), 16K × 32 (or 16K × 36 bits), 8K × 64 (or 8K × 72 bits), and 4K × 128 (or 4K × 144 bits). The 4K × 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2–8 and 2–9 summarize the possible M-RAM block configurations: Table 2–8. M-RAM Block Configurations (Simple Dual-Port) Write Port Read Port 64K × 9 32K × 18 16K × 36 8K × 72 64K × 9 v v v v 32K × 18 v v v v 16K × 36 v v v v 8K × 72 v v v v 4K × 144 2–34 Stratix Device Handbook, Volume 1 4K × 144 v Altera Corporation July 2005 Stratix Architecture Table 2–9. M-RAM Block Configurations (True Dual-Port) Port B Port A 64K × 9 32K × 18 16K × 36 8K × 72 64K × 9 v v v v 32K × 18 v v v v 16K × 36 v v v v 8K × 72 v v v v The read and write operation of the memory is controlled by the WREN signal, which sets the ports into either read or write modes. There is no separate read enable (RE) signal. Writing into RAM is controlled by both the WREN and byte enable (byteena) signals for each port. The default value for the byteena signal is high, in which case writing is controlled only by the WREN signal. The byte enables are available for the ×18, ×36, and ×72 modes. In the ×144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Tables 2–10 and 2–11 summarize the byte selection. Table 2–10. Byte Enable for M-RAM Blocks Notes (1), (2) Altera Corporation July 2005 byteena[3..0] datain ×18 datain ×36 datain ×72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 – [26..18] [26..18] [3] = 1 – [35..27] [35..27] [4] = 1 – – [44..36] [5] = 1 – – [53..45] [6] = 1 – – [62..54] [7] = 1 – – [71..63] 2–35 Stratix Device Handbook, Volume 1 TriMatrix Memory Table 2–11. M-RAM Combined Byte Selection for ×144 Mode Notes (1), (2) byteena[15..0] datain ×144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] Notes to Tables 2–10 and 2–11: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16, × 32, × 64, and × 128 modes. Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. All input registers—renwe, datain, address, and byte enable registers—are clocked together from either of the two clocks feeding the block. The output register can be bypassed. The eight labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 2–19. 2–36 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–19. M-RAM Block Control Signals Dedicated Row LAB Clocks 8 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clocken_b clocken_a clock_a clock_b renwe_b aclr_b aclr_a renwe_a One of the M-RAM block’s horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side closest to the device perimeter contains the interfaces. The one exception is when two M-RAM blocks are paired next to each other. In this case, the side of the M-RAM block opposite the common side of the two blocks contains the input interface. The top and bottom sides of any M-RAM block contain data input and output interfaces to the logic array. The top side has 72 data inputs and 72 data outputs for port B, and the bottom side has another 72 data inputs and 72 data outputs for port A. Figure 2–20 shows an example floorplan for the EP1S60 device and the location of the M-RAM interfaces. Altera Corporation July 2005 2–37 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–20. EP1S60 Device with M-RAM Interface Locations Note (1) Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins. M-RAM pairs interface to top, bottom, and side opposite of block-to-block border. DSP Blocks M-RAM Block M-RAM Block M-RAM Block M-RAM Block M-RAM Block M-RAM Block M512 Blocks M4K Blocks LABs DSP Blocks Note to Figure 2–20: (1) Device shown is an EP1S60 device. The number and position of M-RAM blocks varies in other devices. The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. For independent M-RAM blocks, up to 10 direct link address and control signal input connections to the M-RAM block are possible from the left adjacent LABs for M-RAM 2–38 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture blocks facing to the left, and another 10 possible from the right adjacent LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. Figures 2–21 through 2–23 show the interface between the M-RAM block and the logic array. Altera Corporation July 2005 2–39 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–21. Left-Facing M-RAM to Interconnect Interface Notes (1), (2) M512 RAM Block Columns Row Unit Interface Allows LAB Rows to Drive Address and Control Signals to M-RAM Block LABs in Column M-RAM Boundary Column Interface Block Drives to and from C4 and C8 Interconnects B1 B2 B3 B4 B5 B6 A4 A5 A6 Port B R11 R10 R9 R8 R7 M-RAM Block R6 R5 R4 R3 R2 R1 Port A A1 A2 A3 Column Interface Block Allows LAB Columns to Drive datain and dataout to and from M-RAM Block LABs in Row M-RAM Boundary LAB Interface Blocks Notes to Figure 2–21: (1) (2) Only R24 and C16 interconnects cross the M-RAM block boundaries. The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6 orientation is clipped across the vertical axis for right-facing M-RAM blocks. 2–40 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–22. M-RAM Row Unit Interface to Interconnect C4 and C8 Interconnects R4 and R8 Interconnects M-RAM Block LAB 10 Direct Link Interconnects Up to 24 addressa addressb renwe_a renwe_b byteenaA[ ] byteenaB[ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region Altera Corporation July 2005 2–41 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–23. M-RAM Column Unit Interface to Interconnect C4 and C8 Interconnects LAB LAB LAB M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block 12 12 datain dataout M-RAM Block 2–42 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Table 2–12 shows the input and output data signal connections for the column units (B1 to B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11). Table 2–12. M-RAM Row & Column Interface Unit Signals Altera Corporation July 2005 Unit Interface Block Input SIgnals R1 addressa[7..0] R2 addressa[15..8] R3 byte_enable_a[7..0] renwe_a R4 - R5 - R6 clock_a clocken_a clock_b clocken_b R7 - R8 - R9 byte_enable_b[7..0] renwe_b R10 addressb[15..8] Output Signals R11 addressb[7..0] B1 datain_b[71..60] dataout_b[71..60] B2 datain_b[59..48] dataout_b[59..48] B3 datain_b[47..36] dataout_b[47..36] B4 datain_b[35..24] dataout_b[35..24] B5 datain_b[23..12] dataout_b[23..12] B6 datain_b[11..0] dataout_b[11..0] A1 datain_a[71..60] dataout_a[71..60] A2 datain_a[59..48] dataout_a[59..48] A3 datain_a[47..36] dataout_a[47..36] A4 datain_a[35..24] dataout_a[35..24] A5 datain_a[23..12] dataout_a[23..12] A6 datain_a[11..0] dataout_a[11..0] 2–43 Stratix Device Handbook, Volume 1 TriMatrix Memory Independent Clock Mode The memory blocks implement independent clock mode for true dualport memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2–24 shows a TriMatrix memory block in independent clock mode. 2–44 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 (1) (2) Altera Corporation July 2005 clockA clkenA wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 ENA D ENA D ENA D ENA D 8 LAB Row Clocks Q Q Q Q Write Pulse Generator Q Data Out Write/Read Enable Address A qA[ ] B Data In qB[ ] Q D ENA Data Out Write/Read Enable Address B Byte Enable B Memory Block 256 ´ 16 (2) 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 Byte Enable A ENA D A Data In Write Pulse Generator Q Q Q Q D ENA D ENA D ENA D ENA 8 clockB clkenB wrenB addressB[ ] byteenaB[ ] dataB[ ] Stratix Architecture Figure 2–24. Independent Clock Mode Notes (1), (2) Notes to Figure 2–24 All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–45 Stratix Device Handbook, Volume 1 TriMatrix Memory Input/Output Clock Mode Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block’s data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2–25 and 2–26 show the memory block in input/output clock mode. 2–46 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 (1) (2) Altera Corporation July 2005 clockA clkenA wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 ENA D ENA D ENA D ENA D 8 LAB Row Clocks Q Q Q Q Write Pulse Generator Q Data Out Write/Read Enable Address A ENA D A qA[ ] Data In B qB[ ] Q D ENA Data Out Write/Read Enable Address B Byte Enable B Memory Block 256 × 16 (2) 512 × 8 1,024 × 4 2,048 × 2 4,096 × 1 Byte Enable A Data In Write Pulse Generator Q Q Q Q ENA D ENA D ENA D ENA D 8 clockB clkenB wrenB addressB[ ] byteenaB[ ] dataB[ ] Stratix Architecture Figure 2–25. Input/Output Clock Mode in True Dual-Port Mode Notes (1), (2) Notes to Figure 2–25: All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–47 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2) 8 LAB Row Clocks Memory Block 256 ´ 16 Data In 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 8 data[ ] D Q ENA address[ ] D Q ENA Read Address Data Out byteena[ ] D Q ENA Byte Enable wraddress[ ] D Q ENA Write Address D Q ENA Read Enable D Q ENA To MultiTrack Interconnect rden wren outclken inclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Notes to Figure 2–26: (1) (2) All registers shown except the rden register have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–48 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Read/Write Clock Mode The memory blocks implement read/write clock mode for simple dualport memory. You can use up to two clocks in this mode. The write clock controls the block’s data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2–27 shows a memory block in read/write clock mode. Altera Corporation July 2005 2–49 Stratix Device Handbook, Volume 1 TriMatrix Memory Figure 2–27. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2) 8 LAB Row Clocks Memory Block 256 × 16 512 × 8 1,024 × 4 Data In 2,048 × 2 4,096 × 1 8 data[ ] D Q ENA Data Out address[ ] D Q ENA Read Address wraddress[ ] D Q ENA Write Address byteena[ ] D Q ENA Byte Enable D Q ENA Read Enable D Q ENA To MultiTrack Interconnect rden wren outclken inclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Notes to Figure 2–27: (1) (2) All registers shown except the rden register have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–50 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Single-Port Mode The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2–28. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Figure 2–28. Single-Port Mode Note (1) 8 LAB Row Clocks RAM/ROM 256 × 16 512 × 8 1,024 × 4 Data In 2,048 × 2 4,096 × 1 8 data[ ] D Q ENA Data Out address[ ] D Q ENA Address D Q ENA To MultiTrack Interconnect wren Write Enable outclken inclken inclock D Q ENA Write Pulse Generator outclock Note to Figure 2–28: (1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Altera Corporation July 2005 2–51 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Digital Signal Processing Block The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these blocks have the same fundamental building block: the multiplier. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix device has two columns of DSP blocks to efficiently implement DSP functions faster than LE-based implementations. Larger Stratix devices have more DSP blocks per column (see Table 2–13). Each DSP block can be configured to support up to: ■ ■ ■ Eight 9 × 9-bit multipliers Four 18 × 18-bit multipliers One 36 × 36-bit multiplier As indicated, the Stratix DSP block can support one 36 × 36-bit multiplier in a single DSP block. This is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but the capabilities for dynamic and mixed sign multiplications are handled differently. The following list provides the largest functions that can fit into a single DSP block. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 36 × 36-bit unsigned by unsigned multiplication 36 × 36-bit signed by signed multiplication 35 × 36-bit unsigned by signed multiplication 36 × 35-bit signed by unsigned multiplication 36 × 35-bit signed by dynamic sign multiplication 35 × 36-bit dynamic sign by signed multiplication 35 × 36-bit unsigned by dynamic sign multiplication 36 × 35-bit dynamic sign by unsigned multiplication 35 × 35-bit dynamic sign multiplication when the sign controls for each operand are different 36 × 36-bit dynamic sign multiplication when the same sign control is used for both operands 1 This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions. Figure 2–29 shows one of the columns with surrounding LAB rows. 2–52 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–29. DSP Blocks Arranged in Columns DSP Block Column 8 LAB Rows Altera Corporation July 2005 DSP Block 2–53 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Table 2–13 shows the number of DSP blocks in each Stratix device. Table 2–13. DSP Blocks in Stratix Devices Notes (1), (2) DSP Blocks Total 9 × 9 Multipliers Total 18 × 18 Multipliers Total 36 × 36 Multipliers EP1S10 6 48 24 6 EP1S20 10 80 40 10 EP1S25 10 80 40 10 Device EP1S30 12 96 48 12 EP1S40 14 112 56 14 EP1S60 18 144 72 18 EP1S80 22 176 88 22 Notes to Table 2–13: (1) (2) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations. DSP block multipliers can optionally feed an adder/subtractor or accumulator within the block depending on the configuration. This makes routing to LEs easier, saves LE routing resources, and increases performance, because all connections and blocks are within the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 2–30 shows the top-level diagram of the DSP block configured for 18 × 18-bit multiplier mode. Figure 2–31 shows the 9 × 9-bit multiplier configuration of the DSP block. 2–54 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–30. DSP Block Diagram for 18 × 18-Bit Configuration Optional Serial Shift Register Inputs from Previous DSP Block Multiplier Stage D Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor Q ENA CLRN D D ENA CLRN Q Output Selection Multiplexer Q ENA CLRN Adder/ Subtractor/ Accumulator 1 D Q ENA CLRN D D ENA CLRN Q Q ENA CLRN Summation D Q ENA CLRN D D ENA CLRN Q Q Summation Stage for Adding Four Multipliers Together Optional Output Register Stage ENA CLRN Adder/ Subtractor/ Accumulator 2 D Optional Serial Shift Register Outputs to Next DSP Block in the Column Q ENA CLRN D D ENA CLRN Q ENA CLRN Altera Corporation July 2005 Q Optional Pipeline Register Stage Optional Input Register Stage with Parallel Input or Shift Register Configuration to MultiTrack Interconnect 2–55 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Figure 2–31. DSP Block Diagram for 9 × 9-Bit Configuration D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 1a CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN Summation D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 1b CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN Output Selection Multiplexer CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN D Q ENA CLRN Adder/ Subtractor/ 2a CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN Summation D Q ENA CLRN D Q ENA D Q ENA CLRN Adder/ Subtractor/ 2b CLRN D Q ENA CLRN D Q ENA D Q ENA CLRN CLRN To MultiTrack Interconnect 2–56 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The DSP block consists of the following elements: ■ ■ Multiplier block Adder/output block Multiplier Block The DSP block multiplier block consists of the input registers, a multiplier, and pipeline register for pipelining multiply-accumulate and multiply-add/subtract functions as shown in Figure 2–32. Figure 2–32. Multiplier Sub-Block within Stratix DSP Block sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0] shiftin A shiftin B D Data A Q ENA CLRN D ENA Q CLRN D Data B Q ENA Result to Adder blocks Optional Multiply-Accumulate and Multiply-Add Pipeline CLRN shiftout B shiftout A Note to Figure 2–32: (1) These signals can be unregistered or registered once to match data path pipelines if required. Altera Corporation July 2005 2–57 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Input Registers A bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multiplier. When these registers are configured for parallel data inputs, they are driven by regular routing resources. You can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of A and B inputs for each multiplier in the DSP block. You select these control signals from a set of four different clock[3..0], aclr[3..0], and ena[3..0] signals that drive the entire DSP block. You can also configure the input registers for a shift register application. In this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftoutA and shiftoutB. The shift outputs of one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block) as shown in Figure 2–33, to form a shift register chain. This chain can terminate in any block, that is, you can create any length of shift register chain up to 224 registers. You can use the input shift registers for FIR filter applications. One set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. When implementing 9 × 9- and 18 × 18-bit multipliers, you do not need to implement external shift registers in LAB LEs. You implement all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 × 36-bit multipliers. 2–58 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–33. Multiplier Sub-Blocks Using Input Shift Register Connections Note (1) Data A D Q ENA A[n] × B[n] CLRN D Data B Q D ENA Q CLRN ENA CLRN Data B Data A D Q ENA A[n Ð 1] × B[n Ð 1] CLRN D Q D ENA Q CLRN ENA CLRN Data B Data A D Q ENA A[n Ð 2] × B[n Ð 2] CLRN D Q D ENA Q CLRN ENA CLRN Note to Figure 2–33: (1) Altera Corporation July 2005 Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication. 2–59 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Table 2–14 shows the summary of input register modes for the DSP block. Table 2–14. Input Register Modes Register Input Mode 9×9 18 × 18 36 × 36 Parallel input v v v Shift register input v v Multiplier The multiplier supports 9 × 9-, 18 × 18-, or 36 × 36-bit multiplication. Each DSP block supports eight possible 9 × 9-bit or smaller multipliers. There are four multiplier blocks available for multipliers larger than 9 × 9 bits but smaller than 18 × 18 bits. There is one multiplier block available for multipliers larger than 18 × 18 bits but smaller than or equal to 36 × 36 bits. The ability to have several small multipliers is useful in applications such as video processing. Large multipliers greater than 18 × 18 bits are useful for applications such as the mantissa multiplication of a singleprecision floating-point number. The multiplier operands can be signed or unsigned numbers, where the result is signed if either input is signed as shown in Table 2–15. The sign_a and sign_b signals provide dynamic control of each operand’s representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. These sign signals affect all multipliers and adders within a single DSP block and you can register them to match the data path pipeline. The multipliers are full precision (that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and so on) regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers. Table 2–15. Multiplier Signed Representation 2–60 Stratix Device Handbook, Volume 1 Data A Data B Result Unsigned Unsigned Unsigned Unsigned Signed Signed Signed Unsigned Signed Signed Signed Signed Altera Corporation July 2005 Stratix Architecture Pipeline/Post Multiply Register The output of 9 × 9- or 18 × 18-bit multipliers can optionally feed a register to pipeline multiply-accumulate and multiply-add/subtract functions. For 36 × 36-bit multipliers, this register will pipeline the multiplier function. Adder/Output Blocks The result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtractor/accumulator unit, summation unit, output select multiplexer, and output registers. The results are used to configure the adder/output block as a pure output, accumulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. You can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Figure 2–34 shows the adder and output stages. Altera Corporation July 2005 2–61 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Figure 2–34. Adder/Output Blocks Note (1) Accumulator Feedback accum_sload0 (2) Result A addnsub1 (2) overflow0 Adder/ Subtractor/ Accumulator1 Output Selection Multiplexer Result B signa (2) Summation Output Register Block signb (2) Result C addnsub3 (2) Adder/ Subtractor/ Accumulator2 overflow1 Result D accum_sload1 (2) Accumulator Feedback Notes to Figure 2–34: (1) (2) Adder/output block shown in Figure 2–34 is in 18 × 18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor blocks and two summation blocks. These signals are either not registered, registered once, or registered twice to match the data path pipeline. 2–62 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Adder/Subtractor/Accumulator The adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumulator or as an adder/subtractor. Adder/Subtractor Each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each firstlevel adder in 18 × 18-bit mode. There are two addnsub[1..0] signals available in a DSP block for any configuration. For 9 × 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. A high addnsub signal indicates addition, and a low signal indicates subtraction. The addnsub control signal can be unregistered or registered once or twice when feeding the adder blocks to match data path pipelines. The signa and signb signals serve the same function as the multiplier block signa and signb signals. The only difference is that these signals can be registered up to two times. These signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. Accumulator When configured for accumulation, the adder/output block output feeds back to the accumulator as shown in Figure 2–34. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. Additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. This signal is always registered and must be externally latched in LEs if the design requires a latched overflow signal. Summation The output of the adder/subtractor/accumulator block feeds to an optional summation block. This block sums the outputs of the DSP block multipliers. In 9 × 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 × 9-bit multipliers. In 18 × 18-bit mode, there is one summation providing the sum of one set of four 18 × 18-bit multipliers. Altera Corporation July 2005 2–63 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Output Selection Multiplexer The outputs from the various elements of the adder/output block are routed through an output selection multiplexer. Based on the DSP block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output. Output Registers Optional output registers for the DSP block outputs are controlled by four sets of control signals: clock[3..0], aclr[3..0], and ena[3..0]. Output registers can be used in any mode. Modes of Operation The adder, subtractor, and accumulate functions of a DSP block have four modes of operation: ■ ■ ■ ■ Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder 1 Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported. Simple Multiplier Mode In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register. Up to four 18 × 18-bit multipliers or eight 9 × 9-bit multipliers can drive their results directly out of one DSP block. See Figure 2–35. 2–64 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–35. Simple Multiplier Mode signa (1) signb (1) aclr clock ena shiftin A shiftin B D Data A Q Data Out ENA CLRN D ENA Q D ENA Q CLRN CLRN D Data B Q ENA CLRN shiftout B shiftout A Note to Figure 2–35: (1) These signals are not registered or registered once to match the data path pipeline. DSP blocks can also implement one 36 × 36-bit multiplier in multiplier mode. DSP blocks use four 18 × 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. The input shift register feature is not available for the 36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 × 36-bit multiplier. Figure 2–36 shows the 36 × 36-bit multiply mode. Altera Corporation July 2005 2–65 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Figure 2–36. 36 × 36 Multiply Mode signa (1) signb (1) aclr clock ena A[17..0] D Q ENA CLRN D Q ENA CLRN B[17..0] D Q ENA CLRN A[35..18] D Q CLRN D Q ENA 36 × 36 Multiplier Adder CLRN B[35..18] D Data Out D Q ENA ENA CLRN Q signa (2) ENA signb (2) CLRN A[35..18] D Q ENA CLRN D Q ENA CLRN B[17..0] D Q ENA CLRN A[17..0] D Q ENA CLRN D Q ENA CLRN B[35..18] D Q ENA CLRN Notes to Figure 2–36: (1) (2) These signals are not registered or registered once to match the pipeline. These signals are not registered, registered once, or registered twice for latency to match the pipeline. 2–66 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Multiply-Accumulator Mode In multiply-accumulator mode (see Figure 2–37), the DSP block drives multiplied results to the adder/subtractor/accumulator block configured as an accumulator. You can implement one or two multiply-accumulators up to 18 × 18 bits in one DSP block. The first and third multiplier subblocks are unused in this mode, because only one multiplier can feed one of two accumulators. The multiply-accumulator output can be up to 52 bits—a maximum of a 36-bit result with 16 bits of accumulation. The accum_sload and overflow signals are only available in this mode. The addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. Figure 2–37. Multiply-Accumulate Mode signa (1) signb (1) aclr clock ena Shiftin A Shiftin B D Data A Q ENA CLRN D Q ENA Accumulator D Q ENA Data Out CLRN CLRN D Data B Q overflow ENA CLRN Shiftout B Shiftout A addnsub (2) signa (2) signb (2) accum_sload (2) Notes to Figure 2–37: (1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. Two-Multipliers Adder Mode The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A Altera Corporation July 2005 2–67 Stratix Device Handbook, Volume 1 Digital Signal Processing Block single DSP block can implement two sums or differences from two 18 × 18-bit multipliers each or four sums or differences from two 9 × 9-bit multipliers each. You can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) × (c + jd) = [(a × c) – (b × d)] + j × [(a × d) + (b × c)] The two-multipliers adder mode allows a single DSP block to calculate the real part [(a × c) – (b × d)] using one subtractor and the imaginary part [(a × d) + (b × c)] using one adder, for data widths up to 18 bits. Two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. Figure 2–38 shows an 18-bit two-multipliers adder. Figure 2–38. Two-Multipliers Adder Mode Implementing Complex Multiply 18 DSP Block 18 A 36 18 18 C 18 37 (A × C) − (B × D) (Real Part) Subtractor 18 B 36 18 18 D 18 A 36 18 D 37 Adder 18 B (A × D) + (B × C) (Imaginary Part) 36 18 C Four-Multipliers Adder Mode In the four-multipliers adder mode, the DSP block adds the results of two first -stage adder/subtractor blocks. One sum of four 18 × 18-bit multipliers or two different sums of two sets of four 9 × 9-bit multipliers can be implemented in a single DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. Figure 2–39 shows the four multipliers adder mode. 2–68 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–39. Four-Multipliers Adder Mode signa (1) signb (1) aclr clock ena shiftin A shiftin B D Data A Q ENA CLRN D ENA Q Adder/Subtractor CLRN D Data B Q ENA CLRN D Data A Q D ENA ENA CLRN D ENA Q CLRN D Data B Q addnsub1 (2) signa (2) signb (2) Q Data Out Summation CLRN addnsub3 (2) ENA CLRN D Data A Q ENA CLRN D ENA Q Adder/Subtractor CLRN D Data B Q ENA CLRN D Data A Q ENA CLRN D ENA Q CLRN D Data B Q ENA CLRN shiftout B shiftout A Notes to Figure 2–39: (1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. Altera Corporation July 2005 2–69 Stratix Device Handbook, Volume 1 Digital Signal Processing Block For FIR filters, the DSP block combines the four-multipliers adder mode with the shift register inputs. One set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. The input shift register eliminates the need for shift registers external to the DSP block (i.e., implemented in LEs). This architecture simplifies filter design since the DSP block implements all of the filter circuitry. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, DSP blocks can be cascaded with additional adder stages implemented in LEs. Table 2–16 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions. Table 2–16. Multiplier Size & Configurations per DSP block DSP Block Mode 9×9 18 × 18 36 × 36 (1) Multiplier Eight multipliers with eight product outputs Four multipliers with four product outputs One multiplier with one product output Multiply-accumulator Two multiply and accumulate (52 bits) Two multiply and accumulate (52 bits) – Two-multipliers adder Four sums of two multiplier products each Two sums of two multiplier products each – Four-multipliers adder Two sums of four multiplier products each One sum of four multiplier products each – Note to Table 2–16: (1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations. DSP Block Interface Stratix device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than four taps, with additional adder stages implemented in LEs. If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks. 2–70 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The DSP block is divided into eight block units that interface with eight LAB rows on the left and right. Each block unit can be considered half of an 18 × 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 10 direct link interconnects from the LAB to the left or right of the DSP block in the same row. All row and column routing resources can access the DSP block’s local interconnect region. The outputs also work similarly to LAB outputs as well. Nine outputs from the DSP block can drive to the left LAB through direct link interconnects and nine can drive to the right LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. Figures 2–40 and 2–41 show the DSP block interfaces to LAB rows. Figure 2–40. DSP Block Interconnect Interface DSP Block MultiTrack Interconnect OA[17..0] MultiTrack Interconnect A1[17..0] OB[17..0] B1[17..0] OC[17..0] A2[17..0] OD[17..0] B2[17..0] OE[17..0] A3[17..0] OF[17..0] B3[17..0] OG[17..0] A4[17..0] OH[17..0] B4[17..0] Altera Corporation July 2005 2–71 Stratix Device Handbook, Volume 1 Digital Signal Processing Block Figure 2–41. DSP Block Interface to Interconnect C4 and C8 Interconnects Direct Link Interconnect from Adjacent LAB R4 and R8 Interconnects Nine Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB 18 DSP Block Row Structure LAB 10 LAB 9 9 10 3 Control 18 18 [17..0] [17..0] Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The 2–72 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2–17. Table 2–17. DSP Block Signal Sources & Destinations LAB Row at Interface PLLs & Clock Networks Control Signals Generated Data Inputs Data Outputs 1 signa A1[17..0] OA[17..0] 2 aclr0 accum_sload0 B1[17..0] OB[17..0] 3 addnsub1 clock0 ena0 A2[17..0] OC[17..0] 4 aclr1 clock1 ena1 B2[17..0] OD[17..0] 5 aclr2 clock2 ena2 A3[17..0] OE[17..0] 6 sign_b clock3 ena3 B3[17..0] OF[17..0] 7 clear3 accum_sload1 A4[17..0] OG[17..0] 8 addnsub3 B4[17..0] OH[17..0] Stratix devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Global & Hierarchical Clocking Stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks (for EP1S10, EP1S20, and EP1S25 devices), and 16 dedicated fast regional clock networks (for EP1S30 EP1S40, and EP1S60, and EP1S80 devices). These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within Stratix devices. Altera Corporation July 2005 2–73 Stratix Device Handbook, Volume 1 PLLs & Clock Networks There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figure 2–42. Enhanced and fast PLL outputs can also drive the global and regional clock networks. Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device—IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–42 shows the 16 dedicated CLK pins driving global clock networks. 2–74 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–42. Global Clocking Note (1) CLK[15..12] Global Clock [15..0] CLK[3..0] Global Clock [15..0] CLK[11..8] CLK[7..4] Note to Figure 2–42: (1) The corner fast PLLs can also be driven through the global or regional clock networks. The global or regional clock input to the fast PLL can be driven by an output from another PLL, a pin-driven global or regional clock, or internallygenerated global signals. Regional Clock Network There are four regional clock networks within each quadrant of the Stratix device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the top left quadrant, RCLK[8..11] are in the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and RCLK[12..15] are in the bottom-right quadrant. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. RCLK cannot be driven by internal logic. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 2–43. See Figures 2–50 and 2–51 for RCLK connections from PLLs and CLK pins. Altera Corporation July 2005 2–75 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Figure 2–43. Regional Clocks RCLK[2..3] RCLK[11..10] CLK[15..12] RCLK[9..8] RCLK[1..0] CLK[3..0] CLK[11..8] RCLK[14..15] RCLK[4..5] CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant RCLK[6..7] RCLK[12..13] Fast Regional Clock Network In EP1S25, EP1S20, and EP1S10 devices, there are two fast regional clock networks, FCLK[1..0], within each quadrant, fed by input pins that can connect to fast regional clock networks (see Figure 2–44). In EP1S30 and larger devices, there are two fast regional clock networks within each half-quadrant (see Figure 2–45). Dual-purpose FCLK pins drive the fast clock networks. All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. This signal is driven via the I/O interconnect. The fast regional clock networks can also be driven from internal logic elements. 2–76 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–44. EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks FCLK[1..0] FCLK[7..6] 2 (1), (2) 2 (1), (2) 2 2 FCLK[1..0] FCLK[1..0] FCLK[1..0] FCLK[1..0] 2 (1), (2) 2 (1), (2) 2 FCLK[3..2] 2 FCLK[5..4] Notes to Figure 2–44: (1) (2) Altera Corporation July 2005 This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect. 2–77 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks FCLK1 FCLK0 (1), (2) FCLK7 FCLK6 (1), (2) (1), (2) (1), (2) fclk[1..0] (1), (2) (1), (2) (1), (2) FCLK3 FCLK2 (1), (2) FCLK5 FCLK4 Notes to Figure 2–45: (1) (2) This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect. Combined Resources Within each region, there are 22 distinct dedicated clocking resources consisting of 16 global clock lines, four regional clock lines, and two fast regional clock lines. Multiplexers are used with these clocks to form eight bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select two of the eight row clocks to feed the LE registers within the LAB. See Figure 2–46. 2–78 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–46. Regional Clock Bus Clocks Available to a Quadrant or Half-Quadrant Vertical I/O Cell IO_CLK[7..0] Global Clock Network [15..0] Regional Clock Network [3..0] Clock [21..0] Lab Row Clock [7..0] Fast Regional Clock Network [1..0] Horizontal I/O Cell IO_CLK[7..0] IOE clocks have horizontal and vertical block regions that are clocked by eight I/O clock signals chosen from the 22 quadrant or half-quadrant clock resources. Figures 2–47 and 2–48 show the quadrant and halfquadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins). Altera Corporation July 2005 2–79 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Figure 2–47. EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups IO_CLKA[7..0] IO_CLKB[7..0] 8 8 I/O Clock Regions 8 22 Clocks in the Quadrant 22 Clocks in the Quadrant IO_CLKH[7..0] IO_CLKC[7..0] 8 8 IO_CLKG[7..0] IO_CLKD[7..0] 22 Clocks in the Quadrant 22 Clocks in the Quadrant 8 8 8 IO_CLKF[7..0] 2–80 Stratix Device Handbook, Volume 1 IO_CLKE[7..0] Altera Corporation July 2005 Stratix Architecture Figure 2–48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups IO_CLKA[7:0] IO_CLKB[7:0] 8 IO_CLKC[7:0] 8 IO_CLKD[7:0] 8 8 I/O Clock Regions 8 8 IO_CLKE[7:0] IO_CLKP[7:0] 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8 8 IO_CLKF[7:0] IO_CLKO[7:0] 8 8 IO_CLKN[7:0] IO_CLKG[7:0] 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8 8 IO_CLKH[7:0] IO_CLKM[7:0] 8 8 IO_CLKL[7:0] 8 IO_CLKK[7:0] 8 IO_CLKJ[7:0] IO_CLKI[7:0] You can use the Quartus II software to control whether a clock input pin is either global, regional, or fast regional. The Quartus II software automatically selects the clocking resources if not specified. Enhanced & Fast PLLs Stratix devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clockfrequency synthesis. With features such as clock switchover, spread spectrum clocking, programmable bandwidth, phase and delay control, and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs Altera Corporation July 2005 2–81 Stratix Device Handbook, Volume 1 PLLs & Clock Networks provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Table 2–18 shows the PLLs available for each Stratix device. Table 2–18. Stratix Device PLL Availability Fast PLLs Enhanced PLLs Device 1 2 3 4 EP1S10 v v v EP1S20 v v EP1S25 v v EP1S30 v v 5(1) 6(1) v v v v v v v v v v 7 8 9 10 v v v v (3) v (3) v (3) v (3) v v v (3) v (3) v (3) v v 11(2) 12(2) EP1S40 v v v v v (3) EP1S60 v v v v v v v v v v v v EP1S80 v v v v v v v v v v v v v(3) v(3) Notes to Table 2–18: (1) (2) (3) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output. EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA® package. 2–82 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Table 2–19 shows the enhanced PLL and fast PLL features in Stratix devices. Table 2–19. Stratix PLL Features Feature Enhanced PLL Fast PLL Clock multiplication and division m/(n × post-scale counter) (1) m/(post-scale counter) (2) Phase shift Down to 156.25-ps increments (3), (4) Down to 125-ps increments (3), (4) Delay shift 250-ps increments for ±3 ns Clock switchover v PLL reconfiguration v Programmable bandwidth v Spread spectrum clocking v Programmable duty cycle v v Number of internal clock outputs 6 3 (5) Number of external clock outputs Four differential/eight singled-ended or one single-ended (6) (7) Number of feedback clock inputs 2 (8) Notes to Table 2–19: (1) (2) (3) (4) (5) (6) (7) (8) For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. For fast PLLs, m and post-scale counters range from 1 to 32. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. For degree increments, Stratix devices can shift all output frequencies in increments of at least 45° . Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output. Devices in the 780 pin FineLine BGA packages do not support PLLs 11 and 12. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL. Altera Corporation July 2005 2–83 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Figure 2–49 shows a top-level diagram of the Stratix device and PLL floorplan. Figure 2–49. PLL Locations CLK[15..12] 5 11 FPLL7CLK 7 10 FPLL10CLK CLK[3..0] 1 2 4 3 CLK[8..11] 8 9 FPLL9CLK PLLs FPLL8CLK 6 12 CLK[7..4] 2–84 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–50 shows the global and regional clocking from the PLL outputs and the CLK pins. Figure 2–50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs Note (1), (2) RCLK1 RCLK0 FPLL7CLK G1 G0 G3 G2 G8 G9 G10 G11 RCLK9 RCLK8 l0 l0 PLL 7 l1 CLK0 CLK1 l1 PLL 10 g0 g0 l0 l0 PLL 1 l1 l1 PLL 4 g0 CLK2 CLK3 CLK10 CLK11 g0 l02 PLL 2 l1 g0 2l0 l1 PLL 3 g0 l0 FPLL8CLK FPLL10CLK CLK8 CLK9 l0 PLL 8 l1 g0 l1 PLL 9 g0 RCLK4 RCLK5 Regional Clocks FPLL9CLK RCLK14 Global Clocks RCLK15 Regional Clocks Notes to Figure 2–50: (1) (2) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. Figure 2–51 shows the global and regional clocking from enhanced PLL outputs and top CLK pins. Altera Corporation July 2005 2–85 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Figure 2–51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs Note (1) PLL5_OUT[3..0] CLK14 (1) PLL5_FB CLK15 (2) CLK12 (1) CLK13 (2) E[0..3] PLL 5 PLL 11 L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL11_OUT RCLK10 RCLK11 Regional Clocks RCLK2 RCLK3 G12 G13 G14 G15 Global Clocks Regional Clocks G4 G5 G6 G7 RCLK6 RCLK7 RCLK12 RCLK13 PLL12_OUT L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL 6 PLL6_OUT[3..0] PLL 12 PLL6_FB CLK4 (1) CLK6 (1) CLK7 (2) CLK5 (2) Notes to Figure 2–51: (1) (2) (3) (4) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port. CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12. 2–86 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Enhanced PLLs Stratix devices contain up to four enhanced PLLs with advanced clock management features. Figure 2–52 shows a diagram of the enhanced PLL. Figure 2–52. Stratix Enhanced PLL Programmable Time Delay on Each PLL Port Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL /l0 Δt /l1 Δt Regional Clocks Clock Switch-Over Circuitry Spread Spectrum Phase Frequency Detector INCLK0 4 Δt /n PFD Charge Pump 8 Loop Filter VCO INCLK1 (1) FBIN Δt /m /g0 Δt /g1 Δt /g2 Δt /g3 Δt Global Clocks I/O buffers (2) To I/O buffers or general routing Lock Detect & Filter VCO Phase Selection Affecting All Outputs /e0 Δt /e1 Δt /e2 Δt /e3 Δt 4 I/O Buffers (3) Notes to Figure 2–52: (1) (2) (3) (4) External feedback is available in PLLs 5 and 6. This single-ended external output is available from the g0 counter for PLLs 11 and 12. These four counters and external outputs are available in PLLs 5 and 6. This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12. Altera Corporation July 2005 2–87 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Clock Multiplication & Division Each Stratix device enhanced PLL provides clock synthesis for PLL output ports using m/(n × post-scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN × (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO’s range). There is one pre-scale counter, n, and one multiply counter, m, per PLL, with a range of 1 to 512 on each. There are two post-scale counters (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. The post-scale counters range from 1 to 512 with any non-50% duty cycle setting. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. Clock Switchover To effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. For this reason, Stratix device enhanced PLLs support a flexible clock switchover capability. Figure 2–53 shows a block diagram of the switchover circuit.The switchover circuit is configurable, so you can define how to implement it. Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present. 2–88 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–53. Clock Switchover Circuitry CLK0_BAD CLK1_BAD Active Clock SMCLKSW Clock Sense Switch-Over State Machine CLKLOSS CLKSWITCH Δt INCLK0 MUXOUT INCLK1 n Counter PFD FBCLK Enhanced PLL There are two possible ways to use the clock switchover feature. ■ ■ Altera Corporation July 2005 Use automatic switchover circuitry for switching between inputs of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 2–53. In this case, the secondary clock becomes the reference clock for the PLL. Use the clkswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than ±20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. You can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. 2–89 Stratix Device Handbook, Volume 1 PLLs & Clock Networks During switchover, the PLL VCO continues to run and will either slow down or speed up, generating frequency drift on the PLL outputs. The clock switchover transitions without any glitches. After the switch, there is a finite resynchronization period to lock onto new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock relates to the PLL configuration and may be adjusted by using the programmable bandwidth feature of the PLL. The specification for the maximum time to relock is 100 µs. f For more information on clock switchover, see AN 313, Implementing Clock Switchover in Stratix & Stratix GX Devices. PLL Reconfiguration The PLL reconfiguration feature enables system logic to change Stratix device enhanced PLL counters and delay elements without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis, allowing real-time PLL frequency and output clock delay variation. You can sweep the PLL output frequencies and clock delay in prototype environments. The PLL reconfiguration feature can also dynamically or intelligently control system clock speeds or tCO delays in end systems. Clock delay elements at each PLL output port implement variable delay. Figure 2–54 shows a diagram of the overall dynamic PLL control feature for the counters and the clock delay elements. The configuration time is less than 20 μs for the enhanced PLL using a input shift clock rate of 22 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted. 2–90 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–54. Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs Counters and Clock Delay Settings are Programmable fREF Δt ÷n All Output Counters and Clock Delay Settings can be Programmed Dynamically PFD Charge Pump Loop Filter VCO ÷g Δt ÷l Δt ÷e Δt scandata scanclk ÷m Δt scanaclr PLL reconfiguration data is shifted into serial registers from the logic array or external devices. The PLL input shift data uses a reference input shift clock. Once the last bit of the serial chain is clocked in, the register chain is synchronously loaded into the PLL configuration bits. The shift circuitry also provides an asynchronous clear for the serial registers. f For more information on PLL reconfiguration, see AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices. Programmable Bandwidth You have advanced control of the PLL bandwidth using the programmable control of the PLL loop characteristics, including loop filter and charge pump. The PLL’s bandwidth is a measure of its ability to track the input clock and jitter. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. It also will allow a wide band of input jitter spectrum to pass to the output. A lowbandwidth PLL will take longer to lock, but it will attenuate all highfrequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable Altera Corporation July 2005 2–91 Stratix Device Handbook, Volume 1 PLLs & Clock Networks bandwidth is tuned by varying the charge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. You can manually adjust these values if desired. Bandwidth is programmable from 200 kHz to 1.5 MHz. External Clock Outputs Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). Differential SSTL and HSTL outputs are implemented using 2 single-ended output buffers which are programmed to have opposite polarity. In Quartus II software, simply assign the appropriate differential I/O standard and the software will implement the inversion. See Figure 2–55. 2–92 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–55. External Clock Outputs for PLLs 5 & 6 From IOE (1), (2) pll_out0p (3), (4) (3) e0 Counter From IOE (1) From IOE (1) pll_out0n (3), (4) pll_out1p (3), (4) e1 Counter 4 From IOE (1) From IOE (1) pll_out1n (3), (4) pll_out2p (3), (4) e2 Counter pll_out2n (3), (4) From IOE (1) From IOE (1) pll_out3p (3), (4) e3 Counter From IOE (1) pll_out3n (3), (4) Notes to Figure 2–55: (1) (2) (3) (4) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter⎯either two outputs of the same frequency and phase or one shifted 180° . EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n). Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are programmed to have opposite polarity. Altera Corporation July 2005 2–93 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock’s overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180° out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table 2–20 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. You can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed. Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK LVTTL v v v v LVCMOS v v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v v v 3.3-V PCI-X 1.0 v v v LVPECL v v v 3.3-V PCML v v v LVDS v v v HyperTransport technology v v v Differential HSTL v v v Differential SSTL 3.3-V GTL v v v 3.3-V GTL+ v v v 1.5-V HSTL Class I v v v 2–94 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK 1.5-V HSTL Class II v v v 1.8-V HSTL Class I v v v 1.8-V HSTL Class II v v v SSTL-18 Class I v v v SSTL-18 Class II v v v SSTL-2 Class I v v v SSTL-2 Class II v v v SSTL-3 Class I v v v SSTL-3 Class II v v v AGP (1× and 2× ) v v v CTT v v v Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 2–56). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 2–56. External Clock Outputs for Enhanced PLLs 11 & 12 g0 Counter CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1) From Internal Logic or IOE Note to Figure 2–56: (1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n. Stratix devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases. Altera Corporation July 2005 2–95 Stratix Device Handbook, Volume 1 PLLs & Clock Networks Clock Feedback The following four feedback modes in Stratix device enhanced PLLs allow multiplication and/or phase and delay shifting: ■ Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. Altera recommends using the same I/O standard on the input clock and the output clocks for optimum performance. ■ External feedback: The external feedback input pin, FBIN, is phasealigned with the clock input, CLK, pin. Aligning these clocks allows you to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop. Altera recommends using the same I/O standard on the input clock, the FBIN pin, and the output clocks for optimum performance. ■ Normal mode: If an internal clock is used in this mode, it is phasealigned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. You define which internal clock output from the PLL should be phase-aligned to the internal clock pin. ■ No compensation: In this mode, the PLL will not compensate for any clock networks or external clock outputs. Phase & Delay Shifting Stratix device enhanced PLLs provide advanced programmable phase and clock delay shifting. These parameters are set in the Quartus II software. Phase Delay The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. You enter a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. For phase shifting, enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. This resolution is a function of frequency input and the multiplication and division factors (that is, it is a function of the VCO period), with the finest step being equal to an eighth (×0.125) of the VCO period. Each clock output counter can choose a different phase of the 2–96 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture VCO period from up to eight taps for individual fine step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse and fine shifts allows phase shifting for the entire input clock period. The equation to determine the precision of the phase shifting in degrees is: 45° ÷ post-scale counter value. Therefore, the maximum step size is 45° , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. Clock Delay In addition to the phase shift feature, the ability to fine tune the Δt clock delay provides advanced time delay shift control on each of the four PLL outputs. There are time delays for each post-scale counter (e, g, or l) from the PLL, the n counter, and m counter. Each of these can shift in 250-ps increments for a range of 3.0 ns. The m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. Individual delays on post-scale counters (e, g, and l) provide positive delay for each output. Table 2–21 shows the combined delay for each output for normal or zero delay buffer mode where Δte, Δtg, or Δtl is unique for each PLL output. The tOUTPUT for a single output can range from –3 ns to +6 ns. The total delay shift difference between any two PLL outputs, however, must be less than ±3 ns. For example, shifts on two outputs of –1 and +2 ns is allowed, but not –1 and +2.5 ns because these shifts would result in a difference of 3.5 ns. If the design uses external feedback, the Δte delay will remove delay from outputs, represented by a negative sign (see Table 2–21). This effect occurs because the Δte delay is then part of the feedback loop. Table 2–21. Output Clock Delay for Enhanced PLLs Normal or Zero Delay Buffer Mode ΔteOUTPUT = Δtn −Δtm + Δte ΔtgOUTPUT = Δtn −Δtm + Δtg ΔtlOUTPUT = Δtn −Δtm + Δtl External Feedback Mode ΔteOUTPUT = Δtn −Δtm −Δte (1) ΔtgOUTPUT = Δtn −Δtm + Δtg ΔtlOUTPUT = Δtn −Δtm + Δtl Note to Table 2–21: (1) Altera Corporation July 2005 Δte removes delay from outputs in external feedback mode. 2–97 Stratix Device Handbook, Volume 1 PLLs & Clock Networks The variation due to process, voltage, and temperature is about ±15% on the delay settings. PLL reconfiguration can control the clock delay shift elements, but not the VCO phase shift multiplexers, during system operation. Spread-Spectrum Clocking Stratix device enhanced PLLs use spread-spectrum technology to reduce electromagnetic interference generation from a system by distributing the energy over a broader frequency range. The enhanced PLL typically provides 0.5% down spread modulation using a triangular profile. The modulation frequency is programmable. Enabling spread-spectrum for a PLL affects all of its outputs. Lock Detect The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. You may need to gate the lock signal for use as a system control. The lock signal from the locked port can drive the logic array or an output pin. Whenever the PLL loses lock (for example, inclk jitter, clock switchover, PLL reconfiguration, power supply noise, and so on), the PLL must be reset with the areset signal to guarantee correct phase relationship between the PLL output clocks. If the phase relationship between the input clock versus output clock, and between different output clocks from the PLL is not important in the design, then the PLL need not be reset. f See the Stratix FPGA Errata Sheet for more information on implementing the gated lock signal in a design. Programmable Duty Cycle The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. Advanced Clear & Enable Control There are several control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. 2–98 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true: ■ ■ PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. The VCO will set back to its nominal setting (~700 MHz). When driven low again, the PLL will resynchronize to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency will start at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system continues running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. You can either use your own control signal or a clkloss status signal to trigger pfdena. The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 2–57 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a Altera Corporation July 2005 2–99 Stratix Device Handbook, Volume 1 PLLs & Clock Networks resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization. The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Figure 2–57. extclkena Signals COUNTER OUTPUT CLKENA CLKOUT Fast PLLs Stratix devices contain up to eight fast PLLs with high-speed serial interfacing ability, along with general-purpose features. Figure 2–58 shows a diagram of the fast PLL. 2–100 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–58. Stratix Device Fast PLL Post-Scale Counters diffioclk1 (2) ÷l0 VCO Phase Selection Selectable at each PLL Output Port Global or regional clock (1) Clock Input Phase Frequency Detector Global or regional clock txload_en (3) rxload_en (3) ÷l1 Global or regional clock diffioclk2 (2) PFD Charge Pump 8 Loop Filter VCO ÷g0 Global or regional clock ÷m Notes to Figure 2–58: (1) (2) (3) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin. It cannot be driven by internally-generated global signals. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal. Clock Multiplication & Division Stratix device fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply divider, m, per fast PLL with a range of 1 to 32. There are two post scale L dividers for regional and/or LVDS interface clocks, and g0 counter for global clock output port; all range from 1 to 32. In the case of a high-speed differential interface, set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES. When used for clocking the SERDES, the m counter can range from 1 to 30. The VCO frequency is equal to fIN×m, where VCO frequency must be between 300 and 1000 MHz. Altera Corporation July 2005 2–101 Stratix Device Handbook, Volume 1 PLLs & Clock Networks External Clock Inputs Each fast PLL supports single-ended or differential inputs for source synchronous transmitters or for general-purpose use. Sourcesynchronous receivers support differential clock inputs. The fast PLL inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK pins, as shown in Figure 2–50 on page 2–85. Table 2–22 shows the I/O standards supported by fast PLL input pins. Table 2–22. Fast PLL Port I/O Standards (Part 1 of 2) Input I/O Standard INCLK PLLENABLE LVTTL v v LVCMOS v v 2.5 V v 1.8 V v 1.5 V v 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL v 3.3-V PCML v LVDS v HyperTransport technology v Differential HSTL v Differential SSTL 3.3-V GTL 3.3-V GTL+ v 1.5-V HSTL Class I v 1.5-V HSTL Class II 1.8-V HSTL Class I v 1.8-V HSTL Class II SSTL-18 Class I v SSTL-18 Class II SSTL-2 Class I 2–102 Stratix Device Handbook, Volume 1 v Altera Corporation July 2005 Stratix Architecture Table 2–22. Fast PLL Port I/O Standards (Part 2 of 2) Input I/O Standard INCLK SSTL-2 Class II v SSTL-3 Class I v SSTL-3 Class II v PLLENABLE AGP (1× and 2× ) v CTT Table 2–23 shows the performance on each of the fast PLL clock inputs when using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology. Table 2–23. LVDS Performance on Fast PLL Input Fast PLL Clock Input CLK0, CLK2, CLK9, CLK11, FPLL7CLK, FPLL8CLK, FPLL9CLK, FPLL10CLK CLK1, CLK3, CLK8, CLK10 Maximum Input Frequency (MHz) 717(1) 645 Note to Table 2–23: (1) See the chapter DC & Switching Characteristics of the Stratix Device Handbook, Volume 1 for more information. External Clock Outputs Each fast PLL supports differential or single-ended outputs for sourcesynchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. Any I/O pin can be driven by the fast PLL global or regional outputs as an external output pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank. Phase Shifting Stratix device fast PLLs have advanced clock shift capability that enables programmable phase shifts. You can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can perform phase shifting in time units with a resolution range of 125 to 416.66 ps. This resolution is a function of the VCO period, with the finest step being equal to an eighth (×0.125) of the VCO period. Altera Corporation July 2005 2–103 Stratix Device Handbook, Volume 1 I/O Structure Control Signals The fast PLL has the same lock output, pllenable input, and areset input control signals as the enhanced PLL. If the input clock stops and causes the PLL to lose lock, then the PLL must be reset for correct phase shift operation. For more information on high-speed differential I/O support, see “HighSpeed Differential I/O Support” on page 2–130. I/O Structure IOEs provide many features, including: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Differential on-chip termination for LVDS I/O standard Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers The IOE in Stratix devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2–59 shows the Stratix IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. 2–104 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–59. Stratix IOE Structure Logic Array OE Register D OE Q OE Register D Q Output Register Output A D Q CLK Output Register Output B D Q Input Register D Q Input A Input B Input Register D Q Input Latch D Q ENA The IOEs are located in I/O blocks around the periphery of the Stratix device. There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2–60 shows how a row I/O block connects to the logic array. Figure 2–61 shows how a column I/O block connects to the logic array. Altera Corporation July 2005 2–105 Stratix Device Handbook, Volume 1 I/O Structure Figure 2–60. Row I/O Block Connection to the Interconnect R4, R8 & R24 Interconnects C4, C8 & C16 Interconnects I/O Interconnect I/O Block Local Interconnect 16 Control Signals from I/O Interconnect (1) 16 28 Data & Control Signals from Logic Array (2) 28 LAB Horizontal I/O Block io_dataouta[3..0] io_dataoutb[3..0] Direct Link Interconnect to Adjacent LAB Direct Link Interconnect to Adjacent LAB io_clk[7:0] LAB Local Interconnect Horizontal I/O Block Contains up to Four IOEs Notes to Figure 2–60: (1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_clk[3..0], and four clear signals io_bclr[3..0]. The 28 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear signals io_cclr[3..0]. 2–106 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–61. Column I/O Block Connection to the Interconnect 42 Data & Control Signals from Logic Array (2) 16 Control Signals from I/O Interconnect (1) Vertical I/O Block Contains up to Six IOEs Vertical I/O Block 16 42 io_clk[7..0] IO_datain[3:0] I/O Block Local Interconnect I/O Interconnect R4, R8 & R24 Interconnects LAB LAB Local Interconnect LAB LAB C4, C8 & C16 Interconnects Notes to Figure 2–61: (1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0]. Altera Corporation July 2005 2–107 Stratix Device Handbook, Volume 1 I/O Structure Stratix devices have an I/O interconnect similar to the R4 and C4 interconnect to drive high-fanout signals to and from the I/O blocks. There are 16 signals that drive into the I/O blocks composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The pin’s datain signals can drive the IO interconnect, which in turn drives the logic array or other I/O blocks. In addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from regional, global, or fast regional clocks (see “PLLs & Clock Networks” on page 2–73). Figure 2–62 illustrates the signal paths through the I/O block. Figure 2–62. Signal Path through the I/O Block Row or Column io_clk[7..0] io_boe[3..0] From I/O Interconnect To Other IOEs io_bce[3..0] io_bclk[3..0] io_bclr[3..0] To Logic Array io_datain0 io_datain1 oe ce_in ce_out io_coe io_cce_in Control Signal Selection aclr/apreset IOE sclr/spreset io_cce_out From Logic Array clk_in io_cclr clk_out io_cclk io_dataout0 io_dataout1 2–108 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 2–63 illustrates the control signal selection. Figure 2–63. Control Signal Selection per IOE io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0] Dedicated I/O Clock [7..0] I/O Interconnect [15..0] Local Interconnect io_coe Local Interconnect io_cclr Local Interconnect io_cce_out Local Interconnect io_cce_in Local Interconnect io_cclk ce_out clk_out clk_in ce_in sclr/preset aclr/preset oe In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2–64 shows the IOE in bidirectional configuration. Altera Corporation July 2005 2–109 Stratix Device Handbook, Volume 1 I/O Structure Figure 2–64. Stratix IOE in Bidirectional I/O Configuration Note (1) Column or Row Interconnect ioe_clk[7..0] I/O Interconnect [15..0] OE OE Register D Output tZX Delay Q clkout Output Enable Clock Enable Delay ce_out ENA CLRN/PRN OE Register tCO Delay VCCIO Output Clock Enable Delay Optional PCI Clamp VCCIO Programmable Pull-Up Resistor aclr/prn Chip-Wide Reset Logic Array to Output Register Delay Output Register D sclr/preset Q ENA CLRN/PRN Output Pin Delay Drive Strength Control Open-Drain Output Slew Control Input Pin to Logic Array Delay Input Register D clkin ce_in Input Clock Enable Delay Input Pin to Input Register Delay Bus-Hold Circuit Q ENA CLRN/PRN Note to Figure 2–64: (1) All input signals to the IOE can be inverted at the IOE. The Stratix device IOE includes programmable delays that can be activated to ensure zero hold times, input IOE register-to-logic array register transfers, or logic array-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output 2–110 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture and/or output enable registers. A programmable delay exists to increase the tZX delay to the output pin, which is required for ZBT interfaces. Table 2–24 shows the programmable delays for Stratix devices. Table 2–24. Stratix Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Decrease input delay to internal cells Input pin to input register delay Decrease input delay to input register Output pin delay Increase delay to output pin Output enable register tCO delay Increase delay to output enable pin Output tZX delay Increase tZX delay to output pin Output clock enable delay Increase output clock enable delay Input clock enable delay Increase input clock enable delay Logic array to output register delay Decrease input delay to output register Output enable clock enable delay Increase output enable clock enable delay The IOE registers in Stratix devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device’s active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available for the IOE registers. Double-Data Rate I/O Pins Stratix devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2–65 shows an IOE configured for DDR input. Figure 2–66 shows the DDR input timing diagram. Altera Corporation July 2005 2–111 Stratix Device Handbook, Volume 1 I/O Structure Figure 2–65. Stratix IOE in DDR Input I/O Configuration Note (1) Column or Row Interconnect VCCIO ioe_clk[7..0] (1) I/O Interconnect [15..0] (1) To DQS Local Bus (3) DQS Local Bus (1), (2) Optional PCI Clamp VCCIO Programmable Pull-Up Resistor Input Pin to Input Register Delay sclr Input Register D Q clkin Output Clock Enable Delay ENA CLRN/PRN Bus-Hold Circuit aclr/prn Chip-Wide Reset Latch Input Register D Q ENA CLRN/PRN D Q ENA CLRN/PRN Notes to Figure 2–65: (1) (2) (3) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only. 2–112 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–66. Input Timing Diagram in DDR Mode Data at input pin A0 B1 A1 B2 A2 B3 A3 B4 CLK A' A1 A2 A3 B' B1 B2 B3 Input To Logic Array When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from LEs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a ×2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2–67 shows the IOE configured for DDR output. Figure 2–68 shows the DDR output timing diagram. Altera Corporation July 2005 2–113 Stratix Device Handbook, Volume 1 I/O Structure Figure 2–67. Stratix IOE in DDR Output I/O Configuration Notes (1), (2) Column or Row Interconnect IOE_CLK[7..0] I/O Interconnect [15..0] OE Register D Q Output tZX Delay clkout ENA CLRN/PRN OE Register tCO Delay Output Enable Clock Enable Delay Output Clock Enable Delay aclr/prn VCCIO Optional PCI Clamp Chip-Wide Reset OE Register D VCCIO Q sclr ENA CLRN/PRN Logic Array to Output Register Delay Programmable Pull-Up Resistor Output Register D Q Output Pin Delay ENA CLRN/PRN Logic Array to Output Register Delay Used for DDR SDRAM Output Register D clk Drive Strength Control Open-Drain Output Slew Control Q ENA CLRN/PRN Bus-Hold Circuit Notes to Figure 2–67: (1) (2) All input signals to the IOE can be inverted at the IOE. The tristate is by default active high. It can, however, be designed to be active low. 2–114 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–68. Output Timing Diagram in DDR Mode CLK A A1 A2 A3 A4 B B1 B2 B3 B4 From Internal Registers B1 DDR output A1 B2 A2 B3 A3 The Stratix IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. Stratix device I/O pins transfer data on a DDR bidirectional bus to support DDR SDRAM. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements. External RAM Interfacing Stratix devices support DDR SDRAM at up to 200 MHz (400-Mbps data rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz. Stratix devices also provide preliminary support for reduced latency DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated phase-shift circuitry. 1 f Altera Corporation July 2005 In addition to the required signals for external memory interfacing, Stratix devices offer the optional clock enable signal. By default the Quartus II software sets the clock enable signal high, which tells the output register to update with new values. The output registers hold their own values if the design sets the clock enable signal low. See Figure 2–64. To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. 2–115 Stratix Device Handbook, Volume 1 I/O Structure Tables 2–25 and 2–26 show the performance specification for DDR SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM interfaces in EP1S10 through EP1S40 devices and in EP1S60 and EP1S80 devices. The DDR SDRAM and QDR SRAM numbers in Table 2–25 have been verified with hardware characterization with third-party DDR SDRAM and QDR SRAM devices over temperature and voltage extremes. Table 2–25. External RAM Support in EP1S10 through EP1S40 Devices Maximum Clock Rate (MHz) DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade Flip-Chip Flip-Chip -7 Speed Grade -8 Speed Grade WireBond FlipChip WireBond FlipChip WireBond DDR SDRAM (1), (2) SSTL-2 200 167 133 133 100 100 100 DDR SDRAM - side banks (2), (3), (4) SSTL-2 150 133 110 133 100 100 100 RLDRAM II (4) 1.8-V HSTL 200 (5) (5) (5) (5) (5) (5) QDR SRAM (6) 1.5-V HSTL 167 167 133 133 100 100 100 QDRII SRAM (6) 1.5-V HSTL 200 167 133 133 100 100 100 ZBT SRAM (7) LVTTL 200 200 200 167 167 133 133 Notes to Table 2–25: (1) (2) (3) (4) (5) (6) (7) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. These performance specifications are preliminary. This device does not support RLDRAM II. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. 2–116 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Table 2–26. External RAM Support in EP1S60 & EP1S80 Devices Maximum Clock Rate (MHz) DDR Memory Type I/O Standard DDR SDRAM (1), (2) -5 Speed Grade -6 Speed Grade -7 Speed Grade SSTL-2 167 167 133 DDR SDRAM - side banks (2), (3) SSTL-2 150 133 133 QDR SRAM (4) 1.5-V HSTL 133 133 133 QDRII SRAM (4) 1.5-V HSTL 167 167 133 ZBT SRAM (5) LVTTL 200 200 167 Notes to Table 2–26: (1) (2) (3) (4) (5) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. Numbers are preliminary. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. In addition to six I/O registers and one input latch in the IOE for interfacing to these high-speed memory interfaces, Stratix devices also have dedicated circuitry for interfacing with DDR SDRAM. In every Stratix device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz. These pins support DQS signals with DQ bus modes of ×8, ×16, or ×32. Table 2–27 shows the number of DQ and DQS buses that are supported per device. Table 2–27. DQS & DQ Bus Mode Support Number of ×8 Groups Number of ×16 Groups Number of ×32 Groups 672-pin BGA 672-pin FineLine BGA 12 (2) 0 0 484-pin FineLine BGA 780-pin FineLine BGA 16 (3) 0 4 484-pin FineLine BGA 18(4) 7 (5) 4 672-pin BGA 672-pin FineLine BGA 16(3) 7 (5) 4 780-pin FineLine BGA 20 7 (5) 4 Device EP1S10 EP1S20 (Part 1 of 2) Note (1) Package Altera Corporation July 2005 2–117 Stratix Device Handbook, Volume 1 I/O Structure Table 2–27. DQS & DQ Bus Mode Support (Part 2 of 2) Note (1) Number of ×8 Groups Number of ×16 Groups Number of ×32 Groups 16 (3) 8 4 780-pin FineLine BGA 1,020-pin FineLine BGA 20 8 4 EP1S30 956-pin BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 20 8 4 EP1S40 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 20 8 4 EP1S60 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 20 8 4 EP1S80 956-pin BGA 1,508-pin FineLine BGA 1,923-pin FineLine BGA 20 8 4 Device EP1S25 Package 672-pin BGA 672-pin FineLine BGA Notes to Table 2–27: (1) (2) (3) (4) (5) See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 for VREF guidelines. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8. This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8. These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8. A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. Two separate single phase-shifting reference circuits are located on the top and bottom of the Stratix device. Each circuit is driven by a system reference clock through the CLK pins that is the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase-shift circuitry on the bottom of the device. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device. The phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device 2–118 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture shift by the same degree amount. For example, all 10 DQS pins on the top of the device can be shifted by 90° and all 10 DQS pins on the bottom of the device can be shifted by 72°. The reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. Figure 2–69 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. Figure 2–69. Simplified Diagram of the DQS Phase-Shift Circuitry Input Reference Clock Phase Comparator Up/Down Counter Delay Chains 6 Control Signals to DQS Pins See the External Memory Interfaces chapter in the Stratix Device Handbook, Volume 2 for more information on external memory interfaces. Programmable Drive Strength The output buffer for each Stratix device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standard has several levels of drive strength that the user can control. SSTL-3 Class I and II, SSTL-2 Class I and II, HSTL Class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Altera Corporation July 2005 2–119 Stratix Device Handbook, Volume 1 I/O Structure Table 2–28 shows the possible settings for the I/O standards with drive strength control. Table 2–28. Programmable Drive Strength I/O Standard IOH / IOL Current Strength Setting (mA) 3.3-V LVTTL 24 (1), 16, 12, 8, 4 3.3-V LVCMOS 24 (2), 12 (1), 8, 4, 2 2.5-V LVTTL/LVCMOS 16 (1), 12, 8, 2 1.8-V LVTTL/LVCMOS 12 (1), 8, 2 1.5-V LVCMOS 8 (1), 4, 2 GTL/GTL+ 1.5-V HSTL Class I and II 1.8-V HSTL Class I and II SSTL-3 Class I and II SSTL-2 Class I and II SSTL-18 Class I and II Support max and min strength Notes to Table 2–28: (1) (2) This is the Quartus II software default current setting. I/O banks 1, 2, 5, and 6 do not support this setting. Quartus II software version 4.2 and later will report current strength as “PCI Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative. Open-Drain Output Stratix devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices. Slew-Rate Control The output buffer for each Stratix device I/O pin has a programmable output slew-rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each 2–120 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture I/O pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. Bus Hold Each Stratix device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Table 2–29 shows bus hold support for different pin types. Table 2–29. Bus Hold Support Pin Type I/O pins Bus Hold v CLK[15..0] CLK[0,1,2,3,8,9,10,11] FCLK v FPLL[7..10]CLK The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when using opendrain outputs with the GTL+ I/O standard or when the I/O pin has been configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 kΩ to weakly pull the signal level to the last-driven state. See the DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1 for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Altera Corporation July 2005 2–121 Stratix Device Handbook, Volume 1 I/O Structure Programmable Pull-Up Resistor Each Stratix device I/O pin provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO level of the output pin’s bank. Table 2–30 shows which pin types support the weak pull-up resistor feature. Table 2–30. Programmable Weak Pull-Up Resistor Support Pin Type I/O pins Programmable Weak Pull-Up Resistor v CLK[15..0] FCLK v FPLL[7..10]CLK Configuration pins JTAG pins v (1) Note to Table 2–30: (1) TDO pins do not support programmable weak pull-up resistors. Advanced I/O Standard Support Stratix device IOEs support the following I/O standards: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LVTTL LVCMOS 1.5 V 1.8 V 2.5 V 3.3-V PCI 3.3-V PCI-X 1.0 3.3-V AGP (1× and 2×) LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL Class I and II 2–122 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture ■ ■ ■ ■ ■ 1.8-V HSTL Class I and II SSTL-3 Class I and II SSTL-2 Class I and II SSTL-18 Class I and II CTT Table 2–31 describes the I/O standards supported by Stratix devices. Table 2–31. Stratix Supported I/O Standards Type Input Reference Voltage (VREF) (V) Output Supply Voltage (VCCIO) (V) Board Termination Voltage (VTT) (V) LVTTL Single-ended N/A 3.3 N/A LVCMOS Single-ended N/A 3.3 N/A 2.5 V Single-ended N/A 2.5 N/A 1.8 V Single-ended N/A 1.8 N/A 1.5 V Single-ended N/A 1.5 N/A 3.3-V PCI Single-ended N/A 3.3 N/A 3.3-V PCI-X 1.0 I/O Standard Single-ended N/A 3.3 N/A LVDS Differential N/A 3.3 N/A LVPECL Differential N/A 3.3 N/A 3.3-V PCML Differential N/A 3.3 N/A HyperTransport Differential N/A 2.5 N/A Differential HSTL (1) Differential 0.75 1.5 0.75 Differential SSTL (2) Differential 1.25 2.5 1.25 GTL Voltage-referenced 0.8 N/A 1.20 GTL+ Voltage-referenced 1.0 N/A 1.5 1.5-V HSTL Class I and II Voltage-referenced 0.75 1.5 0.75 1.8-V HSTL Class I and II Voltage-referenced 0.9 1.8 0.9 SSTL-18 Class I and II Voltage-referenced 0.90 1.8 0.90 SSTL-2 Class I and II Voltage-referenced 1.25 2.5 1.25 SSTL-3 Class I and II Voltage-referenced 1.5 3.3 1.5 AGP (1× and 2° ) Voltage-referenced 1.32 3.3 N/A CTT Voltage-referenced 1.5 3.3 1.5 Notes to Table 2–31: (1) (2) This I/O standard is only available on input and output clock pins. This I/O standard is only available on output column clock pins. Altera Corporation July 2005 2–123 Stratix Device Handbook, Volume 1 I/O Structure f For more information on I/O standards supported by Stratix devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2. Stratix devices contain eight I/O banks in addition to the four enhanced PLL external clock out banks, as shown in Figure 2–70. The four I/O banks on the right and left of the device contain circuitry to support highspeed differential I/O for LVDS, LVPECL, 3.3-V PCML, and HyperTransport inputs and outputs. These banks support all I/O standards listed in Table 2–31 except PCI I/O pins or PCI-X 1.0, GTL, SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Table 2–32 shows I/O standard support for each I/O bank. 2–124 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–70. Stratix I/O Banks Notes (1), (2), (3) DQS5T 9 DQS4T PLL11 (5) DQS1T DQS0T 10 Bank 4 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) (5) I/O Banks 1, 2, 5, and 6 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2× PLL2 Bank 1 DQS2T I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards PLL1 Bank 8 PLL3 DQS8B DQS7B DQS6B DQS5B (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) 11 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 DQS9B PLL4 I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) PLL8 DQS3T VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) Bank 2 VREF1B2 VREF2B2 VREF3B2 VREF4B2 Bank 3 VREF1B1 VREF2B1 VREF3B1 VREF4B1 PLL5 12 PLL6 Bank 5 DQS6T VREF4B5 VREF3B5 VREF2B5 VREF1B5 DQS7T Bank 6 DQS8T VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF4B6 VREF3B6 VREF2B6 VREF1B6 DQS9T PLL7 Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 DQS4B DQS3B DQS2B DQS1B PLL9 DQS0B Notes to Figure 2–70: (1) (2) (3) (4) (5) Figure 2–70 is a top view of the silicon die. This will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. Figure 2–70 is a graphic representation only. See the device pin-outs on the web (www.altera.com) and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1× /2× . For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix and Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2. Altera Corporation July 2005 2–125 Stratix Device Handbook, Volume 1 I/O Structure Table 2–32 shows I/O standard support for each I/O bank. Table 2–32. I/O Support by Bank (Part 1 of 2) Top & Bottom Banks (3, 4, 7 & 8) Left & Right Banks (1, 2, 5 & 6) Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) LVTTL v v v LVCMOS v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v 3.3-V PCI-X 1.0 v I/O Standard v v LVPECL v v 3.3-V PCML v v LVDS v v HyperTransport technology v v Differential HSTL (clock inputs) v v Differential HSTL (clock outputs) v Differential SSTL (clock outputs) v 3.3-V GTL v 3.3-V GTL+ v v v v 1.5-V HSTL Class I v v v 1.5-V HSTL Class II v 1.8-V HSTL Class I v 1.8-V HSTL Class II v SSTL-18 Class I v SSTL-18 Class II v SSTL-2 Class I v v v v v v v v v SSTL-2 Class II v v v SSTL-3 Class I v v v 2–126 Stratix Device Handbook, Volume 1 v Altera Corporation July 2005 Stratix Architecture Table 2–32. I/O Support by Bank (Part 2 of 2) Top & Bottom Banks (3, 4, 7 & 8) Left & Right Banks (1, 2, 5 & 6) Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) SSTL-3 Class II v v v AGP (1× and 2× ) v CTT v I/O Standard v v v Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard independently. Each bank also has dedicated VREF pins to support any one of the voltage-referenced standards (such as SSTL-3) independently. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. Differential On-Chip Termination Stratix devices provide differential on-chip termination (LVDS I/O standard) to reduce reflections and maintain signal integrity. Differential on-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. The internal termination is designed using transistors in the linear region of operation. Stratix devices support internal differential termination with a nominal resistance value of 137.5 Ω for LVDS input receiver buffers. LVPECL signals require an external termination resistor. Figure 2–71 shows the device with differential termination. Altera Corporation July 2005 2–127 Stratix Device Handbook, Volume 1 I/O Structure Figure 2–71. LVDS Input Differential On-Chip Termination Transmitting Device Receiving Device with Differential Termination Z0 + + RD Ð Ð Z0 I/O banks on the left and right side of the device support LVDS receiver (far-end) differential termination. Table 2–33 shows the Stratix device differential termination support. Table 2–33. Differential Termination Supported by I/O Banks Differential Termination Support I/O Standard Support Differential termination (1), (2) Top & Bottom Banks (3, 4, 7 & 8) Left & Right Banks (1, 2, 5 & 6) v LVDS Notes to Table 2–33: (1) (2) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination. Differential termination is only supported for LVDS because of a 3.3-V VC C I O . Table 2–34 shows the termination support for different pin types. Table 2–34. Differential Termination Support Across Pin Types Pin Type RD Top and bottom I/O banks (3, 4, 7, and 8) DIFFIO_RX[] v CLK[0,2,9,11],CLK[4-7],CLK[12-15] CLK[1,3,8,10] v FCLK FPLL[7..10]CLK The differential on-chip resistance at the receiver input buffer is 118 Ω ±20 %. 2–128 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture However, there is additional resistance present between the device ball and the input of the receiver buffer, as shown in Figure 2–72. This resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). Figure 2–72. Differential Resistance of LVDS Differential Pin Pair (RD) Pad Package Ball 0.3 Ω 9.3 Ω 0.3 Ω 9.3 Ω LVDS Input Buffer RD Differential On-Chip Termination Resistor Table 2–35 defines the specification for internal termination resistance for commercial devices. Table 2–35. Differential On-Chip Termination Resistance Symbol RD (2) Description Internal differential termination for LVDS Conditions Unit Min Typ Max Commercial (1), (3) 110 135 165 W Industrial (2), (3) 100 135 170 W Notes to Table 2–35: (1) (2) (3) Data measured over minimum conditions (Tj = 0 C, VC C I O +5%) and maximum conditions (Tj = 85 C, VC C I O = –5%). Data measured over minimum conditions (Tj = –40 C, VCCIO +5%) and maximum conditions (Tj = 100 C, VCCIO = –5%). LVDS data rate is supported for 840 Mbps using internal differential termination. MultiVolt I/O Interface The Stratix architecture supports the MultiVolt I/O interface feature, which allows Stratix devices in all packages to interface with systems of different supply voltages. The Stratix VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. Altera Corporation July 2005 2–129 Stratix Device Handbook, Volume 1 High-Speed Differential I/O Support The output levels are compatible with systems of the same voltage as the power supply (i.e., when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 2–36 summarizes Stratix MultiVolt I/O support. Table 2–36. Stratix MultiVolt I/O Support Note (1) Input Signal (5) VCCIO (V) Output Signal (6) 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.5 v v v (2) v (2) v 1.8 v (2) v v (2) v (2) v (3) v 2.5 v v v (3) v (3) v 3.3 v (2) v v (3) v (3) v (3) v (4) 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V v v Notes to Table 2–36: (1) (2) (3) (4) (5) (6) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V. The input pin current may be slightly higher than the typical value. Although VCCIO specifies the voltage necessary for the Stratix device to drive out, a receiving device powered at a different level can still interface with the Stratix device if it has inputs that tolerate the VCCIO value. Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. This is the external signal that is driving the Stratix device. This represents the system voltage that Stratix supports when a VCCIO pin is connected to a specific voltage level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal coming out from Stratix is 3.3 V and is compatible with 3.3-V or 5.0-V systems. High-Speed Differential I/O Support Stratix devices contain dedicated circuitry for supporting differential standards at speeds up to 840 Mbps. The following differential I/O standards are supported in the Stratix device: LVDS, LVPECL, HyperTransport, and 3.3-V PCML. There are four dedicated high-speed PLLs in the EP1S10 to EP1S25 devices and eight dedicated high-speed PLLs in the EP1S30 to EP1S80 devices to multiply reference clocks and drive high-speed differential SERDES channels. f See the Stratix device pin-outs at www.altera.com for additional high speed DIFFIO pin information for Stratix devices. 2–130 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Table 2–37 shows the number of channels that each fast PLL can clock in EP1S10, EP1S20, and EP1S25 devices. Tables 2–38 through Table 2–41 show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices. Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1) Device EP1S10 Package Transmitter/ Receiver 484-pin FineLine BGA Transmitter (2) Receiver 672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver 780-pin FineLine BGA Transmitter (2) Receiver EP1S20 484-pin FineLine BGA Transmitter (2) Receiver 672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver 780-pin FineLine BGA Transmitter (2) Receiver Altera Corporation July 2005 Total Channels 20 20 36 36 44 44 24 20 48 50 66 66 Maximum Speed (Mbps) Center Fast PLLs PLL 1 PLL 2 PLL 3 PLL 4 840 (4) 5 5 5 5 840 (3) 10 10 10 10 840 (4) 5 5 5 5 840 (3) 10 10 10 10 624 (4) 9 9 9 9 624 (3) 18 18 18 18 624 (4) 9 9 9 9 624 (3) 18 18 18 18 840 (4) 11 11 11 11 840 (3) 22 22 22 22 840 (4) 11 11 11 11 840 (3) 22 22 22 22 840 (4) 6 6 6 6 840 (3) 12 12 12 12 840 (4) 5 5 5 5 840 (3) 10 10 10 10 624 (4) 12 12 12 12 624 (3) 24 24 24 24 624 (4) 13 12 12 13 624 (3) 25 25 25 25 840 (4) 17 16 16 17 840 (3) 33 33 33 33 840 (4) 17 16 16 17 840 (3) 33 33 33 33 2–131 Stratix Device Handbook, Volume 1 High-Speed Differential I/O Support Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1) Device EP1S25 Transmitter/ Receiver Package 672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver 780-pin FineLine BGA Transmitter (2) Receiver 1,020-pin FineLine BGA Transmitter (2) Receiver Total Channels 56 58 70 66 78 78 Maximum Speed (Mbps) Center Fast PLLs PLL 1 PLL 2 PLL 3 PLL 4 624 (4) 14 14 14 14 624 (3) 28 28 28 28 624 (4) 14 15 15 14 624 (3) 29 29 29 29 840 (4) 18 17 17 18 840 (3) 35 35 35 35 840 (4) 17 16 16 17 840 (3) 33 33 33 33 840 (4) 19 20 20 19 840 (3) 39 39 39 39 840 (4) 19 20 20 19 840 (3) 39 39 39 39 Notes to Table 2–37: (1) (2) (3) (4) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at 840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design requires a DDR clock, it can use an extra data channel. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. These values show the channels available for each PLL without crossing another bank. When you span two I/O banks using cross-bank support, you can route only two load enable signals total between the PLLs. When you enable rx_data_align, you use both rxloadena and txloadena of a PLL. That leaves no loadena for the second PLL. 2–132 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture The only way you can use the rx_data_align is if one of the following is true: ■ ■ The receiver PLL is only clocking receive channels (no resources for the transmitter) If all channels can fit in one I/O bank Table 2–38. EP1S30 Differential Channels Note (1) Package 780-pin FineLine BGA 956-pin BGA 1,020-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) 70 Receiver 66 Transmitter (4) 80 Receiver 80 Transmitter (4) Receiver 80 (2) (7) 80 (2) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 17 17 18 (6) (6) (6) (6) 840 (5) 35 35 35 35 (6) (6) (6) (6) 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 840 19 20 20 19 20 20 20 20 840 (5) 39 39 39 39 20 20 20 20 840 20 20 20 20 19 20 20 19 840 (5) 40 40 40 40 19 20 20 19 840 19 (1) 20 20 19 (1) 20 20 20 20 840 (5),(8) 39 (1) 39 (1) 39 (1) 39 (1) 20 20 20 20 840 20 20 20 20 19 (1) 20 20 19 (1) 840 (5),(8) 40 40 40 40 19 (1) 20 20 19 (1) Table 2–39. EP1S40 Differential Channels (Part 1 of 2) Note (1) Package 780-pin FineLine BGA Transmitter/ Total Receiver Channels Transmitter (4) 68 Receiver 66 Altera Corporation July 2005 Maximum Speed (Mbps) Center Fast PLLs Corner Fast PLLs (2), (3) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 16 16 18 (6) (6) (6) (6) 840 (5) 34 34 34 34 (6) (6) (6) (6) 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 2–133 Stratix Device Handbook, Volume 1 High-Speed Differential I/O Support Table 2–39. EP1S40 Differential Channels (Part 2 of 2) Note (1) Package 956-pin BGA 1,020-pin FineLine BGA Transmitter/ Total Receiver Channels Transmitter (4) 80 Receiver Transmitter (4) Receiver 1,508-pin FineLine BGA Transmitter (4) Receiver Maximum Speed (Mbps) Center Fast PLLs Corner Fast PLLs (2), (3) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 17 17 18 20 20 20 20 840 (5) 35 35 35 35 20 20 20 20 80 840 20 20 20 20 18 17 17 18 840 (5) 40 40 40 40 18 17 17 18 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5), (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5), (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5), (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5), (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 80 (10) (7) 80 (10) (7) 80 (10) (7) Table 2–40. EP1S60 Differential Channels (Part 1 of 2) Note (1) Package 956-pin BGA Transmitter/ Total Receiver Channels Transmitter (4) 80 Receiver 80 2–134 Stratix Device Handbook, Volume 1 Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 12 10 10 12 20 20 20 20 840 (5), (8) 22 22 22 22 20 20 20 20 840 20 20 20 20 12 10 10 12 840 (5), (8) 40 40 40 40 12 10 10 12 Altera Corporation July 2005 Stratix Architecture Table 2–40. EP1S60 Differential Channels (Part 2 of 2) Note (1) Package 1,020-pin FineLine BGA Transmitter/ Total Receiver Channels Transmitter (4) Receiver 1,508-pin FineLine BGA Transmitter (4) Receiver 80 (12) (7) 80 (10) (7) 80 (36) (7) 80 (36) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 12 (2) 10 (4) 10 (4) 12 (2) 20 20 20 20 840 (5), (8) 22 (6) 22 (6) 22 (6) 22 (6) 20 20 20 20 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5), (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) 840 12 (8) 10 (10) 10 (10) 12 (8) 20 20 20 20 840 (5),(8) 22 (18) 22 (18) 22 (18) 22 (18) 20 20 20 20 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5),(8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) Table 2–41. EP1S80 Differential Channels (Part 1 of 2) Note (1) Package 956-pin BGA 1,020-pin FineLine BGA Transmitter/ Total Receiver Channels Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 Transmitter (4) 80 (40) (7) 840 10 10 10 10 20 20 20 20 840 (5),(8) 20 20 20 20 20 20 20 20 Receiver 80 840 20 20 20 20 10 10 10 10 840 (5),(8) 40 40 40 40 10 10 10 10 Transmitter (4) 92 (12) (7) 840 10 (2) 10 (4) 10 (4) 10 (2) 20 20 20 20 840 (5),(8) 20 (6) 20 (6) 20 (6) 20 (6) 20 20 20 20 840 20 20 20 20 10 (2) 10 (3) 10 (3) 10 (2) 840 (5),(8) 40 40 40 40 10 (2) 10 (3) 10 (3) 10 (2) Receiver Altera Corporation July 2005 90 (10) (7) 2–135 Stratix Device Handbook, Volume 1 High-Speed Differential I/O Support Table 2–41. EP1S80 Differential Channels (Part 2 of 2) Note (1) Package 1,508-pin FineLine BGA Transmitter/ Total Receiver Channels Transmitter (4) Receiver 80 (72) (7) 80 (56) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 10 (10) 10 (10) 10 (10) 10 (10) 20 (8) 20 (8) 20 (8) 20 (8) 840 (5),(8) 20 (20) 20 (20) 20 (20) 20 (20) 20 (8) 20 (8) 20 (8) 20 (8) 840 20 20 20 20 10 (14) 10 (14) 10 (14) 10 (14) 840 (5),(8) 40 40 40 40 10 (14) 10 (14) 10 (14) 10 (14) Notes to Tables 2–38 through 2–41: (1) (2) (3) (4) (5) (6) (7) (8) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and 4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap, see the Stratix device pin-outs at www.altera.com. The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device pin-outs at www.altera.com. The numbers of channels listed include the transmitter clock output (tx_outclock) channel. An extra data channel can be used if a DDR clock is needed. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank channels simultaneously if say PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. PLLs 7, 8, 9, and 10 are not available in this device. The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These channels are independent of the high-speed differential channels. For the location of these channels, see the device pin-outs at www.altera.com. See the Stratix device pin-outs at www.altera.com. Channels marked “high” speed are 840 MBps and “low” speed channels are 462 MBps. The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications: ■ ■ ■ ■ UTOPIA IV SPI-4 Phase 2 (POS-PHY Level 4) SFI-4 10G Ethernet XSBI 2–136 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture ■ ■ RapidIO HyperTransport Dedicated Circuitry Stratix devices support source-synchronous interfacing with LVDS, LVPECL, 3.3-V PCML, or HyperTransport signaling at up to 840 Mbps. Stratix devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by a integer factor W (W = 1 through 32). For example, a HyperTransport application where the data rate is 800 Mbps and the clock rate is 400 MHz would require that W be set to 2. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 7, 8, or 10 and does not have to equal the PLL clock-multiplication W value. For a J factor of 1, the Stratix device bypasses the SERDES block. For a J factor of 2, the Stratix device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. See Figure 2–73. Figure 2–73. High-Speed Differential I/O Receiver / Transmitter Interface Example R4, R8, and R24 Interconnect 8 840 Mbps + – Data + – 8 840 Mbps 8 Data Dedicated Receiver Interface 8× 105 MHz Dedicated Transmitter Interface Local Interconnect Fast PLL rx_load_en 8× tx_load_en Regional or global clock An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed differential I/O clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. Altera Corporation July 2005 2–137 Stratix Device Handbook, Volume 1 High-Speed Differential I/O Support The Quartus II MegaWizard® Plug-In Manager only allows the implementation of up to 20 receiver or 20 transmitter channels for each fast PLL. These channels operate at up to 840 Mbps. The receiver and transmitter channels are interleaved such that each I/O bank on the left and right side of the device has one receiver channel and one transmitter channel per LAB row. Figure 2–74 shows the fast PLL and channel layout in EP1S10, EP1S20, and EP1S25 devices. Figure 2–75 shows the fast PLL and channel layout in the EP1S30 to EP1S80 devices. Figure 2–74. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices Note (1) Up to 20 Receiver and Transmitter Channels (2) Transmitter Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver Receiver CLKIN Fast PLL 1 CLKIN Fast PLL 2 (3) Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2) Fast PLL 4 CLKIN Fast PLL 3 CLKIN (3) Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2) Notes to Figure 2–74: (1) (2) (3) Wire-bond packages support up to 624 Mbps. See Table 2–41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for “low” speed channels, as labeled in the device pin-outs at www.altera.com. 2–138 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Stratix Architecture Figure 2–75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices Note (1) FPLL7CLK Fast PLL 7 Fast PLL 10 Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter FPLL10CLK Transmitter Receiver Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter Transmitter Receiver CLKIN CLKIN Receiver Fast PLL 1 (3) (3) Fast PLL 2 Fast PLL 4 CLKIN Fast PLL 3 CLKIN Transmitter Transmitter Receiver Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter Transmitter Receiver FPLL8CLK Receiver Fast PLL 8 Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Fast PLL 9 FPLL9CLK Notes to Figure 2–75: (1) (2) (3) Wire-bond packages support up to 624 Mbps. See Table 2–38 through 2–41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for “low” speed channels as labeled in the device pin-outs at www.altera.com. Altera Corporation July 2005 2–139 Stratix Device Handbook, Volume 1 Power Sequencing & Hot Socketing The transmitter external clock output is transmitted on a data channel. The txclk pin for each bank is located in between data transmitter pins. For ×1 clocks (e.g., 622 Mbps, 622 MHz), the high-speed PLL clock bypasses the SERDES to drive the output pins. For half-rate clocks (e.g., 622 Mbps, 311 MHz) or any other even-numbered factor such as 1/4, 1/7, 1/8, or 1/10, the SERDES automatically generates the clock in the Quartus II software. For systems that require more than four or eight high-speed differential I/O clock domains, a SERDES bypass implementation is possible using IOEs. Byte Alignment For high-speed source synchronous interfaces such as POS-PHY 4, XSBI, RapidIO, and HyperTransport technology, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Stratix device’s high-speed differential I/O circuitry provides dedicated data realignment circuitry for usercontrolled byte boundary shifting. This simplifies designs while saving LE resources. An input signal to each fast PLL can stall deserializer parallel data outputs by one bit period. You can use an LE-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment. Power Sequencing & Hot Socketing Because Stratix devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Although you can power up or down the VCCIO and VCCINT power supplies in any sequence, you should not power down any I/O banks that contain configuration pins while leaving other I/O banks powered on. For power up and power down, all supplies (VCCINT and all VCCIO power planes) must be powered up and down within 100 ms of each other. This prevents I/O pins from driving out. Signals can be driven into Stratix devices before and during power up without damaging the device. In addition, Stratix devices do not drive out during power up. Once operating conditions are reached and the device is configured, Stratix devices operate as specified by the user. For more information, see Hot Socketing in the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2. 2–140 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 3. Configuration & Testing S51003-1.3 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support All Stratix® devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix devices can also use the JTAG port for configuration together with either the Quartus® II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode through the CONFIG_IO instruction. You can use this ability for JTAG testing before configuration when some of the Stratix pins drive or receive from other devices on the board using voltage-referenced standards. Since the Stratix device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows you to fully test the I/O connection to other devices. The enhanced PLL reconfiguration bits are part of the JTAG chain before configuration and after power-up. After device configuration, the PLL reconfiguration bits are not part of the JTAG chain. The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The TDO pin voltage is determined by the VCCIO of the bank where it resides. The VCCSEL pin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or 3.3-V compatible. Stratix devices also use the JTAG port to monitor the logic operation of the device with the SignalTap® II embedded logic analyzer. Stratix devices support the JTAG instructions shown in Table 3–1. The Quartus II software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. In the Settings dialog box in the Assignments menu, click Device & Pin Options, then General, and then turn on the Auto Usercode option. Altera Corporation July 2005 3–1 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Table 3–1. Stratix JTAG Instructions JTAG Instruction Instruction Code Description SAMPLE/PRELOAD 00 0000 0101 Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. EXTEST (1) 00 0000 0000 Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. HIGHZ (1) 00 0000 1011 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. CLAMP (1) 00 0000 1010 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. ICR instructions Used when configuring an Stratix device via the JTAG port with a MasterBlasterTM, ByteBlasterMVTM, or ByteBlasterTM II download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor or JRunner. PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. CONFIG_IO 00 0000 1101 Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. SignalTap II instructions Monitors internal device operation with the SignalTap II embedded logic analyzer. Note to Table 3–1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. 3–2 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Configuration & Testing The Stratix device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the boundary-scan register length and device IDCODE information for Stratix devices. Table 3–2. Stratix Boundary-Scan Register Length Device Boundary-Scan Register Length EP1S10 1,317 EP1S20 1,797 EP1S25 2,157 EP1S30 2,253 EP1S40 2,529 EP1S60 3,129 EP1S80 3,777 Table 3–3. 32-Bit Stratix Device IDCODE IDCODE (32 Bits) (1) Device Version (4 Bits) Part Number (16 Bits) Manufacturer Identity (11 Bits) LSB (1 Bit) (2) EP1S10 0000 0010 0000 0000 0001 000 0110 1110 1 EP1S20 0000 0010 0000 0000 0010 000 0110 1110 1 EP1S25 0000 0010 0000 0000 0011 000 0110 1110 1 EP1S30 0000 0010 0000 0000 0100 000 0110 1110 1 EP1S40 0000 0010 0000 0000 0101 000 0110 1110 1 EP1S60 0000 0010 0000 0000 0110 000 0110 1110 1 EP1S80 0000 0010 0000 0000 0111 000 0110 1110 1 Notes to Tables 3–2 and 3–3: (1) (2) The most significant bit (MSB) is on the left. The IDCODE’s least significant bit (LSB) is always 1. Altera Corporation July 2005 3–3 Stratix Device Handbook, Volume 1 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Figure 3–1 shows the timing requirements for the JTAG signals. Figure 3–1. Stratix JTAG Waveforms TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX t JPXZ t JPCO TDO tJSH tJSSU Signal to Be Captured Signal to Be Driven tJSCO tJSZX tJSXZ Table 3–4 shows the JTAG timing parameters and values for Stratix devices. Table 3–4. Stratix JTAG Timing Parameters & Values Symbol Parameter Min Max Unit tJCP TCK clock period 100 ns tJCH TCK clock high time 50 ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 ns tJPCO JTAG port clock to output 25 ns tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 ns tJSSU Capture register setup time 20 tJSH Capture register hold time 45 tJSCO Update register clock to output 35 ns tJSZX Update register high impedance to valid output 35 ns tJSXZ Update register valid output to high impedance 35 ns 3–4 Stratix Device Handbook, Volume 1 ns ns Altera Corporation July 2005 Configuration & Testing 1 f Stratix, Stratix II, Cyclone®, and Cyclone II devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they will fail configuration. This does not affect SignalTap II. For more information on JTAG, see the following documents: ■ ■ AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification SignalTap II Embedded Logic Analyzer Stratix devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA® packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. Configuration The logic, circuitry, and interconnects in the Stratix architecture are configured with CMOS SRAM elements. Altera® devices are reconfigurable. Because every device is tested with a high-coverage production test program, you do not have to perform fault testing and can focus on simulation and design verification. Stratix devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix devices via a serial data stream. Stratix devices can be configured in under 100 ms using 8-bit parallel data at 100 MHz. The Stratix device’s optimized interface allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Stratix devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Stratix device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. Operating Modes The Stratix architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after Altera Corporation July 2005 3–5 Stratix Device Handbook, Volume 1 Configuration configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Stratix devices to be reconfigured incircuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select POR delay times of 2 ms or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms; when the PORSEL pin is connected to VCC, the POR time is 2 ms. The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all user I/O pins to VCCIO before and during device configuration. If nIO_PULLUP is connected to VCC during configuration, the weak pullups on all user I/O pins are disabled. If connected to ground, the pull-ups are enabled during configuration. The nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. VCCSEL is a dedicated input that is used to choose whether all dedicated configuration and JTAG input pins can accept 1.5 V/1.8 V or 2.5 V/3.3 V during configuration. A logic low sets 3.3 V/2.5 V, and a logic high sets 1.8 V/1.5 V. VCCSEL affects the following pins: TDI, TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. The VCCSEL signal does not control the dual-purpose configuration pins such as the DATA[7..0] and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration, these dual-purpose pins will drive out voltage levels corresponding to the VCCIO supply voltage that powers the I/O bank containing the pin. After configuration, the dual-purpose pins use I/O standards specified in the user design. TDO and nCEO drive out at the same voltages as the VCCIO supply that powers the I/O bank containing the pin. Users must select the VCCIO supply for bank containing TDO accordingly. For example, when using the ByteBlaster™ MV cable, the VCCIO for the bank containing TDO must be powered up at 3.3 V. 3–6 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Configuration & Testing Configuring Stratix FPGAs with JRunner JRunner is a software driver that configures Altera FPGAs, including Stratix FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms. For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com). Configuration Schemes You can load the configuration data for a Stratix device with one of five configuration schemes (see Table 3–5), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix device. A configuration device can automatically configure a Stratix device at system power-up. Multiple Stratix devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 3–5. Data Sources for Configuration Configuration Scheme Data Source Configuration device Enhanced or EPC2 configuration device Passive serial (PS) MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable or serial data source Passive parallel asynchronous (PPA) Parallel data source Fast passive parallel Parallel data source JTAG MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable, a microprocessor with a Jam or JBC file, or JRunner Partial Reconfiguration The enhanced PLLs within the Stratix device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL’s counter settings in a serial chain. This option provides considerable flexibility for frequency Altera Corporation July 2005 3–7 Stratix Device Handbook, Volume 1 Configuration synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1 for more information on Stratix PLLs. Remote Update Configuration Modes Stratix devices also support remote configuration using an Altera enhanced configuration device (e.g., EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration that contains the design required to control remote updates and handle or recover from errors. You write the factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information. There are two remote configuration modes: remote and local configuration. You can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (for example, EPC16 devices) only support serial and parallel synchronous modes. Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the Stratix device. This host must support page mode settings similar to an EPC16 device. Remote Update Mode When the Stratix device is first powered up in remote update programming mode, it loads the configuration located at page address “000.” The factory configuration should always be located at page address “000,” and should never be remotely updated. The factory configuration contains the required logic to perform the following operations: ■ ■ ■ Determine the page address/load location for the next application’s configuration data Recover from a previous configuration error Receive new configuration data and write it into the configuration device The factory configuration is the default and takes control if an error occurs while loading the application configuration. 3–8 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Configuration & Testing While in the factory configuration, the factory-configuration logic performs the following operations: ■ ■ ■ Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should be if it is enabled The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations. If an error occurs in loading the application configuration, the configuration logic writes a status register to specify the cause of the error. Once this occurs, the Stratix device automatically loads the factory configuration, which reads the status register and determines the reason for reconfiguration. Based on the reason, the factory configuration will take appropriate steps and will write the remote update control register to specify the next application configuration page to be loaded. When the Stratix device successfully loads the application configuration, it enters into user mode. The Stratix device then executes the main application of the user. Intellectual property (IP), such as a Nios® (16-bit ISA) and Nios® II (32-bit ISA) embedded processors, can help the Stratix device determine when remote update is coming. The Nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. The factory configuration will read the remote update status register and determine the valid application configuration to load. Figure 3–2 shows the Stratix remote update. Figure 3–3 shows the transition diagram for remote update mode. Altera Corporation July 2005 3–9 Stratix Device Handbook, Volume 1 Configuration Figure 3–2. Stratix Device Remote Update (1) Watchdog Timer New Remote Configuration Data Configuration Device Application Configuration Page 7 Page 6 Application Configuration Stratix Device Factory Configuration Page 0 Configuration Device Updates Stratix Device with Factory Configuration (to Handle Update) or New Application Configuration Note to Figure 3–2: (1) When the Stratix device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device. 3–10 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Configuration & Testing Figure 3–3. Remote Update Transition Diagram Notes (1), (2) Application 1 Configuration Power-Up Configuration Error Configuration Error Reload an Application Factory Configuration Reload an Application Configuration Error Application n Configuration Notes to Figure 3–3: (1) (2) Remote update of Application Configuration is controlled by a Nios embedded processor or user logic programmed in the Factory or Application configurations. Up to seven pages can be specified allowing up to seven different configuration applications. Altera Corporation July 2005 3–11 Stratix Device Handbook, Volume 1 Stratix Automated Single Event Upset (SEU) Detection Local Update Mode Local update mode is a simplified version of the remote update. This feature is intended for simple systems that need to load a single application configuration immediately upon power up without loading the factory configuration first. Local update designs have only one application configuration to load, so it does not require a factory configuration to determine which application configuration to use. Figure 3–4 shows the transition diagram for local update mode. Figure 3–4. Local Update Transition Diagram Power-Up or nCONFIG nCONFIG Application Configuration Configuration Error Configuration Error nCONFIG Factory Configuration Stratix Automated Single Event Upset (SEU) Detection Stratix devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. FPGA devices that operate at high elevations or in close proximity to earth’s North or South Pole require periodic checks to ensure continued data integrity. The error detection cyclic redundancy check (CRC) feature controlled by the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. 3–12 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 Configuration & Testing For Stratix, the CRC is computed by the Quartus II software and downloaded into the device as a part of the configuration bit stream. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration. Custom-Built Circuitry Dedicated circuitry is built in the Stratix devices to perform error detection automatically. You can use the built-in dedicated circuitry for error detection using CRC feature in Stratix devices, eliminating the need for external logic. This circuitry will perform error detection automatically when enabled. This error detection circuitry in Stratix devices constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a re-configuration cycle. Select the desired time between checks by adjusting a built-in clock divider. Software Interface In the Quartus II software version 4.1 and later, you can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 100 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, see AN 357: Error Detection Using CRC in Altera FPGA Devices. Temperature Sensing Diode Stratix devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Stratix diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device’s output represents the junction temperature of the Stratix device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Stratix device to connect to the external temperature-sensing device, as shown in Figure 3–5. The temperature sensing diode is a passive element and therefore can be used before the Stratix device is powered. Altera Corporation July 2005 3–13 Stratix Device Handbook, Volume 1 Temperature Sensing Diode Figure 3–5. External Temperature-Sensing Diode Stratix Device Temperature-Sensing Device tempdiodep tempdioden Table 3–6 shows the specifications for bias voltage and current of the Stratix temperature sensing diode. Table 3–6. Temperature-Sensing Diode Electrical Characteristics Parameter Minimum Typical Maximum Unit IBIAS high 80 100 120 μA IBIAS low 8 10 12 μA VBP – VBN VBN Series resistance 3–14 Stratix Device Handbook, Volume 1 0.3 0.9 0.7 V V 3 W Altera Corporation July 2005 Configuration & Testing The temperature-sensing diode works for the entire operating range shown in Figure 3–6. Figure 3–6. Temperature vs. Temperature-Sensing Diode Voltage 0.95 0.90 100 μA Bias Current 10 μA Bias Current 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 –55 –30 –5 20 45 70 95 120 Temperature ( C) Altera Corporation July 2005 3–15 Stratix Device Handbook, Volume 1 Temperature Sensing Diode 3–16 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 4. DC & Switching Characteristics S51004-3.4 Stratix® devices are offered in both commercial and industrial grades. Industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 (fastest), -6, -7, and -8 speed grades. This section specifies the operation conditions for operating junction temperature, VCCINT and VCCIO voltage levels, and input voltage requirements. The voltage specifications in this section are specified at the pins of the device (and not the power supply). If the device operates outside these ranges, then all DC and AC specifications are not guaranteed. Furthermore, the reliability of the device may be affected. The timing parameters in this chapter apply to both commercial and industrial temperature ranges unless otherwise stated. Operating Conditions Tables 4–1 through 4–8 provide information on absolute maximum ratings. Table 4–1. Stratix Device Absolute Maximum Ratings Notes (1), (2) Symbol VCCINT Parameter Supply voltage Conditions With respect to ground VCCIO Minimum Maximum Unit –0.5 2.4 V –0.5 4.6 V VI DC input voltage (3) –0.5 4.6 V IOUT DC output current, per pin –25 40 mA TSTG Storage temperature No bias TJ Junction temperature BGA packages under bias –65 150 °C 135 °C Table 4–2. Stratix Device Recommended Operating Conditions (Part 1 of 2) Symbol VCCINT Parameter Supply voltage for internal logic and input buffers Altera Corporation January 2006 Conditions (4) Minimum Maximum Unit 1.425 1.575 V 4–1 Operating Conditions Table 4–2. Stratix Device Recommended Operating Conditions (Part 2 of 2) Symbol Parameter Conditions Minimum Maximum Unit 3.00 (3.135) 3.60 (3.465) V Supply voltage for output buffers, 3.3-V operation (4), (5) Supply voltage for output buffers, 2.5-V operation (4) 2.375 2.625 V Supply voltage for output buffers, 1.8-V operation (4) 1.71 1.89 V Supply voltage for output buffers, 1.5-V operation (4) 1.4 1.6 V VI Input voltage (3), (6) –0.5 4.0 V VO Output voltage 0 VCCIO V TJ Operating junction temperature 0 85 °C –40 100 °C VCCIO For commercial use For industrial use Table 4–3. Stratix Device DC Operating Conditions Note (7) (Part 1 of 2) Symbol Parameter Conditions Minimum Typical Maximum Unit II Input pin leakage current VI = VCCIOmax to 0 V (8) –10 10 μA IOZ Tri-stated I/O pin leakage current VO = VCCIOmax to 0 V (8) –10 10 μA ICC0 VCC supply current (standby) (All memory blocks in power-down mode) VI = ground, no load, no toggling inputs mA EP1S10. VI = ground, no load, no toggling inputs 37 mA EP1S20. VI = ground, no load, no toggling inputs 65 mA EP1S25. VI = ground, no load, no toggling inputs 90 mA EP1S30. VI = ground, no load, no toggling inputs 114 mA EP1S40. VI = ground, no load, no toggling inputs 145 mA EP1S60. VI = ground, no load, no toggling inputs 200 mA EP1S80. VI = ground, no load, no toggling inputs 277 mA 4–2 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–3. Stratix Device DC Operating Conditions Note (7) (Part 2 of 2) Symbol RCONF Parameter Conditions Minimum Value of I/O pin pull- VCCIO = 3.0 V (9) up resistor before VCCIO = 2.375 V (9) and during VCCIO = 1.71 V (9) configuration Typical Maximum Unit 20 50 kΩ 30 80 kΩ 60 150 kΩ Table 4–4. LVTTL Specifications Symbol Parameter Conditions Minimum Maximum Unit 3.0 3.6 V VCCIO Output supply voltage VI H High-level input voltage 1.7 4.1 V VIL Low-level input voltage –0.5 0.7 V VOH High-level output voltage IOH = –4 to –24 mA (10) VOL Low-level output voltage IOL = 4 to 24 mA (10) 2.4 V 0.45 V Minimum Maximum Unit 3.0 3.6 V Table 4–5. LVCMOS Specifications Symbol Parameter Conditions VCCIO Output supply voltage VIH High-level input voltage 1.7 4.1 V VIL Low-level input voltage –0.5 0.7 V VOH High-level output voltage VCCIO = 3.0, IOH = –0.1 mA VOL Low-level output voltage VCCIO = 3.0, IOL = 0.1 mA VCCIO – 0.2 V 0.2 V Minimum Maximum Unit 2.375 2.625 V 1.7 4.1 V –0.5 0.7 V Table 4–6. 2.5-V I/O Specifications Symbol Parameter Conditions VCCIO Output supply voltage VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage IOH = –1 mA (10) VOL Low-level output voltage IOL = 1 mA (10) Altera Corporation January 2006 2.0 V 0.4 V 4–3 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–7. 1.8-V I/O Specifications Symbol Parameter VCCIO Output supply voltage VI H High-level input voltage Conditions VIL Low-level input voltage VOH High-level output voltage IOH = –2 to –8 mA (10) VOL Low-level output voltage IOL = 2 to 8 mA (10) Minimum Maximum Unit 1.65 1.95 V 0.65 × VCCIO 2.25 V –0.3 0.35 × VCCIO VCCIO – 0.45 V V 0.45 V Minimum Maximum Unit 1.4 1.6 V 0.65 × VCCIO VCCIO + 0.3 V –0.3 0.35 × VCCIO V Table 4–8. 1.5-V I/O Specifications Symbol Parameter VCCIO Output supply voltage VI H High-level input voltage Conditions VIL Low-level input voltage VOH High-level output voltage IOH = –2 mA (10) VOL Low-level output voltage IOL = 2 mA (10) 0.75 × VCCIO V 0.25 × VCCIO V Notes to Tables 4–1 through 4–8: (1) (2) See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in Table 4–9, based on input duty cycle for input currents less than 100 mA. The overshoot is dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses. (6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (7) Typical values are for TA = 25°C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (8) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). (9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. (10) Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1. Table 4–9. Overshoot Input Voltage with Respect to Duty Cycle (Part 1 of 2) 4–4 Stratix Device Handbook, Volume 1 Vin (V) Maximum Duty Cycle (%) 4.0 100 4.1 90 4.2 50 Altera Corporation January 2006 DC & Switching Characteristics Table 4–9. Overshoot Input Voltage with Respect to Duty Cycle (Part 2 of 2) Vin (V) Maximum Duty Cycle (%) 4.3 30 4.4 17 4.5 10 Figures 4–1 and 4–2 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 4–1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p−n=0V VID Altera Corporation January 2006 4–5 Stratix Device Handbook, Volume 1 Operating Conditions Figure 4–2. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p−n=0V VOD Tables 4–10 through 4–33 recommend operating conditions, DC operating conditions, and capacitance for 1.5-V Stratix devices. Table 4–10. 3.3-V LVDS I/O Specifications (Part 1 of 2) Symbol Parameter VCCIO I/O supply voltage VID (6) Input differential voltage swing (single-ended) 4–6 Stratix Device Handbook, Volume 1 Conditions Minimum Typical Maximum Unit 3.135 3.3 3.465 V 0.1 V ≤VCM < 1.1 V W = 1 through 10 300 1,000 mV 1.1 V ≤VCM ≤1.6 V W=1 200 1,000 mV 1.1 V ≤VCM ≤1.6 V W = 2 through10 100 1,000 mV 1.6 V < VCM ≤1.8 V W = 1 through 10 300 1,000 mV Altera Corporation January 2006 DC & Switching Characteristics Table 4–10. 3.3-V LVDS I/O Specifications (Part 2 of 2) Symbol VICM Parameter Input common mode voltage (6) Conditions Typical Maximum Unit LVDS 0.3 V ≤VID ≤1.0 V W = 1 through 10 100 1,100 mV LVDS 0.3 V ≤VID ≤1.0 V W = 1 through 10 1,600 1,800 mV LVDS 0.2 V ≤VID ≤1.0 V W=1 1,100 1,600 mV LVDS 0.1 V ≤VID ≤1.0 V W = 2 through 10 1,100 1,600 mV 550 mV 50 mV 1,375 mV 50 mV 110 Ω VOD (1) Output differential voltage (single-ended) RL = 100 Ω Δ VOD Change in VOD between high and low RL = 100 Ω VOCM Output common mode voltage RL = 100 Ω Δ VOCM Change in VOCM between high and low RL = 100 Ω RL Receiver differential input discrete resistor (external to Stratix devices) Altera Corporation January 2006 Minimum 250 375 1,125 90 1,200 100 4–7 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–11. 3.3-V PCML Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 3.135 3.3 3.465 V VCCIO I/O supply voltage VID (peakto-peak) Input differential voltage swing (single-ended) 300 600 mV VICM Input common mode voltage 1.5 3.465 V VOD Output differential voltage (single-ended) 300 500 mV Δ VOD Change in VOD between high and low 50 mV VOCM Output common mode voltage 3.3 V Δ VOCM Change in VOCM between high and low 50 mV 2.5 370 2.85 VT Output termination voltage R1 Output external pull-up resistors 45 VCCIO 50 55 V Ω R2 Output external pull-up resistors 45 50 55 Ω Minimum Typical Maximum Unit 3.135 3.3 3.465 V 300 1,000 mV 1 2 V Table 4–12. LVPECL Specifications Symbol Parameter Conditions VCCIO I/O supply voltage VID (peakto-peak) Input differential voltage swing (single-ended) VICM Input common mode voltage VOD Output differential voltage (single-ended) RL = 100 Ω 525 700 970 mV VOCM Output common mode voltage RL = 100 Ω 1.5 1.7 1.9 V RL Receiver differential input resistor 90 100 110 Ω 4–8 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–13. HyperTransport Technology Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 2.375 2.5 2.625 V VCCIO I/O supply voltage VID (peakto-peak) Input differential voltage swing (single-ended) 300 900 mV VICM Input common mode voltage 300 900 mV VOD Output differential voltage (single-ended) RL = 100 Ω 820 mV Δ VOD Change in VOD between high and low RL = 100 Ω 50 mV VOCM Output common mode voltage RL = 100 Ω 780 mV Δ VOCM Change in VOCM between high and low RL = 100 Ω 50 mV RL Receiver differential input resistor 380 485 440 650 90 100 110 Ω Minimum Typical Maximum Unit 3.0 3.3 3.6 V Table 4–14. 3.3-V PCI Specifications Symbol Parameter Conditions VCCIO Output supply voltage VIH High-level input voltage 0.5 × VCCIO VCCIO + 0.5 V VIL Low-level input voltage –0.5 0.3 × VCCIO V VOH High-level output voltage IOUT = –500 μA VOL Low-level output voltage IOUT = 1,500 μA Altera Corporation January 2006 0.9 × VCCIO V 0.1 × VCCIO V 4–9 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–15. PCI-X 1.0 Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 3.0 3.6 V VCCIO Output supply voltage VIH High-level input voltage 0.5 × VCCIO VCCIO + 0.5 V VIL Low-level input voltage –0.5 0.35 × VCCIO V VIPU Input pull-up voltage 0.7 × VCCIO V VOH High-level output voltage IOUT = –500 μA 0.9 × VCCIO V VOL Low-level output voltage IOUT = 1,500 μA 0.1 × VCCIO V Table 4–16. GTL+ I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VTT Termination voltage 1.35 1.5 1.65 V VREF Reference voltage 0.88 1.0 1.12 V VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage VREF + 0.1 V IOL = 34 mA (3) VREF – 0.1 V 0.65 V Table 4–17. GTL I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VTT Termination voltage 1.14 1.2 1.26 V VREF Reference voltage 0.74 0.8 0.86 V VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage 4–10 Stratix Device Handbook, Volume 1 VREF + 0.05 IOL = 40 mA (3) V VREF – 0.05 V 0.4 V Altera Corporation January 2006 DC & Switching Characteristics Table 4–18. SSTL-18 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 1.65 1.8 1.95 V VREF Reference voltage 0.8 0.9 1.0 V VREF – 0.04 VREF VREF + 0.04 VTT Termination voltage VIH(DC) High-level DC input voltage VIL(DC) Low-level DC input voltage VIH(AC) High-level AC input voltage VREF + 0.125 VREF – 0.125 VREF + 0.275 VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –6.7 mA (3) VOL Low-level output voltage IOL = 6.7 mA (3) V V V V VREF – 0.275 VTT + 0.475 V V VTT – 0.475 V Typical Maximum Unit Table 4–19. SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum VCCIO Output supply voltage 1.65 1.8 1.95 V VREF Reference voltage 0.8 0.9 1.0 V VTT Termination voltage VREF – 0.04 VREF VREF + 0.04 V VIH(DC) High-level DC input voltage VIL(DC) Low-level DC input voltage VIH(AC) High-level AC input voltage VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –13.4 mA (3) VOL Low-level output voltage IOL = 13.4 mA (3) Altera Corporation January 2006 VREF + 0.125 V VREF – 0.125 VREF + 0.275 V V VREF – 0.275 VTT + 0.630 V V VTT – 0.630 V 4–11 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–20. SSTL-2 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 2.375 2.5 2.625 V VREF – 0.04 VREF VREF + 0.04 V 1.15 1.25 VCCIO Output supply voltage VTT Termination voltage VREF Reference voltage 1.35 V VIH(DC) High-level DC input voltage VREF + 0.18 3.0 V VIL(DC) Low-level DC input voltage –0.3 VREF – 0.18 V VIH(AC) High-level AC input voltage VREF + 0.35 VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –8.1 mA (3) VOL Low-level output voltage IOL = 8.1 mA (3) V VREF – 0.35 VTT + 0.57 V V VTT – 0.57 V Maximum Unit Table 4–21. SSTL-2 Class II Specifications Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage VTT Termination voltage 2.375 2.5 2.625 V VREF – 0.04 VREF VREF + 0.04 V VREF Reference voltage 1.15 1.25 1.35 V VIH(DC) High-level DC input voltage VREF + 0.18 VCCIO + 0.3 V VIL(DC) Low-level DC input voltage –0.3 VREF – 0.18 V VIH(AC) High-level AC input voltage VREF + 0.35 VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –16.4 mA (3) VOL Low-level output voltage IOL = 16.4 mA (3) V VREF – 0.35 VTT + 0.76 V V VTT – 0.76 V Table 4–22. SSTL-3 Class I Specifications (Part 1 of 2) Symbol Parameter VCCIO Output supply voltage Conditions Minimum Typical Maximum Unit 3.0 3.3 3.6 V VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V VREF Reference voltage 1.3 1.5 1.7 V VIH(DC) High-level DC input voltage VREF + 0.2 VCCIO + 0.3 V VIL(DC) Low-level DC input voltage –0.3 VREF – 0.2 V VIH(AC) High-level AC input voltage VREF + 0.4 4–12 Stratix Device Handbook, Volume 1 V Altera Corporation January 2006 DC & Switching Characteristics Table 4–22. SSTL-3 Class I Specifications (Part 2 of 2) Symbol Parameter Conditions VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –8 mA (3) VOL Low-level output voltage IOL = 8 mA (3) Minimum Typical Maximum Unit VREF – 0.4 V VTT + 0.6 V VTT – 0.6 V Table 4–23. SSTL-3 Class II Specifications Symbol Parameter VCCIO Output supply voltage Conditions Minimum Typical Maximum Unit 3.0 3.3 3.6 V VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V VREF Reference voltage 1.3 1.5 1.7 V VIH(DC) High-level DC input voltage VREF + 0.2 VCCIO + 0.3 V VREF – 0.2 V VIL(DC) Low-level DC input voltage –0.3 VIH(AC) High-level AC input voltage VREF + 0.4 VIL(AC) Low-level AC input voltage VOH High-level output voltage IOH = –16 mA (3) VOL Low-level output voltage IOL = 16 mA (3) V VREF – 0.4 VT T + 0.8 V V VTT – 0.8 V Maximum Unit Table 4–24. 3.3-V AGP 2× Specifications Symbol Parameter Conditions Minimum Typical 3.15 3.3 VCCIO Output supply voltage 3.45 V VREF Reference voltage 0.39 × VCCIO 0.41 × VCCIO V VIH High-level input voltage (4) 0.5 × VCCIO VCCIO + 0.5 V VIL Low-level input voltage (4) 0.3 × VCCIO V VOH High-level output voltage IOUT = –0.5 mA VOL Low-level output voltage IOUT = 1.5 mA 0.9 × VCCIO 3.6 V 0.1 × VCCIO V Table 4–25. 3.3-V AGP 1× Specifications (Part 1 of 2) Symbol Parameter VCCIO Output supply voltage VIH High-level input voltage (4) VIL Low-level input voltage (4) Altera Corporation January 2006 Conditions Minimum Typical Maximum Unit 3.15 3.3 3.45 V VCCIO + 0.5 V 0.3 × VCCIO V 0.5 × VCCIO 4–13 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–25. 3.3-V AGP 1× Specifications (Part 2 of 2) Symbol Parameter Conditions VOH High-level output voltage IOUT = –0.5 mA VOL Low-level output voltage IOUT = 1.5 mA Minimum Typical 0.9 × VCCIO Maximum Unit 3.6 V 0.1 × VCCIO V Table 4–26. 1.5-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 1.4 1.5 1.6 V VREF Input reference voltage 0.68 0.75 0.9 V VTT Termination voltage 0.7 0.75 0.8 V VIH (DC) DC high-level input voltage VREF + 0.1 VIL (DC) DC low-level input voltage –0.3 VIH (AC) AC high-level input voltage VREF + 0.2 VIL (AC) AC low-level input voltage VOH High-level output voltage IOH = –8 mA (3) VOL Low-level output voltage IOL = 8 mA (3) V VREF – 0.1 V VREF – 0.2 V V VCCIO – 0.4 V 0.4 V Table 4–27. 1.5-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 1.5 1.6 V VCCIO Output supply voltage 1.4 VREF Input reference voltage 0.68 0.75 0.9 V VTT Termination voltage 0.7 0.75 0.8 V VIH (DC) DC high-level input voltage VREF + 0.1 VIL (DC) DC low-level input voltage –0.3 VIH (AC) AC high-level input voltage VREF + 0.2 VIL (AC) AC low-level input voltage VOH High-level output voltage IOH = –16 mA (3) VOL Low-level output voltage IOL = 16 mA (3) 4–14 Stratix Device Handbook, Volume 1 V VREF – 0.1 V VREF – 0.2 V V VCCIO – 0.4 V 0.4 V Altera Corporation January 2006 DC & Switching Characteristics Table 4–28. 1.8-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 1.65 1.80 1.95 V VREF Input reference voltage 0.70 0.90 0.95 V VTT Termination voltage VIH (DC) DC high-level input voltage VCCIO × 0.5 V VREF + 0.1 VIL (DC) DC low-level input voltage –0.5 VIH (AC) AC high-level input voltage VREF + 0.2 VIL (AC) AC low-level input voltage VOH High-level output voltage IOH = –8 mA (3) VOL Low-level output voltage IOL = 8 mA (3) V VREF – 0.1 V V VREF – 0.2 VCCIO – 0.4 V V 0.4 V Maximum Unit Table 4–29. 1.8-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical VCCIO Output supply voltage 1.65 1.80 1.95 V VREF Input reference voltage 0.70 0.90 0.95 V VTT Termination voltage VIH (DC) DC high-level input voltage VREF + 0.1 VIL (DC) DC low-level input voltage –0.5 VIH (AC) AC high-level input voltage VREF + 0.2 VIL (AC) AC low-level input voltage VOH High-level output voltage IOH = –16 mA (3) VOL Low-level output voltage IOL = 16 mA (3) VCCIO × 0.5 V V VREF – 0.1 V VREF – 0.2 V V VCCIO – 0.4 V 0.4 V Table 4–30. 1.5-V Differential HSTL Class I & Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit 1.5 1.6 V VCCIO I/O supply voltage 1.4 VDIF (DC) DC input differential voltage 0.2 VCM (DC) DC common mode input voltage 0.68 VDIF (AC) AC differential input voltage 0.4 Altera Corporation January 2006 V 0.9 V V 4–15 Stratix Device Handbook, Volume 1 Operating Conditions Table 4–31. CTT I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 2.05 3.3 3.6 V VTT/VREF Termination and input reference voltage 1.35 1.5 1.65 V VIH High-level input voltage VREF + 0.2 VIL Low-level input voltage VOH High-level output voltage IOH = –8 mA VOL Low-level output voltage IOL = 8 mA IO Output leakage current (when output is high Z) GND ≤VOUT ≤ VCCIO V VREF – 0.2 VREF + 0.4 V V VREF – 0.4 V 10 μA –10 Table 4–32. Bus Hold Parameters VCCIO Level Parameter Conditions 1.5 V Min 1.8 V Max Min Max 2.5 V Min Unit 3.3 V Max Min Max VIN > VIL (maximum) 25 30 50 70 μA High sustaining VIN < VIH current (minimum) -25 –30 –50 –70 μA Low sustaining current Low overdrive current 0 V < VIN < VCCIO 160 200 300 500 μA High overdrive current 0 V < VIN < VCCIO -160 –200 –300 –500 μA 2.0 V Bus-hold trip point 0.5 4–16 Stratix Device Handbook, Volume 1 1.0 0.68 1.07 0.7 1.7 0.8 Altera Corporation January 2006 DC & Switching Characteristics Table 4–33. Stratix Device Capacitance Note (5) Symbol Parameter Minimum Typical Maximum Unit CIOTB Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8. 11.5 pF CIOLR Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. 8.2 pF CCLKTB Input capacitance on top/bottom clock input pins: CLK[4:7] and CLK[12:15]. 11.5 pF CCLKLR Input capacitance on left/right clock inputs: CLK1, CLK3, CLK8, CLK10. 7.8 pF CCLKLR+ Input capacitance on left/right clock inputs: CLK0, CLK2, CLK9, and CLK11. 4.4 pF Notes to Tables 4–10 through 4–33: (1) (2) (3) (4) (5) (6) When tx_outclock port of altlvds_tx megafunction is 717 MHz, VO D ( m i n ) = 235 mV on the output clock pin. Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1. VREF specifies the center point of the switching range. Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF. VIO and VCM have multiple ranges and values for J=1 through 10. Power Consumption Altera® offers two ways to calculate power for a design: the Altera web power calculator and the PowerGaugeTM feature in the Quartus® II software. The interactive power calculator on the Altera web site is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II software PowerGauge feature allows you to apply test vectors against your design for more accurate power consumption modeling. In both cases, these calculations should only be used as an estimation of power, not as a specification. Stratix devices require a certain amount of power-up current to successfully power up because of the small process geometry on which they are fabricated. Table 4–34 shows the maximum power-up current (ICCINT) required to power a Stratix device. This specification is for commercial operating conditions. Measurements were performed with an isolated Stratix device on the board to characterize the power-up current of an isolated Altera Corporation January 2006 4–17 Stratix Device Handbook, Volume 1 Power Consumption device. Decoupling capacitors were not used in this measurement. To factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: I = C (dV/dt) If the regulator or power supply minimum output current is more than the Stratix device requires, then the device may consume more current than the maximum current listed in Table 4–34. However, the device does not require any more current to successfully power up than what is listed in Table 4–34. Table 4–34. Stratix Power-Up Current (ICCINT) Requirements Note (1) Power-Up Current Requirement Device Unit Typical Maximum EP1S10 250 700 mA EP1S20 400 1,200 mA EP1S25 500 1,500 mA EP1S30 550 1,900 mA EP1S40 650 2,300 mA EP1S60 800 2,600 mA EP1S80 1,000 3,000 mA Note to Table 4–34: (1) The maximum test conditions are for 0° C and typical test conditions are for 40° C. The exact amount of current consumed varies according to the process, temperature, and power ramp rate. Stratix devices typically require less current during power up than shown in Table 4–34. The user-mode current during device operation is generally higher than the power-up current. The duration of the ICCINT power-up requirement depends on the VCCINT voltage supply rise time. The power-up current consumption drops when the VCCINT supply reaches approximately 0.75 V. 4–18 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Timing Model The DirectDrive™ technology and MultiTrack™ interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. Preliminary & Final Timing Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 4–35 shows the status of the Stratix device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worstcase voltage and junction temperature conditions. Table 4–35. Stratix Device Timing Model Status Device Altera Corporation January 2006 Preliminary Final EP1S10 v EP1S20 v EP1S25 v EP1S30 v EP1S40 v EP1S60 v EP1S80 v 4–19 Stratix Device Handbook, Volume 1 Timing Model Performance Table 4–36 shows Stratix performance for some common designs. All performance values were obtained with Quartus II software compilation of LPM, or MegaCore® functions for the FIR and FFT designs. Table 4–36. Stratix Performance (Part 1 of 2) Notes (1), (2) Resources Used Applications LE 16-to-1 multiplexer (1) TriMatrix memory M-RAM block TriMatrix DSP LEs Memory Blocks Blocks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Units 22 407.83 324.56 288.68 228.67 MHz 0 0 32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 185.18 MHz 16-bit counter 16 0 0 422.11 422.11 390.01 348.67 MHz 64-bit counter 64 0 0 321.85 290.52 261.23 220.5 MHz 0 1 0 317.76 277.62 241.48 205.21 MHz 30 1 0 319.18 278.86 242.54 206.14 MHz Simple dual-port RAM 128 × 36 bit 0 1 0 290.86 255.55 222.27 188.89 MHz True dual-port RAM 128 × 18 bit 0 1 0 290.86 255.55 222.27 188.89 MHz FIFO 128 × 36 bit 34 1 0 290.86 255.55 222.27 188.89 MHz Single port RAM 4K × 144 bit 1 1 0 255.95 223.06 194.06 164.93 MHz Simple dual-port RAM 4K × 144 bit 0 1 0 255.95 233.06 194.06 164.93 MHz True dual-port RAM 4K × 144 bit 0 1 0 255.95 233.06 194.06 164.93 MHz Single port RAM 8K × 72 bit 0 1 0 278.94 243.19 211.59 179.82 MHz Simple dual-port RAM 8K × 72 bit 0 1 0 255.95 223.06 194.06 164.93 MHz True dual-port RAM 8K × 72 bit 0 1 0 255.95 223.06 194.06 164.93 MHz Single port RAM 16K × 36 bit 0 1 0 280.66 254.32 221.28 188.00 MHz Simple dual-port RAM 16K × 36 bit 0 1 0 269.83 237.69 206.82 175.74 MHz Simple dual-port RAM TriMatrix 32 × 18 bit memory M512 block FIFO 32 × 18 bit TriMatrix memory M4K block Performance 4–20 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–36. Stratix Performance (Part 2 of 2) Notes (1), (2) Resources Used Applications TriMatrix memory M-RAM block DSP block Larger Designs TriMatrix DSP LEs Memory Blocks Blocks Performance -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Units True dual-port RAM 16K × 36 bit 0 1 0 269.83 237.69 206.82 175.74 MHz Single port RAM 32K × 18 bit 0 1 0 275.86 244.55 212.76 180.83 MHz Simple dual-port RAM 32K × 18 bit 0 1 0 275.86 244.55 212.76 180.83 MHz True dual-port RAM 32K × 18 bit 0 1 0 275.86 244.55 212.76 180.83 MHz Single port RAM 64K × 9 bit 0 1 0 287.85 253.29 220.36 187.26 MHz Simple dual-port RAM 64K × 9 bit 0 1 0 287.85 253.29 220.36 187.26 MHz True dual-port RAM 64K × 9 bit 0 1 0 287.85 253.29 220.36 187.26 MHz 9 × 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 217.24 MHz 18 × 18-bit multiplier (4) 0 0 1 278.78 237.41 206.52 175.50 MHz 36 × 36-bit multiplier (4) 0 0 1 148.25 134.71 117.16 99.59 MHz 36 × 36-bit multiplier (5) 0 0 1 278.78 237.41 206.52 175.5 MHz 18-bit, 4-tap FIR filter 0 0 1 278.78 237.41 206.52 175.50 MHz 8-bit, 16-tap parallel FIR filter 58 0 4 141.26 133.49 114.88 100.28 MHz 8-bit, 1,024-point FFT function 870 5 1 261.09 235.51 205.21 175.22 MHz Notes to Table 4–36: (1) (2) (3) (4) (5) These design performance numbers were obtained using the Quartus II software. Numbers not listed will be included in a future version of the data sheet. This application uses registered inputs and outputs. This application uses registered multiplier input and output stages within the DSP block. This application uses registered multiplier input, pipeline, and output stages within the DSP block. Altera Corporation January 2006 4–21 Stratix Device Handbook, Volume 1 Timing Model Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–37 through 4–42 describe the Stratix device internal timing microparameters for LEs, IOEs, TriMatrix™ memory structures, DSP blocks, and MultiTrack interconnects. Table 4–37. LE Internal Timing Microparameter Descriptions Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LE combinatorial LUT delay for data-in to data-out tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Register minimum clock high or low time. The maximum core clock frequency can be calculated by 1/(2 × tCLKHL). Table 4–38. IOE Internal Timing Microparameter Descriptions Symbol Parameter tSU_R Row IOE input register setup time tSU_C Column IOE input register setup time tH IOE input and output register hold time after clock tCO_R Row IOE input and output register clock-to-output delay tC O _ C Column IOE input and output register clock-to-output delay tPIN2COMBOUT_R Row input pin to IOE combinatorial output tPIN2COMBOUT_C Column input pin to IOE combinatorial output tCOMBIN2PIN_R Row IOE data input to combinatorial output pin tCOMBIN2PIN_C Column IOE data input to combinatorial output pin tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Register minimum clock high or low time. The maximum I/O clock frequency can be calculated by 1/(2 × tCLKHL). Performance may also be affected by I/O timing, use of PLL, and I/O programmable settings. 4–22 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–39. DSP Block Internal Timing Microparameter Descriptions Symbol Altera Corporation January 2006 Parameter tSU Input, pipeline, and output register setup time before clock tH Input, pipeline, and output register hold time after clock tCO Input, pipeline, and output register clock-to-output delay tINREG2PIPE9 Input Register to DSP Block pipeline register in 9 × 9-bit mode tINREG2PIPE18 Input Register to DSP Block pipeline register in 18 × 18-bit mode tPIPE2OUTREG2ADD DSP Block Pipeline Register to output register delay in TwoMultipliers Adder mode tPIPE2OUTREG4ADD DSP Block Pipeline Register to output register delay in FourMultipliers Adder mode tPD9 Combinatorial input to output delay for 9 × 9 tPD18 Combinatorial input to output delay for 18 × 18 tPD36 Combinatorial input to output delay for 36 × 36 tCLR Minimum clear pulse width tCLKHL Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4–36 on page 4–20 and as reported by the timing analyzer in the Quartus II software. 4–23 Stratix Device Handbook, Volume 1 Timing Model Table 4–40. M512 Block Internal Timing Microparameter Descriptions Symbol Parameter tM512RC Synchronous read cycle time tM512WC Synchronous write cycle time tM512WERESU Write or read enable setup time before clock tM512WEREH Write or read enable hold time after clock tM512CLKENSU Clock enable setup time before clock tM512CLKENH Clock enable hold time after clock tM512DATASU Data setup time before clock tM512DATAH Data hold time after clock tM512WADDRSU Write address setup time before clock tM512WADDRH Write address hold time after clock tM512RADDRSU Read address setup time before clock tM512RADDRH Read address hold time after clock tM512DATACO1 Clock-to-output delay when using output registers tM512DATACO2 Clock-to-output delay without output registers tM512CLKHL Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4–36 on page 4–20 and as reported by the timing analyzer in the Quartus II software. tM512CLR Minimum clear pulse width Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol Parameter tM4KRC Synchronous read cycle time tM4KWC Synchronous write cycle time tM4KWERESU Write or read enable setup time before clock tM4KWEREH Write or read enable hold time after clock tM4KCLKENSU Clock enable setup time before clock tM4KCLKENH Clock enable hold time after clock tM4KBESU Byte enable setup time before clock tM4KBEH Byte enable hold time after clock tM4KDATAASU A port data setup time before clock 4–24 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol Parameter tM4KDATAAH A port data hold time after clock tM4KADDRASU A port address setup time before clock tM4KADDRAH A port address hold time after clock tM4KDATABSU B port data setup time before clock tM4KDATABH B port data hold time after clock tM4KADDRBSU B port address setup time before clock tM4KADDRBH B port address hold time after clock tM4KDATACO1 Clock-to-output delay when using output registers tM4KDATACO2 Clock-to-output delay without output registers tM4KCLKHL Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown inTable 4–36 on page 4–20 and as reported by the timing analyzer in the Quartus II software. tM4KCLR Minimum clear pulse width Table 4–42. M-RAM Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol Altera Corporation January 2006 Parameter tMRAMRC Synchronous read cycle time tMRAMWC Synchronous write cycle time tMRAMWERESU Write or read enable setup time before clock tMRAMWEREH Write or read enable hold time after clock tMRAMCLKENSU Clock enable setup time before clock tMRAMCLKENH Clock enable hold time after clock tMRAMBESU Byte enable setup time before clock tMRAMBEH Byte enable hold time after clock tMRAMDATAASU A port data setup time before clock tMRAMDATAAH A port data hold time after clock tMRAMADDRASU A port address setup time before clock tMRAMADDRAH A port address hold time after clock tMRAMDATABSU B port setup time before clock 4–25 Stratix Device Handbook, Volume 1 Timing Model Table 4–42. M-RAM Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol Parameter tMRAMDATABH B port hold time after clock tMRAMADDRBSU B port address setup time before clock tMRAMADDRBH B port address hold time after clock tMRAMDATACO1 Clock-to-output delay when using output registers tMRAMDATACO2 Clock-to-output delay without output registers tMRAMCLKHL Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4–36 on page 4–20 and as reported by the timing analyzer in the Quartus II software. tMRAMCLR Minimum clear pulse width. 4–26 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Figure 4–3 shows the TriMatrix memory waveforms for the M512, M4K, and M-RAM timing parameters shown in Tables 4–40 through 4–42. Figure 4–3. Dual-Port RAM Timing Microparameter Waveform wrclock tWEREH tWERESU wren tWADDRH tWADDRSU wraddress an-1 an a0 a1 a2 a3 a4 a5 a6 din4 din5 din6 tDATAH data-in din-1 din tDATASU rdclock tWEREH tWERESU rden tRC rdaddress bn b1 b0 b2 b3 tDATACO1 reg_data-out doutn-1 doutn-2 doutn dout0 tDATACO2 unreg_data-out doutn doutn-1 dout0 Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–44 through 4–50 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4–43. Routing Delay Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol Altera Corporation January 2006 Parameter tR4 Delay for an R4 line with average loading; covers a distance of four LAB columns. tR8 Delay for an R8 line with average loading; covers a distance of eight LAB columns. tR24 Delay for an R24 line with average loading; covers a distance of 24 LAB columns. 4–27 Stratix Device Handbook, Volume 1 Timing Model Table 4–43. Routing Delay Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol Parameter tC4 Delay for a C4 line with average loading; covers a distance of four LAB rows. tC8 Delay for a C8 line with average loading; covers a distance of eight LAB rows. tC16 Delay for a C16 line with average loading; covers a distance of 16 LAB rows. tLOCAL Local interconnect delay, for connections within a LAB, and for the final routing hop of connections to LABs, DSP blocks, RAM blocks and I/Os. Table 4–44. LE Internal Timing Microparameters -5 -6 -7 -8 Parameter Unit Min Max Min Max Min Max Min Max tSU 10 10 11 13 ps tH 100 100 114 135 ps tCO 156 tLUT 176 366 202 459 238 527 ps 621 ps tCLR 100 100 114 135 ps tPRE 100 100 114 135 ps tCLKHL 1000 1111 1190 1400 ps Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2) -5 Device Min EP1S10 EP1S20 EP1S25 EP1S30 -6 -7 -8 Unit Symbol Max Min Max Min Max Min Max tSU_R 76 80 80 80 ps tSU_C 176 80 80 80 ps tSU_R 76 80 80 80 ps tSU_C 76 80 80 80 ps tSU_R 276 280 280 280 ps tSU_C 276 280 280 280 ps tSU_R 76 80 80 80 ps tSU_C 176 180 180 180 ps 4–28 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 2 of 2) -5 Device Min EP1S40 EP1S60 EP1S80 -6 -7 -8 Unit Symbol Max Min Max Min Max Min Max tSU_R 76 80 80 80 ps tSU_C 376 380 380 380 ps tSU_R 276 280 280 280 ps tS U _ C 276 280 280 280 ps tSU_R 426 430 430 430 ps tSU_C 76 80 80 80 ps Table 4–46. IOE Internal Timing Microparameters -5 -6 -7 -8 Symbol Unit Min tH Max 68 Min Max 71 Min Max 82 Min Max 96 ps tCO_R 171 179 206 242 ps tCO_C 171 179 206 242 ps tPIN2COMBOUT_R 1,234 1,295 1,490 1,753 ps tPIN2COMBOUT_C 1,087 1,141 1,312 1,544 ps tCOMBIN2PIN_R 3,894 4,089 4,089 4,089 ps tCOMBIN2PIN_C 4,299 4,494 4,494 4,494 ps tCLR 276 tPRE tCLKHL 289 333 392 ps 260 273 313 369 ps 1,000 1,111 1,190 1,400 ps Table 4–47. DSP Block Internal Timing Microparameters (Part 1 of 2) -5 -6 -7 -8 Symbol Unit Min tSU 0 tH 67 tCO Max Min Max 0 Min Max 0 75 Min Max 0 86 ps 101 ps 142 158 181 214 ps tINREG2PIPE9 2,613 2,982 3,429 4,035 ps tINREG2PIPE18 3,390 3,993 4,591 5,402 ps Altera Corporation January 2006 4–29 Stratix Device Handbook, Volume 1 Timing Model Table 4–47. DSP Block Internal Timing Microparameters (Part 2 of 2) -5 -6 -7 -8 Symbol Unit Min Max Min Max Min Max Min Max tPIPE2OUTREG2ADD 2,002 2,203 2,533 2,980 ps tPIPE2OUTREG4ADD 2,899 3,189 3,667 4,314 ps tPD9 3,709 4,081 4,692 5,520 ps tPD18 4,795 5,275 6,065 7,135 ps tPD36 7,495 tCLR tCLKHL 8,245 9,481 11,154 ps 450 500 575 676 ps 1,350 1,500 1,724 2,029 ps Table 4–48. M512 Block Internal Timing Microparameters -5 -6 -7 -8 Symbol Unit Min Max Min Max Min Max Min Max tM512RC 3,340 3,816 4,387 5,162 ps tM512WC 3,138 3,590 4,128 4,860 ps tM512WERESU 110 123 141 166 ps tM512WEREH 34 38 43 51 ps tM512CLKENSU 215 215 247 290 ps tM512CLKENH –70 –70 –81 –95 ps tM512DATASU 110 123 141 166 ps tM512DATAH 34 38 43 51 ps tM512WADDRSU 110 123 141 166 ps tM512WADDRH 34 38 43 51 ps tM512RADDRSU 110 123 141 166 ps tM512RADDRH 34 38 43 51 ps tM512DATACO1 424 472 541 637 ps tM512DATACO2 3,366 3,846 4,421 5,203 ps tM512CLKHL tM512CLR 1,000 1,111 1,190 1,400 ps 170 189 217 255 ps 4–30 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–49. M4K Block Internal Timing Microparameters -5 -6 -7 -8 Symbol Unit Min Max tM4KRC Min Max 3,807 tM4KWC Min Max 4,320 2,556 Min Max 4,967 2,840 5,844 3,265 3,842 ps ps tM4KWERESU 131 149 171 202 ps tM4KWEREH 34 38 43 51 ps tM4KCLKENSU 193 215 247 290 ps tM4KCLKENH –63 –70 –81 –95 ps tM4KBESU 131 149 171 202 ps tM4KBEH 34 38 43 51 ps tM4KDATAASU 131 149 171 202 ps tM4KDATAAH 34 38 43 51 ps tM4KADDRASU 131 149 171 202 ps tM4KADDRAH 34 38 43 51 ps tM4KDATABSU 131 149 171 202 ps tM4KDATABH 34 38 43 51 ps tM4KADDRBSU 131 149 171 202 ps tM4KADDRBH 34 38 43 51 ps tM4KDATACO1 571 tM4KDATACO2 tM4KCLKHL tM4KCLR 635 3,984 729 4,507 858 5,182 6,097 ps ps 1,000 1,111 1,190 1,400 ps 170 189 217 255 ps Table 4–50. M-RAM Block Internal Timing Microparameters (Part 1 of 2) -5 -6 -7 -8 Symbol Unit Min tMRAMRC Max Min 4,364 tMRAMWC Max Min 4,838 3,654 Max Min 5,562 4,127 Max 6,544 4,746 5,583 ps ps tMRAMWERESU 25 25 28 33 ps tMRAMWEREH 18 20 23 27 ps tMRAMCLKENSU 99 111 127 150 ps tMRAMCLKENH –48 –53 –61 –72 ps Altera Corporation January 2006 4–31 Stratix Device Handbook, Volume 1 Timing Model Table 4–50. M-RAM Block Internal Timing Microparameters (Part 2 of 2) -5 -6 -7 -8 Symbol Unit Min Max Min Max Min Max Min Max tMRAMBESU 25 25 28 33 ps tMRAMBEH 18 20 23 27 ps tMRAMDATAASU 25 25 28 33 ps tMRAMDATAAH 18 20 23 27 ps tMRAMADDRASU 25 25 28 33 ps tMRAMADDRAH 18 20 23 27 ps tMRAMDATABSU 25 25 28 33 ps tMRAMDATABH 18 20 23 27 ps tMRAMADDRBSU 25 25 28 33 ps tMRAMADDRBH 18 20 23 27 ps tMRAMDATACO1 1,038 tMRAMDATACO2 1,053 4,362 tMRAMCLKHL 1,210 4,939 1,424 5,678 ps 6,681 ps 1,000 1,111 1,190 1,400 ps 135 150 172 202 ps tMRAMCLR Table 4–51. Routing Delay Internal Timing Parameters -5 -6 -7 -8 Unit Symbol Min Max Min Max Min Max Min Max tR 4 268 295 339 390 ps tR 8 371 349 401 461 ps tR 2 4 465 512 588 676 ps tC 4 440 484 557 641 ps tC 8 577 634 730 840 ps tC 1 6 445 489 563 647 ps tL O C A L 313 345 396 455 ps Routing delays vary depending on the load on that specific routing line. The Quartus II software reports the routing delay information when running the timing analysis for a design. 4–32 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics External Timing Parameters External timing parameters are specified by device density and speed grade. Figure 4–4 shows the pin-to-pin timing model for bidirectional IOE pin timing. All registers are within the IOE. Figure 4–4. External Timing in Stratix Devices OE Register D PRN Q Dedicated Clock CLRN Output Register D PRN Q tINSU tINH tOUTCO tXZ tZX Bidirectional Pin CLRN Input Register D PRN Q CLRN All external timing parameters reported in this section are defined with respect to the dedicated clock pin as the starting point. All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the 24-mA current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4–103 through 4–108. Altera Corporation January 2006 4–33 Stratix Device Handbook, Volume 1 Timing Model Table 4–52 shows the external I/O timing parameters when using fast regional clock networks. Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters Notes (1), (2) Symbol Parameter tINSU Setup time for input or bidirectional pin using IOE input register with fast regional clock fed by FCLK pin tINH Hold time for input or bidirectional pin using IOE input register with fast regional clock fed by FCLK pin tOUTCO Clock-to-output delay output or bidirectional pin using IOE output register with fast regional clock fed by FCLK pin tXZ Synchronous IOE output enable register to output pin disable delay using fast regional clock fed by FCLK pin tZX Synchronous IOE output enable register to output pin enable delay using fast regional clock fed by FCLK pin Notes to Table 4–52: (1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin. Table 4–53 shows the external I/O timing parameters when using regional clock networks. Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 1 of 2) Notes (1), (2) Symbol Parameter tINSU Setup time for input or bidirectional pin using IOE input register with regional clock fed by CLK pin tINH Hold time for input or bidirectional pin using IOE input register with regional clock fed by CLK pin tOUTCO Clock-to-output delay output or bidirectional pin using IOE output register with regional clock fed by CLK pin tINSUPLL Setup time for input or bidirectional pin using IOE input register with regional clock fed by Enhanced PLL with default phase setting tINHPLL Hold time for input or bidirectional pin using IOE input register with regional clock fed by Enhanced PLL with default phase setting tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output register with regional clock Enhanced PLL with default phase setting 4–34 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2 of 2) Notes (1), (2) Symbol Parameter tXZPLL Synchronous IOE output enable register to output pin disable delay using regional clock fed by Enhanced PLL with default phase setting tZXPLL Synchronous IOE output enable register to output pin enable delay using regional clock fed by Enhanced PLL with default phase setting Notes to Table 4–53: (1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin. Table 4–54 shows the external I/O timing parameters when using global clock networks. Table 4–54. Stratix Global Clock External I/O Timing Parameters Notes (1), (2) Symbol Parameter tINSU Setup time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tINH Hold time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tOUTCO Clock-to-output delay output or bidirectional pin using IOE output register with global clock fed by CLK pin tINSUPLL Setup time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting tINHPLL Hold time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output register with global clock Enhanced PLL with default phase setting tXZPLL Synchronous IOE output enable register to output pin disable delay using global clock fed by Enhanced PLL with default phase setting tZXPLL Synchronous IOE output enable register to output pin enable delay using global clock fed by Enhanced PLL with default phase setting Notes to Table 4–54: (1) (2) Altera Corporation January 2006 These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin. 4–35 Stratix Device Handbook, Volume 1 Timing Model Stratix External I/O Timing These timing parameters are for both column IOE and row IOE pins. In EP1S30 devices and above, you can decrease the tSU time by using the FPLLCLK, but may get positive hold time in EP1S60 and EP1S80 devices. You should use the Quartus II software to verify the external devices for any pin. Tables 4–55 through 4–60 show the external timing parameters on column and row pins for EP1S10 devices. Table 4–55. EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 2.238 2.325 2.668 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.240 4.549 2.240 4.836 2.240 5.218 NA NA ns tXZ 2.180 4.423 2.180 4.704 2.180 5.094 NA NA ns tZX 2.180 4.423 2.180 4.704 2.180 5.094 NA NA ns Table 4–56. EP1S10 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min -8 Speed Grade Parameter Unit Max Max 2.054 Max tINSU 1.992 2.359 tINH 0.000 tOUTCO 2.395 4.795 2.395 5.107 2.395 5.527 NA NA ns tXZ 2.335 4.669 2.335 4.975 2.335 5.403 NA NA ns tZX 2.335 4.669 2.335 4.975 2.335 5.403 NA NA ns tINSUPLL 0.975 0.985 1.097 NA tINHPLL 0.000 0.000 0.000 NA NA ns tOUTCOPLL 1.262 2.636 1.262 2.680 1.262 2.769 NA NA ns tXZPLL 1.202 2.510 1.202 2.548 1.202 2.645 NA NA ns tZXPLL 1.202 2.510 1.202 2.548 1.202 2.645 NA NA ns 0.000 4–36 Stratix Device Handbook, Volume 1 NA 0.000 ns NA ns ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–57. EP1S10 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.692 Max 1.940 Max tINSU 1.647 tINH 0.000 tOUTCO 2.619 5.184 2.619 5.515 2.619 5.999 NA NA ns tXZ 2.559 5.058 2.559 5.383 2.559 5.875 NA NA ns tZX 2.559 5.058 2.559 5.383 2.559 5.875 NA NA ns tINSUPLL 1.239 1.229 1.374 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.109 2.372 1.109 2.436 1.109 2.492 NA NA ns tXZPLL 1.049 2.246 1.049 2.304 1.049 2.368 NA NA ns tZXPLL 1.049 2.246 1.049 2.304 1.049 2.368 NA NA ns 0.000 NA 0.000 ns NA ns Table 4–58. EP1S10 External I/O Timing on Row Pin Using Fast Regional Clock Network Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.759 Max tINSU 2.212 tINH 0.000 tOUTCO 2.391 4.838 2.391 5.159 2.391 5.569 NA NA ns tXZ 2.418 4.892 2.418 5.215 2.418 5.637 NA NA ns tZX 2.418 4.892 2.418 5.215 2.418 5.637 NA NA ns Altera Corporation January 2006 2.403 Max 0.000 NA 0.000 ns NA ns 4–37 Stratix Device Handbook, Volume 1 Timing Model Table 4–59. EP1S10 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.336 Max 2.685 Max tINSU 2.161 tINH 0.000 tOUTCO 2.434 4.889 2.434 5.226 2.434 5.643 NA NA ns tXZ 2.461 4.493 2.461 5.282 2.461 5.711 NA NA ns tZX 2.461 4.493 2.461 5.282 2.461 5.711 NA NA ns tINSUPLL 1.057 1.172 1.315 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.327 2.773 1.327 2.848 1.327 2.940 NA NA ns tXZPLL 1.354 2.827 1.354 2.904 1.354 3.008 NA NA ns tZXPLL 1.354 2.827 1.354 2.904 1.354 3.008 NA NA ns 0.000 NA 0.000 ns NA ns Table 4–60. EP1S10 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.944 Max 2.232 Max tINSU 1.787 tINH 0.000 tOUTCO 2.647 5.263 2.647 5.618 2.647 6.069 NA NA ns tXZ 2.674 5.317 2.674 5.674 2.674 6.164 NA NA ns tZX 2.674 5.317 2.674 5.674 2.674 6.164 NA NA ns tINSUPLL 1.371 1.1472 1.654 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.144 2.459 1.144 2.548 1.144 2.601 NA NA ns tXZPLL 1.171 2.513 1.171 2.604 1.171 2.669 NA NA ns tZXPLL 1.171 2.513 1.171 2.604 1.171 2.669 NA NA ns 0.000 NA 0.000 ns NA ns Note to Tables 4–55 to 4–60: (1) Only EP1S25, EP1S30, and EP1S40 have speed grade of -8. 4–38 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Tables 4–61 through 4–66 show the external timing parameters on column and row pins for EP1S20 devices. Table 4–61. EP1S20 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.245 Max 2.576 Max tINSU 2.065 tINH 0.000 tOUTCO 2.283 4.622 2.283 4.916 2.283 5.310 NA NA ns tXZ 2.223 4.496 2.223 4.784 2.223 5.186 NA NA ns tZX 2.223 4.496 2.223 4.784 2.223 5.186 NA NA ns 0.000 NA 0.000 ns NA ns Table 4–62. EP1S20 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 1.541 1.680 1.931 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.597 5.146 2.597 5.481 2.597 5.955 NA NA ns tXZ 2.537 5.020 2.537 5.349 2.537 5.831 NA NA ns tZX 2.537 5.020 2.537 5.349 2.537 5.831 NA NA ns tINSUPLL 0.777 tINHPLL 0.000 tOUTCOPLL 1.296 2.690 1.296 2.801 1.296 2.876 NA NA ns tXZPLL 1.236 2.564 1.236 2.669 1.236 2.752 NA NA ns tZXPLL 1.236 2.564 1.236 2.669 1.236 2.752 NA NA ns Altera Corporation January 2006 0.818 0.937 0.000 NA 0.000 ns NA ns 4–39 Stratix Device Handbook, Volume 1 Timing Model Table 4–63. EP1S20 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.479 Max 1.699 Max tINSU 1.351 tINH 0.000 tOUTCO 2.732 5.380 2.732 5.728 2.732 6.240 NA NA ns tXZ 2.672 5.254 2.672 5.596 2.672 6.116 NA NA ns tZX 2.672 5.254 2.672 5.596 2.672 6.116 NA NA tINSUPLL 0.923 0.971 1.098 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.210 2.544 1.210 2.648 1.210 2.715 NA NA ns tXZPLL 1.150 2.418 1.150 2.516 1.150 2.591 NA NA ns tZXPLL 1.150 2.418 1.150 2.516 1.150 2.591 NA NA ns 0.000 NA 0.000 ns NA ns ns Table 4–64. EP1S20 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.207 Max 2.535 Max tINSU 2.032 tINH 0.000 tOUTCO 2.492 5.018 2.492 5.355 2.492 5.793 NA NA ns tXZ 2.519 5.072 2.519 5.411 2.519 5.861 NA NA ns tZX 2.519 5.072 2.519 5.411 2.519 5.861 NA NA ns 0.000 4–40 Stratix Device Handbook, Volume 1 NA 0.000 ns NA ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–65. EP1S20 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.967 Max 2.258 Max tINSU 1.815 tINH 0.000 tOUTCO 2.633 5.235 2.663 5.595 2.663 6.070 NA NA ns tXZ 2.660 5.289 2.660 5.651 2.660 6.138 NA NA ns tZX 2.660 5.289 2.660 5.651 2.660 6.138 NA NA tINSUPLL 1.060 1.112 1.277 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.325 2.770 1.325 2.908 1.325 2.978 NA NA ns tXZPLL 1.352 2.824 1.352 2.964 1.352 3.046 NA NA ns tZXPLL 1.352 2.824 1.352 2.964 1.352 3.046 NA NA ns 0.000 NA 0.000 ns NA ns ns Table 4–66. EP1S20 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.887 Max 2.170 Max tINSU 1.742 tINH 0.000 tOUTCO 2.674 5.308 2.674 5.675 2.674 6.158 NA NA ns tXZ 2.701 5.362 2.701 5.731 2.701 6.226 NA NA ns tZX 2.701 5.362 2.701 5.731 2.701 6.226 NA NA tINSUPLL 1.353 1.418 1.613 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.158 2.447 1.158 2.602 1.158 2.642 NA NA ns tXZPLL 1.185 2.531 1.158 2.602 1.185 2.710 NA NA ns tZXPLL 1.185 2.531 1.158 2.602 1.185 2.710 NA NA ns 0.000 NA 0.000 ns NA ns ns Note to Tables 4–61 to 4–66: (1) Only EP1S25, EP1S30, and EP1S40 have a speed grade of -8. Altera Corporation January 2006 4–41 Stratix Device Handbook, Volume 1 Timing Model Tables 4–67 through 4–72 show the external timing parameters on column and row pins for EP1S25 devices. Table 4–67. EP1S25 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.613 Max 2.968 Max tINSU 2.412 tINH 0.000 tOUTCO 2.196 4.475 2.196 4.748 2.196 5.118 2.196 5.603 ns tXZ 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns tZX 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns 0.000 3.468 0.000 ns 0.000 ns Table 4–68. EP1S25 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 1.535 1.661 1.877 2.125 ns tINH 0.000 0.000 0.000 0.000 ns tOUTCO 2.739 5.396 2.739 5.746 2.739 6.262 2.739 6.946 ns tXZ 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns tZX 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns tINSUPLL 0.934 tINHPLL 0.000 tOUTCOPLL 1.316 2.733 1.316 2.839 1.316 2.921 1.316 3.110 ns tXZPLL 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns tZXPLL 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns 0.980 1.092 0.000 4–42 Stratix Device Handbook, Volume 1 1.231 0.000 ns 0.000 ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–69. EP1S25 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.471 Max 1.657 Max tINSU 1.371 tINH 0.000 tOUTCO 2.809 5.516 2.809 5.890 2.809 6.429 2.809 7.155 ns tXZ 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns tZX 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 tINSUPLL 1.271 1.327 1.491 1.677 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.124 2.396 1.124 2.492 1.124 2.522 1.124 2.602 ns tXZPLL 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns tZXPLL 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns 0.000 1.916 0.000 ns 0.000 ns ns Table 4–70. EP1S25 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade Min Min Min -8 Speed Grade Parameter Unit Max Max 2.990 Min Max tINSU 2.429 tINH 0.000 tOUTCO 2.376 4.821 2.376 5.131 2.376 5.538 2.376 6.063 ns tXZ 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns tZX 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns Altera Corporation January 2006 2.631 Max 0.000 3.503 0.000 ns 0.000 ns 4–43 Stratix Device Handbook, Volume 1 Timing Model Table 4–71. EP1S25 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.927 Max 2.182 Max tINSU 1.793 tINH 0.000 tOUTCO 2.759 5.457 2.759 5.835 2.759 6.346 2.759 7.024 ns tXZ 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns tZX 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 tINSUPLL 1.169 1.221 1.373 1.600 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.375 2.861 1.375 2.999 1.375 3.082 1.375 3.174 ns tXZPLL 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns tZXPLL 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns 0.000 2.542 0.000 ns 0.000 ns ns Table 4–72. EP1S25 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 1.779 Max 2.012 Max tINSU 1.665 tINH 0.000 tOUTCO 2.834 5.585 2.834 5.983 2.834 6.516 2.834 7.194 ns tXZ 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns tZX 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 tINSUPLL 1.538 1.606 1.816 2.121 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.164 2.492 1.164 2.614 1.164 2.639 1.164 2.653 ns tXZPLL 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns tZXPLL 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns 0.000 4–44 Stratix Device Handbook, Volume 1 2.372 0.000 ns 0.000 ns ns Altera Corporation January 2006 DC & Switching Characteristics Tables 4–73 through 4–78 show the external timing parameters on column and row pins for EP1S30 devices. Table 4–73. EP1S30 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Unit Parameter Max Max 2.680 Max 3.062 Max tINSU 2.502 tINH 0.000 tOUTCO 2.473 4.965 2.473 5.329 2.473 5.784 2.473 6.392 ns tXZ 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns tZX 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns 0.000 3.591 0.000 ns 0.000 ns Table 4–74. EP1S30 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 2.286 2.426 2.769 3.249 ns tINH 0.000 0.000 0.000 0.000 ns tOUTCO 2.641 5.225 2.641 5.629 2.641 6.130 2.641 6.796 ns tXZ 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns tZX 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns tINSUPLL 1.200 tINHPLL 0.000 tOUTCOPLL 1.108 2.367 1.108 2.534 1.108 2.569 1.108 2.517 ns tXZPLL 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns tZXPLL 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns 1.185 1.344 0.000 1.662 0.000 ns 0.000 Table 4–75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks ns (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 1.935 2.029 2.310 2.709 ns tINH 0.000 0.000 0.000 0.000 ns tOUTCO 2.814 Altera Corporation January 2006 5.532 2.814 5.980 2.814 6.536 2.814 7.274 ns 4–45 Stratix Device Handbook, Volume 1 Timing Model Table 4–75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Max Min Max Min Max Min Max tXZ 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 tZX 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 tINSUPLL 1.265 1.236 1.403 1.756 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.068 2.302 1.068 2.483 1.068 2.510 1.068 2.423 ns tXZPLL 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns tZXPLL 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns Parameter Unit ns ns Table 4–76. EP1S30 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameters Unit Max Max Max Max tINSU 2.616 2.808 3.223 3.797 ns tINH 0.000 0.000 0.000 0.000 ns tOUTCO 2.542 5.114 2.542 5.502 2.542 5.965 2.542 6.581 ns tXZ 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns tZX 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns 4–46 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–77. EP1S30 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.467 Max 2.828 Max tINSU 2.322 tINH 0.000 tOUTCO 2.731 5.408 2.731 5.843 2.731 6.360 2.731 7.036 ns tXZ 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns tZX 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 tINSUPLL 1.291 1.283 1.469 1.832 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.192 2.539 1.192 2.737 1.192 2.786 1.192 2.742 ns tXZPLL 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns tZXPLL 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns 0.000 3.342 0.000 ns 0.000 ns ns Table 4–78. EP1S30 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.398 Max tINSU 1.995 tINH 0.000 tOUTCO 2.917 5.735 2.917 6.221 2.917 6.790 2.917 7.548 ns tXZ 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns tZX 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 tINSUPLL 1.337 1.312 1.508 1.902 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.164 2.493 1.164 2.708 1.164 2.747 1.164 2.672 ns tXZPLL 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns tZXPLL 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns Altera Corporation January 2006 2.089 Max 0.000 2.830 0.000 ns 0.000 ns ns 4–47 Stratix Device Handbook, Volume 1 Timing Model Tables 4–79 through 4–84 show the external timing parameters on column and row pins for EP1S40 devices. Table 4–79. EP1S40 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.907 Max 3.290 Max tINSU 2.696 tINH 0.000 tOUTCO 2.506 5.015 2.506 5.348 2.506 5.809 2.698 7.286 ns tXZ 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns tZX 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns 0.000 2.899 0.000 ns 0.000 ns Table 4–80. EP1S40 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 2.413 2.581 2.914 2.938 ns tINH 0.000 0.000 0.000 0.000 ns tOUTCO 2.668 5.254 2.668 5.628 2.668 6.132 2.869 7.307 ns tXZ 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns tZX 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns tINSUPLL 1.385 tINHPLL 0.000 tOUTCOPLL 1.117 2.382 1.117 2.552 1.117 2.504 1.117 2.542 ns tXZPLL 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns tZXPLL 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns 1.376 1.609 0.000 4–48 Stratix Device Handbook, Volume 1 1.837 0.000 ns 0.000 ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–81. EP1S40 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.268 Max 2.558 Max tINSU 2.126 tINH 0.000 tOUTCO 2.856 5.585 2.856 5.987 2.856 6.541 2.847 7.253 ns tXZ 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns tZX 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 tINSUPLL 1.466 1.455 1.711 1.906 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.092 2.345 1.092 2.510 1.092 2.455 1.089 2.473 ns tXZPLL 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns tZXPLL 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns 0.000 2.930 0.000 ns 0.000 ns ns Table 4–82. EP1S40 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 3.083 Max tINSU 2.472 tINH 0.000 tOUTCO 2.631 5.258 2.631 5.625 2.631 6.105 2.745 7.324 ns tXZ 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns tZX 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns Altera Corporation January 2006 2.685 Max 0.000 3.056 0.000 ns 0.000 ns 4–49 Stratix Device Handbook, Volume 1 Timing Model Table 4–83. EP1S40 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.526 Max 2.898 Max tINSU 2.349 tINH 0.000 tOUTCO 2.725 5.381 2.725 5.784 2.725 6.290 2.725 7.426 ns tXZ 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns tZX 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 tINSUPLL 1.328 1.322 1.605 1.883 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.169 2.502 1.169 2.698 1.169 2.650 1.169 2.691 ns tXZPLL 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns tZXPLL 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns 0.000 2.952 0.000 ns 0.000 ns ns Table 4–84. EP1S40 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.171 Max 2.491 Max tINSU 2.020 tINH 0.000 tOUTCO 2.912 5.710 2.912 6.139 2.912 6.697 2.931 7.480 ns tXZ 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns tZX 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 tINSUPLL 1.370 1.368 1.654 1.881 ns tINHPLL 0.000 0.000 0.000 0.000 ns tOUTCOPLL 1.144 2.460 1.144 2.652 1.144 2.601 1.170 2.693 ns tXZPLL 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns tZXPLL 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns 0.000 4–50 Stratix Device Handbook, Volume 1 2.898 0.000 ns 0.000 ns ns Altera Corporation January 2006 DC & Switching Characteristics Tables 4–85 through 4–90 show the external timing parameters on column and row pins for EP1S60 devices. Table 4–85. EP1S60 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 3.277 Max 3.733 Max tINSU 3.029 tINH 0.000 tOUTCO 2.446 4.871 2.446 5.215 2.446 5.685 NA NA ns tXZ 2.386 4.745 2.386 5.083 2.386 5.561 NA NA ns tZX 2.386 4.745 2.386 5.083 2.386 5.561 NA NA ns 0.000 NA 0.000 ns NA ns Table 4–86. EP1S60 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 2.491 2.691 3.060 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.767 5.409 2.767 5.801 2.767 6.358 NA NA ns tXZ 2.707 5.283 2.707 5.669 2.707 6.234 NA NA ns tZX 2.707 5.283 2.707 5.669 2.707 6.234 NA NA ns tINSUPLL 1.233 tINHPLL 0.000 tOUTCOPLL 1.078 2.278 1.078 2.395 1.078 2.428 NA NA ns tXZPLL 1.018 2.152 1.018 2.263 1.018 2.304 NA NA ns tZXPLL 1.018 2.152 1.018 2.263 1.018 2.304 NA NA ns Altera Corporation January 2006 1.270 1.438 0.000 NA 0.000 ns NA ns 4–51 Stratix Device Handbook, Volume 1 Timing Model Table 4–87. EP1S60 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.152 Max 2.441 Max tINSU 2.000 tINH 0.000 tOUTCO 3.051 5.900 3.051 6.340 3.051 6.977 NA NA ns tXZ 2.991 5.774 2.991 6.208 2.991 6.853 NA NA ns tZX 2.991 5.774 2.991 6.208 2.991 6.853 NA NA tINSUPLL 1.315 1.362 1.543 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.029 2.196 1.029 2.303 1.029 2.323 NA NA ns tXZPLL 0.969 2.070 0.969 2.171 0.969 2.199 NA NA ns tZXPLL 0.969 2.070 0.969 2.171 0.969 2.199 NA NA ns 0.000 NA 0.000 ns NA ns ns Table 4–88. EP1S60 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 3.393 Max 3.867 Max tINSU 3.144 tINH 0.000 tOUTCO 2.643 5.275 2.643 5.654 2.643 6.140 NA NA ns tXZ 2.670 5.329 2.670 5.710 2.670 6.208 NA NA ns tZX 2.670 5.329 2.670 5.710 2.670 6.208 NA NA ns 0.000 4–52 Stratix Device Handbook, Volume 1 NA 0.000 ns NA ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–89. EP1S60 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.990 Max 3.407 Max tINSU 2.775 tINH 0.000 tOUTCO 2.867 5.644 2.867 6.057 2.867 6.600 NA NA ns tXZ 2.894 5.698 2.894 6.113 2.894 6.668 NA NA ns tZX 2.894 5.698 2.894 6.113 2.894 6.668 NA NA tINSUPLL 1.523 1.577 1.791 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.174 2.507 1.174 2.643 1.174 2.664 NA NA ns tXZPLL 1.201 2.561 1.201 2.699 1.201 2.732 NA NA ns tZXPLL 1.201 2.561 1.201 2.699 1.201 2.732 NA NA ns 0.000 NA 0.000 ns NA ns ns Table 4–90. EP1S60 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.393 Max 2.721 Max tINSU 2.232 tINH 0.000 tOUTCO 3.182 6.187 3.182 6.654 3.182 7.286 NA NA ns tXZ 3.209 6.241 3.209 6.710 3.209 7.354 NA NA ns tZX 3.209 6.241 3.209 6.710 3.209 7.354 NA NA tINSUPLL 1.651 1.612 1.833 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.154 2.469 1.154 2.608 1.154 2.622 NA NA ns tXZPLL 1.181 2.523 1.181 2.664 1.181 2.690 NA NA ns tZXPLL 1.181 2.523 1.181 2.664 1.181 2.690 NA NA ns 0.000 NA 0.000 ns NA ns ns Note to Tables 4–85 to 4–90: (1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade. Altera Corporation January 2006 4–53 Stratix Device Handbook, Volume 1 Timing Model Tables 4–91 through 4–96 show the external timing parameters on column and row pins for EP1S80 devices. Table 4–91. EP1S80 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 2.528 Max 2.900 Max tINSU 2.328 tINH 0.000 tOUTCO 2.422 4.830 2.422 5.169 2.422 5.633 NA NA ns tXZ 2.362 4.704 2.362 5.037 2.362 5.509 NA NA ns tZX 2.362 4.704 2.362 5.037 2.362 5.509 NA NA ns 0.000 NA 0.000 ns NA ns Table 4–92. EP1S80 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max Max Max tINSU 1.760 1.912 2.194 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.761 5.398 2.761 5.785 2.761 6.339 NA NA ns tXZ 2.701 5.272 2.701 5.653 2.701 6.215 NA NA ns tZX 2.701 5.272 2.701 5.653 2.701 6.215 NA NA ns tINSUPLL 0.462 tINHPLL 0.000 tOUTCOPLL 1.661 2.849 1.661 2.859 1.661 2.881 NA NA ns tXZPLL 1.601 2.723 1.601 2.727 1.601 2.757 NA NA ns tZXPLL 1.601 2.723 1.601 2.727 1.601 2.757 NA NA ns 0.606 0.785 0.000 4–54 Stratix Device Handbook, Volume 1 NA 0.000 ns NA ns Altera Corporation January 2006 DC & Switching Characteristics Table 4–93. EP1S80 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Parameter Unit Max Max 0.976 Max 1.118 Max tINSU 0.884 tINH 0.000 tOUTCO 3.267 6.274 3.267 6.721 3.267 7.415 NA NA ns tXZ 3.207 6.148 3.207 6.589 3.207 7.291 NA NA ns tZX 3.207 6.148 3.207 6.589 3.207 7.291 NA NA tINSUPLL 0.506 0.656 0.838 NA ns tINHPLL 0.000 0.000 0.000 NA ns tOUTCOPLL 1.635 2.805 1.635 2.809 1.635 2.828 NA NA ns tXZPLL 1.575 2.679 1.575 2.677 1.575 2.704 NA NA ns tZXPLL 1.575 2.679 1.575 2.677 1.575 2.704 NA NA ns 0.000 NA 0.000 ns NA ns ns Table 4–94. EP1S80 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min Max Min Max Min Max Min Max tINSU 2.792 2.993 3.386 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.619 5.235 2.619 5.609 2.619 6.086 NA NA ns tXZ 2.646 5.289 2.646 5.665 2.646 6.154 NA NA ns tZX 2.646 5.289 2.646 5.665 2.646 6.154 NA NA ns Altera Corporation January 2006 4–55 Stratix Device Handbook, Volume 1 Timing Model Table 4–95. EP1S80 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min Max Min Max Min Max Min Max tINSU 2.295 2.454 2.767 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 2.917 5.732 2.917 6.148 2.917 6.705 NA NA ns tXZ 2.944 5.786 2.944 6.204 2.944 6.773 NA NA ns tZX 2.944 5.786 2.944 6.204 2.944 6.773 NA NA ns tINSUPLL 1.011 tINHPLL 0.000 tOUTCOPLL 1.808 3.169 1.808 3.209 1.808 3.233 NA NA ns tXZPLL 1.835 3.223 1.835 3.265 1.835 3.301 NA NA ns tZXPLL 1.835 3.223 1.835 3.265 1.835 3.301 NA NA ns 1.161 1.372 0.000 NA 0.000 ns NA ns Table 4–96. EP1S80 External I/O Timing on Rows Using Pin Global Clock Networks Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Min Min Min Min Symbol Unit Max Max Max Max tINSU 1.362 1.451 1.613 NA ns tINH 0.000 0.000 0.000 NA ns tOUTCO 3.457 6.665 3.457 7.151 3.457 7.859 NA NA ns tXZ 3.484 6.719 3.484 7.207 3.484 7.927 NA NA ns tZX 3.484 6.719 3.484 7.207 3.484 7.927 NA NA ns tINSUPLL o.994 tINHPLL 0.000 tOUTCOPLL 1.821 3.186 1.821 3.227 1.821 3.254 NA NA ns tXZPLL 1.848 3.240 1.848 3.283 1.848 3.322 NA NA ns tZXPLL 1.848 3.240 1.848 3.283 1.848 3.322 NA NA ns 1.143 1.351 0.000 NA 0.000 ns NA ns Note to Tables 4–91 to 4–96: (1) Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade. 4–56 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Definition of I/O Skew I/O skew is defined as the absolute value of the worst-case difference in clock-to-out times (tCO) between any two output registers fed by a common clock source. I/O bank skew is made up of the following components: ■ ■ Clock network skews: This is the difference between the arrival times of the clock at the clock input port of the two IOE registers. Package skews: This is the package trace length differences between (I/O pad A to I/O pin A) and (I/O pad B to I/O pin B). Figure 4–5 shows an example of two IOE registers located in the same bank, being fed by a common clock source. The clock can come from an input pin or from a PLL output. Figure 4–5. I/O Skew within an I/O Bank I/O Bank I/O Pin A Common Source of GCLK I/O Pin B Fast Edge I/O Pin A Slow Edge I/O Pin B I/O Skew Altera Corporation January 2006 I/O Skew 4–57 Stratix Device Handbook, Volume 1 Timing Model Figure 4–6 shows the case where four IOE registers are located in two different I/O banks. Figure 4–6. I/O Skew Across Two I/O Banks I/O Bank I/O Pin A I/O Pin B Common Source of GCLK I/O Pin C I/O Pin D I/O Bank I/O Pin Skew across two Banks I/O Pin A I/O Pin B I/O Pin C I/O Pin D Table 4–97 defines the timing parameters used to define the timing for horizontal I/O pins (side banks 1, 2, 5, 6) and vertical I/O pins (top and bottom banks 3, 4, 7, 8). The timing parameters define the skew within an I/O bank, across two neighboring I/O banks on the same side of the device, across all horizontal I/O banks, across all vertical I/O banks, and the skew for the overall device. Table 4–97. Output Pin Timing Skew Definitions (Part 1 of 2) Symbol Definition tSB_HIO Row I/O (HIO) within one I/O bank (1) tSB_VIO Column I/O (VIO) within one I/O bank (1) tSS_HIO Row I/O (HIO) same side of the device, across two banks (2) tSS_VIO Column I/O (VIO) same side of the device, across two banks (2) 4–58 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–97. Output Pin Timing Skew Definitions (Part 2 of 2) Symbol Definition tLR_HIO Across all HIO banks (1, 2, 5, 6); across four similar type I/O banks tTB_VIO Across all VIO banks (3, 4, 7, 8); across four similar type I/O banks tOVERALL Output timing skew for all I/O pins on the device. Notes to Table 4–97: (1) (2) See Figure 4–5 on page 4–57. See Figure 4–6 on page 4–58. Table 4–98 shows the I/O skews when using the same global or regional clock to feed IOE registers in I/O banks around each device. These values can be used for calculating the timing budget on the output (write) side of a memory interface. These values already factor in the package skew. Table 4–98. Output Skew for Stratix by Device Density Skew (ps) (1) Symbol EP1S10 to EP1S30 EP1S40 EP1S60 & EP1S80 tSB_HIO 90 290 500 tSB_VIO 160 290 500 tSS_HIO 90 460 600 tSS_VIO 180 520 630 tLR_HIO 150 490 600 tTB_VIO 190 580 670 tOVERALL 430 630 880 Note to Table 4–98: (1) Altera Corporation January 2006 The skew numbers in Table 4–98 account for worst case package skews. 4–59 Stratix Device Handbook, Volume 1 Timing Model Skew on Input Pins Table 4–99 shows the package skews that were considered to get the worst case I/O skew value. You can use these values, for example, when calculating the timing budget on the input (read) side of a memory interface. Table 4–99. Package Skew on Input Pins Package Parameter Pins in the same I/O bank Worst-Case Skew (ps) 50 Pins in top/bottom (vertical I/O) banks 50 Pins in left/right side (horizontal I/O) banks 50 Pins across the entire device 100 PLL Counter & Clock Network Skews Table 4–100 shows the clock skews between different clock outputs from the Stratix device PLL. Table 4–100. PLL Counter & Clock Network Skews Parameter Worst-Case Skew (ps) Clock skew between two external clock outputs driven by the same counter 100 Clock skew between two external clock outputs driven by the different counters with the same settings 150 Dual-purpose PLL dedicated clock output used as I/O pin vs. regular I/O pin 270 (1) Clock skew between any two outputs of the PLL that drive global clock networks 150 Note to Table 4–100: (1) The Quartus II software models 270 ps of delay on the PLL dedicated clock output (PLL6_OUT[3..0]p/n and PLL5_OUT[3..0]p/n) pins both when used as clocks and when used as I/O pins. I/O Timing Measurement Methodology Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination and loading for each I/O standard. The timing information is specified from the input clock pin up to the output pin of 4–60 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standard. Altera measures clock-to-output delays (tCO) at worst-case process, minimum voltage, and maximum temperature (PVT) for the 3.3-V LVTTL I/O standard with 24 mA (default case) current drive strength setting and fast slew rate setting. I/O adder delays are measured to calculate the tCO change at worst-case PVT across all I/O standards and current drive strength settings with the default loading shown in Table 4–101 on page 4–62. Timing derating data for additional loading is taken for tCO across worst-case PVT for all I/O standards and drive strength settings. These three pieces of data are used to predict the timing at the output pin. tCO at pin = tOUTCO max for 3.3-V 24 mA LVTTL + I/O Adder + Output Delay Adder for Loading Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook. 1. Simulate the output driver of choice into the generalized test setup using values from Table 4–101 on page 4–62. 2. Record the time to VMEAS. 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS input buffer model or an equivalent capacitance value to represent the load. 4. Record the time to VMEAS. 5. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-input) of the PCB trace. The Quartus II software reports maximum timing with the conditions shown in Table 4–101 on page 4–62 using the proceeding equation. Figure 4–7 on page 4–62 shows the model of the circuit that is represented by the Quartus II output timing. Altera Corporation January 2006 4–61 Stratix Device Handbook, Volume 1 Timing Model Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II VCCIO Single-Ended Outputs VCCIO VTT RUP Output Buffer RT RS OUTPUT VMEAS CL RDN GND GND GND Notes to Figure 4–7: (1) (2) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations. VCCINT is 1.42-V unless otherwise specified. Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2) Notes (1), (2), (3) Measurement Point Loading and Termination I/O Standard RUP RDN RS RT Ω Ω Ω 3.3-V LVTTL – – 2.5-V LVTTL – 1.8-V LVTTL – Ω VCCIO (V) VTT (V) CL (pF) VMEAS 0 – 2.950 2.95 10 1.500 – 0 – 2.370 2.37 10 1.200 – 0 – 1.650 1.65 10 0.880 1.5-V LVTTL – – 0 – 1.400 1.40 10 0.750 3.3-V LVCMOS – – 0 – 2.950 2.95 10 1.500 2.5-V LVCMOS – – 0 – 2.370 2.37 10 1.200 1.8-V LVCMOS – – 0 – 1.650 1.65 10 0.880 1.5-V LVCMOS – – 0 – 1.400 1.40 10 0.750 3.3-V GTL – – 0 25 2.950 1.14 30 0.740 2.5-V GTL – – 0 25 2.370 1.14 30 0.740 3.3-V GTL+ – – 0 25 2.950 1.35 30 0.880 2.5-V GTL+ – – 0 25 2.370 1.35 30 0.880 3.3-V SSTL-3 Class II – – 25 25 2.950 1.25 30 1.250 4–62 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 2 of 2) Notes (1), (2), (3) Measurement Point Loading and Termination I/O Standard RUP RDN RS RT Ω Ω Ω Ω VCCIO (V) VTT (V) CL (pF) VMEAS 3.3-V SSTL-3 Class I – – 25 50 2.950 1.250 30 1.250 2.5-V SSTL-2 Class II – – 25 25 2.370 1.110 30 1.110 2.5-V SSTL-2 Class I – – 25 50 2.370 1.110 30 1.110 1.8-V SSTL-18 Class II – – 25 25 1.650 0.760 30 0.760 1.8-V SSTL-18 Class I – – 25 50 1.650 0.760 30 0.760 1.5-V HSTL Class II – – 0 25 1.400 0.700 20 0.680 1.5-V HSTL Class I – – 0 50 1.400 0.700 20 0.680 1.8-V HSTL Class II – – 0 25 1.650 0.700 20 0.880 1.8-V HSTL Class I – – 0 50 1.650 0.700 20 0.880 3.3-V PCI (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814 3.3-V PCI-X 1.0 (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814 3.3-V Compact PCI (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814 3.3-V AGP 1X (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814 – – 25 50 2.050 1.350 30 1.350 3.3-V CTT Notes to Table 4–101: (1) (2) (3) (4) Input measurement point at internal node is 0.5 × VCCINT. Output measuring point for data is VMEAS. Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the IO buffer. The first value is for output rising edge and the second value is for output falling edge. The hyphen (-) indicates infinite resistance or disconnection. Altera Corporation January 2006 4–63 Stratix Device Handbook, Volume 1 Timing Model Table 4–102 shows the reporting methodology used by the Quartus II software for minimum timing information for output pins. Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 1 of 2) Notes (1), (2), (3) Measurement Point Loading and Termination I/O Standard RUP RDN RS RT Ω Ω Ω Ω VCCIO (V) VTT (V) CL (pF) VMEAS 3.3-V LVTTL – – 0 – 3.600 3.600 10 1.800 2.5-V LVTTL – – 0 – 2.630 2.630 10 1.200 1.8-V LVTTL – – 0 – 1.950 1.950 10 0.880 1.5-V LVTTL – – 0 – 1.600 1.600 10 0.750 3.3-V LVCMOS – – 0 – 3.600 3.600 10 1.800 2.5-V LVCMOS – – 0 – 2.630 2.630 10 1.200 1.8-V LVCMOS – – 0 – 1.950 1.950 10 0.880 1.5-V LVCMOS – – 0 – 1.600 1.600 10 0.750 3.3-V GTL – – 0 25 3.600 1.260 30 0.860 2.5-V GTL – – 0 25 2.630 1.260 30 0.860 3.3-V GTL+ – – 0 25 3.600 1.650 30 1.120 2.5-V GTL+ – – 0 25 2.630 1.650 30 1.120 3.3-V SSTL-3 Class II – – 25 25 3.600 1.750 30 1.750 3.3-V SSTL-3 Class I – – 25 50 3.600 1.750 30 1.750 2.5-V SSTL-2 Class II – – 25 25 2.630 1.390 30 1.390 2.5-V SSTL-2 Class I – – 25 50 2.630 1.390 30 1.390 1.8-V SSTL-18 Class II – – 25 25 1.950 1.040 30 1.040 1.8-V SSTL-18 Class I – – 25 50 1.950 1.040 30 1.040 1.5-V HSTL Class II – – 0 25 1.600 0.800 20 0.900 1.5-V HSTL Class I – – 0 50 1.600 0.800 20 0.900 1.8-V HSTL Class II – – 0 25 1.950 0.900 20 1.000 1.8-V HSTL Class I – – 0 50 1.950 0.900 20 1.000 3.3-V PCI (4) –/25 25/– 0 – 3.600 1.950 10 1.026/2.214 3.3-V PCI-X 1.0 (4) –/25 25/– 0 – 3.600 1.950 10 1.026/2.214 3.3-V Compact PCI (4) –/25 25/– 0 – 3.600 3.600 10 1.026/2.214 3.3-V AGP 1× (4) –/25 25/– 0 – 3.600 3.600 10 1.026/2.214 4–64 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2) Notes (1), (2), (3) Measurement Point Loading and Termination I/O Standard 3.3-V CTT RUP RDN RS RT Ω Ω Ω Ω VCCIO (V) VTT (V) CL (pF) VMEAS – – 25 50 3.600 1.650 30 1.650 Notes to Table 4–102: (1) (2) (3) (4) Input measurement point at internal node is 0.5 × VCCINT. Output measuring point for data is VMEAS. When two values are given, the first is the measurement point on the rising edge and the other is for the falling edge. Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the I/O buffer. The first value is for the output rising edge and the second value is for the output falling edge. The hyphen (-) indicates infinite resistance or disconnection. Figure 4–8 shows the measurement setup for output disable and output enable timing. The TCHZ stands for clock to high Z time delay and is the same as TXZ. The TCLZ stands for clock to low Z (driving) time delay and is the same as TZX. Figure 4–8. Measurement Setup for TXZ and TZX CLK T CHZ 200mV OUT VT =1.5V R =50Ω 200mV T CLZ 200mV C TOTAL=10pF OUT 200mV Altera Corporation January 2006 4–65 Stratix Device Handbook, Volume 1 Timing Model External I/O Delay Parameters External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. All of the timing parameters in this section apply to both flip-chip and wire-bond packages. Tables 4–103 and 4–104 show the input adder delays associated with column and row I/O pins. If an I/O standard is selected other than 3.3-V LVTTL or LVCMOS, add the selected delay to the external tINSU and tINSUPLL I/O parameters shown in Tables 4–54 through 4–96. Table 4–103. Stratix I/O Standard Column Pin Input Delay Adders -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min LVCMOS Max 0 Min Max 0 Min Max 0 Min Max 0 ps 3.3-V LVTTL 0 0 0 0 ps 2.5-V LVTTL 19 19 22 26 ps 1.8-V LVTTL 221 232 266 313 ps 1.5-V LVTTL 352 369 425 500 ps GTL –45 –48 –55 –64 ps GTL+ –75 –79 –91 –107 ps 3.3-V PCI 0 0 0 0 ps 3.3-V PCI-X 1.0 0 0 0 0 ps Compact PCI 0 0 0 0 ps AGP 1× 0 0 0 0 ps AGP 2× 0 0 0 0 ps CTT 120 126 144 170 ps SSTL-3 Class I –162 –171 –196 –231 ps SSTL-3 Class II –162 –171 –196 –231 ps SSTL-2 Class I –202 –213 –244 –287 ps SSTL-2 Class II –202 –213 –244 –287 ps SSTL-18 Class I 78 81 94 110 ps SSTL-18 Class II 78 81 94 110 ps 1.5-V HSTL Class I –76 –80 –92 –108 ps 1.5-V HSTL Class II –76 –80 –92 –108 ps 1.8-V HSTL Class I –52 –55 –63 –74 ps 1.8-V HSTL Class II –52 –55 –63 –74 ps 4–66 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–104. Stratix I/O Standard Row Pin Input Delay Adders -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min Max Min Max Min Max Min Max LVCMOS 0 0 0 0 ps 3.3-V LVTTL 0 0 0 0 ps 2.5-V LVTTL 21 22 25 29 ps 1.8-V LVTTL 181 190 218 257 ps 1.5-V LVTTL 300 315 362 426 ps GTL+ –152 –160 –184 –216 ps CTT –168 –177 –203 –239 ps SSTL-3 Class I –193 –203 –234 –275 ps SSTL-3 Class II –193 –203 –234 –275 ps SSTL-2 Class I –262 –276 –317 –373 ps SSTL-2 Class II –262 –276 –317 –373 ps SSTL-18 Class I –105 –111 –127 –150 ps SSTL-18 Class II 0 0 0 0 ps 1.5-V HSTL Class I –151 –159 –183 –215 ps 1.8-V HSTL Class I –126 –133 –153 –179 ps LVDS –149 –157 –180 –212 ps LVPECL –149 –157 –180 –212 ps 3.3-V PCML –65 –69 –79 –93 ps HyperTransport 77 –81 –93 –110 ps Altera Corporation January 2006 4–67 Stratix Device Handbook, Volume 1 Timing Model Tables 4–105 through 4–108 show the output adder delays associated with column and row I/O pins for both fast and slow slew rates. If an I/O standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with a fast slew rate, add the selected delay to the external tOUTCO, tOUTCOPLL, tXZ, tZX, tXZPLL, and tZXPLL I/O parameters shown in Table 4–55 on page 4–36 through Table 4–96 on page 4–56. Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL Max Min Max Min Max Min Max 2 mA 1,895 1,990 1,990 1,990 ps 4 mA 956 1,004 1,004 1,004 ps 8 mA 189 198 198 198 ps 12 mA 0 0 0 0 ps 24 mA –157 –165 –165 –165 ps 4 mA 1,895 1,990 1,990 1,990 ps 8 mA 1,347 1,414 1,414 1,414 ps 12 mA 636 668 668 668 ps 16 mA 561 589 589 589 ps 24 mA 0 0 0 0 ps 2 mA 2,517 2,643 2,643 2,643 ps 8 mA 834 875 875 875 ps 12 mA 504 529 529 529 ps 16 mA 194 203 203 203 ps 2 mA 1,304 1,369 1,369 1,369 ps 8 mA 960 1,008 1,008 1,008 ps 12 mA 960 1,008 1,008 1,008 ps 2 mA 6,680 7,014 7,014 7,014 ps 4 mA 3,275 3,439 3,439 3,439 ps 8 mA 1,589 1,668 1,668 1,668 ps 16 17 17 17 ps GTL GTL+ 9 9 9 9 ps 3.3-V PCI 50 52 52 52 ps 3.3-V PCI-X 1.0 50 52 52 52 ps Compact PCI 50 52 52 52 ps AGP 1× 50 52 52 52 ps AGP 2× 1,895 1,990 1,990 1,990 ps 4–68 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min Max Min Max Min Max Min Max CTT 973 1,021 1,021 1,021 ps SSTL-3 Class I 719 755 755 755 ps SSTL-3 Class II 146 153 153 153 ps SSTL-2 Class I 678 712 712 712 ps SSTL-2 Class II 223 234 234 234 ps SSTL-18 Class I 1,032 1,083 1,083 1,083 ps SSTL-18 Class II 447 469 469 469 ps 1.5-V HSTL Class I 660 693 693 693 ps 1.5-V HSTL Class II 537 564 564 564 ps 1.8-V HSTL Class I 304 319 319 319 ps 1.8-V HSTL Class II 231 242 242 242 ps Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade (Part 1 of 2) -8 Speed Grade Parameter Unit Min LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL Altera Corporation January 2006 Max Min Max 1,594 Min Max 1,594 Min Max 2 mA 1,518 1,594 ps 4 mA 746 783 783 783 ps 8 mA 96 100 100 100 ps 12 mA 0 0 0 0 ps 4 mA 1,518 1,594 1,594 1,594 ps 8 mA 1,038 1,090 1,090 1,090 ps 12 mA 521 547 547 547 ps 16 mA 414 434 434 434 ps 24 mA 0 0 0 0 ps 2 mA 2,032 2,133 2,133 2,133 ps 8 mA 699 734 734 734 ps 12 mA 374 392 392 392 ps 16 mA 165 173 173 173 ps 2 mA 3,714 3,899 3,899 3,899 ps 8 mA 1,055 1,107 1,107 1,107 ps 12 mA 830 871 871 871 ps 4–69 Stratix Device Handbook, Volume 1 Timing Model Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade (Part 2 of 2) -8 Speed Grade Parameter Unit Min 1.5-V LVTTL Max Min Max Min Max Min Max 2 mA 5,460 5,733 5,733 5,733 ps 4 mA 2,690 2,824 2,824 2,824 ps 8 mA 1,398 1,468 1,468 1,468 ps GTL+ 6 6 6 6 ps CTT 845 887 887 887 ps SSTL-3 Class I 638 670 670 670 ps SSTL-3 Class II 144 151 151 151 ps SSTL-2 Class I 604 634 634 634 ps SSTL-2 Class II 211 221 221 221 ps SSTL-18 Class I 955 1,002 1,002 1,002 ps 1.5-V HSTL Class I 733 769 769 769 ps 1.8-V HSTL Class I 372 390 390 390 ps LVDS –196 –206 –206 –206 ps LVPECL –148 –156 –156 –156 ps PCML –147 –155 –155 –155 ps HyperTransport technology –93 –98 –98 –98 ps Note to Table 4–103 through 4–106: (1) These parameters are only available on row I/O pins. Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min LVCMOS Max Min Max Min Max Min Max 2 mA 1,822 1,913 1,913 1,913 ps 4 mA 684 718 718 718 ps 8 mA 233 245 245 245 ps 12 mA 1 1 1 1 ps 24 mA –608 –638 –638 –638 ps 4–70 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Unit Min 3.3-V LVTTL Max Min Max Min Max Min Max 4 mA 1,822 1,913 1,913 1,913 ps 8 mA 1,586 1,665 1,665 1,665 ps 12 mA 686 720 720 720 ps 16 mA 630 662 662 662 ps 24 mA 0 0 0 0 ps 2 mA 2,925 3,071 3,071 3,071 ps 2.5-V LVTTL 8 mA 1,496 1,571 1,571 1,571 ps 12 mA 937 984 984 984 ps 16 mA 1,003 1,053 1,053 1,053 ps 2 mA 7,101 7,456 7,456 7,456 ps 1.8-V LVTTL 8 mA 3,620 3,801 3,801 3,801 ps 12 mA 3,109 3,265 3,265 3,265 ps 1.5-V LVTTL 2 mA 10,941 11,488 11,488 11,488 ps 4 mA 7,431 7,803 7,803 7,803 ps 8 mA 5,990 6,290 6,290 6,290 ps GTL –959 –1,007 –1,007 –1,007 ps GTL+ –438 –460 –460 –460 ps 3.3-V PCI 660 693 693 693 ps 3.3-V PCI-X 1.0 660 693 693 693 ps Compact PCI 660 693 693 693 ps AGP 1× 660 693 693 693 ps AGP 2× 288 303 303 303 ps CTT 631 663 663 663 ps SSTL-3 Class I 301 316 316 316 ps SSTL-3 Class II –359 –377 –377 –377 ps SSTL-2 Class I 523 549 549 549 ps SSTL-2 Class II –49 –51 –51 –51 ps SSTL-18 Class I 2,315 2,431 2,431 2,431 ps SSTL-18 Class II 723 759 759 759 ps 1.5-V HSTL Class I 1,687 1,771 1,771 1,771 ps 1.5-V HSTL Class II 1,095 1,150 1,150 1,150 ps 1.8-V HSTL Class I 599 629 678 744 ps 1.8-V HSTL Class II 87 102 102 102 ps Altera Corporation January 2006 4–71 Stratix Device Handbook, Volume 1 Timing Model Table 4–108. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade I/O Standard Unit Min LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL Max Min Max Min Max Min Max 2 mA 1,571 1,650 1,650 1,650 ps 4 mA 594 624 624 624 ps 8 mA 208 218 218 218 ps 12 mA 0 0 0 0 ps 4 mA 1,571 1,650 1,650 1,650 ps 8 mA 1,393 1,463 1,463 1,463 ps 12 mA 596 626 626 626 ps 16 mA 562 590 590 590 ps 2 mA 2,562 2,690 2,690 2,690 ps 8 mA 1,343 1,410 1,410 1,410 ps 12 mA 864 907 907 907 ps 16 mA 945 992 992 992 ps 2 mA 6,306 6,621 6,621 6,621 ps 8 mA 3,369 3,538 3,538 3,538 ps 12 mA 2,932 3,079 3,079 3,079 ps 2 mA 9,759 10,247 10,247 10,247 ps 4 mA 6,830 7,172 7,172 7,172 ps 8 mA 5,699 5,984 5,984 5,984 ps GTL+ –333 –350 –350 –350 ps CTT 591 621 621 621 ps 1.5-V LVTTL SSTL-3 Class I 267 280 280 280 ps SSTL-3 Class II –346 –363 –363 –363 ps SSTL-2 Class I 481 505 505 505 ps SSTL-2 Class II –58 –61 –61 –61 ps SSTL-18 Class I 2,207 2,317 2,317 2,317 ps 1.5-V HSTL Class I 1,966 2,064 2,064‘ 2,064 ps 1.8-V HSTL Class I 1,208 1,268 1,460 1,720 ps 4–72 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Tables 4–109 and 4–110 show the adder delays for the column and row IOE programmable delays. These delays are controlled with the Quartus II software logic options listed in the Parameter column. Table 4–109. Stratix IOE Programmable Delays on Column Pins Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Setting Unit Min Decrease input delay to internal cells Max Min Max Min Max Min Max Off 3,970 4,367 5,022 5,908 ps Small 3,390 3,729 4,288 5,045 ps Medium 2,810 3,091 3,554 4,181 ps 224 235 270 318 ps Large On 224 235 270 318 ps Decrease input delay to input register Off 3,900 4,290 4,933 5,804 ps On 0 0 0 0 ps Decrease input delay to output register Off 1,240 1,364 1,568 1,845 ps On 0 0 0 0 ps Increase delay to output pin Off 0 0 0 0 ps On 397 417 417 417 ps Increase delay to output enable pin Off 0 0 0 0 ps On 338 372 427 503 ps Increase output clock enable delay Off 0 0 0 0 ps Increase input clock enable delay Increase output enable clock enable delay Increase tZX delay to output pin Altera Corporation January 2006 Small 540 594 683 804 ps Large 1,016 1,118 1,285 1,512 ps On 1,016 1,118 1,285 1,512 ps Off 0 0 0 0 ps Small 540 594 683 804 ps Large 1,016 1,118 1,285 1,512 ps On 1,016 1,118 1,285 1,512 ps Off 0 0 0 0 ps Small 540 594 683 804 ps Large 1,016 1,118 1,285 1,512 ps On 1,016 1,118 1,285 1,512 ps Off 0 0 0 0 ps On 2,199 2,309 2,309 2,309 ps 4–73 Stratix Device Handbook, Volume 1 Timing Model Table 4–110. Stratix IOE Programmable Delays on Row Pins Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter Setting Unit Min Decrease input delay to internal cells Max Min Max Min Max Min Max Off 3,970 4,367 5,022 5,908 ps Small 3,390 3,729 4,288 5,045 ps Medium 2,810 3,091 3,554 4,181 ps 173 181 208 245 ps Large On 173 181 208 245 ps Decrease input delay to input register Off 3,900 4,290 4,933 5,804 ps On 0 0 0 0 ps Decrease input delay to output register Off 1,240 1,364 1,568 1,845 ps On 0 0 0 0 ps Increase delay to output pin Off 0 0 0 0 ps On 397 417 417 417 ps Increase delay to output enable pin Off 0 0 0 0 ps On 348 383 441 518 ps Increase output clock enable delay Off 0 0 0 0 ps Small 180 198 227 267 ps Large 260 286 328 386 ps On 260 286 328 386 ps Off 0 0 0 0 ps Small 180 198 227 267 ps Large 260 286 328 386 ps On 260 286 328 386 ps Off 0 0 0 0 ps Increase input clock enable delay Increase output enable clock enable delay Increase tZX delay to output pin Small 540 594 683 804 ps Large 1,016 1,118 1,285 1,512 ps On 1,016 1,118 1,285 1,512 ps Off 0 0 0 0 ps On 1,993 2,092 2,092 2,092 ps Note to Table 4–109 and Table 4–110: (1) The delay chain delays vary for different device densities. These timing values only apply to EP1S30 and EP1S40 devices. Reference the timing information reported by the Quartus II software for other devices. 4–74 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics The scaling factors for column output pin timing in Tables 4–111 to 4–113 are shown in units of time per pF unit of capacitance (ps/pF). Add this delay to the tCO or combinatorial timing path for output or bidirectional pins in addition to the I/O adder delays shown in Tables 4–103 through 4–108 and the IOE programmable delays in Tables 4–109 and 4–110. Table 4–111. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers Note (1) Conditions Parameter Drive Strength Output Pin Adder Delay (ps/pF) Value 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL LVCMOS 24mA 15 – – - 8 16mA 25 18 – – – 12mA 30 25 25 – 15 8mA 50 35 40 35 20 4mA 60 – – 80 30 2mA – 75 120 160 60 Note to Table 4–111: (1) The timing information in this table is preliminary. Table 4–112. Output Delay Adder for Loading on SSTL/HSTL Output Buffers Note (1) Output Pin Adder Delay (ps/pF) Conditions Class I Class II SSTL-3 SSTL-2 SSTL-1.8 1.5-V HSTL 25 25 25 25 25 20 25 20 Note to Table 4–112: (1) The timing information in this table is preliminary. Table 4–113. Output Delay Adder for Loading on GTL+/GTL/CTT/PCI Output Buffers Conditions Note (1) Output Pin Adder Delay (ps/pF) Parameter Value GTL+ GTL CTT PCI AGP VCCIO Voltage Level 3.3V 18 18 25 20 20 2.5V 15 18 - - - Note to Table 4–113: (1) The timing information in this table is preliminary. Altera Corporation January 2006 4–75 Stratix Device Handbook, Volume 1 Timing Model Maximum Input & Output Clock Rates Tables 4–114 through 4–119 show the maximum input clock rate for column and row pins in Stratix devices. Table 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Flip-Chip Packages (Part 1 of 2) I/O Standard -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVTTL 422 422 390 390 MHz 2.5 V 422 422 390 390 MHz 1.8 V 422 422 390 390 MHz 1.5 V 422 422 390 390 MHz LVCMOS 422 422 390 390 MHz GTL 300 250 200 200 MHz GTL+ 300 250 200 200 MHz SSTL-3 Class I 400 350 300 300 MHz SSTL-3 Class II 400 350 300 300 MHz SSTL-2 Class I 400 350 300 300 MHz SSTL-2 Class II 400 350 300 300 MHz SSTL-18 Class I 400 350 300 300 MHz SSTL-18 Class II 400 350 300 300 MHz 1.5-V HSTL Class I 400 350 300 300 MHz 1.5-V HSTL Class II 400 350 300 300 MHz 1.8-V HSTL Class I 400 350 300 300 MHz 1.8-V HSTL Class II 400 350 300 300 MHz 3.3-V PCI 422 422 390 390 MHz 3.3-V PCI-X 1.0 422 422 390 390 MHz Compact PCI 422 422 390 390 MHz AGP 1× 422 422 390 390 MHz AGP 2× 422 422 390 390 MHz CTT 300 250 200 200 MHz Differential 1.5-V HSTL C1 400 350 300 300 MHz LVPECL (1) 645 645 622 622 MHz PCML (1) 300 275 275 275 MHz 4–76 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Flip-Chip Packages (Part 2 of 2) I/O Standard -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVDS (1) 645 645 622 622 MHz HyperTransport technology (1) 500 500 450 450 MHz Table 4–115. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Flip-Chip Packages I/O Standard Altera Corporation January 2006 -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVTTL 422 422 390 390 MHz 2.5 V 422 422 390 390 MHz 1.8 V 422 422 390 390 MHz 1.5 V 422 422 390 390 MHz LVCMOS 422 422 390 390 MHz GTL+ 300 250 200 200 MHz SSTL-3 Class I 400 350 300 300 MHz SSTL-3 Class II 400 350 300 300 MHz SSTL-2 Class I 400 350 300 300 MHz SSTL-2 Class II 400 350 300 300 MHz SSTL-18 Class I 400 350 300 300 MHz SSTL-18 Class II 400 350 300 300 MHz 1.5-V HSTL Class I 400 350 300 300 MHz 1.8-V HSTL Class I 400 350 300 300 MHz CTT 300 250 200 200 MHz Differential 1.5-V HSTL C1 400 350 300 300 MHz LVPECL (1) 717 717 640 640 MHz PCML (1) 400 375 350 350 MHz LVDS (1) 717 717 640 640 MHz HyperTransport technology (1) 717 717 640 640 MHz 4–77 Stratix Device Handbook, Volume 1 Timing Model Table 4–116. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Flip-Chip Packages I/O Standard -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVTTL 422 422 390 390 MHz 2.5 V 422 422 390 390 MHz 1.8 V 422 422 390 390 MHz 1.5 V 422 422 390 390 MHz LVCMOS 422 422 390 390 MHz GTL+ 300 250 200 200 MHz SSTL-3 Class I 400 350 300 300 MHz SSTL-3 Class II 400 350 300 300 MHz SSTL-2 Class I 400 350 300 300 MHz SSTL-2 Class II 400 350 300 300 MHz SSTL-18 Class I 400 350 300 300 MHz SSTL-18 Class II 400 350 300 300 MHz 1.5-V HSTL Class I 400 350 300 300 MHz 1.8-V HSTL Class I 400 350 300 300 MHz CTT 300 250 200 200 MHz Differential 1.5-V HSTL C1 400 350 300 300 MHz LVPECL (1) 645 645 640 640 MHz PCML (1) 300 275 275 275 MHz LVDS (1) 645 645 640 640 MHz HyperTransport technology (1) 500 500 450 450 MHz Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVTTL 422 390 390 MHz 2.5 V 422 390 390 MHz 1.8 V 422 390 390 MHz 1.5 V 422 390 390 MHz LVCMOS 422 390 390 MHz GTL 250 200 200 MHz 4–78 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit GTL+ 250 200 200 MHz SSTL-3 Class I 300 250 250 MHz SSTL-3 Class II 300 250 250 MHz SSTL-2 Class I 300 250 250 MHz SSTL-2 Class II 300 250 250 MHz SSTL-18 Class I 300 250 250 MHz SSTL-18 Class II 300 250 250 MHz 1.5-V HSTL Class I 300 180 180 MHz 1.5-V HSTL Class II 300 180 180 MHz 1.8-V HSTL Class I 300 180 180 MHz 1.8-V HSTL Class II 300 180 180 MHz 3.3-V PCI 422 390 390 MHz 3.3-V PCI-X 1.0 422 390 390 MHz Compact PCI 422 390 390 MHz AGP 1× 422 390 390 MHz AGP 2× 422 390 390 MHz CTT 250 180 180 MHz Differential 1.5-V HSTL C1 300 180 180 MHz LVPECL (1) 422 400 400 MHz PCML (1) 215 200 200 MHz LVDS (1) 422 400 400 MHz HyperTransport technology (1) 422 400 400 MHz Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard Altera Corporation January 2006 -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVTTL 422 390 390 MHz 2.5 V 422 390 390 MHz 1.8 V 422 390 390 MHz 1.5 V 422 390 390 MHz 4–79 Stratix Device Handbook, Volume 1 Timing Model Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVCMOS 422 390 390 MHz GTL+ 250 200 200 MHz SSTL-3 Class I 350 300 300 MHz SSTL-3 Class II 350 300 300 MHz SSTL-2 Class I 350 300 300 MHz SSTL-2 Class II 350 300 300 MHz SSTL-18 Class I 350 300 300 MHz SSTL-18 Class II 350 300 300 MHz 1.5-V HSTL Class I 350 300 300 MHz 1.8-V HSTL Class I 350 300 300 MHz CTT 250 200 200 MHz Differential 1.5-V HSTL C1 350 300 300 MHz LVPECL (1) 717 640 640 MHz PCML (1) 375 350 350 MHz LVDS (1) 717 640 640 MHz HyperTransport technology (1) 717 640 640 MHz Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVTTL 422 390 390 MHz 2.5 V 422 390 390 MHz 1.8 V 422 390 390 MHz 1.5 V 422 390 390 MHz LVCMOS 422 390 390 MHz GTL+ 250 200 200 MHz SSTL-3 Class I 350 300 300 MHz SSTL-3 Class II 350 300 300 MHz SSTL-2 Class I 350 300 300 MHz SSTL-2 Class II 350 300 300 MHz 4–80 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit SSTL-18 Class I 350 300 300 MHz SSTL-18 Class II 350 300 300 MHz 1.5-V HSTL Class I 350 300 300 MHz 1.8-V HSTL Class I 350 300 300 MHz CTT 250 200 200 MHz Differential 1.5-V HSTL C1 350 300 300 MHz LVPECL (1) 645 622 622 MHz PCML (1) 275 275 275 MHz LVDS (1) 645 622 622 MHz HyperTransport technology (1) 500 450 450 MHz Note to Tables 4–114 through 4–119: (1) These parameters are only available on row I/O pins. Tables 4–120 through 4–123 show the maximum output clock rate for column and row pins in Stratix devices. Table 4–120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages (Part 1 of 2) I/O Standard Altera Corporation January 2006 -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVTTL 350 300 250 250 MHz 2.5 V 350 300 300 300 MHz 1.8 V 250 250 250 250 MHz 1.5 V 225 200 200 200 MHz LVCMOS 350 300 250 250 MHz GTL 200 167 125 125 MHz GTL+ 200 167 125 125 MHz SSTL-3 Class I 200 167 167 133 MHz SSTL-3 Class II 200 167 167 133 MHz SSTL-2 Class I (3) 200 200 167 167 MHz SSTL-2 Class I (4) 200 200 167 167 MHz SSTL-2 Class I (5) 150 134 134 134 MHz 4–81 Stratix Device Handbook, Volume 1 Timing Model Table 4–120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages (Part 2 of 2) I/O Standard -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit SSTL-2 Class II (3) 200 200 167 167 MHz SSTL-2 Class II (4) 200 200 167 167 MHz SSTL-2 Class II (5) 150 134 134 134 MHz SSTL-18 Class I 150 133 133 133 MHz SSTL-18 Class II 150 133 133 133 MHz 1.5-V HSTL Class I 250 225 200 200 MHz 1.5-V HSTL Class II 225 200 200 200 MHz 1.8-V HSTL Class I 250 225 200 200 MHz 1.8-V HSTL Class II 225 200 200 200 MHz 3.3-V PCI 350 300 250 250 MHz 3.3-V PCI-X 1.0 350 300 250 250 MHz Compact PCI 350 300 250 250 MHz AGP 1× 350 300 250 250 MHz AGP 2× 350 300 250 250 MHz CTT 200 200 200 200 MHz Differential 1.5-V HSTL C1 225 200 200 200 MHz Differential 1.8-V HSTL Class I 250 225 200 200 MHz Differential 1.8-V HSTL Class II 225 200 200 200 MHz Differential SSTL-2 (6) 200 200 167 167 MHz LVPECL (2) 500 500 500 500 MHz PCML (2) 350 350 350 350 MHz LVDS (2) 500 500 500 500 MHz HyperTransport technology (2) 350 350 350 350 MHz 4–82 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–121. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Flip-Chip Packages I/O Standard Altera Corporation January 2006 -5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade Unit LVTTL 400 350 300 300 MHz 2.5 V 400 350 300 300 MHz 1.8 V 400 350 300 300 MHz 1.5 V 350 300 300 300 MHz LVCMOS 400 350 300 300 MHz GTL 200 167 125 125 MHz GTL+ 200 167 125 125 MHz SSTL-3 Class I 167 150 133 133 MHz SSTL-3 Class II 167 150 133 133 MHz SSTL-2 Class I 150 133 133 133 MHz SSTL-2 Class II 150 133 133 133 MHz SSTL-18 Class I 150 133 133 133 MHz SSTL-18 Class II 150 133 133 133 MHz 1.5-V HSTL Class I 250 225 200 200 MHz 1.5-V HSTL Class II 225 225 200 200 MHz 1.8-V HSTL Class I 250 225 200 200 MHz 1.8-V HSTL Class II 225 225 200 200 MHz 3.3-V PCI 250 225 200 200 MHz 3.3-V PCI-X 1.0 225 225 200 200 MHz Compact PCI 400 350 300 300 MHz AGP 1× 400 350 300 300 MHz AGP 2× 400 350 300 300 MHz CTT 300 250 200 200 MHz LVPECL (2) 717 717 500 500 MHz PCML (2) 420 420 420 420 MHz LVDS (2) 717 717 500 500 MHz HyperTransport technology (2) 420 420 420 420 MHz 4–83 Stratix Device Handbook, Volume 1 Timing Model Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVTTL 175 150 150 MHz 2.5 V 175 150 150 MHz 1.8 V 175 150 150 MHz 1.5 V 175 150 150 MHz LVCMOS 175 150 150 MHz GTL 125 100 100 MHz GTL+ 125 100 100 MHz SSTL-3 Class I 110 90 90 MHz SSTL-3 Class II 133 125 125 MHz SSTL-2 Class I 166 133 133 MHz SSTL-2 Class II 133 100 100 MHz SSTL-18 Class I 110 100 100 MHz SSTL-18 Class II 110 100 100 MHz 1.5-V HSTL Class I 167 167 167 MHz 1.5-V HSTL Class II 167 133 133 MHz 1.8-V HSTL Class I 167 167 167 MHz 1.8-V HSTL Class II 167 133 133 MHz 3.3-V PCI 167 167 167 MHz 3.3-V PCI-X 1.0 167 133 133 MHz Compact PCI 175 150 150 MHz AGP 1× 175 150 150 MHz AGP 2× 175 150 150 MHz CTT 125 100 100 MHz Differential 1.5-V HSTL C1 167 133 133 MHz Differential 1.8-V HSTL Class I 167 167 167 MHz Differential 1.8-V HSTL Class II 167 133 133 MHz Differential SSTL-2 (1) 110 100 100 MHz LVPECL (2) 311 275 275 MHz PCML (2) 250 200 200 MHz 4–84 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVDS (2) 311 275 275 MHz HyperTransport technology (2) 311 275 275 MHz Table 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard Altera Corporation January 2006 -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVTTL 200 175 175 MHz 2.5 V 200 175 175 MHz 1.8 V 200 175 175 MHz 1.5 V 200 175 175 MHz LVCMOS 200 175 175 MHz GTL 125 100 100 MHz GTL+ 125 100 100 MHz SSTL-3 Class I 110 90 90 MHz SSTL-3 Class II 150 133 133 MHz SSTL-2 Class I 90 80 80 MHz SSTL-2 Class II 110 100 100 MHz SSTL-18 Class I 110 100 100 MHz SSTL-18 Class II 110 100 100 MHz 1.5-V HSTL Class I 225 200 200 MHz 1.5-V HSTL Class II 200 167 167 MHz 1.8-V HSTL Class I 225 200 200 MHz 1.8-V HSTL Class II 200 167 167 MHz 3.3-V PCI 200 175 175 MHz 3.3-V PCI-X 1.0 200 175 175 MHz Compact PCI 200 175 175 MHz AGP 1× 200 175 175 MHz AGP 2× 200 175 175 MHz CTT 125 100 100 MHz LVPECL (2) 311 270 270 MHz PCML (2) 400 311 311 MHz 4–85 Stratix Device Handbook, Volume 1 Timing Model Table 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard -6 Speed -7 Speed -8 Speed Grade Grade Grade Unit LVDS (2) 400 311 311 MHz HyperTransport technology (2) 420 400 400 MHz Notes to Tables 4–120 through 4–123: (1) (2) (3) Differential SSTL-2 outputs are only available on column clock pins. These parameters are only available on row I/O pins. SSTL-2 in maximum drive strength condition. See Table 4–101 on page 4–62 for more information on exact loading conditions for each I/O standard. (4) (5) (6) SSTL-2 in minimum drive strength with 10pF output load condition. SSTL-2 in minimum drive strength with > 10pF output load condition. Differential SSTL-2 outputs are only supported on column clock pins. 4–86 Stratix Device Handbook, Volume 1 ≤ Altera Corporation January 2006 DC & Switching Characteristics High-Speed I/O Specification Table 4–124 provides high-speed timing specifications definitions. Table 4–124. High-Speed Timing Specifications & Terminology High-Speed Timing Specification Terminology tC High-speed receiver/transmitter input and output clock period. fHSCLK High-speed receiver/transmitter input and output clock frequency. tRISE Low-to-high transmission time. tFALL High-to-low transmission time. Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = tC/w). fHSDR Maximum LVDS data transfer rate (fHSDR = 1/TUI). Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. Sampling window (SW) The period of time during which the data must be valid to be captured correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) – tSW (min). Input jitter (peak-to-peak) Peak-to-peak input jitter on high-speed PLLs. Output jitter (peak-to-peak) Peak-to-peak output jitter on high-speed PLLs. tDUTY Duty cycle on high-speed transmitter output clock. tLOCK Lock time for high-speed transmitter and receiver PLLs. J Deserialization factor (width of internal data bus). W PLL multiplication factor. Altera Corporation January 2006 4–87 Stratix Device Handbook, Volume 1 Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 4) Notes (1), (2) -5 Speed Grade Symbol fHSDR Device operation (LVDS, LVPECL, HyperTransport technology) -7 Speed Grade -8 Speed Grade Unit Min fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology) fHSCLK = fHSDR / W -6 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max Min Typ Max W = 4 to 30 (Serdes used) 10 210 10 210 10 156 10 115.5 MHz W = 2 (Serdes bypass) 50 231 50 231 50 231 50 231 MHz W = 2 (Serdes used) 150 420 150 420 150 312 150 231 MHz W = 1 (Serdes bypass) 100 462 100 462 100 462 100 462 MHz W = 1 (Serdes used) 300 717 300 717 300 624 300 462 MHz J = 10 300 840 300 840 300 640 300 462 Mbps J=8 300 840 300 840 300 640 300 462 Mbps J=7 300 840 300 840 300 640 300 462 Mbps J=4 300 840 300 840 300 640 300 462 Mbps J=2 100 462 100 462 100 640 100 462 Mbps J = 1 (LVDS and LVPECL only) 100 462 100 462 100 640 100 462 Mbps High-Speed I/O Specification 4–88 Stratix Device Handbook, Volume 1 Tables 4–125 and 4–126 show the high-speed I/O timing for Stratix devices. Altera Corporation January 2006 -5 Speed Grade Symbol fHSDR Device operation (PCML) 4–89 Stratix Device Handbook, Volume 1 TCCS -7 Speed Grade -8 Speed Grade Unit Min fHSCLK (Clock frequency) (PCML) fHSCLK = fHSDR / W -6 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max Min Typ Max W = 4 to 30 (Serdes used) 10 100 10 100 10 77.75 10 77.75 MHz W = 2 (Serdes bypass) 50 200 50 200 50 150 50 150 MHz W = 2 (Serdes used) 150 200 150 200 150 155.5 150 155.5 MHz W = 1 (Serdes bypass) 100 250 100 250 100 200 100 200 MHz W = 1 (Serdes used) 300 400 300 400 300 311 300 311 MHz J = 10 300 400 300 400 300 311 300 311 Mbps J=8 300 400 300 400 300 311 300 311 Mbps J=7 300 400 300 400 300 311 300 311 Mbps J=4 300 400 300 400 300 311 300 311 Mbps J=2 100 400 100 400 100 300 100 300 Mbps J=1 100 250 100 250 100 200 100 200 Mbps 300 ps All 200 200 300 High-Speed I/O Specification Altera Corporation January 2006 Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 4) Notes (1), (2) -5 Speed Grade Symbol -7 Speed Grade -8 Speed Grade Unit Min SW -6 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max Min Typ Max PCML (J = 4, 7, 8, 10) 750 750 800 800 ps PCML (J = 2) 900 900 1,200 1,200 ps PCML (J = 1) 1,500 1,500 1,700 1,700 ps LVDS and LVPECL (J = 1) 500 500 550 550 ps LVDS, LVPECL, HyperTransport technology (J = 2 through 10) 440 440 500 500 ps Altera Corporation January 2006 Input jitter tolerance (peak-to-peak) All 250 250 250 250 ps Output jitter (peak-to-peak) All 160 160 200 200 ps Output tRISE LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 120 170 200 120 170 200 ps LVPECL 90 130 150 90 130 150 100 135 150 100 135 150 ps PCML 80 110 135 80 110 135 80 110 135 80 110 135 ps LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 110 170 200 110 170 200 ps LVPECL 90 130 160 90 130 160 100 135 160 100 135 160 ps PCML 105 140 175 105 140 175 110 145 175 110 145 175 ps Output tFALL High-Speed I/O Specification 4–90 Stratix Device Handbook, Volume 1 Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 4) Notes (1), (2) -5 Speed Grade Symbol tDUTY LVDS (J = 2 through 10) LVDS (J =1) and LVPECL, PCML, HyperTransport technology tLOCK -7 Speed Grade -8 Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % 45 50 55 45 50 55 45 50 55 45 50 55 % 100 μs All Notes to Table 4–125: (1) (2) -6 Speed Grade Conditions When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed. 100 100 100 High-Speed I/O Specification Altera Corporation January 2006 Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 4 of 4) Notes (1), (2) 4–91 Stratix Device Handbook, Volume 1 -6 Speed Grade Symbol fHSCLK (Clock frequency) (LVDS,LVPECL, HyperTransport technology) fHSCLK = fHSDR / W W = 4 to 30 (Serdes used) fHSDR Device operation, (LVDS,LVPECL, HyperTransport technology) Device operation, fH S D R (PCML) Altera Corporation January 2006 TCCS -8 Speed Grade Unit Min fH S C L K (Clock frequency) (PCML) fHSCLK = fHSDR / W -7 Speed Grade Conditions 10 Typ Max Min 156 10 Typ Max Min 115.5 10 Typ Max 115.5 MHz W = 2 (Serdes bypass) 50 231 50 231 50 231 MHz W = 2 (Serdes used) 150 312 150 231 150 231 MHz W = 1 (Serdes bypass) 100 311 100 270 100 270 MHz W = 1 (Serdes used) 300 624 300 462 300 462 MHz J = 10 300 624 300 462 300 462 Mbps J=8 300 624 300 462 300 462 Mbps J=7 300 624 300 462 300 462 Mbps J=4 300 624 300 462 300 462 Mbps J=2 100 462 100 462 100 462 Mbps J = 1 (LVDS and LVPECL only) 100 311 100 270 100 270 Mbps W = 4 to 30 (Serdes used) 10 77.75 W = 2 (Serdes bypass) 50 150 W = 2 (Serdes used) 150 155.5 MHz 50 77.5 50 77.5 MHz MHz W = 1 (Serdes bypass) 100 200 W = 1 (Serdes used) 300 311 MHz J = 10 300 311 Mbps J=8 300 311 Mbps J=7 300 311 Mbps J=4 300 311 Mbps J=2 100 300 100 155 100 155 Mbps J=1 100 200 100 155 100 155 Mbps 400 ps All 400 100 155 400 100 155 MHz High-Speed I/O Specification 4–92 Stratix Device Handbook, Volume 1 Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2) -6 Speed Grade Symbol -8 Speed Grade Unit Min SW -7 Speed Grade Conditions PCML (J = 4, 7, 8, 10) only Typ Max Min Typ Max Min Typ Max 800 800 800 ps PCML (J = 2) only 1,200 1,200 1,200 ps PCML (J = 1) only 1,700 1,700 1,700 ps LVDS and LVPECL (J = 1) only 550 550 550 ps LVDS, LVPECL, HyperTransport technology (J = 2 through 10) only 500 500 500 ps Input jitter tolerance (peak-to-peak) All 250 250 250 ps Output jitter (peak-topeak) All 200 200 200 ps Output tR I S E LVDS 120 ps 4–93 Stratix Device Handbook, Volume 1 Output tFA L L tD U T Y 110 120 80 110 120 80 110 HyperTransport technology 120 170 200 120 170 200 120 170 200 ps LVPECL 100 135 150 100 135 150 100 135 150 ps PCML 80 110 135 80 110 135 80 110 135 ps LVDS 80 110 120 80 110 120 80 110 120 ps HyperTransport 110 170 200 110 170 200 110 170 200 ps LVPECL 100 135 160 100 135 160 100 135 160 ps PCML 110 145 175 110 145 175 110 145 175 ps LVDS (J = 2 through10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % 45 50 55 45 50 55 45 50 55 % 100 μs LVDS (J =1) and LVPECL, PCML, HyperTransport technology tL O C K 80 All 100 100 High-Speed I/O Specification Altera Corporation January 2006 Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 2) PLL Specifications PLL Specifications Tables 4–127 through 4–129 describe the Stratix device enhanced PLL specifications. Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2) Symbol Parameter Min Typ Max Unit 3 (1), (2) 684 MHz 3 420 MHz fIN Input clock frequency fINPFD Input frequency to PFD fINDUTY Input clock duty cycle 40 60 % fEINDUTY External feedback clock input duty cycle 40 60 % tINJITTER Input clock period jitter ±200 (3) ps tEINJITTER External feedback clock period jitter ±200 (3) ps tFCOMP External feedback clock compensation time (4) 6 ns fOUT Output frequency for internal global or regional clock 0.3 500 MHz fOUT_EXT Output frequency for external clock (3) 0.3 526 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 55 % tJITTER Period jitter for external clock output (6) ±100 ps for >200-MHz outclk ±20 mUI for 200-MHz outclk ±20 mUI for 200-MHz outclk ±20 mUI for 200-MHz outclk ±20 mUI for 200 MHz. See the Stratix FPGA Errata Sheet for more information on the PLL. Altera Corporation January 2006 4–99 Stratix Device Handbook, Volume 1 PLL Specifications Tables 4–131 through 4–133 describe the Stratix device fast PLL specifications. Table 4–131. Fast PLL Specifications for -5 & -6 Speed Grade Devices Symbol Parameter Min Max Unit fIN CLKIN frequency (1), (2), (3) 10 717 MHz fINPFD Input frequency to PFD 10 500 MHz fOUT Output frequency for internal global or regional clock (3) 9.375 420 MHz fOUT_DIFFIO Output frequency for external clock driven out on a differential I/O data channel (2) (5) (5) fVCO VCO operating frequency 300 1,000 MHz tINDUTY CLKIN duty cycle 40 60 % ±200 ps 55 % (5) ps tINJITTER Period jitter for CLKIN pin tDUTY Duty cycle for DFFIO 1× CLKOUT pin (6) tJITTER Period jitter for DIFFIO clock out (6) tLOCK Time required for PLL to acquire lock 10 100 μs m Multiplication factors for m counter (6) 1 32 Integer l0, l1, g0 Multiplication factors for l0, l1, and g0 counter (7), (8) 1 32 Integer tARESET Minimum pulse width on areset signal 10 45 ns Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 1 of 2) Symbol Parameter Min Max Unit fIN CLKIN frequency (1), (3) 10 640 MHz fINPFD Input frequency to PFD 10 500 MHz fOUT Output frequency for internal global or regional clock (4) 9.375 420 MHz fOUT_DIFFIO Output frequency for external clock driven out on a differential I/O data channel (5) (5) MHz fVCO VCO operating frequency 300 700 MHz tINDUTY CLKIN duty cycle 40 60 % tINJITTER Period jitter for CLKIN pin ±200 ps tDUTY Duty cycle for DFFIO 1× CLKOUT pin (6) 55 % 4–100 Stratix Device Handbook, Volume 1 45 Altera Corporation January 2006 DC & Switching Characteristics Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2) Symbol Parameter tJITTER Period jitter for DIFFIO clock out (6) tLOCK Time required for PLL to acquire lock Min 10 Max Unit (5) ps 100 μs m Multiplication factors for m counter (7) 1 32 Integer l0, l1, g0 Multiplication factors for l0, l1, and g0 counter (7), (8) 1 32 Integer tARESET Minimum pulse width on areset signal 10 ns Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2) Symbol Parameter fIN CLKIN frequency (1), (3) fINPFD Input frequency to PFD fOUT Output frequency for internal global or regional clock (4) fOUT_DIFFIO Min Max Unit 10 460 MHz 10 500 MHz 9.375 420 MHz Output frequency for external clock driven out on a differential I/O data channel (5) (5) MHz fVCO VCO operating frequency 300 700 MHz tINDUTY CLKIN duty cycle 40 60 % tINJITTER Period jitter for CLKIN pin ±200 ps tDUTY Duty cycle for DFFIO 1× CLKOUT pin (6) 45 55 % tJITTER Period jitter for DIFFIO clock out (6) (5) ps tLOCK Time required for PLL to acquire lock 10 100 μs m Multiplication factors for m counter (7) 1 32 Integer l0, l1, g0 Multiplication factors for l0, l1, and g0 counter (7), (8) 1 32 Integer Altera Corporation January 2006 4–101 Stratix Device Handbook, Volume 1 DLL Specifications Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2) Symbol tARESET Parameter Min Minimum pulse width on areset signal Max Unit 10 ns Notes to Tables 4–131 through 4–133: (1) (2) See “Maximum Input & Output Clock Rates” on page 4–76. PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output. (3) Use this equation (fO U T = fI N * ml(n × post-scale counter)) in conjunction with the specified fI N P F D and fV C O ranges to determine the allowed PLL settings. When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor of 4). (4) (5) (6) (7) (8) Refer to the section “High-Speed I/O Specification” on page 4–87 for more information. This parameter is for high-speed differential I/O mode only. These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum of 16. High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10. DLL Specifications Table 4–134 reports the jitter for the DLL in the DQS phase shift reference circuit. Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit Frequency (MHz) f DLL Jitter (ps) 197 to 200 ± 100 160 to 196 ± 300 100 to 159 ± 500 For more information on DLL jitter, see the DDR SRAM section in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1. Table 4–135 lists the Stratix DLL low frequency limit for full phase shift across all PVT conditions. The Stratix DLL can be used below these frequencies, but it will not achieve the full phase shift requested across all 4–102 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 DC & Switching Characteristics process and operating conditions. Run the timing analyzer in the Quartus II software at the fast and slow operating conditions to see the phase shift range that is achieved below these frequencies. Table 4–135. Stratix DLL Low Frequency Limit for Full Phase Shift Altera Corporation January 2006 Phase Shift Minimum Frequency for Full Phase Shift Unit 72° 119 MHz 90° 149 MHz 4–103 Stratix Device Handbook, Volume 1 DLL Specifications 4–104 Stratix Device Handbook, Volume 1 Altera Corporation January 2006 5. Reference & Ordering Information S51005-2.1 Software Stratix® devices are supported by the Altera® Quartus® II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap® II logic analyzer, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink® interface. Device Pin-Outs Stratix device pin-outs can be found on the Altera web site (www.altera.com). Ordering Information Figure 5–1 describes the ordering codes for Stratix devices. For more information on a specific package, see the Package Information for Stratix Devices chapter. Altera Corporation September 2004 5–1 Ordering Information Figure 5–1. Stratix Device Packaging Ordering Information EP1S 80 F 1508 C Family Signature 7 ES Optional Suffix EP1S: Stratix Indicates specific device options or shipment method. ES: Engineering sample Device Type 10 20 25 30 40 60 80 Speed Grade 5, 6, or 7, with 5 being the fastest Operating Temperature C: Commercial temperature (tJ = 0˚ C to 85˚ C) I: Industrial temperature (tJ = -40˚ C to 100˚ C) Package Type B: Ball-grid array (BGA) F: FineLine BGA 5–2 Stratix Device Handbook, Volume 1 Pin Count Number of pins for a particular BGA or FineLine BGA package Altera Corporation September 2004 Index A Accumulator 2–63 Adder/Output Blocks 2–61 Adder/Subtractor 2–63 Accumulator 2–63 AGP 1x Specifications 4–13 AGP 2x Specifications 4–13 Architecture 2–1 36 x 36 Multiply Mode 2–66 addnsub Signal 2–8 Block Diagram 2–2 Bus Hold 2–121 Byte Alignment 2–140 Carry-Select Chain 2–11 Clear & Preset Logic Control 2–13 Combined Resources 2–78 Dedicated Circuitry 2–137 Device Resources 2–3 Device Routing Scheme 2–20 Digital Signal Processing Block 2–52 Direct Link Connection 2–5 Dynamic Arithmetic Mode 2–10 in LE 2–11 Four-Multipliers Adder Mode 2–68 Functional Description 2–1 LAB Interconnects 2–4 Logic Array Blocks 2–3 Structure 2–4 LE Operating Modes 2–8 Logic Elements 2–6 Modes of Operation 2–64 Multiplier Size & Configurations per DSP block 2–70 Multiply-Accumulator Mode 2–67 MultiTrack Interconnect 2–14 Normal Mode 2–9 in LE 2–9 Altera Corporation Open-Drain Output 2–120 Power Sequencing & Hot Socketing 2–140 Programmable Drive Strength 2–119 Programmable Pull-Up Resistor 2–122 Simple Multiplier Mode 2–64 Single-Port Mode 2–51 Slew-Rate Control 2–120 Two-Multipliers Adder Mode 2–67 Adder Mode Implementing Complex Multiply 2–68 C Class I Specifications 4–11, 4–12 Class II Specifications 4–11, 4–12, 4–13 Clocks Clock Feedback 2–96 Clock Multiplication & Division 2–88, 2–101 Clock Switchover 2–88 Delay 2–97 EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups 2–80 EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks 2–77 EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks 2–78 EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups 2–81 External Clock Inputs 2–102 Outputs 2–92, 2–103 Outputs for Enhanced PLLs 11 & 12 2–95 Outputs for PLLs 5 & 6 2–93 Fast Regional Clock External I/O Timing Parameters 4–34 Fast Regional Clock Network 2–76 Index–1 Stratix Device Handbook, Volume 1 Global & Hierarchical Clocking 2–73 Global & Regional Clock Connections from Side Pins & Fast PLL Outputs 2–85 from Top Clock Pins & Enhanced PLL Outputs 2–86 Global Clock External I/O Timing Parameters 4–35 Global Clock Network 2–74 Global Clocking 2–75 Independent Clock Mode 2–44 Input/Output Clock Mode 2–46 Simple Dual-Port Mode 2–48 True Dual-Port Mode 2–47 Maximum Input & Output Clock Rates 4–76 Maximum Input Clock Rate for CLK (0, 2, 9, 11) Pins in Flip-Chip Packages Wire-Bond Packages 4–77 4–79 (1, 3, 8, 10) Pins in Flip-Chip Packages Wire-Bond Packages 4–78 (5, 6, 11, 12) Pins in Flip-Chip Index–2 4–84 Phase & Delay Shifting 2–96 Phase Delay 2–96 PLL Clock Networks 2–73 Read/Write Clock Mode 2–49 in Simple Dual-Port Mode 2–50 Regional Clock 2–75 External I/O Timing Parameters 4–34 Regional Clock Bus 2–79 Regional Clock Network 2–75 Spread-Spectrum Clocking 2–98 Configuration 3–5 32-Bit IDCODE 3–3 and Testing 3–1 Data Sources for Configuration 3–7 Local Update Mode 3–12 Local Update Transition Diagram 3–12 Operating Modes 3–5 Partial Reconfiguration 3–7 Remote Update 3–8 Remote Update Transition Diagram 3–11 Schemes 3–7 SignalTap II Embedded Logic Analyzer 3–5 Stratix FPGAs with JRunner 3–7 Control Signals 2–104 D 4–76 4–78 Maximum Output Clock Rate for PLL (1, 2, 3, 4) Pins in Flip-Chip Packages Wire-Bond Packages 4–81 4–80 (7..4) & CLK(15..12) Pins in Flip-Chip Packages Wire-Bond Packages Packages Wire-Bond Packages 4–83 4–85 DC Switching Absolute Maximum Ratings 4–1 Bus Hold Parameters 4–16 Capacitance 4–17 DC & Switching Characteristics 4–1 External Timing Parameters 4–33 Operating Conditions 4–1 Performance 4–20 Power Consumption 4–17 Recommended Operating Conditions 4–1 DDR Double-Data Rate I/O Pins 2–111 Device Features EP1S10, EP1S20, EP1S25, EP1S30, 1–3 EP1S40, EP1S60, EP1S80, 1–3 Altera Corporation Stratix Device Handbook, Volume 1 Differential HSTL Specifications 4–15 DSP Block Diagram Configuration for 18 x 18-Bit 2–55 for 9 x 9-Bit 2–56 Block Interconnect Interface 2–71 Block Interface 2–70 Block Signal Sources & Destinations 2–73 Blocks Arranged in Columns 2–53 in Stratix Devices 2–54 Input Register Modes 2–60 Input Registers 2–58 Multiplier 2–60 Block 2–57 Signed Representation 2–60 Sub-Block 2–57 Sub-Blocks Using Input Shift Register Connections 2–59 Pipeline/Post Multiply Register 2–61 E EP1S10 Devices Column Pin Fast Regional Clock External I/O Parameters 4–36 Global Clock External I/O Parameters 4–37 Regional Clock External I/O Parameters 4–36 Row Pin Fast Regional Clock External I/O Parameters 4–37 Global Clock External I/O Parameters 4–38 Regional Clock External I/O Parameters 4–38 EP1S20 Devices Column Pin Fast Regional Clock External I/O Parameters 4–39 Global Clock External I/O Parameters 4–40 Regional Clock External I/O Altera Corporation Timing Timing Timing Timing Timing Timing Timing Timing Timing Parameters 4–39 Row Pin Fast Regional Clock External I/O Parameters 4–40 Global Clock External I/O Parameters 4–41 Regional Clock External I/O Parameters 4–41 EP1S25 Devices Column Pin Fast Regional Clock External I/O Parameters 4–42 Global Clock External I/O Parameters 4–43 Regional Clock External I/O Parameters 4–42 Row Pin Fast Regional Clock External I/O Parameters 4–43 Global Clock External I/O Parameters 4–44 Regional Clock External I/O Parameters 4–44 EP1S30 Devices Column Pin Fast Regional Clock External I/O Parameters 4–45 Global Clock External I/O Parameters 4–45 Regional Clock External I/O Parameters 4–45 Row Pin Fast Regional Clock External I/O Parameters 4–46 Global Clock External I/O Parameters 4–47 Regional Clock External I/O Parameters 4–47 EP1S40 Devices Column Pin Fast Regional Clock External I/O Parameters 4–48 Global Clock External I/O Parameters 4–49 Regional Clock External I/O Parameters 4–48 Row Pin Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Index–3 Stratix Device Handbook, Volume 1 Fast Regional Clock External I/O Parameters 4–49 Global Clock External I/O Parameters 4–50 Regional Clock External I/O Parameters 4–50 EP1S60 Devices Column Pin Fast Regional Clock External I/O Parameters 4–51 Global Clock External I/O Parameters 4–52 Regional Clock External I/O Parameters 4–51 M-RAM Interface Locations 2–38 Row Pin Fast Regional Clock External I/O Parameters 4–52 Global Clock External I/O Parameters 4–53 Regional Clock External I/O Parameters 4–53 EP1S80 Devices Column Pin Fast Regional Clock External I/O Parameters 4–54 Global Clock External I/O Parameters 4–55 Regional Clock External I/O Parameters 4–54 Global Clock External I/O Parameters 4–56 Row Pin Fast Regional Clock External I/O Parameters 4–55 Regional Clock External I/O Parameters 4–56 H HSTL Class I Specifications 4–14, 4–15 Class II Specifications 4–14, 4–15 Index–4 Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing Timing I I/O Standards 1.5-V 4–14, 4–15 I/O Specifications 4–4 1.8-V I/O Specifications 4–4 2.5-V I/O Specifications 4–3 3.3-V 4–13 LVDS I/O Specifications 4–6 PCI Specifications 4–9 PCML Specifications 4–8 Advanced I/O Standard Support 2–122 Column I/O Block Connection to the Interconnect 2–107 Column Pin Input Delay Adders 4–66 Control Signal Selection per IOE 2–109 CTT I/O Specifications 4–16 Differential LVDS Input On-Chip Termination 2–128 External I/O Delay Parameters 4–66 GTL+ I/O Specifications 4–10 High-Speed Differential I/O Support 2–130 HyperTransport Technology Specifications 4–9 I/O Banks 2–125 I/O Structure 2–104 I/O Support by Bank 2–126 IOE Structure 2–105 LVCMOS Specifications 4–3 LVDS Performance on Fast PLL Input 2–103 LVPECL Specifications 4–8 LVTTL Specifications 4–3 MultiVolt I/O Interface 2–129 MultiVolt I/O Support 2–130 Output Delay Adders for Fast Slew Rate on Column Pins 4–68 Output Delay Adders for Fast Slew Rate on Row Pins 4–69 Output Delay Adders for Slow Slew Rate on Column Pins 4–70 Package Options & I/O Pin Counts 1–4 Receiver Input Waveforms for Differential Altera Corporation Stratix Device Handbook, Volume 1 I/O Standards 4–5 I/O Block Connection to the Interconnect 2–106 Row Pin Input Delay Adders 4–67 Signal Path through the I/O Block 2–108 SSTL-18 4–11 SSTL-2 4–12 SSTL-3 4–12, 4–13 Stratix IOE in Bidirectional I/O Configuration 2–110 Supported I/O Standards 2–123 Transmitter Output Waveforms for Differential I/O Standards 4–6 Interconnect C4 Connections 2–18 DSP Block Interface to Interconnect 2–72 Left-Facing M-RAM to Interconnect Interface 2–40 LUT Chain Register Chain Interconnects 2–17 M-RAM Column Unit Interface to Interconnect 2–42 Row Unit Interface to Interconnect 2–41 R4 Connections 2–15 IOE Internal Timing Microparameters 4–29 Row J JTAG Boundary-Scan Register Length 3–3 Support 3–1 Stratix JTAG Instructions 3–2 Waveforms 3–4 L LAB Control Signals 2–5 Wide Control Signals 2–6 LUT Chain & Register Chain 2–8 Altera Corporation M Memory Architecture Byte Enable for M4K RAM Block 2–32 Byte Enable for M-RAM Block 2–35 External RAM Interfacing 2–115 M4K Block Internal Timing Microparameter Descriptions 4–24 Microparameters 4–31 RAM Block 2–30 Configurations (Simple DualPort) 2–31 Configurations (True DualPort) 2–31 Control Signals 2–33 LAB Row Interface 2–33 M512 Block Internal Timing Microparameter Descriptions 4–24 Microparameters 4–30 RAM Block Architecture 2–27 Configurations (Simple Dual-Port RAM) 2–27 Control Signals 2–29 LAB Row Interface 2–30 Memory Block Size 2–26 Memory Modes 2–21 M-RAM Block 2–34 Configurations (Simple DualPort) 2–34 Configurations (True DualPort) 2–35 Block Control Signals 2–37 Block Internal Timing Microparameter Descriptions 4–25 Combined Byte Selection for x144 Index–5 Stratix Device Handbook, Volume 1 Mode 2–36 & Column Interface Unit Signals 2–43 Parity Bit Support 2–24 Shift Register Memory Configuration 2–26 Support 2–25 Simple Dual-Port & Single-Port Memory Configurations 2–23 Stratix IOE in DDR Input I/O Configuration 2–112 Stratix IOE in DDR Output I/O Configuration 2–114 TriMatrix Memory 2–21 True Dual-Port Memory Configuration 2–22 Port I/O Standards 2–102 I/O Standards Supported for Enhanced PLL Pins 2–94 Lock Detect & Programmable Gated Locked 2–98 PLL Locations 2–84 Programmable Bandwidth 2–91 Programmable Delay Chain 2–111 Programmable Duty Cycle 2–98 Reconfiguration 2–90 Row O Ordering Information 5–1 Device Pin-Outs 5–1 Packaging Ordering Information 5–2 Reference & Ordering Information 5–1 Output Registers 2–64 Output Selection Multiplexer 2–64 P Packaging BGA Package Sizes 1–4 Device Speed Grades 1–5 FineLine BGA Package Sizes 1–5 PCI-X 1.0 Specifications 4–10 Phase Shifting 2–103 PLL Advanced Clear & Enable Control 2–98 Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs 2–91 Enhanced Fast PLLs 2–81 Fast PLL 2–100 Channel Layout EP1S10, EP1S20 or EP1S25 Devices 2–138 Channel Layout EP1S30 to EP1S80 Devices 2–139 Index–6 T Testing Temperature Sensing Diode 3–13 Electrical Characteristics 3–14 External 3–14 Temperature vs. Temperature-Sensing Diode Voltage 3–15 Timing DSP Block Internal Timing Microparameter Descriptions 4–23 Microparameters 4–29 Dual-Port RAM Timing Microparameter Waveform 4–27 External Timing in Stratix Devices 4–33 High-Speed I/O Timing 4–87 High-Speed Timing Specifications & Terminology 4–87 Internal Parameters 4–22 IOE Internal Timing Microparameter Descriptions 4–22 LE Internal Timing Microparameters 4–28 Logic Elements Internal Timing Microparameter Descriptions 4–22 Model 4–19 PLL Timing 4–94 Preliminary & Final 4–19 Stratix Device Timing Model Status 4–19 Stratix JTAG Timing Parameters & Values 3–4 TriMatrix Memory TriMatrix Memory Features 2–21 Altera Corporation Stratix Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com S5V2-3.5 Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ii Altera Corporation Contents Chapter Revision Dates ......................................................................... xiii About This Handbook ............................................................................. xv How to Find Information ...................................................................................................................... xv How to Contact Altera ........................................................................................................................... xv Typographic Conventions .................................................................................................................... xvi Section I. Clock Management Revision History ....................................................................................................................... Section I–1 Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 1–1 Enhanced PLLs ....................................................................................................................................... 1–5 Clock Multiplication & Division .................................................................................................... 1–9 External Clock Outputs ................................................................................................................. 1–10 Clock Feedback ............................................................................................................................... 1–14 Phase Shifting ................................................................................................................................. 1–14 Lock Detect ...................................................................................................................................... 1–15 Programmable Duty Cycle ........................................................................................................... 1–16 General Advanced Clear & Enable Control ............................................................................... 1–16 Programmable Bandwidth ............................................................................................................ 1–18 Clock Switchover ............................................................................................................................ 1–25 Spread-Spectrum Clocking ........................................................................................................... 1–25 PLL Reconfiguration ...................................................................................................................... 1–30 Enhanced PLL Pins ........................................................................................................................ 1–30 Fast PLLs ............................................................................................................................................... 1–31 Clock Multiplication & Division .................................................................................................. 1–34 External Clock Outputs ................................................................................................................. 1–34 Phase Shifting ................................................................................................................................. 1–35 Programmable Duty Cycle ........................................................................................................... 1–36 Control Signals ................................................................................................................................ 1–36 Pins ................................................................................................................................................... 1–37 Clocking ................................................................................................................................................ 1–39 Global & Hierarchical Clocking ................................................................................................... 1–39 Clock Input Connections ............................................................................................................... 1–41 Clock Output Connections ............................................................................................................ 1–43 Board Layout ........................................................................................................................................ 1–50 VCCA & GNDA ............................................................................................................................. 1–50 Altera Corporation iii Contents Stratix Device Handbook, Volume 2 VCCG & GNDG .............................................................................................................................. External Clock Output Power ...................................................................................................... Guidelines ........................................................................................................................................ Conclusion ............................................................................................................................................ 1–52 1–53 1–56 1–56 Section II. Memory Revision History ..................................................................................................................... Section II–1 Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 2–1 TriMatrix Memory ................................................................................................................................. 2–1 Clear Signals ...................................................................................................................................... 2–3 Parity Bit Support ............................................................................................................................. 2–3 Byte Enable Support ........................................................................................................................ 2–4 Using TriMatrix Memory ..................................................................................................................... 2–7 Implementing Single-Port Mode .................................................................................................... 2–7 Implementing Simple Dual-Port Mode ......................................................................................... 2–8 Implementing True Dual-Port Mode .......................................................................................... 2–11 Implementing Shift-Register Mode ............................................................................................. 2–14 Implementing ROM Mode ............................................................................................................ 2–15 Implementing FIFO Buffers .......................................................................................................... 2–16 Clock Modes ......................................................................................................................................... 2–16 Independent Clock Mode .............................................................................................................. 2–16 Input/Output Clock Mode ........................................................................................................... 2–18 Read/Write Clock Mode ............................................................................................................... 2–21 Single-Port Mode ............................................................................................................................ 2–23 Designing With TriMatrix Memory .................................................................................................. 2–23 Selecting TriMatrix Memory Blocks ............................................................................................ 2–24 Pipeline & Flow-Through Modes ................................................................................................ 2–24 Power-up Conditions & Memory Initialization ......................................................................... 2–25 Read-During-Write Operation at the Same Address ..................................................................... 2–25 Same-Port Read-During-Write Mode .......................................................................................... 2–25 Mixed-Port Read-During-Write Mode ........................................................................................ 2–26 Conclusion ............................................................................................................................................ 2–27 Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 3–1 External Memory Standards ................................................................................................................ 3–1 DDR SDRAM .................................................................................................................................... 3–1 RLDRAM II ....................................................................................................................................... 3–4 QDR & QDRII SRAM ...................................................................................................................... 3–6 ZBT SRAM ......................................................................................................................................... 3–8 DDR Memory Support Overview ..................................................................................................... 3–10 DDR Memory Interface Pins ......................................................................................................... 3–11 DQS Phase-Shift Circuitry ............................................................................................................ 3–15 iv Altera Corporation Contents Contents DDR Registers ................................................................................................................................. 3–20 PLL ................................................................................................................................................... 3–27 Conclusion ............................................................................................................................................ 3–27 Section III. I/O Standards Revision History .................................................................................................................... Section III–1 Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 4–1 Stratix & Stratix GX I/O Standards .................................................................................................... 4–1 3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) - EIA/JEDEC Standard JESD8-B . 4–2 3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B ........................................................................ 4–3 2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 .......................... 4–3 2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 ..................... 4–3 1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 .......................... 4–4 1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 ..................... 4–4 1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard JESD8-11 ............................ 4–4 1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6 ................................................. 4–5 1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6 ................................................ 4–6 3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus Specification Rev. 2.3 ....... 4–6 3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus Specification Revision 1.0a ................ 4–7 3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification Revision 2.3 .......................... 4–7 3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–7 3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–8 GTL - EIA/JEDEC Standard EIA/JESD8-3 .................................................................................. 4–8 GTL+ .................................................................................................................................................. 4–8 CTT - EIA/JEDEC Standard JESD8-4 ............................................................................................ 4–9 SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8 .................................................................. 4–9 SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A ............................................................. 4–10 SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3 ............................................ 4–11 Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................. 4–11 LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644 .......................................................... 4–12 LVPECL ........................................................................................................................................... 4–13 Pseudo Current Mode Logic (PCML) ......................................................................................... 4–13 HyperTransport Technology - HyperTransport Consortium ................................................. 4–14 High-Speed Interfaces ......................................................................................................................... 4–15 OIF-SPI4.2 ........................................................................................................................................ 4–15 OIF-SFI4.1 ........................................................................................................................................ 4–15 10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft Standard P802.3ae/D2.0 ...... 4–16 RapidIO Interconnect Specification Revision 1.1 ....................................................................... 4–16 HyperTransport Technology - HyperTransport Consortium ................................................. 4–17 UTOPIA Level 4 – ATM Forum Technical Committee Standard AF-PHY-0144.001 ........... 4–17 Stratix & Stratix GX I/O Banks .......................................................................................................... 4–17 Non-Voltage-Referenced Standards ............................................................................................ 4–24 Voltage-Referenced Standards ..................................................................................................... 4–24 Altera Corporation v Contents Stratix Device Handbook, Volume 2 Mixing Voltage Referenced & Non-Voltage Referenced Standards ....................................... 4–25 Drive Strength ...................................................................................................................................... 4–26 Standard Current Drive Strength ................................................................................................. 4–26 Programmable Current Drive Strength ...................................................................................... 4–27 Hot Socketing ....................................................................................................................................... 4–27 DC Hot Socketing Specification ................................................................................................... 4–28 AC Hot Socketing Specification ................................................................................................... 4–28 I/O Termination .................................................................................................................................. 4–28 Voltage-Referenced I/O Standards ............................................................................................. 4–28 Differential I/O Standards ............................................................................................................ 4–29 Differential Termination (RD) ...................................................................................................... 4–29 Transceiver Termination ............................................................................................................... 4–30 I/O Pad Placement Guidelines .......................................................................................................... 4–30 Differential Pad Placement Guidelines ....................................................................................... 4–30 VREF Pad Placement Guidelines ................................................................................................. 4–31 Output Enable Group Logic Option in Quartus II .................................................................... 4–34 Toggle Rate Logic Option in Quartus II ...................................................................................... 4–35 DC Guidelines ................................................................................................................................. 4–35 Power Source of Various I/O Standards ......................................................................................... 4–38 Quartus II Software Support .............................................................................................................. 4–38 Compiler Settings ........................................................................................................................... 4–38 Device & Pin Options .................................................................................................................... 4–39 Assign Pins ...................................................................................................................................... 4–39 Programmable Drive Strength Settings ...................................................................................... 4–40 I/O Banks in the Floorplan View ................................................................................................. 4–40 Auto Placement & Verification of Selectable I/O Standards ................................................... 4–41 Conclusion ............................................................................................................................................ 4–42 More Information ................................................................................................................................ 4–42 References ............................................................................................................................................. 4–42 Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices Introduction ............................................................................................................................................ 5–1 Stratix I/O Banks ................................................................................................................................... 5–1 Stratix Differential I/O Standards ................................................................................................. 5–2 Stratix Differential I/O Pin Location ............................................................................................. 5–5 Principles of SERDES Operation ......................................................................................................... 5–6 Stratix Differential I/O Receiver Operation ................................................................................. 5–7 Stratix Differential I/O Transmitter Operation ........................................................................... 5–9 Transmitter Clock Output ............................................................................................................. 5–10 Divided-Down Transmitter Clock Output ................................................................................. 5–10 Center-Aligned Transmitter Clock Output ................................................................................ 5–11 SDR Transmitter Clock Output .................................................................................................... 5–12 Using SERDES to Implement DDR ................................................................................................... 5–13 Using SERDES to Implement SDR .................................................................................................... 5–14 Differential I/O Interface & Fast PLLs ............................................................................................. 5–16 Clock Input & Fast PLL Output Relationship ............................................................................ 5–18 Fast PLL Specifications .................................................................................................................. 5–20 vi Altera Corporation Contents Contents High-Speed Phase Adjust ............................................................................................................. 5–21 Counter Circuitry ........................................................................................................................... 5–22 Fast PLL SERDES Channel Support ............................................................................................ 5–23 Advanced Clear & Enable Control .............................................................................................. 5–25 Receiver Data Realignment ................................................................................................................ 5–25 Data Realignment Principles of Operation ................................................................................. 5–25 Generating the TXLOADEN Signal ............................................................................................. 5–27 Realignment Implementation ....................................................................................................... 5–28 Source-Synchronous Timing Budget ................................................................................................ 5–30 Differential Data Orientation ........................................................................................................ 5–30 Differential I/O Bit Position ......................................................................................................... 5–31 Timing Definition ........................................................................................................................... 5–32 Input Timing Waveform ............................................................................................................... 5–39 Output Timing ................................................................................................................................ 5–40 Receiver Skew Margin ................................................................................................................... 5–40 Switching Characteristics .............................................................................................................. 5–42 Timing Analysis .............................................................................................................................. 5–42 SERDES Bypass DDR Differential Signaling ................................................................................... 5–42 SERDES Bypass DDR Differential Interface Review ................................................................. 5–42 SERDES Clock Domains ................................................................................................................ 5–42 SERDES Bypass DDR Differential Signaling Receiver Operation .......................................... 5–43 SERDES Bypass DDR Differential Signaling Transmitter Operation ..................................... 5–44 High-Speed Interface Pin Locations ................................................................................................. 5–45 Differential I/O Termination ............................................................................................................. 5–46 RD Differential Termination .......................................................................................................... 5–46 HyperTransport & LVPECL Differential Termination ............................................................. 5–47 PCML Differential Termination ................................................................................................... 5–47 Differential HSTL Termination .................................................................................................... 5–48 Differential SSTL-2 Termination .................................................................................................. 5–49 Board Design Consideration .............................................................................................................. 5–50 Software Support ................................................................................................................................. 5–51 Differential Pins in Stratix ............................................................................................................. 5–51 Fast PLLs .......................................................................................................................................... 5–52 LVDS Receiver Block ..................................................................................................................... 5–60 LVDS Transmitter Module ........................................................................................................... 5–65 SERDES Bypass Mode ................................................................................................................... 5–70 Summary ............................................................................................................................................... 5–75 Section IV. Digital Signal Processing (DSP) Revision History .................................................................................................................... Section IV–1 Chapter 6. DSP Blocks in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 6–1 DSP Block Overview ............................................................................................................................. 6–2 Architecture ............................................................................................................................................ 6–5 Altera Corporation vii Contents Stratix Device Handbook, Volume 2 Multiplier Block ................................................................................................................................ 6–5 Adder/Output Block ....................................................................................................................... 6–9 Routing Structure & Control Signals ........................................................................................... 6–12 Operational Modes .............................................................................................................................. 6–18 Simple Multiplier Mode ................................................................................................................ 6–18 Multiply Accumulator Mode ........................................................................................................ 6–22 Two-Multiplier Adder Mode ........................................................................................................ 6–23 Four-Multiplier Adder Mode ....................................................................................................... 6–24 Software Support ................................................................................................................................. 6–28 Conclusion ............................................................................................................................................ 6–28 Chapter 7. Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 7–1 Stratix & Stratix GX DSP Block Overview ......................................................................................... 7–1 TriMatrix Memory Overview .............................................................................................................. 7–4 DSP Function Overview ....................................................................................................................... 7–5 Finite Impulse Response (FIR) Filters ................................................................................................. 7–5 FIR Filter Background ...................................................................................................................... 7–6 Basic FIR Filter .................................................................................................................................. 7–7 Time-Domain Multiplexed FIR Filters ........................................................................................ 7–13 Polyphase FIR Interpolation Filters ............................................................................................. 7–17 Polyphase FIR Decimation Filters ................................................................................................ 7–24 Complex FIR Filter ......................................................................................................................... 7–31 Infinite Impulse Response (IIR) Filters ............................................................................................. 7–34 IIR Filter Background .................................................................................................................... 7–34 Basic IIR Filters ............................................................................................................................... 7–36 Butterworth IIR Filters ................................................................................................................... 7–39 Matrix Manipulation ........................................................................................................................... 7–45 Background on Matrix Manipulation .......................................................................................... 7–45 Two-Dimensional Filtering & Video Imaging ........................................................................... 7–46 Discrete Cosine Transform (DCT) ..................................................................................................... 7–52 DCT Background ............................................................................................................................ 7–52 2-D DCT Algorithm ....................................................................................................................... 7–53 Arithmetic Functions ........................................................................................................................... 7–59 Background ..................................................................................................................................... 7–59 Arithmetic Function Implementation ......................................................................................... 7–60 Arithmetic Function Implementation Results ............................................................................ 7–62 Arithmetic Function Design Example ......................................................................................... 7–62 Conclusion ............................................................................................................................................ 7–62 References ............................................................................................................................................. 7–63 Section V. IP & Design Considerations Revision History ..................................................................................................................... Section V–1 viii Altera Corporation Contents Contents Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 8–1 Related Links ..................................................................................................................................... 8–1 10-Gigabit Ethernet ................................................................................................................................ 8–1 Interfaces ................................................................................................................................................. 8–5 XSBI .................................................................................................................................................... 8–5 XGMII ............................................................................................................................................... 8–13 XAUI ................................................................................................................................................. 8–19 I/O Characteristics for XSBI, XGMII & XAUI ................................................................................. 8–21 Software Implementation .............................................................................................................. 8–22 AC/DC Specifications ................................................................................................................... 8–22 10-Gigabit Ethernet MAC Core .................................................................................................... 8–24 Conclusion ....................................................................................................................................... 8–25 Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices Introduction ............................................................................................................................................ 9–1 System Topology .............................................................................................................................. 9–3 Interface Implementation in Stratix & Stratix GX Devices ......................................................... 9–5 AC Timing Specifications .............................................................................................................. 9–10 Electrical Specifications ................................................................................................................. 9–12 Software Implementation .............................................................................................................. 9–13 Conclusion ....................................................................................................................................... 9–13 Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices Introduction .......................................................................................................................................... 10–1 General Architecture ........................................................................................................................... 10–1 Logic Elements ................................................................................................................................ 10–2 MultiTrack Interconnect ................................................................................................................ 10–3 DirectDrive Technology ................................................................................................................ 10–4 Architectural Element Names ...................................................................................................... 10–5 TriMatrix Memory ............................................................................................................................... 10–8 Same-Port Read-During-Write Mode ........................................................................................ 10–10 Mixed-Port Read-During-Write Mode ...................................................................................... 10–11 Memory Megafunctions .............................................................................................................. 10–12 FIFO Conditions ........................................................................................................................... 10–13 Design Migration Mode in Quartus II Software ...................................................................... 10–13 DSP Block ............................................................................................................................................ 10–16 DSP Block Megafunctions ........................................................................................................... 10–16 PLLs & Clock Networks ................................................................................................................... 10–18 Clock Networks ............................................................................................................................ 10–18 PLLs ................................................................................................................................................ 10–19 I/O Structure ...................................................................................................................................... 10–25 External RAM Interfacing ........................................................................................................... 10–25 I/O Standard Support ................................................................................................................. 10–26 High-Speed Differential I/O Standards .................................................................................... 10–26 altlvds Megafunction ................................................................................................................... 10–29 Configuration ..................................................................................................................................... 10–30 Altera Corporation ix Contents Stratix Device Handbook, Volume 2 Configuration Speed & Schemes ................................................................................................ Remote Update Configuration ................................................................................................... JTAG Instruction Support ........................................................................................................... Conclusion .......................................................................................................................................... 10–30 10–31 10–31 10–32 Section VI. System Configuration & Upgrades Revision History .................................................................................................................... Section VI–2 Chapter 11. Configuring Stratix & Stratix GX Devices Introduction .......................................................................................................................................... 11–1 Device Configuration Overview ....................................................................................................... 11–2 MSEL[2..0] Pins ............................................................................................................................... 11–3 VCCSEL Pins ...................................................................................................................................... 11–3 PORSEL Pins ................................................................................................................................... 11–5 nIO_PULLUP Pins ......................................................................................................................... 11–5 TDO & nCEO Pins .......................................................................................................................... 11–6 Configuration File Size ....................................................................................................................... 11–6 Altera Configuration Devices ............................................................................................................ 11–7 Configuration Schemes ....................................................................................................................... 11–7 PS Configuration ............................................................................................................................ 11–7 FPP Configuration ........................................................................................................................ 11–21 PPA Configuration ....................................................................................................................... 11–30 JTAG Programming & Configuration ....................................................................................... 11–36 JTAG Programming & Configuration of Multiple Devices ................................................... 11–39 Configuration with JRunner Software Driver .......................................................................... 11–41 Jam STAPL Programming & Test Language ............................................................................ 11–42 Configuring Using the MicroBlaster Driver .................................................................................. 11–51 Device Configuration Pins ............................................................................................................... 11–51 Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices Introduction .......................................................................................................................................... 12–1 Remote Configuration Operation ...................................................................................................... 12–1 Remote System Configuration Modes ........................................................................................ 12–3 Remote System Configuration Components .............................................................................. 12–5 Quartus II Software Support ............................................................................................................ 12–12 altremote_update Megafunction ................................................................................................ 12–14 Remote Update WYSIWYG ATOM ........................................................................................... 12–17 Using Enhanced Configuration Devices ........................................................................................ 12–19 Local Update Programming File Generation ........................................................................... 12–21 Remote Update Programming File Generation ....................................................................... 12–32 Combining MAX Devices & Flash Memory .................................................................................. 12–42 Using an External Processor ............................................................................................................ 12–43 Conclusion .......................................................................................................................................... 12–44 x Altera Corporation Contents Contents Section VII. PCB Layout Guidelines Revision History .................................................................................................................. Section VII–1 Chapter 13. Package Information for Stratix Devices Introduction .......................................................................................................................................... 13–1 Device & Package Cross Reference ................................................................................................... 13–1 Thermal Resistance .............................................................................................................................. 13–2 Package Outlines ................................................................................................................................. 13–3 484-Pin FineLine BGA - Flip Chip ............................................................................................... 13–4 672-Pin FineLine BGA - Flip Chip ............................................................................................... 13–6 780-Pin FineLine BGA - Flip Chip ............................................................................................... 13–8 956-Pin Ball Grid Array (BGA) - Flip Chip ............................................................................... 13–10 1,020-Pin FineLine BGA - Flip Chip .......................................................................................... 13–12 1,508-Pin FineLine BGA - Flip Chip .......................................................................................... 13–14 Chapter 14. Designing with 1.5-V Devices Introduction .......................................................................................................................................... 14–1 Power Sequencing & Hot Socketing ................................................................................................. 14–1 Using MultiVolt I/O Pins ................................................................................................................... 14–2 Voltage Regulators .............................................................................................................................. 14–3 Linear Voltage Regulators ............................................................................................................. 14–5 Switching Voltage Regulators ...................................................................................................... 14–7 Maximum Output Current ........................................................................................................... 14–8 Selecting Voltage Regulators ........................................................................................................ 14–9 Voltage Divider Network ............................................................................................................ 14–10 1.5-V Regulator Circuits .............................................................................................................. 14–10 1.5-V Regulator Application Examples .......................................................................................... 14–19 Synchronous Switching Regulator Example ............................................................................ 14–20 Board Layout ...................................................................................................................................... 14–21 Split-Plane Method ....................................................................................................................... 14–23 Conclusion .......................................................................................................................................... 14–23 References ........................................................................................................................................... 14–24 Altera Corporation xi Contents xii Stratix Device Handbook, Volume 2 Altera Corporation Chapter Revision Dates The chapters in this book, Stratix Device Handbook, Volume 2, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices Revised: July 2005 Part number: S52001-3.2 Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Revised: July 2005 Part number: S52003-3.3 Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices Revised: June 2006 Part number: SII52003-3.3 Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices Revised: June 2006 Part number: S52004-3.4 Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices Revised: July 2005 Part number: S52005-3.2 Chapter 6. DSP Blocks in Stratix & Stratix GX Devices Revised: July 2005 Part number: S52006-2.2 Chapter 7. Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Revised: September 2004 Part number: S52007-1.1 Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices Revised: July 2005 Part number: S52010-2.0 Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices Revised: July 2005 Part number: S52011-2.0 Altera Corporation xiii Chapter Revision Dates Stratix Device Handbook, Volume 2 Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices Revised: July 2005 Part number: S52012-3.0 Chapter 11. Configuring Stratix & Stratix GX Devices Revised: July 2005 Part number: S52013-3.2 Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices Revised: September 2004 Part number: S52015-3.1 Chapter 13. Package Information for Stratix Devices Revised: July 2005 Part number: S53008-3.0 Chapter 14. Designing with 1.5-V Devices Revised: January 2005 Part number: C51012-1.1 xiv Altera Corporation About This Handbook This handbook provides comprehensive information about the Altera® Stratix® family of devices. How to Find Information You can find more information in the following ways: ■ ■ ■ ■ How to Contact Altera Information Type Technical support Product literature The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. Acrobat bookmarks, which serve as an additional table of contents in PDF documents. Thumbnail icons, which provide miniature previews of each page and provide a link to the pages. Numerous links, shown in green text, which allow you to jump to related information. For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada All Other Locations www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time www.altera.com www.altera.com Altera literature services literature@altera.com literature@altera.com Non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time FTP site ftp.altera.com ftp.altera.com Altera Corporation xv Typographic Conventions Typographic Conventions Visual Cue Stratix Device Handbook, Volume 2 This document uses the typographic conventions shown below. Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Designs. Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.” Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■ Bullets are used in a list of items when the sequence of the items is not important. ● • v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. xvi Altera Corporation Section I. Clock Management This section provides information on the different types of phase-lock loops (PLLs). The feature-rich, enhanced PLLs assist you in managing clocks internally and also have the ability to drive off-chip to control system-level clock networks. The fast PLLs offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential I/O interfaces. This chapter contains detailed information on the features, the interconnections to the core and off-chip, and the specifications for both types of PLLs. This section contains the following: ■ Revision History Chapter Date/Version 1 July 2005, v3.2 Chapter 1, General-Purpose PLLs in Stratix & Stratix GX Devices The table below shows the revision history for Chapter 1. Changes Made ● ● ● ● ● ● September 2004, v3.1 ● ● ● April 2004, v3.0 ● ● ● ● ● ● ● ● ● ● Altera Corporation Removed information regarding delay shift (time delay elements). Updated Table 1–8. Updated “Clock Switchover” section. Updated Figure 1–22. Updated “Control Signals” section. Updated Table 1–16. Updated Note 1 in Table 1–17 on page 1–32. Updated Note 1 in Table 1–21 on page 1–48. Updated Table 1–12 on page 1–34. Changed PCI-X to PCI-X 1.0 throughout volume. Note 3 added to columns 11 and 12 in Table 1–1. Deleted “Stratix GX Clock Input Sources for Enhanced and Fast PLLs” table. Deleted “Stratix GX Global and Regional Clock Output Line Sharing for Enhanced and Fast PLLS” table. Deleted “Stratix GX CLK and FPLLCLK Input Pin Connections to Global & Regional Clock Networks” table. Changed CLK checkmarks in Table 1–14. Updated notes to Table 1–3. and Figure 1–3. Added Table 1–7. Clock Switchover section has been moved to AN 313. Changed RCLK values in Figures 1–20 and 1–22. Section I–1 Clock Management Stratix Device Handbook, Volume 2 Chapter Date/Version Changes Made 1 November 2003, v2.2 ● Updated the “Lock Detect” section. October 2003, v2.1 ● Updated the “VCCG & GNDG” section. Updated Figure 1–14. ● July 2003, v2.0 ● ● ● ● ● ● ● ● ● Section I–2 Updated clock multiplication and division, spread spectrum, and Notes 1 and 8 in Table 1-3. Updated inclk[1..0] port name in Table 1-4. Updated ranges for EPLL post-scale and pre-scale dividers on page 1-9 Added 1.8V HSTL support for EPLL in Table 1-6 and 1-13. New requirement to assert are set signal each PLL when it has to reacquire lock on either a new clock after loss of lock (page 1-16) Corrected input port extswitch to clkswitch throughout this chapter. Updated clkloss description in Table 1-9. Updated text on jitter for spread spectrum on page 1-38. Removed PLL specifications. See Chapter 4 of Volume 1. Altera Corporation 1. General-Purpose PLLs in Stratix & Stratix GX Devices S52001-3.2 Introduction Stratix® and Stratix GX devices have highly versatile phase-locked loops (PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX device: enhanced PLLs and fast PLLs. Each device has up to four enhanced PLLs, which are feature-rich, general-purpose PLLs supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread spectrum clocking, and programmable bandwidth. There are also up to eight fast PLLs per device, which offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential I/O interfaces. The Altera® Quartus® II software enables the PLLs and their features without requiring any external devices. Tables 1–1 and 1–2 show PLL availability for Stratix and Stratix GX devices, respectively. Table 1–1. Stratix Device PLL Availability Fast PLLs Enhanced PLLs Device 1 2 3 4 EP1S10 v v v EP1S20 v v EP1S25 v EP1S30 7 8 9 10 5(1) 6(1) 11(2) 12(2) v v v v v v v v v v v v v v v v v (3) v (3) v (3) v (3) v v EP1S40 v v v v v (3) v (3) v (3) v (3) v v v (3) v (3) EP1S60 v v v v v v v v v v v v EP1S80 v v v v v v v v v v v v Notes to Table 1–1: (1) (2) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output. (3) EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA® package. Altera Corporation July 2005 1–1 Introduction Table 1–2. Stratix GX Device PLL Availability Fast PLLs Enhanced PLLs Device 1 2 EP1S10C v EP1S10D 5 6 v v v v v v v EP1S25C v v v v EP1S25D v v v v EP1S25F v v v v EP1S40D v v v v v EP1S40G v v v v v 1–2 Stratix Device Handbook, Volume 2 7 8 11 12 v v v v v v Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–3 shows the enhanced and fast PLL features in Stratix and Stratix GX devices. Table 1–3. Stratix & Stratix GX PLL Features Feature Enhanced PLL Fast PLL Clock multiplication and division m/(n × post-scale counter) (1) m/(post-scale counter) (2) Down to 156.25-ps increments (3), (4) Down to 125-ps increments (3), (4) Phase shift Clock switchover v PLL reconfiguration v Programmable bandwidth v Spread spectrum clocking v Programmable duty cycle v v Number of internal clock outputs 6 3 (5) Number of external clock outputs Four differential/eight singled-ended or one single-ended (6) (7) Number of feedback clock inputs 2 (8) Notes to Table 1–3: (1) (2) (3) (4) (5) (6) (7) (8) For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. For fast PLLs, m, n, and post-scale counters range from 1 to 32. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. For degree increments, Stratix and Stratix GX devices can shift all output frequencies in increments of at least 45° . Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. On Stratix GX devices, PLLs 3, 4, 9, and 10 are not available for general-purpose use. Every Stratix and Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, EP1S40 (PLL 11 and 12 not supported for F780 package), and EP1SGX40 devices each have one single-ended output. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix and Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per PLL. Altera Corporation July 2005 1–3 Stratix Device Handbook, Volume 2 Introduction Figure 1–1 shows a top-level diagram of the Stratix device and PLL floorplan. Figure 1–2 shows a top-level diagram of the Stratix GX device and PLL floorplan. See “Clocking” on page 1–39 for more detail on PLL connections to global and regional clocks. Figure 1–1. Stratix PLL Locations CLK12-15 5 11 FPLL7CLK 7 10 FPLL10CLK CLK0-3 1 2 4 3 CLK8-11 8 9 FPLL9CLK PLLs FPLL8CLK 6 12 CLK4-7 1–4 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–2. Stratix GX PLL Locations CLK12-15 5 LVDSCLK0 11 7 HSSI CLK0-3 1 2 PLLs LVDSCLK1 HSSI 8 6 12 CLK4-7 Enhanced PLLs Altera Corporation July 2005 Stratix and Stratix GX devices contain up to four enhanced PLLs with advanced clock management features. Figure 1–3 shows a diagram of the enhanced PLL. 1–5 Stratix Device Handbook, Volume 2 Enhanced PLLs Figure 1–3. Stratix & Stratix GX Enhanced PLL Programmable Time Delay on Each PLL Port Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL (4) ÷l0 Δt Regional Clocks Clock Switch-Over Circuitry ÷l1 Δt Spread Spectrum Phase Frequency Detector (PFD) INCLK0 4 Δtn ÷n Charge Pump 8 Loop Filter VCO INCLK1 (1) FBIN Δtm ÷m ÷g0 Δt ÷g1 Δt ÷g2 Δt ÷g3 Δt ÷e0 Δt ÷e1 Δt ÷e2 Δt ÷e3 Δt Global Clocks I/O Buffers (2) to I/O or general routing Lock Detect & Filter VCO Phase Selection Affecting All Outputs 4 I/O Buffers (3) Notes to Figure 1–3: (1) (2) (3) (4) External feedback is available in PLLs 5 and 6. This single-ended external output is available from the g0 counter for PLLs 11 and 12. These four counters and external outputs are available in PLLs 5 and 6. This connection is only available on EP1SGX40 Stratix GX devices and EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the F780 package does not support PLLs 11 and 12. 1–6 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–4 shows all the possible ports of the enhanced PLLs. Figure 1–4. Enhanced PLL Signals (1) pllenable (2) inclk0 (2) inclk1 areset clkswitch scanclk Physical Pin clk[5..0] Signal Driven by Internal Logic Signal Driven to Internal Logic Internal Clock Signal locked clkloss clkbad[1..0] active_clock scandata scanaclr clkena[5..0] Only PLLs 11 and 12 extclk4 scandataout pfdena (2) fbin Only PLLs 5 and 6 pll_out0p pll_out0n extclkena[3..0] pll_out1p pll_out1n pll_out2p (3) pll_out2n (3) pll_out3p (3) pll_out3n (3) Notes to Figure 1–4: (1) (2) (3) This input pin is shared by all enhanced and fast PLLs. These are either single-ended or differential pins. EP1S10, EP1S20, and EP1S25 devices in 672-pin ball grid array (BGA) and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n). Altera Corporation July 2005 1–7 Stratix Device Handbook, Volume 2 Enhanced PLLs Tables 1–4 and 1–5 describe all the enhanced PLL ports. Table 1–4. Enhanced PLL Input Signals Port Description Source Destination inclk[1..0] Primary and secondary reference clock inputs to PLL Pin ×n counter fbin External feedback input to the PLL (PLLs 5 and 6 only) Pin Phase frequency detector (PFD) pllena Enable pin for enabling or disabling all or a set of PLLs⎯active high Pin General PLL control signal clkswitch Switchover signal used to initiate external clock switchover control⎯this signal switches the clock on the rising edge of clkswitch Logic array PLL switchover circuit areset Signal used to reset the PLL which resynchronizes all the counter outputs⎯active high Logic array General PLL control signal clkena[5..0] Enable clock driving regional or global clock⎯active high Logic array Clock output extclkena[3..0] Enable clock driving external clock (PLLs 5 and 6 only)⎯active high Logic array Clock output pfdena Enables the outputs from the phase frequency detector⎯active high Logic array PFD scanclk Serial clock signal for the real-time PLL control feature Logic array Reconfiguration circuit scandata Serial input data stream for the real-time PLL control feature Logic array Reconfiguration circuit scanaclr Serial shift register reset clearing all registers in the serial shift chain⎯active high Logic array Reconfiguration circuit 1–8 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–5. Enhanced PLL Output Signals Port Description Source Destination clk[5..0] PLL outputs driving regional or global clock PLL counter Internal Clock pll_out[3..0]p/n pll_out[3..0] are PLL outputs driving the four PLL counter Pin(s) differential or eight single-ended external clock output pins for PLLs 5 or 6. p or n are the positive (p) and negative (n) pins for differential pins. extclk4 PLL output driving external clock output pin from PLLs 11 and 12 clkloss Signal indicating the switchover circuit detected a PLL switchover condition switchover circuit Logic array clkbad[1..0] Signals indicating which reference clock is no longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status PLL switchover circuit Logic array locked Lock output from lock detect circuit⎯active high PLL lock detect Logic array activeclock Signal to indicate which clock (1 = inclk0 or 0 = inclk1) is driving the PLL. PLL clock multiplexer Logic array scandataout Output of the last shift register in the scan chain PLL scan chain Logic array PLL g0 counter Pin Clock Multiplication & Division Each Stratix and Stratix GX device enhanced PLL provides clock synthesis for PLL output ports using m/(n × post-scale counter) scaling factors. The input clock is divided by a pre-scale counter, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN × (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale counters scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, then the Quartus II software sets the VCO to 330 MHz (the least common multiple of 33 and 66 MHz within the VCO range). There is one pre-scale counter, n, and one multiply counter, m, per PLL, with a range of 1 to 512 on each. There are two post-scale counters (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. The post-scale counters Altera Corporation July 2005 1–9 Stratix Device Handbook, Volume 2 Enhanced PLLs range from 1 to 512 with any non-50% duty cycle setting. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the altpll MegaWizard Plug-In Manager. External Clock Outputs Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 1–5. 1–10 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–5. External Clock Outputs for PLLs 5 & 6 From IOE (1), (2) pll_out0p (3), (4) (3) e0 Counter From IOE (1) From IOE (1) pll_out0n (3), (4) pll_out1p (3), (4) e1 Counter 4 From IOE (1) From IOE (1) pll_out1n (3), (4) pll_out2p (3), (4) e2 Counter pll_out2n (3), (4) From IOE (1) From IOE (1) pll_out3p (3), (4) e3 Counter From IOE (1) pll_out3n (3), (4) Notes to Figure 1–5: (1) (2) (3) (4) LE: logic element. The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter⎯either two outputs of the same frequency and phase or one shifted 180° . EP1S10, EP1S20, and EP1S25 devices in 672-pin ball grid array (BGA) and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n). Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each Altera Corporation July 2005 1–11 Stratix Device Handbook, Volume 2 Enhanced PLLs pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock’s overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180° out of phase. The Quartus II software transfers the NOT gate in the design into the IOE to implement 180° phase with respect to the other pin in the pair. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, PCML, HyperTransportTM technology, differential HSTL, and differential SSTL. Table 1–6 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, one power pin supports two differential or four single-ended pins. Both outputs use the same standards in single-ended mode to maintain performance. You can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed. The enhanced PLL can also drive out to any regular I/O pin through the global or regional clock network. The jitter on the output clock is not guaranteed for this case. Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK LVTTL v v v v LVCMOS v v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v v v 3.3-V PCI-X 1.0 v v v LVPECL v v v PCML v v v LVDS v v v HyperTransport technology v v v Differential HSTL v v v Differential SSTL 3.3-V GTL 1–12 Stratix Device Handbook, Volume 2 v v v Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK 3.3-V GTL+ v v v 1.5-V HSTL Class I v v v 1.5-V HSTL Class II v v v 1.8-V HSTL Class I v v v 1.8-V HSTL Class II v v v SSTL-18 Class I v v v SSTL-18 Class II v v v SSTL-2 Class I v v v SSTL-2 Class II v v v SSTL-3 Class I v v v SSTL-3 Class II v v v AGP (1× and 2×) v v v CTT v v v Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 1–6). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 1–6. External Clock Outputs for Enhanced PLLs 11 & 12 g0 Counter CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1) From Internal Logic or IOE Note to Figure 1–6: (1) For PLL11, this pin is CLK13n; for PLL 12 this pin is CLK6n. Altera Corporation July 2005 1–13 Stratix Device Handbook, Volume 2 Enhanced PLLs Stratix and Stratix GX devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases. Clock Feedback The following three feedback modes in Stratix and Stratix GX device enhanced PLLs allow multiplication and/or phase shifting: ■ ■ ■ ■ Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. Altera recommends using the same I/O standard on the input clock and the output clocks for optimum performance. External feedback: The external feedback input pin, FBIN, is phasealigned with the clock input, CLK, pin. Aligning these clocks allows you to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one encounter feeds back to the PLL FBIN input, becoming part of the feedback loop. Normal mode: If an internal clock is used in this mode, it is phasealigned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. No compensation: In this mode, the PLL does not compensate for any clock networks or external clock outputs. Table 1–7 shows which modes are supported by which PLL type. Table 1–7. Clock Feedback Mode Availability Mode Available in Clock Feedback Mode Enhanced PLLs Fast PLLs Yes Yes Normal Mode Yes Yes Zero delay buffer mode Yes No External feedback mode Yes No No compensation mode Phase Shifting Stratix and Stratix GX device enhanced PLLs provide advanced programmable phase shifting. You set these parameters in the Quartus II software. 1–14 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Phase Delay The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. You enter a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. For phase shifting, enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. This resolution is a function of frequency input and the multiplication and division factors (that is, it is a function of the VCO period), with the finest step being equal to an eighth (× 0.125) of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps for individual fine-step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse-shift selection in steps of one VCO period. The combination of coarse and fine shifts allows phase shifting for the entire input clock period. The equation to determine the precision of the phase shifting in degrees is: 45° ÷ post-scale counter value. Therefore, the maximum step size is 45° , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. Lock Detect The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. You may need to gate the lock signal for use as a system control. The lock signal from the locked port can drive the logic array or an output pin. Whenever the PLL loses lock for any reason (be it excessive inclk jitter, clock switchover, PLL reconfiguration, power supply noise, etc.), the PLL must be reset with the areset signal to guarantee correct phase relationship between the PLL output clocks. If the phase relationship between the input clock versus output clock, and between different output clocks from the PLL is not important in your design, the PLL need not be reset. f Altera Corporation July 2005 See the Stratix FPGA Errata Sheet for more information on implementing the gated lock signal in your design. 1–15 Stratix Device Handbook, Volume 2 Enhanced PLLs Programmable Duty Cycle The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale counters. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. The precision of the duty cycle is determined by the post-scale counter value chosen on an output. The precision is defined by 50% divided by the postscale counter value. The closest value to 100% is not achievable for a given counter value. For example, if the g0 counter is 10, then steps of 5% are possible for duty cycle choices between 5 to 90%. If the device uses external feedback, you must set the duty cycle for the counter driving off the device to 50%. General Advanced Clear & Enable Control There are several control signals for clearing and enabling PLLs and PLL outputs. You can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true: ■ ■ PLL reconfiguration or clock switchover enables in the design Phase relationships between output clocks need to be maintained after a loss of lock condition The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO sets back to its nominal setting (~700 MHz). When driven low again, the PLL resynchronizes to its input as it relocks. If the target VCO frequency is below this nominal 1–16 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices frequency, then the output frequency starts at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system continues running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. You can either use your own control signal or a clkloss status signal to trigger pdfena. The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 1–7 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the looprelated counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization. The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Altera Corporation July 2005 1–17 Stratix Device Handbook, Volume 2 Enhanced PLLs Figure 1–7. extclkena Signals COUNTER OUTPUT CLKENA CLKOUT Programmable Bandwidth Enhanced PLLs provide advanced control of the PLL bandwidth using the programmable characteristics of the PLL loop, including loop filter and charge pump. Background The PLL bandwidth is the measure of the PLLs ability to track the input clock and jitter. It is determined by the −3-dB frequency of the closed-loop gain in the PLL or approximately the unity gain point for open loop PLL response. As Figure 1–8 shows, these points correspond to approximately the same frequency. 1–18 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–8. Open- & Closed-Loop Response Bode Plots Open-Loop Reponse Bode Plot Increasing the PLL's bandwidth in effect pushes the open loop response out. 0 dB Gain Frequency Closed-Loop Reponse Bode Plot Gain Frequency A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A lowbandwidth PLL filters out reference clock jitter, but increases lock time. Stratix device enhanced PLLs allow you to control the bandwidth over a Altera Corporation July 2005 1–19 Stratix Device Handbook, Volume 2 Enhanced PLLs finite range to customize the PLL characteristics for a particular application. Applications that require clock switchover (such as TDMA, frequency hopping wireless, and redundant clocking) can benefit from the programmable bandwidth feature of the Stratix and Stratix GX PLLs. The bandwidth and stability of such a system is determined by a number of factors including the charge pump current, the loop filter resistor value, the high-frequency capacitor value (in the loop filter), and the mcounter value. You can use the Quartus II software to control these factors and to set the bandwidth to the desired value within a given range. You can set the bandwidth to the appropriate value to balance the need for jitter filtering and lock time. Figures 1–9 and 1–10 show the output of a low- and high-bandwidth PLL, respectively, as it locks onto the input clock. Figure 1–9. Low-Bandwidth PLL Lock Time 160 155 Lock Time = 8 μs 150 145 Frequency (MHz) 140 135 130 125 120 0 5 10 15 Time (μs) 1–20 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–10. High-Bandwidth PLL Lock Time 160 155 Lock Time = 4 μs 150 145 Frequency (MHz) 140 135 130 125 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (μs) A high-bandwidth PLL may benefit a system with two cascaded PLLs. If the first PLL uses spread spectrum (as user-induced jitter), the second PLL needs a high bandwidth so it can track the jitter that is feeding it. A low-bandwidth PLL may, in this case, lose lock due to the spread spectrum-induced jitter on the input clock. A low-bandwidth PLL may benefit a system using clock switchover. When the clock switchover happens, the PLL input temporarily stops. A low-bandwidth PLL would react more slowly to changes to its input clock and take longer to drift to a lower frequency (caused by the input stopping) than a high-bandwidth PLL. Figures 1–11 and 1–12 demonstrate this property. The two plots show the effects of clock switchover with a low- or highbandwidth PLL. When the clock switchover happens, the output of the low-bandwidth PLL (see Figure 1–11) drifts to lower frequency much slower than the high-bandwidth PLL output (see Figures 1–12). Altera Corporation July 2005 1–21 Stratix Device Handbook, Volume 2 Enhanced PLLs Figure 1–11. Effect of Low Bandwidth on Clock Switchover 164 162 160 158 Frequency (MHz) Input Clock Stops Re-lock 156 Initial Lock 154 152 Switchover 150 0 5 10 15 20 25 30 35 40 Time (μs) 1–22 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–12. Effect of High Bandwidth on Clock Switchover 160 Input Clock Stops Re-lock 155 Initial Lock 150 145 Frequency (MHz) 140 135 Switchover 130 125 0 2 4 6 8 10 12 14 16 18 20 Time (μs) Implementation Traditionally, external components such as the VCO or loop filter control a PLL’s bandwidth. Most loop filters are made up of passive components, such as resistors and capacitors, which take up unnecessary board space and increase cost. With Stratix and Stratix GX device enhanced PLLs, all the components are contained within the device to increase performance and decrease cost. Stratix and Stratix GX device enhanced PLLs implement programmable bandwidth by giving you control of the charge pump current and loop filter resistor (R) and high-frequency capacitor (Ch) values (see Table 1–8). The Stratix and Stratix GX device enhanced PLL bandwidth ranges from approximately 150 kHz to 2 MHz. Altera Corporation July 2005 1–23 Stratix Device Handbook, Volume 2 Enhanced PLLs The charge pump current directly affects the PLL bandwidth. The higher the charge pump current, the higher the PLL bandwidth. You can choose from a fixed set of values for the charge pump current. Figure 1–13 shows the loop filter and the components that you can set via the Quartus II software. Figure 1–13. Loop Filter Programmable Components IUP PFD R Ch IDN C Software Support The Quartus II software provides two levels of programmable bandwidth control. The first level allows you to enter a value for the desired bandwidth directly into the Quartus II software using the MegaWizard® Plug-In Manager. Alternatively, you can set the bandwidth parameter in the altpll function to the desired bandwidth. The Quartus II software then chooses each individual bandwidth parameter to achieve the desired setting. If designs cannot achieve the desired bandwidth setting, the Quartus II software selects the closest achievable value. For preset low, medium, and high bandwidth settings, the Quartus II software sets the bandwidth as follows: ■ ■ ■ Low bandwidth is set at 150 KHz Medium bandwidth is set at 800 KHz High bandwidth is set at 2 Mhz If you choose Auto bandwidth, the Quartus II software chooses the PLL settings and you can get a bandwidth setting outside the 150-Khz to 2-Mhz range. 1–24 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices An advanced level of control is also possible for precise control of the loop filter parameters. This level allows you to specifically select the charge pump current, loop filter resistor value, and loop filter (high frequency) capacitor value. These parameters are: charge_pump_current, loop_filter_r, and loop_filter_c. Each parameter supports the specific range of values listed in Table 1–8. Table 1–8. Advanced Loop Filter Parameters Parameter f Values Resistor values (kΩ) 1, 2, 3, 4, 7, 8, 9, 10 High-frequency capacitance values (pF) 5, 10, 15, 20 Charge pump current settings (μA) 10, 15, 20, 24, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 100, 112, 135, 148, 164, 212 For more information on PLL software support in the Quartus II software, see the altpll Megafunction User Guide. Clock Switchover f For more information on implementing clock switchover, see AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices. Spread-Spectrum Clocking Digital clocks are generally square waves with short rise times and a 50% duty cycle. These high-speed digital clocks concentrate a significant amount of energy in a narrow bandwidth at the target frequency and at the higher frequency harmonics. This results in high energy peaks and increased electromagnetic interference (EMI). The radiated noise from the energy peaks travels in free air and, if not minimized, can lead to corrupted data and intermittent system errors, which can jeopardize system reliability. Background Traditional methods for limiting EMI include shielding, filtering, and multi-layer printed circuit boards (PCBs). However, these methods significantly increase the overall system cost and sometimes are not enough to meet EMI compliance. Spread-spectrum technology provides a simple and effective technique for reducing EMI emissions without additional cost and the trouble of re-designing a board. Altera Corporation July 2005 1–25 Stratix Device Handbook, Volume 2 Enhanced PLLs Spread-spectrum technology modulates the target frequency over a small range. For example, if a 100-MHz signal has a 0.5% down-spread modulation, then the frequency is swept from 99.5 to 100 MHz. Figure 1–14 gives a graphical representation of the energy present in a spread-spectrum signal as opposed to a non-spread-spectrum signal. It is apparent that instead of concentrating the energy at the target frequency, the energy is re-distributed across a wider band of frequencies, which reduces peak energy. Not only is there a reduction in the fundamental peak EMI components, but there is also a reduction in EMI of the higher order harmonics. Since some regulations focus on peak EMI emissions, rather than average EMI emissions, spread-spectrum technology is a valuable method of EMI reduction. Figure 1–14. Spread-Spectrum Signal Energy versus Non-Spread-Spectrum Signal Energy Spread-Spectrum Signal Non-Spread-Spectrum Signal Δ = ~5 dB Amplitude (dB) δ = 0.5% Frequency (MHz) Spread-spectrum technology would benefit a design with high EMI emissions and/or strict EMI requirements. Device-generated EMI is dependent on frequency, output voltage swing amplitude, and slew rate. For example, a design using LVDS already has low EMI emissions 1–26 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices because of the low-voltage swing. The differential LVDS signal also allows for EMI rejection within the signal. Therefore, this situation may not require spread-spectrum technology. Description Stratix and Stratix GX device enhanced PLLs feature spread-spectrum technology to reduce the EMI emitted from the device. The enhanced PLL provides up to a 0.5% down spread (–0.5%) using a triangular, also known as linear, modulation profile. The modulation frequency is programmable and ranges from approximately 30 to 150 kHz. The spread percentage is based on the clock input to the PLL and the m and n settings. Spread-spectrum technology reduces the peak energy by 2 to 5 dB at the target frequency. However, this number is dependent on bandwidth and the m and n counter values and can vary from design to design. Spread percentage, also known as modulation width, is defined as the percentage that the design modulates the target frequency. A negative (–) percentage indicates a down spread, a positive (+) percentage indicates an up spread, and a (±) indicates a center spread. Modulation frequency is the frequency of the spreading signal or how fast the signal sweeps from the minimum to the maximum frequency. Down-spread modulation shifts the target frequency down by half the spread percentage, centering the modulated waveforms on a new target frequency. The m and n counter values are toggled at the same time between two fixed values. The loop filter then slowly changes the VCO frequency to provide the spreading effect, which results in a triangular modulation. An additional spread-spectrum counter (shown in Figure 1–15) sets the modulation frequency. Figure 1–15 shows how spread-spectrum technology is implemented in the Stratix device enhanced PLL. Altera Corporation July 2005 1–27 Stratix Device Handbook, Volume 2 Enhanced PLLs Figure 1–15. Spread-Spectrum Circuit Block Diagram ÷n refclk Up PFD Down Spread Spectrum Counter ÷m n count1 n count2 m count2 m count1 Figure 1–16 shows a VCO frequency waveform when toggling between different counter values. Since the enhanced PLL switches between two different m and n values, the result is a straight line between two frequencies, which gives a linear modulation. The magnitude of modulation is determined by the ratio of two m/n sets. The percent spread is determined by: percent spread = (fVCOmax −fVCOmin)/fVCOmax = 1 −[(m2 × n1)/(m1 × n2)] The maximum and minimum VCO frequency is defined as: fVCOmax = (m1/n1) × fref fVCOmin = (m2/n2) × fref 1–28 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–16. VCO Frequency Modulation Waveforms count2 values count1 values VCO Frequency Software Support You can enter the desired down-spread percentage and modulation frequency in the MegaWizard Plug-In Manager through the Quartus II software. Alternatively, the MegaWizard Plug-In Manager can set the downspread parameter in the altpll megafunction to the desired down-spread percentage. Timing analysis ensures the design operates at the maximum spread frequency and meets all timing requirements. f For more information on PLL software support in the Quartus II software, see the altpll Megafunction User Guide. Guidelines If the design cascades PLLs, the source, or upstream PLL should have a low bandwidth setting, while the destination, or downstream PLL should have a high bandwidth setting. The upstream PLL must have a low bandwidth setting because a PLL does not generate jitter higher than its bandwidth. The downstream PLL must have a high bandwidth setting to track the jitter. The design must use the spread-spectrum feature in a lowbandwidth PLL and, therefore, the Quartus II software automatically sets the spread-spectrum PLL’s bandwidth to low. 1 Designs cannot use spread-spectrum PLLs with the programmable bandwidth feature. Stratix and Stratix GX devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the downstream PLL. Spread spectrum should only have a minor effect on period jitter, but period jitter increases. Period jitter is the deviation of a clock’s cycle time from its previous cycle position. Period jitter measures the variation of a clock’s output transition from its ideal position over consecutive edges. Altera Corporation July 2005 1–29 Stratix Device Handbook, Volume 2 Enhanced PLLs With down-spread modulation, the peak of the modulated waveform is the actual target frequency. Therefore, the system never exceeds the maximum clock speed. To maintain reliable communication, the entire system/subsystem should use the Stratix or Stratix GX device as the clock source. Communication could fail if the Stratix or Stratix GX logic array is clocked by the spread-spectrum clock, but the data it receives from another device is not. Since spread spectrum affects the m counter values, all spread-spectrum PLL outputs are affected. Therefore, if only one spread-spectrum signal is needed, the clock signal should use a separate PLL without other outputs from that PLL. No special considerations are needed when using spread spectrum with the clock switchover feature. This is because the clock switchover feature does not affect the m and n counter values, which are the counter values that are switching when using spread spectrum. PLL Reconfiguration f See AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices for information on PLL reconfiguration. Enhanced PLL Pins Table 1–9 shows the physical pins and their purpose for the Enhanced PLLs. For inclk port connections to pins see “Clocking” on page 1–39. Table 1–9. Enhanced PLL Pins (Part 1 of 2) Pin Description CLK4p/n Single-ended or differential pins that can drive the inclk port for PLL 6. CLK5p/n Single-ended or differential pins that can drive the inclk port for PLL 6. CLK6p/n Single-ended or differential pins that can drive the inclk port for PLL 12. CLK7p/n Single-ended or differential pins that can drive the inclk port for PLL 12. CLK12p/n Single-ended or differential pins that can drive the inclk port for PLL 11. CLK13p/n Single-ended or differential pins that can drive the inclk port for PLL 11. CLK14p/n Single-ended or differential pins that can drive the inclk port for PLL 5. CLK15p/n Single-ended or differential pins that can drive the inclk port for PLL 5. PLL5_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 5. PLL6_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 6. PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use this pin, connect it to ground. 1–30 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–9. Enhanced PLL Pins (Part 2 of 2) Pin Description PLL5_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 5. PLL6_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 6. PLL11_OUT, CLK13n Single-ended output pin driven by clk0 port from PLL 11. PLL12_OUT, CLK6n Single-ended output pin driven by clk0 port from PLL 12. VCCA_PLL5 Analog power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL5 Guard ring power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL5 Analog ground for PLL 5. You can connect this pin to the GND plane on the board. GNDG_PLL5 Guard ring ground for PLL 5. You can connect this pin to the GND plane on the board. VCCA_PLL6 Analog power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL6 Guard ring power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL6 Analog ground for PLL 6. You can connect this pin to the GND plane on the board. GNDG_PLL6 Guard ring ground for PLL 6. You can connect this pin to the GND plane on the board. VCCA_PLL11 Analog power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL11 Guard ring power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL11 Analog ground for PLL 11. You can connect this pin to the GND plane on the board. GNDG_PLL11 Guard ring ground for PLL 11.You can connect this pin to the GND plane on the board. VCCA_PLL12 Analog power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL12 Guard ring power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL12 Analog ground for PLL 12. You can connect this pin to the GND plane on the board. GNDG_PLL12 Guard ring ground for PLL 12. You can connect this pin to the GND plane on the board. VCC_PLL5_OUTA External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p, and PLL5_OUT1n outputs from PLL 5. VCC_PLL5_OUTB External clock output VCCIO power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p, and PLL5_OUT3n outputs from PLL 5. VCC_PLL6_OUTA External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p, and PLL5_OUT1n outputs from PLL 6. VCC_PLL6_OUTB External clock output VCCIO power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p, and PLL5_OUT3n outputs from PLL 6. Fast PLLs Altera Corporation July 2005 Stratix devices contain up to eight fast PLLs and Stratix GX devices contain up to four fast PLLs. Both device PLLs have high-speed differential I/O interface ability along with general-purpose features. Figure 1–17 shows a diagram of the fast PLL. This section discusses the 1–31 Stratix Device Handbook, Volume 2 Fast PLLs general purpose abilities of the Fast PLL. For information on the highspeed differential I/O interface capabilities, see the High-Speed Differential I/O Interfaces in Stratix Devices chapter. Figure 1–17. Stratix & Stratix GX Fast PLL Block Diagram Post-Scale Counters diffioclk1 (2) ÷l0 VCO Phase Selection Selectable at each PLL Output Port Global or regional clock (1) Clock Input Phase Frequency Detector Global or regional clock txload_en (3) rxload_en (3) ÷l1 Global or regional clock diffioclk2 (2) PFD Charge Pump 8 Loop Filter VCO ÷g0 Global or regional clock ÷m Notes to Figure 1–17: (1) (2) (3) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin. It cannot be driven by internally-generated global signals. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix and Stratix GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal. 1–32 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–18 shows all possible ports related to fast PLLs. Figure 1–18. Fast PLL Ports & Physical Destinations Fast PLL Signals (1) pllena (2) inclk0 clk[2..0] locked areset pfdena Physical Pin Signal Driven by Internal Logic Signal Driven to Internal Logic Internal Clock Signal Notes to Figure 1–18: (1) (2) This input pin is shared by all enhanced and fast PLLs. This input pin is either single-ended or differential. Tables 1–10 and 1–11 show the description of all fast PLL ports. Table 1–10. Fast PLL Input Signals Name Description Source Destination inclk1 Reference clock input to PLL Pin PFD pllena Enable pin for enabling or disabling all or a set of PLLs – active high Pin PLL control signal areset Signal used to reset the PLL which resynchronizes all the counter outputs⎯active high Logic array PLL control signal pfdena Enables the up/down outputs from the phasefrequency detector⎯active high Logic array PFD Table 1–11. Fast PLL Output Signals Name Description Source Destination clk[2..0] PLL outputs driving regional or global clock PLL counter Internal clock locked Lock output from lock detect circuit⎯active high PLL lock detect Logic array Altera Corporation July 2005 1–33 Stratix Device Handbook, Volume 2 Fast PLLs Clock Multiplication & Division Stratix and Stratix GX device fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply counter, m, per fast PLL with a range of 1 to 32. There are three post-scale counters (g0, l0, and l1) for the regional and global clock output ports. All post-scale counters range from 1 to 32. If the design uses a high-speed serial interface, you can set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES. External Clock Outputs Each fast PLL supports differential or single-ended outputs for sourcesynchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. The fast PLL global or regional outputs can drive any I/O pin as an external clock output pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank. See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device Handbook, Volume 2 for output standard support. Table 1–12 shows the I/O standards supported by fast PLL input pins. Table 1–12. Fast PLL Port I/O Standards (Part 1 of 2) Input I/O Standard INCLK PLLENABLE LVTTL v v LVCMOS v v 2.5 V v 1.8 V v 1.5 V v 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL v PCML v LVDS v HyperTransport technology v Differential HSTL v 1–34 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–12. Fast PLL Port I/O Standards (Part 2 of 2) Input I/O Standard INCLK PLLENABLE Differential SSTL 3.3-V GTL 3.3-V GTL+ v 1.5-V HSTL Class I v 1.5-V HSTL Class II 1.8-V HSTL Class I v 1.8-V HSTL Class II SSTL-18 Class I v SSTL-18 Class II SSTL-2 Class I v SSTL-2 Class II v SSTL-3 Class I v SSTL-3 Class II v AGP (1× and 2×) CTT v Phase Shifting Stratix and Stratix GX device fast PLLs have advanced clock shift ability to provide programmable phase shift. These parameters are set in the Quartus II software. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. Enter a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. You can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can perform phase shifting in time units with a resolution range of 125 to 416.66 ps to create a function of frequency input and the multiplication and division factors (that is, it is a function of the VCO period), with the finest step being equal to an eighth (× 0.125) of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps for individual fine-step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse and grain shifts allows phase shifting for the entire input clock period. Altera Corporation July 2005 1–35 Stratix Device Handbook, Volume 2 Fast PLLs The equation to determine the precision of phase in degrees is: 45° ÷ postscale counter value. Therefore, the maximum step size is 45° , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. Programmable Duty Cycle The programmable duty cycle allows the fast PLL to generate clock outputs with a variable duty cycle. This feature is supported on each fast PLL post-scale counter. g0, l0, and l1 all support programmable duty. You use a low- and high-time count setting for the post-scale counters to set the duty cycle. The Quartus II software uses the frequency input and multiply/divide rate desired to select the post-scale counter, which determines the possible choices for each duty cycle. The precision of the duty cycle is determined by the post-scale counter value chosen on an output. The precision is defined by 50% divided by the post-scale counter value. The closest value to 100% is not achievable for a given counter value. For example, if the g0 counter is 10, then steps of 5% are possible for duty cycle choices between 5 to 90%. If the device uses external feedback, you must set the duty cycle for the counter driving off the device to 50%. Control Signals The lock output indicates a stable clock output signal in phase with the reference clock. Unlike enhanced PLLs, fast PLLs do not have a lock filter counter. The pllenable pin is a dedicated pin that enables/disables both PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each fast PLL. The Stratix and Stratix GX devices can drive these input signals from an input pin or from LEs. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO sets back to its nominal setting (~700 MHz). When driven low again, the PLL 1–36 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices resynchronizes to its input clock as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency starts at a higher value then desired as it locks. The pfdena signals control the PFD output with a programmable gate. If you disable the PFD, the VCO operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system continues running when the PLL goes out of lock or the input clock disables. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. If the PLL loses lock for any reason (for example, because of excessive inclk jitter, clock switchover, PLL reconfiguration, or power supply noise), the PLL must be reset with the areset signal to guarantee correct phase relationship between the PLL output clocks. If the phase relationship between the input clock and the output clock and between different output clocks from the PLL is not important in your design, it is not necessary to reset the PLL. Pins Table 1–13 shows the physical pins and their purpose for the Fast PLLs. For inclk port connections to pins see “Clocking” on page 1–39. Table 1–13. Fast PLL Pins (Part 1 of 3) Pin Description CLK0p/n Single-ended or differential pins that can drive the inclk port for PLL 1 or 7. CLK1p/n Single-ended or differential pins that can drive the inclk port for PLL 1. CLK2p/n Single-ended or differential pins that can drive the inclk port for PLL 2 or 8. CLK3p/n Single-ended or differential pins that can drive the inclk port for PLL 2. CLK8p/n Single-ended or differential pins that can drive the inclk port for PLL 3 or 9. (1) CLK9p/n Single-ended or differential pins that can drive the inclk port for PLL 3. (1) CLK10p/n Single-ended or differential pins that can drive the inclk port for PLL 4 or 10. (1) CLK11p/n Single-ended or differential pins that can drive the inclk port for PLL 4. (1) FPLL7CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 7. FPLL8CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 8. FPLL9CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 9. (1) FPLL10CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 10. (1) PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use this pin, connect it to ground. VCCA_PLL1 Analog power for PLL 1. Connect this pin to 1.5 V, even if the PLL is not used. Altera Corporation July 2005 1–37 Stratix Device Handbook, Volume 2 Fast PLLs Table 1–13. Fast PLL Pins (Part 2 of 3) Pin Description VCCG_PLL1 Guard ring power for PLL 1. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL1 Analog ground for PLL 1. You can connect this pin to the GND plane on the board. GNDG_PLL1 Guard ring ground for PLL 1. You can connect this pin to the GND plane on the board. VCCA_PLL2 Analog power for PLL 2. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL2 Guard ring power for PLL 2. Connect this pin to1.5 V, even if the PLL is not used. GNDA_PLL2 Analog ground for PLL 2. You can connect this pin to the GND plane on the board. GNDG_PLL2 Guard ring ground for PLL 2. You can connect this pin to the GND plane on the board. VCCA_PLL3 Analog power for PLL 3. Connect this pin to 1.5 V, even if the PLL is not used. (1) VCCG_PLL3 Guard ring power for PLL 3. Connect this pin to 1.5 V, even if the PLL is not used. (1) GNDA_PLL3 Analog ground for PLL 3. You can connect this pin to the GND plane on the board. (1) GNDG_PLL3 Guard ring ground for PLL 3. You can connect this pin to the GND plane on the board. (1) VCCA_PLL4 Analog power for PLL 4. Connect this pin to 1.5 V, even if the PLL is not used. (1) VCCG_PLL4 Guard ring power for PLL 4. Connect this pin to 1.5 V, even if the PLL is not used. (1) GNDA_PLL4 Analog ground for PLL 4. You can connect this pin to the GND plane on the board. (1) GNDG_PLL4 Guard ring ground for PLL 4. You can connect this pin to the GND plane on the board. (1) VCCA_PLL7 Analog power for PLL 7. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL7 Guard ring power for PLL 7. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL7 Analog ground for PLL 7. You can connect this pin to the GND plane on the board. GNDG_PLL7 Guard ring ground for PLL 7. You can connect this pin to the GND plane on the board. VCCA_PLL8 Analog power for PLL 8. Connect this pin to 1.5 V, even if the PLL is not used. VCCG_PLL8 Guard ring power for PLL 8. Connect this pin to 1.5 V, even if the PLL is not used. GNDA_PLL8 Analog ground for PLL 8. You can connect this pin to the GND plane on the board. GNDG_PLL8 Guard ring ground for PLL 8. You can connect this pin to the GND plane on the board. VCCA_PLL9 Analog power for PLL 9. Connect this pin to 1.5 V, even if the PLL is not used. (1) VCCG_PLL9 Guard ring power for PLL 9. Connect this pin to 1.5 V, even if the PLL is not used. (1) 1–38 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–13. Fast PLL Pins (Part 3 of 3) Pin Description GNDA_PLL9 Analog ground for PLL 9. You can connect this pin to the GND plane on the board. (1) GNDG_PLL9 Guard ring ground for PLL 9. You can connect this pin to the GND plane on the board. (1) VCCA_PLL10 Analog power for PLL 10. Connect this pin to 1.5 V, even if the PLL is not used. (1) VCCG_PLL10 Guard ring power for PLL 10. Connect this pin to 1.5 V, even if the PLL is not used. (1) GNDA_PLL10 Analog ground for PLL 10. Connect this pin to the GND plane on the board. (1) GNDG_PLL10 Guard ring ground for PLL 10. You can connect this pin to the GND plane on the board. (1) Note to Table 1–13: (1) PLLs 3, 4, 9, and 10 are not available on Stratix GX devices for general-purpose configuration. These PLLs are part of the HSSI block. See AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices for more information. Clocking Stratix and Stratix GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Global & Hierarchical Clocking Stratix and Stratix GX devices provide 16 dedicated global clock networks, 16 regional clock networks (4 per device quadrant), and 8 dedicated fast regional clock networks. These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within Stratix and Stratix GX devices. There are 16 dedicated clock pins (CLK[15..0]) on Stratix devices and 12 dedicated clock pins (CLK[11..0]) on Stratix GX devices to drive either the global or regional clock networks. Four clock pins drive each side of the Stratix device, as shown in Figures 1–19 and 1–20. On Stratix GX devices, four clock pins drive the top, left, and bottom sides of the device. The clocks on the right side of the device are not available for general-purpose PLLs. Enhanced and fast PLL outputs can also drive the global and regional clock networks. Altera Corporation July 2005 1–39 Stratix Device Handbook, Volume 2 Clocking Global Clock Network These clocks drive throughout the entire device, feeding all device quadrants. All resources within the device—IOEs, LEs, DSP blocks, and all memory blocks—can use the global clock networks as clock sources. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. Internal logic can also drive the global clock networks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 1–19 shows the 16 dedicated CLK pins driving global clock networks. Figure 1–19. Global Clocking CLK[15..12] Global Clock [15..0] CLK[3..0] Global Clock [15..0] CLK[11..8] CLK[7..4] Regional Clock Network There are four regional clock networks within each quadrant of the Stratix or Stratix GX device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and 1–40 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices RCLK[12..15] are in the bottom-right quadrant. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. RCLK clock networks cannot be driven by internal logic. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 1–20. See Figures 1–21 and 1–22 for RCLK connections from PLLs and CLK pins. Figure 1–20. Regional Clocks RCLK[2..3] RCLK[11..10] CLK[15..12] RCLK[9..8] RCLK[1..0] CLK[3..0] CLK[11..8] RCLK[14..15] RCLK[4..5] CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant RCLK[6..7] RCLK[12..13] Clock Input Connections Two CLK pins drive each enhanced PLL. You can use either one or both pins for clock switchover inputs into the PLL. Either pin can be the primary clock source for clock switchover, which is controlled in the Quartus II software. Enhanced PLLs 5 and 6 also have feedback input pins as shown in Table 1–14. Altera Corporation July 2005 1–41 Stratix Device Handbook, Volume 2 Clocking Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. Stratix GX devices use PLLs 3 and 4 in the HSSI block only. A multiplexer chooses one of two possible CLK pins to drive each PLL. This multiplexer is not a clock switchover multiplexer and is only used for clock input connectivity. Either a FPLLCLK input pin or a CLK pin can drive the fast PLLs in the corners (7, 8, 9, and 10) when used for general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode. PLLs 9 and 10 are used for the HSSI block in Stratix GX devices and are not available. Table 1–14 shows which PLLs are available for each Stratix device and which input clock pin drives which PLLs. Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 1 of 2) EP1S30, EP1S40, EP1S60 & EP1S80 Devices Only All Stratix Devices Clock Input Pins EP1S40 (3), EP1S60 & EP1S80 Devices Only PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL 9 PLL PLL PLL (1) (1) (1) (1) (2) (2) (1) (1) (1) 10 (1) 11 (2) 12 (2) CLK0p/n v CLK1p/n v v CLK2p/n v CLK3p/n v v CLK4p/n v CLK5p/n v CLK6p/n v CLK7p/n v CLK8p/n v CLK9p/n v v CLK10p/n v CLK11p/n v v CLK12p/n v CLK13p/n v CLK14p/n v CLK15p/n v 1–42 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 2 of 2) EP1S30, EP1S40, EP1S60 & EP1S80 Devices Only All Stratix Devices Clock Input Pins EP1S40 (3), EP1S60 & EP1S80 Devices Only PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL 9 PLL PLL PLL (1) (1) (1) (1) (2) (2) (1) (1) (1) 10 (1) 11 (2) 12 (2) v FPll7clk v FPll8clk v FPll9clk v FPll10clk Clock Feedback Input Pins Pll5_fbp/n Pll6_fbp/n v v Notes to Table 1–14: (1) (2) (3) This is a fast PLL. The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. This is an enhanced PLL. The EP1S40 device in the F780 package does not support PLLs 11 and 12. Clock Output Connections Enhanced PLLs have outputs for two regional clock outputs and four global outputs. There is line sharing between clock pins, global and regional clock networks and all PLL outputs. Check Tables 1–15 and 1–16 and Figures 1–21 and 1–22 to make sure that the clocking scheme is valid. The Quartus II software automatically maps to regional and global clocks to avoid any restrictions. Enhanced PLLs 5 and 6 drive out to singleended pins as shown in Table 1–15. PLLs 11 and 12 drive out to singleended pins. You can connect each fast PLL 1, 2, 3, or 4 outputs (g0, l0, and l1) to either a global or a regional clock. (PLLs 3 and 4 are not available on Stratix GX devices.) There is line sharing between clock pins, FPLLCLK pins, global and regional clock networks and all PLL outputs. Check Figures 1–21 and 1–22 to make sure that the clocking is valid. The Quartus II software automatically maps to regional and global clocks to avoid any restrictions. Altera Corporation July 2005 1–43 Stratix Device Handbook, Volume 2 Clocking Table 1–15 shows the global and regional clocks that each PLL drives outputs to for Stratix devices. Table 1–16 shows the global and regional clock network each of the CLK and FPLLCLK pins drive when bypassing the PLL. Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 1 of 2) EP1S30, EP1S40, EP1S60 & EP1S80 Devices Only All Devices Clock Network EP1S40 (5), EP1S60 & EP1S80 Devices Only PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL PLL PLL PLL (1) (1) (1) (1) (2) (2) (1) (1) 9 (1) 10 (1) 11 (2) 12 (2) GCLK0 v v v v GCLK1 v v v v GCLK2 v v v v GCLK3 v v v v GCLK4 v v GCLK5 v v GCLK6 v v GCLK7 v v GCLK8 v v v v GCLK9 v v v v GCLK10 v v v v GCLK11 v v v v GCLK12 v v GCLK13 v v GCLK14 v v GCLK15 v v RCLK0 v v v RCLK1 v v v RCLK2 v v RCLK3 v v RCLK4 v v v RCLK5 v v v 1–44 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 2 of 2) EP1S30, EP1S40, EP1S60 & EP1S80 Devices Only All Devices Clock Network EP1S40 (5), EP1S60 & EP1S80 Devices Only PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL PLL PLL PLL (1) (1) (1) (1) (2) (2) (1) (1) 9 (1) 10 (1) 11 (2) 12 (2) RCLK6 v v RCLK7 v v RCLK8 v v v RCLK9 v v v RCLK10 v v RCLK11 v v RCLK12 v v RCLK13 v v RCLK14 v v v RCLK15 v v v External Clock Output PLL5_OUT [3..0]p/n PLL6_OUT [3..0]p/n v v PLL11_OUT v (3) PLL12_OUT v (4) Notes to Table 1–15: (1) (2) (3) (4) (5) This is a fast PLL. This is an enhanced PLL. This pin is a tri-purpose pin; it can be an I/O pin, CLK13n, or used for PLL 11 output. This pin is a tri-purpose pin; it can be an I/O pin, CLK7n, or used for PLL 12 output. The EP1S40 device in the F780 package does not support PLLs 11 and 12. Altera Corporation July 2005 1–45 Stratix Device Handbook, Volume 2 Clocking Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1) CLK Pins FPLLCLK (2) Clock Network 0 GCLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v v v v GCLK4 v GCLK5 v GCLK6 v GCLK7 v GCLK8 v v v GCLK9 v v v GCLK10 v v v GCLK11 v v v GCLK12 v GCLK13 v GCLK14 v GCLK15 v v v v v RCLK2 RCLK5 v v RCLK3 RCLK4 10 v v v GCLK3 RCLK1 9 v v v GCLK2 RCLK0 8 v v v GCLK1 7 v v v RCLK6 RCLK7 v v v RCLK8 v RCLK9 v v RCLK11 1–46 Stratix Device Handbook, Volume 2 v v RCLK10 RCLK12 v v v Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1) CLK Pins FPLLCLK (2) Clock Network 0 RCLK13 RCLK14 RCLK15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 8 9 10 v v v Notes to Table 1–16: (1) (2) The CLK and FPLLCLK pins cannot drive. The FPLLCLK pin is only available in EP1S80, EP1S60, EP1S40, and EP1S30 devices. The fast PLLs also drive high-speed SERDES clocks for differential I/O interfacing. For information on these FPLLCLK pins, see the High-Speed Differential I/O Interfaces in Stratix Devices chapter. Figure 1–21 shows the global and regional clock input and output connections from the enhanced. Figure 1–21 shows graphically the same information as Tables 1–15 and 1–16 but with the added detail of where each specific PLL output port drives to. Altera Corporation July 2005 1–47 Stratix Device Handbook, Volume 2 Clocking Figure 1–21. Global & Regional Clock Connections from Side Clock Pins & Fast PLL Outputs RCLK1 RCLK0 FPLL7CLK G3 G1 G0 G2 G8 G9 G10 G11 RCLK9 RCLK8 l0 l0 PLL 7 l1 CLK0 CLK1 g0 g0 l0 l0 PLL 1 l1 l1 PLL 4 g0 CLK2 CLK3 CLK10 CLK11 g0 l02 PLL 2 l1 g0 2l0 l1 PLL 3 g0 l0 FPLL8CLK FPLL10CLK l1 PLL 10 CLK8 CLK9 l0 PLL 8 l1 g0 l1 PLL 9 g0 RCLK4 RCLK5 Regional Clocks FPLL9CLK RCLK14 Global Clocks RCLK15 Regional Clocks Notes to Figures 1–21: (1) (2) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix GX devices and are not available for this use. When using a fast PLL to compensate for clock delays to drive logic on the chip, the clock delay from the input pin to the clock input port of the PLL is compensated only if the clock is fed by the dedicated input pin closest to the PLL. If the fast PLL gets its input clock from a global or regional clock or from another dedicated clock pin, which does not directly feed the fast PLL, the clock signal is first routed onto a global clock network. The signal then drives into the PLL. In this case, the clock delay is not fully compensated and the delay compensation is equal to the clock delay from the dedicated clock pin closest to the PLL to the clock input port of the PLL. For example, if you use CLK0 to feed PLL 7, the input clock path delay is not fully compensated, but if FPLL7CLK feeds PLL 7, the input clock path delay is fully compensated. Figure 1–22 shows the global and regional clock input and output connections from the fast PLLs. Figure 1–22 shows graphically the same information as Tables 1–15 and 1–16 but with the added detail of where each specific PLL output port drives to. 1–48 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–22. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs PLL5_OUT[3..0] CLK14 (1) PLL5_FB CLK15 (2) CLK12 (1) CLK13 (2) E[0..3] PLL 5 PLL 11 L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL11_OUT RCLK10 RCLK11 Regional Clocks RCLK2 RCLK3 G12 G13 G14 G15 Global Clocks Regional Clocks G4 G5 G6 G7 RCLK6 RCLK7 RCLK12 RCLK13 PLL12_OUT L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1 PLL 6 PLL6_OUT[3..0] PLL 12 PLL6_FB CLK4 (1) CLK6 (1) CLK7 (2) CLK5 (2) Notes to Figures 1–22: (1) (2) CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port. CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port. Altera Corporation July 2005 1–49 Stratix Device Handbook, Volume 2 Board Layout Board Layout The enhanced and fast PLL circuits in Stratix and Stratix GX devices contain analog components embedded in a digital device. These analog components have separate power and ground pins to minimize noise generated by the digital components. Both Stratix and Stratix GX enhanced and fast PLLs use separate VCC and ground pins to isolate circuitry and improve noise resistance. VCCA & GNDA Each enhanced and fast PLL uses separate VCC and ground pin pairs for their analog circuitry. The analog circuit power and ground pin for each PLL is called PLL_VCCA and PLL_GNDA. Connect the VCCA power pin to a 1.5-V power supply, even if you do not use the PLL. Isolate the power connected to VCCA from the power to the rest of the Stratix and Stratix GX device or any other digital device on the board. You can use one of three different methods of isolating the VCCA pin: separate VCCA power planes, a partitioned VCCA island within the VCCINT plane, and thick VCCA traces. Separate VCCA Power Plane A mixed signal system is already partitioned into analog and digital sections, each with its own power planes on the board. To isolate the VCCA pin using a separate VCCA power plane, connect the VCCA pin to the analog 1.5-V power plane. Partitioned VCCA Island within VCCINT Plane Fully digital systems do not have a separate analog power plane on the board. Because it is expensive to add new planes to the board, you can create islands for VCCA_PLL. Figure 1–23 shows an example board layout with an analog power island. The dielectric boundary that creates the island should be 25 mils thick. Figure 1–23 shows a partitioned plane within VCCINT for VCCA. 1–50 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Figure 1–23. VCCINT Plane Partitioned for VCCA Island Thick VCCA Trace Because of board constraints, you might not be able to partition a VCCA island. Instead, run a thick trace from the power supply to each VCCA pin. The traces should be at least 20 mils thick. In each of these three cases, you should filter each VCCA pin with a decoupling circuit shown in Figure 1–24. Place a ferrite bead that exhibits high impedance at frequencies of 50 MHz or higher and a 10-μF tantalum parallel capacitor where the power enters the board. Decouple each VCCA pin with a 0.1-μF and 0.001-μF parallel combination of ceramic capacitors located as close as possible to the Stratix or Stratix GX device. You can connect the GNDA pins directly to the same ground plane as the device’s digital ground. Altera Corporation July 2005 1–51 Stratix Device Handbook, Volume 2 Board Layout Figure 1–24. PLL Power Schematic for Stratix or Stratix GX PLLs Ferrite Bead 1.5-V Supply 10 μF PLL_VCCA 0.1 μF 0.001 μF PLL_GNDA VCCINT PLL_VCCG Repeat for Each PLL Power and Ground Set PLL_GNDG Stratix Device VCCG & GNDG The guard ring power and ground pins are called PLL_VCCG and PLL_GNDG. The guard ring isolates the PLL circuit from the rest of the device. Connect these guard ring VCCG pins to the quietest digital supply on the board. In most systems, this is the digital 1.5-V supply supplied to the device's VCCINT pins. Connect the VCCG pins to a power supply even if you do not use the PLL. You can connect the GNDG pins directly to the same ground plane as the device’s digital ground. See Figure 1–24. 1–52 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices External Clock Output Power Enhanced PLLs 5 and 6 also have isolated power pins for their dedicated external clock outputs (VCC_PLL5_OUTA and VCC_PLL5_OUTB, or VCC_PLL6_OUTA and VCC_PLL6_OUTB, respectively). PLLs 5 and 6 both have two banks of outputs. Each bank is powered by a unique output power, OUTA or OUTB, as illustrated in Figure 1–25. These outputs can by powered by 3.3, 2.5, 1.8, or 1.5 V depending on the I/O standard for the clock output in the A or B groups. Altera Corporation July 2005 1–53 Stratix Device Handbook, Volume 2 Board Layout Figure 1–25. External Clock Output Pin Association to Output Power Note (1) VCC_PLL5_OUTA PLL5_OUT0p PLL5_OUT0n PLL5_OUT0p PLL5_OUT0n VCC_PLL5_OUTB PLL5_OUT2p PLL5_OUT2n PLL5_OUT3p PLL5_OUT3n Note to Figure 1–25: (1) These pins apply to PLL 5. The figure for PLL 6 is similar, except that the pin names begin with the prefix PLL6 instead of PLL5. 1–54 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 General-Purpose PLLs in Stratix & Stratix GX Devices Filter each isolated power pin with a decoupling circuit shown in Figure 1–26. Decouple the isolated power pins with a 0.1-μF and a 0.001-μF parallel combination of ceramic capacitors located as close as possible to the Stratix device. Figure 1–26. Stratix PLL External Clock Output Power Ball Connections Note (1) VCCIO Supply VCC_PLL5_OUTA 0.1 μF 0.001 μF VCC_PLL5_OUTB 0.1 μF 0.001 μF Stratix Device Note to Figure 1–26: (1) Altera Corporation July 2005 Figure 1–26 also applies to VCC_PLL6_OUTA/B. 1–55 Stratix Device Handbook, Volume 2 Conclusion Guidelines Use the following guidelines for optimal jitter performance on the external clock outputs from enhanced PLLs 5 and 6. If all outputs are running at the same frequency, these guidelines are not necessary to improve performance. ■ ■ ■ When driving two or more clock outputs from PLL 5 or 6, separate the outputs into the two groups shown in Figure 1–24. For example, if you are driving 100- and 200-MHz clock outputs off-chip from PLL 5, place one output on PLL5_OUT0p (powered by VCC_PLL5_OUTA) and the other output on PLL5_OUT2p (powered by VCC_PLL5_OUTB). Since the output buffers are powered by different pins, they are less susceptible to bimodal jitter. Bimodal jitter is a deterministic jitter not caused by the PLL but rather by coincident edges of clock outputs that are multiples of each other. Use phase shift to ensure edges are not coincident on all the clock outputs. Use phase shift to skew clock edges with respect to each other for best jitter performance. 1 ■ Conclusion Delay shift (time delay elements) are no longer supported in Stratix PLLs. Use the phase shift feature to implement the desired time shift. If you cannot drive multiple clocks of different frequencies and phase shifts or isolate banks, you should control the drive capability on the lower frequency clock. Reducing how much current the output buffer has to supply can reduce the noise. Minimize capacitive load on the slower frequency output and configure the output buffer to drive slow slew rate and lower current strength. The higher frequency output should have an improved performance, but this may degrade the performance of your lower frequency clock output. Stratix and Stratix GX device enhanced PLLs provide you with complete control of your clocks and system timing. These PLLs are capable of offering flexible system level clock management that was previously only available in discrete PLL devices. The embedded PLLs meet and exceed the features offered by these high-end discrete devices, reducing the need for other timing devices in the system. 1–56 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 Section II. Memory This section provides information on the TriMatrix™ Embedded Memory blocks internal to Stratix® devices and the supported external memory interfaces. It contains the following chapters: ■ Chapter 2, TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices ■ Chapter 3, External Memory Interfaces in Stratix & Stratix GX Devices The QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices chapter is removed in this version of the Stratix Device Handbook. The information is available in AN 349: Interfacing QDR SRAM with Stratix and Stratix GX Devices. Revision History The table below shows the revision history for Chapters 2 and 3. Chapter Date/Version Changes Made 2 July 2005, v3.3 ● Updated “Implementing True Dual-Port Mode” section. January 2005, v3.2 ● Minor technical content update. September 2004, v3.1 ● Updated Note 1 in Figure 2–12 on page 2–22. Updated description about using two different clocks in a dual-port RAM on page 2–27. Deleted description of M-RAM block and document references on page 2–27. ● ● April 2004, v3.0 ● ● ● July 2003, v2.0 ● ● ● Altera Corporation Comments Synchronous occurrences are renamed to pipelined. Pseudo-synchronous occurrences are renamed flowthrough. Added AND gate to Figure 2–12. Updated performance specification for TriMatrix memory in Table 2-1. Added addressing example for a RAM that is using mixed-width mode, page 2-9. Added Note 1 to Tables 2-9 and 2-10, Note 3 to Figure 211, and Note 2 to Figures 2-12 and 2-13. Section II–1 Memory Stratix Device Handbook, Volume 2 Chapter Date/Version 3 June 2006, v3.3 Changes Made ● ● July 2005, v3.2 ● ● September 2004, v3.1 ● ● ● ● ● ● ● April 2004, v3.0 ● ● ● ● ● ● Updated mathematical symbols in Table 3–3. Updated “DQS Phase-Shift Circuitry” section. Moved Figure 8 to become Figure 1, “Example of Where a DQS Signal is Center-Aligned in the IOE” on page 3–3. Updated Table 3–1 on page 3–10, updated Note 4. Note 4, 5, and 6, are now Note 5, 6, and 7, respectively. Updated Table 3–2 on page 3–10. Updated Table 3–3 on page 3–13. Updated Note on page 3–14. Moved the “External Memory Standards” on page 3–1 to follow the Introduction section. Moved “Conclusion” on page 3–27 to end of chapter. Chapter renamed Chapter 3, External Memory Interfaces in Stratix & Stratix GX Devices. Table 3–1: DDR SDRAM - side banks row added, ZBT SRAM row updated. Added Tables 3–2 and 3–4. DQSn pins removed (page 3-5) Deleted “QDR SRAM Interfacing” figure. Replaced “tZX & tXZ Timing Diagram.” ● Removed support for series and parallel on-chip termination. July 2003, v2.0 ● altddio_bidir function is used for DQS in versions before Quartus II 3.0. (page 3-2) Updated naming convention for DQS pins on page 3-9 to match pin tables. Clarified input clock to PLL must come from an external input pin on page 3-12. ● Section II–2 Changed the name of the chapter from External Memory Interfaces to External Memory Interfaces in Stratix & Stratix GX Devices to reflect its shared status between those device handbooks. Added cross reference regarding frequency limits for 72 and 90° phase shift for DQS. November 2003, v2.1 ● Comments Altera Corporation 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices S52003-3.3 Introduction Stratix® and Stratix GX devices feature the TriMatrix™ memory structure, composed of three sizes of embedded RAM blocks. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, each of which is configurable to support a wide range of features. Offering up to 10 Mbits of RAM and up to 12 terabits per second of device memory bandwidth, the TriMatrix memory structure makes the Stratix and Stratix GX families ideal for memory-intensive applications. TriMatrix Memory TriMatrix memory structures can implement a wide variety of complex memory functions. For example, use the small M512 blocks for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical. The M4K blocks are an ideal size for applications requiring medium-sized memory, such as asynchronous transfer mode (ATM) cell processing. M-RAM blocks enhance programmable logic device (PLD) memory capabilities for large buffering applications, such as internet protocol (IP) packet buffering and system cache. TriMatrix memory blocks support various memory configurations, including single-port, simple dual-port, true dual-port (also known as bidirectional dual-port), shift-register, ROM, and FIFO mode. The TriMatrix memory architecture also includes advanced features and capabilities, such as byte enable support, parity-bit support, and mixedport width support. This chapter describes the various TriMatrix memory modes and features. Table 2–1 summarizes the features supported by the three sizes of TriMatrix memory. f Altera Corporation July 2005 For more information on selecting which memory block to use, see AN 207: TriMatrix Memory Selection Using the Quartus II Software. 2–1 TriMatrix Memory Table 2–1. Summary of TriMatrix Memory Features Feature Performance Total RAM bits (including parity bits) Configurations Parity bits M512 Block M4K Block M-RAM Block 319 MHz 290 MHz 287 MHz 576 4,608 589,824 512 × 1 256 × 2 128 × 4 64 × 8 64 × 9 32 × 16 32 × 18 4K × 1 2K × 2 1K × 4 512 × 8 512 × 9 256 × 16 256 × 18 128 × 32 128 × 36 64K × 8 64K × 9 32K × 16 32K × 18 16K × 32 16K × 36 8K × 64 8K × 72 4K × 128 4K × 144 v v v v v Byte enable Single-port memory v v v Simple dual-port memory v v v v v True dual-port memory Embedded shift register v v ROM v v FIFO buffer v v v Simple dual-port mixed width support v v v v v True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode v v v v v Power-up condition Outputs cleared Outputs cleared Outputs unknown Register clears Input and output registers (1) Input and output registers (2) Output registers Same-port read-during-write New data available at positive clock edge New data available at positive clock edge New data available at positive clock edge Mixed-port read-during-write Outputs set to unknown or old data Outputs set to unknown or old data Unknown output Notes to Table 2–1: (1) (2) The rden register on the M512 memory block does not have a clear port. On the M4K block, asserting the clear port of the rden and byte enable registers drives the output of these registers high. 2–2 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices The extremely high memory bandwidth of the Stratix and Stratix GX device families is a result of increased memory capacity and speed. Table 2–2 shows the memory capacity for TriMatrix memory blocks in each Stratix device. Table 2–3 shows the memory capacity for TriMatrix memory blocks in each Stratix GX device. Table 2–2. TriMatrix Memory Distribution in Stratix Devices Device M512 M4K Columns/Blocks Columns/Blocks EP1S10 4 / 94 EP1S20 EP1S25 M-RAM Blocks Total RAM Bits 2 / 60 1 920,448 6 / 194 2 / 82 2 1,669,248 6 / 224 3 / 138 2 1,944,576 EP1S30 7 / 295 3 / 171 4 3,317,184 EP1S40 8 / 384 3 / 183 4 3,423,744 EP1S60 10 / 574 4 / 292 6 5,215,104 EP1S80 11 / 767 4 / 364 9 7,427,520 Table 2–3. TriMatrix Memory Distribution in Stratix GX Devices Device M512 M4K Columns/Blocks Columns/Blocks M-RAM Blocks Total RAM Bits EP1SGX10 4 / 94 2 / 60 1 920,448 EP1SGX25 6 / 224 3 / 138 2 1,944,576 EP1SGX40 8 / 384 3 / 183 4 3,423,744 Clear Signals When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. Parity Bit Support The memory blocks support a parity bit for each byte. Parity bits are in addition to the amount of memory in each RAM block. For example, the M512 block has 576 bits, 64 of which are optionally used for parity bit Altera Corporation July 2005 2–3 Stratix Device Handbook, Volume 2 TriMatrix Memory storage. The parity bit, along with logic implemented in logic elements (LEs), can implement parity checking for error detection to ensure data integrity. Parity-size data words can also store user-specified control bits. Byte Enable Support In the M4K and M-RAM blocks, byte enables can mask the input data so that only specific bytes of data are written. The unwritten bytes retain the previous written value. The write enable signals (wren), in conjunction with the byte enable signals (byteena), controls the RAM block’s write operations. The default value for the byteena signals is high (enabled), in which case writing is controlled only by the wren signals. Asserting the clear port of the byte enable registers drives the byte enable signals to their default high level. M4K Blocks M4K blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. Table 2–4 summarizes the byte selection. Table 2–4. Byte Enable for M4K Blocks Notes (1), (2) byteena datain × 18 datain × 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 – [26..18] [3] = 1 – [35..27] Notes to Table 2–4: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32 modes. 2–4 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices M-RAM Blocks M-RAM blocks support byte enables for the × 16, × 18, × 32, × 36, × 64, and × 72 modes. In the × 128 or × 144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) combine to form the necessary 16 byte enables. Tables 2–5 and 2–6 summarize the byte selection. Table 2–5. Byte Enable for M-RAM Blocks Notes (1), (2) byteena datain × 18 datain × 36 datain × 72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 – [26..18] [26..18] [3] = 1 – [35..27] [35..27] [4] = 1 – – [44..36] [5] = 1 – – [53..45] [6] = 1 – – [62..54] [7] = 1 – – [71..63] Notes to Table 2–5: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, that is, in × 16, × 32, and × 64 modes. Table 2–6. M-RAM Combined Byte Selection for × 144 Mode (Part 1 of 2), Notes (1), (2) byteena_a Altera Corporation July 2005 datain × 144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] 2–5 Stratix Device Handbook, Volume 2 TriMatrix Memory Table 2–6. M-RAM Combined Byte Selection for × 144 Mode (Part 2 of 2), Notes (1), (2) byteena_a datain × 144 [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] Notes to Table 2–6: (1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16, × 32, × 64, and × 128 modes. Byte Enable Functional Waveform Figure 2–1 shows how both the wren and the byteena signals control the write operations of the RAM. Figure 2–1. Byte Enable Functional Waveform Note (1) inclock wren a0 address an data_in XXXX byteena XX contents at a0 contents at a1 a2 a0 a1 ABCD 10 a2 XXXX 01 11 FFFF XX ABFF FFFF FFCD FFFF contents at a2 asynch_data_out a1 doutn ABXX ABCD XXCD ABCD ABFF FFCD ABCD Note to Figure 2–1: (1) For more information on simulation output when a read-during-write occurs at the same address location, see “Read-During-Write Operation at the Same Address” on page 2–25. 2–6 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Using TriMatrix Memory f The TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. All TriMatrix memory blocks are pipelined, meaning that all inputs are registered, but outputs are either registered or combinatorial. TriMatrix memory can emulate a flow-through memory by using combinatorial outputs. For more information, see AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs. Depending on the TriMatrix memory block type, the memory can have various modes, including: ■ ■ ■ ■ ■ ■ Single-port Simple dual-port True dual-port (bidirectional dual-port) Shift-register ROM FIFO Implementing Single-Port Mode Single-port mode supports non-simultaneous reads and writes. Figure 2–2 shows the single-port memory configuration for TriMatrix memory. All memory block types support the single-port mode. Figure 2–2. Single-Port Memory Note (1) data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr Note to Figure 2–2: (1) Two single-port memory blocks can be implemented in a single M4K block. M4K memory blocks can also be divided in half and used for two independent single-port RAM blocks. The Altera Quartus II software automatically uses this single-port memory packing when running low on memory resources. To force two single-port memories into one M4K block, first ensure that each of the two independent RAM blocks is equal to or less than half the size of the M4K block. Second, assign both singleport RAMs to the same M4K block. Altera Corporation July 2005 2–7 Stratix Device Handbook, Volume 2 Using TriMatrix Memory In the single-port RAM configuration, the outputs can only be in read-during-write mode, which means that during the write operation, data written to the RAM flows through to the RAM outputs. When the output registers are bypassed, the new data is available on the rising edge of the same clock cycle it was written on. For more information about read-during-write mode, see “Read-During-Write Operation at the Same Address” on page 2–25. Figure 2–3 shows timing waveforms for read and write operations in single-port mode. Figure 2–3. Single-Port Timing Waveforms in clock wren address an-1 an data_in din-1 din synch_data_out asynch_data_out a0 din-2 din din-1 din din-1 a1 a2 dout0 dout0 dout1 a3 dout1 dout2 a4 a5 a6 din4 din5 din6 dout2 dout3 dout3 din4 din4 din5 Implementing Simple Dual-Port Mode Simple dual-port memory supports a simultaneous read and write. Figure 2–4 shows the simple dual-port memory configuration for TriMatrix memory. All memory block types support this configuration. Figure 2–4. Simple Dual-Port Memory Note (1) Dual-Port Memory data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr Note to Figure 2–4: (1) Simple dual-port RAM supports read/write clock mode in addition to the input/output clock mode shown. 2–8 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices TriMatrix memory supports mixed-width configurations, allowing different read and write port widths. When using mixed-width mode, the LSB is written to or read from first. For example, take a RAM that is set up in mixed-width mode with write data width ×8 and read data width ×2. If a binary 00000001 is written to write dress 0, the following is read out of the ×2 output side: Read Address ×2 data 00 01(LSB of ×8 data) 01 00 10 00 11 00(MSB of ×8 data) Tables 2–7 to 2–9 show the mixed width configurations for the M512, M4K, and M-RAM blocks, respectively. Table 2–7. M512 Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port 512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 v v v v v v v 512 × 1 256 × 2 v v v 128 × 4 v v v 64 × 8 v v 32 × 16 v v 64 × 9 32 × 18 v v v v 64 × 9 v 32 × 18 v Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2) Write Port Read Port 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 4K × 1 v v v v v v 2K × 2 v v v v v v 1K × 4 v v v v v v 512 × 8 v v v v v v 256 × 16 v v v v v v Altera Corporation July 2005 128 × 36 2–9 Stratix Device Handbook, Volume 2 Using TriMatrix Memory Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2) Write Port Read Port 128 × 32 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 v v v v v 128 × 32 512 × 9 256 × 18 128 × 36 v 512 × 9 v v v 256 × 18 v v v 128 × 36 v v v Table 2–9. M-RAM Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port 64K × 9 32K × 18 16K × 36 8K × 72 64K × 9 v v v v 32K × 18 v v v v 16K × 36 v v v v 8K × 72 v v v v 4K × 144 4K × 144 v M512 blocks support serializer and deserializer (SERDES) applications. By using the mixed-width support in combination with double data rate (DDR) I/O standards, the block can function as a SERDES to support lowspeed serial I/O standards using global or regional clocks. f For more information on Stratix device I/O structure see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. For more information on Stratix GX device I/O structure see the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1. In simple dual-port mode, the M512 and M4K blocks have one write enable and one read enable signal. The M512 does not support a clear port on the rden register. On the M4K block, asserting the clear port of the rden register drives rden high, which allows the read operation to occur. When the read enable is deactivated, the current data is retained at the output ports. If the read enable is activated during a write operation with the same address location selected, the simple dual-port RAM output is either unknown or can be set to output the old data stored at the memory address. For more information, see “Read-During-Write Operation at the Same Address” on page 2–25. 2–10 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices M-RAM blocks have one write enable signal in simple dual-port mode. To perform a write operation, the write enable is held high. The M-RAM block is always enabled for read operation. If the read address and the write address select the same address location during a write operation, the M-RAM block output is unknown. Figure 2–5 shows timing waveforms for read and write operations in simple dual-port mode. Figure 2–5. Simple Dual-Port Timing Waveforms Note (1) wrclock wren wraddress an-1 an data_in din-1 din a0 a1 a2 a3 a4 a5 a6 din4 din5 din6 rdclock rden rdaddress synch_data_out asynch_data_out bn doutn-2 doutn-1 b1 b0 doutn-1 doutn b2 doutn b3 dout0 dout0 Note to Figure 2–5: (1) The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading out the data stored at the current read address location. Implementing True Dual-Port Mode M4K and M-RAM blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2–6 shows the true dual-port memory configuration for TriMatrix memory. Altera Corporation July 2005 2–11 Stratix Device Handbook, Volume 2 Using TriMatrix Memory Figure 2–6. True Dual-Port Memory Note (1) A B dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB Note to Figure 2–6: (1) True dual-port memory supports input/output clock mode in addition to the independent clock mode shown. The widest bit configuration of the M4K and M-RAM blocks in true dualport mode is 256 × 16-bit (× 18-bit with parity) and 8K × 64-bit (× 72-bit with parity), respectively. The 128 × 32-bit (× 36-bit with parity) configuration of the M4K block and the 4K × 128-bit (× 144-bit with parity) configuration of the M-RAM block are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, the maximum width of the true dual-port RAM equals half of the total number of output drivers. Tables 2–10 and 2–11 list the possible M4K RAM block and M-RAM block configurations, respectively. Table 2–10. M4K Block Mixed-Port Width Configurations (True Dual-Port) Port B Port A 4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 512 × 9 256 × 18 4K × 1 v v v v v 2K × 2 v v v v v 1K × 4 v v v v v 512 × 8 v v v v v 256 × 16 v v v v v 512 × 9 v v 256 × 18 v v 2–12 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Table 2–11. M-RAM Block Mixed-Port Width Configurations (True Dual-Port) Port B Port A 64K × 9 32K × 18 16K × 36 8K × 72 64K × 9 v v v v 32K × 18 v v v v 16K × 36 v v v v 8K × 72 v v v v In true dual-port configuration, the RAM outputs can only be configured for read-during-write mode. This means that during write operation, data being written to the A or B port of the RAM flows through to the A or B outputs, respectively. When the output registers are bypassed, the new data is available on the rising edge of the same clock cycle it was written on. For waveforms and information on mixed-port read-duringwrite mode, see “Read-During-Write Operation at the Same Address” on page 2–25. Potential write contentions must be resolved external to the RAM because writing to the same address location at both ports results in unknown data storage at that location. Data is written on the rising edge of the write clock for the M-RAM block. For a valid write operation to the same address of the M-RAM block, the rising edge of the write clock for port A must occur following the maximum write cycle time interval after the rising edge of the write clock for port B. Since data is written into the M512 and M4K blocks at the falling edge of the write clock, the rising edge of the write clock for port A should occur following half of the maximum write cycle time interval after the falling edge of the write clock for port B. If this timing is not met, the data stored in that particular address is invalid. f See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 for the maximum synchronous write cycle time. Figure 2–7 shows true dual-port timing waveforms for write operation at port A and read operation at port B. Altera Corporation July 2005 2–13 Stratix Device Handbook, Volume 2 Using TriMatrix Memory Figure 2–7. True Dual-Port Timing Waveforms A_clk A_wren A_address A_data_in an-1 an din-1 din A_synch_data_out din-2 A_asynch_data_out a0 din din-1 din din-1 a1 a2 dout0 dout1 dout1 dout0 a3 a4 a5 a6 din4 din5 din6 dout2 dout2 din4 dout3 dout3 din5 din4 B_clk B_wren B_address B_synch_data_out B_asynch_data_out bn doutn-2 doutn-1 b1 b0 doutn-1 doutn b2 dout0 doutn dout0 b3 dout1 dout2 dout1 Implementing Shift-Register Mode Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto-correlation and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops that can quickly consume many logic cells for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation. The size of a (w × m × n) shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a (w × m × n) shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 block and 4,608 bits for the M4K block. In addition, the size of w × n must be less than or equal to the maximum width of the respective block: 18 bits for the M512 block and 36 bits for the M4K block. If a larger shift register is required, the memory blocks can be cascaded together. 1 2–14 Stratix Device Handbook, Volume 2 M-RAM blocks do not support the shift-register mode. Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift-register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2–8 shows the TriMatrix memory block in the shift-register mode. Figure 2–8. Shift-Register Memory Configuration w × m × n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Implementing ROM Mode The M512 and the M4K blocks support ROM mode. Use a memory initialization file (.mif) to initialize the ROM contents of M512 and M4K blocks. The M-RAM block does not support ROM mode. All Stratix memory configurations must have synchronous inputs; therefore, the address lines of the ROM are registered. The outputs can be registered or combinatorial. The ROM read operation is identical to the read operation in the single-port RAM configuration. Altera Corporation July 2005 2–15 Stratix Device Handbook, Volume 2 Clock Modes Implementing FIFO Buffers While the small M512 memory blocks are ideal for designs with many shallow FIFO buffers, all three memory sizes support FIFO mode. All memory configurations have synchronous inputs; however, the FIFO buffer outputs are always combinatorial. Simultaneous read and write from an empty FIFO is not supported. Clock Modes Depending on the TriMatrix memory mode, independent, input/output, read/write, and/or single-port clock modes are available. Table 2–12 shows the clock modes supported by the TriMatrix memory modes. Table 2–12. TriMatrix Memory Clock Modes Clocking Mode True-Dual Port Mode Independent v Input/output v Read/write Single-port Simple DualPort Mode Single-Port Mode v v v Independent Clock Mode The TriMatrix memory blocks can implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2–9 shows a TriMatrix memory block in independent clock mode. 2–16 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices clockB clkenB wrenB addressB[ ] D ENA D D Q ENA ENA Q Q ENA D Q ENA ENA D clockA clkenA wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 D 8 LAB Row Clocks Q Write Pulse Generator D Data Out Address A Write/Read Enable qA[ ] qB[ ] Q Data Out Write/Read Enable Address B Byte Enable B Byte Enable A B Data In Memory Block 256 ´ 16 (2) 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 A Data In ENA Write Pulse Generator Q D ENA Q D ENA Q D Q ENA 8 dataB[ ] byteenaB[ ] Figure 2–9. Independent Clock Mode Note (1), (2) Note to Figure 2–9: (1) (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have asynchronous clear ports on their output registers only. Altera Corporation July 2005 2–17 Stratix Device Handbook, Volume 2 Clock Modes Input/Output Clock Mode The TriMatrix memory blocks can implement input/output clock mode for true and simple dual-port memory. On each of the two ports, A and B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block’s data output registers. Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2–10 and 2–11 show the memory block in input/output clock mode for true and simple dual-port modes, respectively. 2–18 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 (1) Altera Corporation July 2005 clockA clkenA wrenA addressA[ ] byteenaA[ ] dataA[ ] 8 ENA D ENA D ENA D ENA D 8 LAB Row Clocks Q Q Q Q Write Pulse Generator Q Data Out Write/Read Enable Address A ENA D A qA[ ] Data In B qB[ ] Q D ENA Data Out Write/Read Enable Address B Byte Enable B Memory Block 256 × 16 (2) 512 × 8 1,024 × 4 2,048 × 2 4,096 × 1 Byte Enable A Data In Write Pulse Generator Q Q Q Q ENA D ENA D ENA D ENA D 8 clockB clkenB wrenB addressB[ ] byteenaB[ ] dataB[ ] TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Figure 2–10. Input/Output Clock Mode in True Dual-Port Mode Note (1) Note to Figure 2–10: Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–19 Stratix Device Handbook, Volume 2 Clock Modes All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have asynchronous clear ports on their output registers only. Figure 2–11. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3), (4) 8 LAB Row Clocks Memory Block 256 ´ 16 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 8 data[ ] D Q ENA Data In address[ ] D Q ENA Read Address Data Out byteena[ ] D Q ENA Byte Enable wraddress[ ] D Q ENA Write Address D Q ENA Read Enable D Q ENA To MultiTrack Interconnect rden wren outclken inclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Notes to Figure 2–11: (1) (2) (3) (4) The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading out the data stored at the current read address location. For more information on the MultiTrack™ interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1. All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have asynchronous clear ports on their output registers only. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–20 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Read/Write Clock Mode The TriMatrix memory blocks can implement read/write clock mode for simple dual-port memory. This mode can use up to two clocks. The write clock controls the block’s data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2–12 shows a memory block in read/write clock mode. Altera Corporation July 2005 2–21 Stratix Device Handbook, Volume 2 Clock Modes Figure 2–12. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3) 8 LAB Row Clocks Memory Block 256 × 16 512 × 8 1,024 × 4 Data In 2,048 × 2 4,096 × 1 8 data[ ] D Q ENA Data Out address[ ] D Q ENA Read Address wraddress[ ] D Q ENA Write Address byteena[ ] D Q ENA Byte Enable D Q ENA To MultiTrack Interconnect rden D Q ENA wren Read Pulse Generator Read Enable rdclocken wrclocken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Notes to Figure 2–12: (1) (2) (3) For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1. All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have asynchronous clear ports on their output registers only. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 2–22 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Single-Port Mode The TriMatrix memory blocks can implement single-port clock mode for single-port memory mode. Single-port mode is used when simultaneous reads and writes are not required. See Figure 2–13. A single block in a memory block can support up to two single-port mode RAM blocks in M4K blocks. Figure 2–13. Single-Port Mode Notes (1), (2), (3) 8 LAB Row Clocks RAM/ROM 256 × 16 512 × 8 1,024 × 4 Data In 2,048 × 2 4,096 × 1 8 data[ ] D Q ENA Data Out address[ ] D Q ENA Address D Q ENA To MultiTrack Interconnect wren Write Enable outclken inclken inclock D Q ENA Write Pulse Generator outclock Notes to Figure 2–13: (1) (2) (3) For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1. All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have asynchronous clear ports on their output registers only. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Designing With TriMatrix Memory Altera Corporation July 2005 When instantiating TriMatrix memory you must understand the various features that set it apart from other memory architectures. The following sections describe some of the important attributes and functionality of TriMatrix memory. 2–23 Stratix Device Handbook, Volume 2 Designing With TriMatrix Memory f For information on the difference between APEX-style memory and TriMatrix memory, see the Transitioning APEX Designs to Stratix Devices chapter. Selecting TriMatrix Memory Blocks The Quartus II software automatically partitions user-defined memory into embedded memory blocks using the most efficient size combinations. The memory can also be manually assigned to a specific block size or a mixture of block sizes. Table 2–1 on page 2–2 is a guide for selecting a TriMatrix memory block size based on supported features. 1 f Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. For more information on selecting which memory block to use, see AN 207: TriMatrix Memory Selection Using the Quartus II Software. 1 Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Pipeline & Flow-Through Modes TriMatrix memory architecture implements synchronous (pipelined) RAM by registering both the input and output signals to the RAM block. All TriMatrix memory inputs are registered providing synchronous write cycles. In synchronous operation, RAM generates its own self-timed strobe write enable (wren) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. The output registers can be bypassed. In an asynchronous memory neither the input nor the output is registered. While Stratix and Stratix GX devices do not support asynchronous memory, they do support a flow-through read where the output data is available during the clock cycle when the read address is driven into it. Flow-through reading is possible in the simple and true dual-port modes of the M512 and M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. f For more information, see AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Devices. 2–24 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Power-up Conditions & Memory Initialization Upon power-up, TriMatrix memory is in an idle state. The M512 and M4K block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. Even if a memory initialization file is used to pre-load the contents of the RAM block, the outputs still power-up cleared. For example, if address 0 is pre-initialized to FF, the M512 and M4K blocks power-up with the output at 00. M-RAM blocks do not support memory initialization files; therefore, they cannot be pre-loaded with data upon power-up. M-RAM blocks combinatorial outputs and memory controls always power-up to an unknown state. If M-RAM block outputs are registered, the registers power-up cleared. The undefined output appears one clock cycle later. The output remains undefined until a read operation is performed on an address that has been written to. Read-DuringWrite Operation at the Same Address The following two sections describe the functionality of the various RAM configurations when reading from an address during a write operation at that same address. There are two types of read-during-write operations: same-port and mixed-port. Figure 2–14 illustrates the difference in data flow between same-port and mixed-port read-during-write. Figure 2–14. Read-During-Write Data Flow Port A data in Port B data in Mixed-port data flow Same-port data flow Port A data out Port B data out Same-Port Read-During-Write Mode For read-during-write operation of a single-port RAM or the same port of a true dual-port RAM, the new data is available on the rising edge of the same clock cycle it was written on. This behavior is valid on all memoryblock sizes. See Figure 2–15 for a sample functional waveform. Altera Corporation July 2005 2–25 Stratix Device Handbook, Volume 2 Read-During-Write Operation at the Same Address When using byte enables in true dual-port RAM mode, the outputs for the masked bytes on the same port are unknown. (See Figure 2–1 on page 2–6.) The non-masked bytes are read out as shown in Figure 2–15. Figure 2–15. Same-Port Read-During-Write Functionality Note (1) inclock data_in A B wren data_out Old A Note to Figure 2–15: (1) Outputs are not registered. Mixed-Port Read-During-Write Mode This mode is used when a RAM in simple or true dual-port mode has one port reading and the other port writing to the same address location with the same clock. The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512 and M4K memory blocks determines whether to output the old data at the address or a “don’t care” value. Setting this parameter to OLD_DATA outputs the old data at that address. Setting this parameter to DONT_CARE outputs a “don’t care” or unknown value. See Figures 2–16 and 2–17 for sample functional waveforms showing this operation. These figures assume that the outputs are not registered. The DONT_CARE setting allows memory implementation in any TriMatrix memory block. The OLD_DATA setting restricts memory implementation to only M512 or M4K memory blocks. Selecting DONT_CARE gives the compiler more flexibility when placing memory functions into TriMatrix memory. 2–26 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA inclock addressA and addressB Port A data_in Address Q A B Port A wren Port B wren Port B data_out Old A B For mixed-port read-during-write operation of the same address location of a M-RAM block, the RAM outputs are unknown, as shown in Figure 2–17. Figure 2–17. Mixed-Port Read-During-Write: DONT_CARE inclock addressA and addressB Port A data_in Address Q A B Port A wren Port B wren Port B data_out Unknown B Mixed-port read-during-write is not supported when two different clocks are used in a dual-port RAM. The output value will be unknown during a mixed-port read-during-write operation. Conclusion Altera Corporation July 2005 TriMatrix memory, an enhanced RAM architecture with extremely high memory bandwidth in Stratix and Stratix GX devices, gives advanced control of memory applications with features such as byte enables, parity bit storage, and shift-register mode, as well as mixed-port width support and true dual-port mode. 2–27 Stratix Device Handbook, Volume 2 Conclusion 2–28 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 3. External Memory Interfaces in Stratix & Stratix GX Devices S52008-3.3 Introduction Stratix® and Stratix GX devices support a broad range of external memory interfaces such as double data rate (DDR) SDRAM, RLDRAM II, quad data rate (QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT) SRAM, and single data rate (SDR) SDRAM. The dedicated phase-shift circuitry allows the Stratix and Stratix GX devices to interface at twice the system clock speed with an external memory (up to 200 MHz/400 Mbps). Typical I/O architectures transmit a single data word on each positive clock edge and are limited to the associated clock speed using this protocol. To achieve a 400-megabits per second (Mbps) transfer rate, a SDR system requires a 400-MHz clock. Many new applications have introduced a DDR I/O architecture as an alternative to SDR architectures. While SDR architectures capture data on one edge of a clock, the DDR architectures captures data on both the rising and falling edges of the clock, doubling the throughput for a given clock frequency and accelerating performance. For example, a 200-MHz clock can capture a 400-Mbps data stream, enhancing system performance and simplifying board design. Most current memory architectures use a DDR I/O interface. These DDR memory standards cover a broad range of applications for embedded processor systems, image processing, storage, communications, and networking. This chapter describes the hardware features in Stratix and Stratix GX devices that facilitate the high-speed memory interfacing for each memory standard. It then briefly explains how each memory standard uses the features of the Stratix and Stratix GX devices. f External Memory Standards You can use this document with AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices, AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices, and AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. The following sections provide an overview on using the Stratix and Stratix GX device external memory interfacing features. DDR SDRAM DDR SDRAM is a memory architecture that transmits and receives data at twice the clock speed of traditional SDR architectures. These devices transfer data on both the rising and falling edge of the clock signal. Altera Corporation June 2006 3–1 External Memory Standards Interface Pins DDR devices use interface pins including data, data strobe, clock, command, and address pins. Data is sent and captured at twice the clock rate by transferring data on both the positive and negative edge of a clock. The commands and addresses only use one active edge of a clock. Connect the memory device’s DQ and DQS pins to the DQ and DQS pins, respectively, as listed in the Stratix and Stratix GX devices pin table. DDR SDRAM also uses active-high data mask pins for writes. You can connect DM pins to any of the I/O pins in the same bank as the DQ pins of the FPGA. There is one DM pin per DQS/DQ group. DDR SDRAM ×16 devices use two DQS pins, and each DQS pin is associated with eight DQ pins. However, this is not the same as the ×16 mode in Stratix and Stratix GX devices. To support a ×16 DDR SDRAM, you need to configure the Stratix and Stratix GX FPGAs to use two sets of DQ pins in ×8 mode. Similarly if your ×32 memory device uses four DQS pins where each DQS pin is associated with eight DQ pins, you need to configure the Stratix and Stratix GX FPGA to use four sets of pins in ×8 mode. You can also use any I/O pins in banks 1, 2, 5, or 6 to interface with DDR SDRAM devices. These banks do not have dedicated circuitry, though. You can also use any of the user I/O pins for commands and addresses to the DDR SDRAM. f For more information, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. If the DDR SDRAM device supports ECC, the design uses a DQS/DQ group for ECC pins. You can use any of the user I/O pins for commands and addresses. Because of the symmetrical setup and hold time for the command and address pins at the memory, you might need to generate these signals from the system clock’s negative edge. The clocks to the SDRAM device are called CK and CK#. Use any of the user I/O pins via the DDR registers to generate the CK and CK# signals to meet the DDR SDRAM tDQSS requirement. The memory device’s tDQSS requires that the DQS signal’s positive edge write operations must be within 25% of the positive edge of the DDR SDRAM clock input. Using user I/O pins for CK and CK# ensures that any PVT variations seen by the DQS signal are tracked by these pins, too. 3–2 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Read & Write Operations When reading from the DDR SDRAM, the DQS signal coming into the Stratix and Stratix GX device is edge-aligned with the DQ pins. The dedicated circuitry center-aligns the DQS signal with respect to the DQ signals and the shifted DQS bus drives the clock input of the DDR input registers. The DDR input registers bring the data from the DQ signals to the device. The system clock clocks the DQS output enable and output paths. The -90° shifted clock clocks the DQ output enable and output paths. Figure 3–1 shows an example of the DQ and DQS relationship during a burst-of-two read. It shows where the DQS signal is center-aligned in the IOE. Figure 3–1. Example of Where a DQS Signal is Center-Aligned in the IOE Pin to register delay DQS at FPGA Pin Postamble Preamble DQ at FPGA Pin DQS at DQ IOE registers DQ at DQ IOE registers 90 degree shift Pin to register delay When writing to the DDR SDRAM, the DQS signal must be centeraligned with the DQ pins. Two PLL outputs are needed to generate the DQS signal and to clock the DQ pins. The DQS are clocked by the 0° phase-shift PLL output, while the DQ pins are clocked by the -90° phaseshifted PLL output. Figure 3–2 shows the DQS and DQ relationship during a DDR SDRAM burst-of-two write. Figure 3–2. DQ & DQS Relationship During a Burst-of-Two Write DQS at FPGA Pin DQ at FPGA Pin Altera Corporation June 2006 3–3 Stratix Device Handbook, Volume 2 External Memory Standards Figure 3–3 shows DDR SDRAM interfacing from the I/O through the dedicated circuitry to the logic array. When the DQS pin acts as an input strobe, the dedicated circuitry shifts the incoming DQS pin by either 72° or 90° and clocks the DDR input registers. Because of the DDR input registers architecture in Stratix and Stratix GX devices, the shifted DQS signal must be inverted. The DDR registers outputs are sent to two LE registers to be synchronized with the system clock. f Refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix Device Handbook for frequency limits regarding the 72 and 90° phase shift for DQS. Figure 3–3. DDR SDRAM Interfacing DQ DQS Compensated Delay Shift OE PLL DDR OE Registers User logic/ 2 GND 2 DDR Output Registers OE Δt DDR OE Registers 2 DDR Output Registers DDR Input Registers I/O Elements & Periphery − 90˚ DQS Bus LE Register LE Register Resynchronizing Global Clock f Adjacent LAB LEs For more information on DDR SDRAM specifications, see JEDEC standard publications JESD79C from www.jedec.org, or see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. RLDRAM II RLDRAM II provides fast random access as well as high bandwidth and high density, making this memory technology ideal for high-speed network and communication data storage applications. The fast random access speeds in RLDRAM II devices make them a viable alternative to SRAM devices at a lower cost. Additionally, RLDRAM II devices have minimal latency to support designs that require fast response times. 3–4 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Interface Pins RLDRAM II devices use interface pins such as data, clock, command, and address pins. There are two types of RLDRAM II memory: common I/O (CIO) and separate I/O (SIO). The data pins in RLDRAM II CIO device are bidirectional while the data pins in a RLDRAM II SIO device are uni-directional. Instead of bidirectional data strobes, RLDRAM II uses differential free-running read and write clocks to accompany the data. As in DDR SDRAM, data is sent and captured at twice the clock rate by transferring data on both the positive and negative edge of a clock. The commands and addresses still only use one active edge of a clock. If the data pins are bidirectional, connect them to the Stratix and Stratix GX device DQ pins. If the data pins are uni-directional, connect the RLDRAM II device Q ports to the Stratix and Stratix GX device DQ pins and connect the D ports to any user I/O pins in I/O banks 3, 4, 7, and 8. RLDRAM II also uses active-high data mask pins for writes. You can connect DM pins to any of the I/O pins in the same bank as the DQ pins of the FPGA. When interfacing with SIO devices, connect the DM pins to any of the I/O pins in the same bank as the D pins. There is one DM pin per DQS/DQ group. Connect the read clock pins (QK) to Stratix and Stratix GX device DQS pins. You must configure the DQS signals as bidirectional pins. However, since QK pins are output-only pins from the memory, RLDRAM memory interfacing in Stratix and Stratix GX devices requires that you ground the DQS and DQSn pin output enables. The Stratix and Stratix GX devices use the shifted QK signal from the DQS logic block to capture data. You can leave the QK# signal of the RLDRAM II device unconnected. RLDRAM II devices have both input clocks (CK and CK#) and write clocks (DK and DK#). Use the external clock buffer to generate CK, CK#, DK, and DK# to meet the CK, CK#, DK, and DK# skew requirements from the RLDRAM II device. If you are interfacing with multiple RLDRAM II devices, perform IBIS simulations to analyze the loading effects on the clock pair. You can use any of the user I/O pins for commands and addresses. RLDRAM II also offers QVLD pins to indicate the read data availability. Connect the QVLD pins to the Stratix and Stratix GX device DQVLD pins, listed in the pin table. Read & Write Operations When reading from the RLDRAM II device, data is sent edge-aligned with the read clock QK or QK# signal. When writing to the RLDRAM II device, data must be center-aligned with the write clock (DK or DK# signal). The Stratix and Stratix GX device RLDRAM II interface uses the Altera Corporation June 2006 3–5 Stratix Device Handbook, Volume 2 External Memory Standards same scheme as in DDR SDRAM interfaces whereby the dedicated circuitry is used during reads to center-align the data and the read clock inside the FPGA and the PLL center-aligns the data and write clock outputs. The data and clock relationship for reads and writes in RLDRAM II is similar to those in DDR SDRAM as already depicted in Figure 3–1 on page 3–3 and Figure 3–3 on page 3–4. QDR & QDRII SRAM QDR SRAM provides independent read and write ports that eliminate the need for bus turnaround. The memory uses two sets of clocks: K and Kn for write access, and optional C and Cn for read accesses, where Kn and Cn are the inverse of the K and C clocks, respectively. You can use differential HSTL I/O pins to drive the QDR SRAM clock into the Stratix and Stratix GX devices. The separate write data and read data ports permit a transfer rate up to four words on every cycle through the DDR circuitry. Stratix and Stratix GX devices support both burst-of-two and burst-of-four QDR SRAM architectures, with clock cycles up to 167 MHz using the 1.5-V HSTL Class I or Class II I/O standard. Figure 3–4 shows the block diagram for QDR SRAM burst-of-two architecture. Figure 3–4. QDR SRAM Block Diagram for Burst-of-Two Architecture Discrete QDR SRAM Device A 18 BWSn Write Port WPSn D 36 Data 256K × 18 Memory Array 256K × 18 Memory 36 Array Data Read Port RPSn 2 C, Cn 18 Q 18 2 K, Kn VREF Control Logic QDRII SRAM is a second generation of QDR SRAM devices. It can transfer four words per clock cycle, fulfilling the requirements facing next-generation communications system designers. QDRII SRAM devices provide concurrent reads and writes, zero latency, and increased data throughput. Stratix and Stratix GX devices support QDRII SRAM at speeds up to 200 MHz since the timing requirements for QDRII SRAM are not as strict as QDR SRAM. 3–6 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Interface Pins QDR and QDRII SRAM uses two separate, uni-directional data ports for read and write operations, enabling quad data-rate data transfer. Both QDR and QDRII SRAM use shared address lines for reads and writes. Stratix and Stratix GX devices utilize dedicated DDR I/O circuitry for the input and output data bus and the K and Kn output clock signals. Both QDR and QDRII SRAM burst-of-two devices sample the read address on the rising edge of the K clock and sample the write address on the rising edge of the Kn clock while QDR and QDRII SRAM burst-offour devices sample both read and write addresses on the K clock's rising edge. You can use any of the Stratix and Stratix GX device user I/O pins in I/O banks 3, 4, 7, and 8 for the D write data ports, commands, and addresses. QDR SRAM uses the following clock signals: input clocks K and Kn and output clocks C and Cn. In addition to the aforementioned two pairs of clocks, QDRII SRAM also uses echo clocks CQ and CQn. Clocks Cn, Kn, and CQn are logical complements of clocks C, K, and CQ respectively. Clocks C, Cn, K, and Kn are inputs to the QDRII SRAM while clocks CQ and CQn are outputs from the QDRII SRAM. Stratix and Stratix GX devices use single-clock mode for single-device QDR and QDRII SRAM interfacing where the K and Kn are used for both read and write operations, and the C and Cn clocks are unused. Use both C or Cn and K or Kn clocks when interfacing with a bank of multiple QDRII SRAM devices with a single controller. You can generate C, Cn, K, and Kn clocks using any of the I/O registers in I/O banks 3, 4, 7, or 8 via the DDR registers. Due to strict skew requirements between K and Kn signals, use adjacent pins to generate the clock pair. Surround the pair with buffer pins tied to VCC and ground for better noise immunity from other signals. In general, all output signals to the QDR and QDRII SRAM should use the top and bottom banks (I/O banks 3, 4, 7, or 8). You can place the input signals from the QDR and QDRII SRAM in any I/O banks. Read & Write Operations Figure 3–5 shows the data and clock relationships in QDRII SRAM devices at the memory pins during reads. QDR and QDRII SRAM devices send data within a tCO time after each rising edge of the input clock C or Cn in multi-clock mode, or the input clock K or Kn in single clock mode. Data is valid until tDOH time, after each rising edge of the C or Cn in multi- Altera Corporation June 2006 3–7 Stratix Device Handbook, Volume 2 External Memory Standards clock mode, or K or Kn in single clock mode. The edge-aligned CQ and CQn clocks accompany the read data for data capture in Stratix and Stratix GX devices. Figure 3–5. Data & Clock Relationship During a QDRII SRAM Read Note (1) C/K Cn/Kn tCO (2) Q tCO (2) QA tCLZ (3) QA + 1 tDOH (2) QA + 2 QA + 3 tCHZ (3) CQ tCQD (4) CQn tCCQO (5) tCQOH (5) tCQD (4) Notes to Figure 3–5: (1) (2) (3) (4) (5) The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18. CO is the data clock-to-out time and tDOH is the data output hold time between burst. tCLZ and tCHZ are bus turn-on and turn-off times respectively. tCQD is the skew between CQn and data edges. tCQQO and tCQOH are skew between the C or Cn (or K or Kn in single-clock mode) and the CQ or CQn clocks. When writing to QDRII SRAM devices, data is generated by the write clock, while the K clock is 90° shifted from the write clock, creating a center-aligned arrangement. f Go to www.qdrsram.com for the QDR SRAM and QDRII SRAM specifications. For more information on QDR and QDRII SRAM interfaces in Stratix and Stratix GX devices, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. ZBT SRAM ZBT SRAM eliminate dead bus cycles when turning a bidirectional bus around between reads and writes or between writes and reads. ZBT allows for 100% bus utilization because ZBT SRAM can be read or written on every clock cycle. Bus contention can occur when shifting from a write cycle to a read cycle or vice versa with no idle cycles in between. ZBT SRAM allows small amounts of bus contention. To avoid bus contention, the output clock-to-low-impedance time (tZX) must be greater 3–8 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices than the clock-to-high-impedance time (tXZ). Stratix and Stratix GX device I/O pins can interface with ZBT SRAM devices at up to 200 MHz and can meet ZBT tCO and tSU timing requirements by controlling phase delay in clocks to the OE or output and input registers using an enhanced PLL. Figure 3–6 shows a flow-through ZBT SRAM operation where A1 and A3 are read addresses and A2 and A4 are write addresses. For pipelined ZBT SRAM operation, data is delayed by another clock cycle. Stratix and Stratix GX devices support up to 200-MHz ZBT SRAM operation using the 2.5-V or 3.3-V LVTTL I/O standard. Figure 3–6. tZX & tXZ Timing Diagram tZX clock addr A1 A2 A3 A4 tXZ dataout Q(A1) Q(A3) ZBT Bus Sharing Device tZX datain D(A3) wren Interface Pins ZBT SRAM uses one system clock input for all clocking purposes. Only the rising edge of this clock is used, since ZBT SRAM uses a single data rate scheme. The data bus, DQ, is bidirectional. There are three control signals to the ZBT SRAM: RW_N, BW_N, and ADV_LD_N. You can use any of the Stratix and Stratix GX device user I/O pins to interface to the ZBT SRAM device. f Altera Corporation June 2006 For more information on ZBT SRAM Interfaces in Stratix devices, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices. 3–9 Stratix Device Handbook, Volume 2 DDR Memory Support Overview DDR Memory Support Overview Table 3–1 shows the external RAM support in Stratix EP1S10 through EP1S40 devices and all Stratix GX devices. Table 3–2 shows the external RAM support in Stratix EP1S60 and EP1S80 devices. Table 3–1. External RAM Support in Stratix EP1S10 through EP1S40 & All Stratix GX Devices Maximum Clock Rate (MHz) DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade Flip-Chip Flip-Chip -7 Speed Grade -8 Speed Grade WireBond FlipChip WireBond FlipChip WireBond DDR SDRAM (1), (2) SSTL-2 200 167 133 133 100 100 100 DDR SDRAM - side banks (2), (3), (4) SSTL-2 150 133 110 133 100 100 100 RLDRAM II (4) 1.8-V HSTL 200 (5) (5) (5) (5) (5) (5) QDR SRAM (6) 1.5-V HSTL 167 167 133 133 100 100 100 QDRII SRAM (6) 1.5-V HSTL 200 167 133 133 100 100 100 ZBT SRAM (7) LVTTL 200 200 200 167 167 133 133 Notes to Table 3–1: (1) (2) (3) (4) (5) (6) (7) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available on the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. These performance specifications are preliminary. This device does not support RLDRAM II. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix and Stratix GX Devices. Table 3–2. External RAM Support in Stratix EP1S60 & EP1S80 (Part 1 of 2) Maximum Clock Rate (MHz) DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade SSTL-2 167 167 133 DDR SDRAM - side banks (2), (3) SSTL-2 150 133 133 QDR SRAM (4) 1.5-V HSTL 133 133 133 QDRII SRAM (4) 1.5-V HSTL 167 167 133 DDR SDRAM (1), (2) 3–10 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Table 3–2. External RAM Support in Stratix EP1S60 & EP1S80 (Part 2 of 2) Maximum Clock Rate (MHz) DDR Memory Type ZBT SRAM (5) I/O Standard LVTTL -5 Speed Grade -6 Speed Grade -7 Speed Grade 200 200 167 Notes to Table 3–2: (1) (2) (3) (4) (5) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available on the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the side banks (I/O banks 1, 2, 5, and 6) with no dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix and Stratix GX Devices. Stratix and Stratix GX devices support the data strobe or read clock signal (DQS) used in DDR SDRAM, and RLDRAM II devices. DQS signals are associated with a group of data (DQ) pins. Stratix and Stratix GX devices contain dedicated circuitry to shift the incoming DQS signals by 0°, 72°, and 90°. The DQS phase-shift circuitry uses a frequency reference to dynamically generate control signals for the delay chains in each of the DQS pins, allowing it to compensate for process, voltage, and temperature (PVT) variations. The dedicated circuitry also creates consistent margins that meet your data sampling window requirements. f Refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix Device Handbook for frequency limits regarding the 72 and 90° phase shift for DQS. In addition to the DQS dedicated phase-shift circuitry, every I/O element (IOE) in Stratix and Stratix GX devices contains six registers and one latch to achieve DDR operation. There is also a programmable delay chain in the IOE that can help reduce contention when interfacing with ZBT SRAM devices. DDR Memory Interface Pins Stratix and Stratix GX devices use data (DQ), data strobe (DQS), and clock pins to interface with DDR SDRAM and RLDRAM II devices. This section explains the pins used in the DDR SDRAM and RLDRAM II interfaces. For QDR, QDRII, and ZBT SRAM interfaces, see the “External Memory Standards” section. Altera Corporation June 2006 3–11 Stratix Device Handbook, Volume 2 DDR Memory Support Overview Figure 3–7 shows the DQ and DQS pins in ×8 mode. Figure 3–7. Stratix & Stratix GX Device DQ & DQS Groups in × 8 Mode Top or Bottom I/O Bank DQ Pins (1) DQS Pin Note to Figure 3–7: (1) There are at least eight DQ pins per group. Data & Data Strobe Pins Stratix and Stratix GX data pins for the DDR memory interfaces are called DQ pins. The Stratix and Stratix GX device I/O banks at the top (I/O banks 3 and 4) and the bottom (I/O banks 7 and 8) of the device support DDR SDRAM and RLDRAM II up to 200 MHz. These pins support DQS signals with DQ bus modes of ×8, ×16, or ×32. Stratix and Stratix GX devices can support either bidirectional data strobes or uni-directional read clocks. Depending on the external memory interface, either the memory device's read data strobes or read clocks feed the DQS pins. For ×8 mode, there are up to 20 groups of programmable DQS and DQ pins—10 groups in I/O banks 3 and 4 and 10 groups in I/O banks 7 and 8 (see Table 3–3). Each group consists of one DQS pin and a set of eight DQ pins. For ×16 mode, there are up to eight groups of programmable DQS and DQ pins—four groups in I/O banks 3 and 4, and four groups in I/O banks 7 and 8. The EP1S20 device supports seven ×16 mode groups. The EP1S10 device does not support ×16 mode. All other devices support the full eight groups. See Table 3–3. Each group consists of one DQS and 16 DQ pins. In ×16 mode, DQS1T, DQS3T, DQS6T, and DQS8T pins on the top side of the device, and DQS1B, DQS3B, DQS6B, and DQS8B pins on the 3–12 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices bottom side of the device are dedicated DQS pins. The DQS2T, DQS7T, DQS2B, and DQS7B pins are dedicated DQS pins for ×32 mode, and each group consists of one DQS and 32 DQ pins. Table 3–3. DQS & DQ Bus Mode Support Device Package Note (1) Number of ×8 Number of ×16 Groups Groups Number of ×32 Groups 672-pin BGA 672-pin FineLine BGA® 12 (2) 0 0 484-pin FineLine BGA 780-pin FineLine BGA 16 (3) 0 4 484-pin FineLine BGA 18 (4) 7 (5) 4 672-pin BGA 672-pin FineLine BGA 16 (3) 7 (5) 4 780-pin FineLine BGA 20 7 (5) 4 672-pin BGA 672-pin FineLine BGA 16 (3) 8 4 780-pin FineLine BGA 1,020-pin FineLine BGA 20 8 4 EP1S30 956-pin BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 20 8 4 EP1S40 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 20 8 4 EP1S60 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 20 8 4 EP1S80 956-pin BGA 1,508-pin FineLine BGA 1,923-pin FineLine BGA 20 8 4 EP1S10 EP1S20 EP1S25 Notes to Table 3–3: (1) (2) (3) (4) (5) For VREF guidelines, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2 or the Stratix GX Handbook, Volume 2. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8. This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8. These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8. Altera Corporation June 2006 3–13 Stratix Device Handbook, Volume 2 DDR Memory Support Overview The DQS pins are marked in the Stratix and Stratix GX device pin table as DQS[9..0]T or DQS[9..0]B, where T stands for top and B for bottom. The corresponding DQ pins are marked as DQ[9..0]T[7..0], where [9..0] indicates which DQS group the pins belong to. The numbering scheme starts from right to left on the package bottom view. When not used as DQ or DQS pins, these pins are available as user I/O pins. You can also create a design in a mode other than the ×8, ×16, or ×32 mode. The Quartus® II software uses the next larger mode with the unused DQ pins available as regular use I/O pins. For example, if you create a design for ×9 mode for an RLDRAM II interface (nine DQ pins driven by one DQS pin), the Quartus II software implements a ×16 mode with seven DQ pins unconnected to the DQS bus. These seven unused DQ pins can be used as regular I/O pins. 1 On the top and bottom side of the device, the DQ and DQS pins must be configured as bidirectional DDR pins to enable the DQS phase-shift circuitry. If you only want to use the DQ and/or DQS pins as inputs, you need to set the output enable of the DQ and/or DQS pins to ground. Use the altdqs and altdq megafunctions to configure the DQS and DQ pins, respectively. However, you should use the Altera® IP Toolbench to create the data path for your memory interfaces. Stratix and Stratix GX device side I/O banks (I/O banks 1, 2, 5, and 6) support SDR SDRAM, ZBT SRAM, QDR SRAM, QDRII SRAM, and DDR SDRAM interfaces and can use any of the user I/O pins in these banks for the interface. Since these I/O banks do not have any dedicated circuitry for memory interfacing, they can support DDR SDRAM up to 150 MHz in -5 speed grade devices. However, these I/O banks do not support the HSTL-18 Class II I/O standard, which is required to interface with RLDRAM II. Clock Pins You can use any of the DDR I/O registers in the top or bottom bank of the device (I/O banks 3, 4, 7, or 8) to generate clocks to the memory device. You can also use any of the DDR I/O registers in the side I/O banks 1, 2, 5, or 6 to generate clocks for DDR SDRAM interfaces on the side I/O banks (not using the DQS circuitry). 3–14 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Command & Address Pins You can use any of the user I/O pins in the top or bottom bank of the device (I/O banks 3, 4, 7, or 8) for commands and addresses. For DDR SDRAM, you can also use any of the user I/O pins in the side I/O banks 1, 2, 5, or 6, regardless of whether you use the DQS phase-shift circuitry or not. Other Pins (Parity, DM, ECC & QVLD Pins) You can use any of the DQ pins for the parity pins in Stratix and Stratix GX devices. However, this may mean that you are using the next larger DQS/DQ mode. For example, if you need a parity bit for each byte of data, you are actually going to have nine DQ pins per DQS pin. The Quartus II software then implements a ×16 mode, with the seven unused DQ pins available as user I/O pins. The data mask (DM) pins are only required when writing to DDR SDRAM and RLDRAM II devices. A low signal on the DM pins indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. You can use any of the I/O pins in the same bank as the DQ pins for the DM signals. Each group of DQS and DQ signals requires a DM pin. The DDR register, clocked by the –90° shifted clock, creates the DM signals, similar to DQ output signals. Some DDR SDRAM devices support error correction coding (ECC), which is a method of detecting and automatically correcting errors in data transmission. Connect the DDR ECC pins to a Stratix and Stratix GX device DQS/DQ group. In 72-bit DDR SDRAM, there are eight ECC pins in addition to the 64 data pins. The memory controller needs extra logic to encode and decode the ECC data. QVLD pins are used in RLDRAM II interfacing to indicate the read data availability. There is one QVLD pin per RLDRAM II device. A high on QVLD indicates that the memory is outputting the data requested. Similar to DQ inputs, this signal is edge-aligned with the RLDRAM II read clocks, QK and QK#, and is sent half a clock cycle before data starts coming out of the memory. You can connect QVLD pins to any of the I/O pins in the same bank as the DQ pins for the QVLD signals. DQS Phase-Shift Circuitry Two single phase-shifting reference circuits are located on the top and bottom of the Stratix and Stratix GX devices. Each circuit is driven by a system reference clock that is of the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase-shift circuitry on the Altera Corporation June 2006 3–15 Stratix Device Handbook, Volume 2 DDR Memory Support Overview bottom of the device. The phase-shift circuitry cannot be fed from other sources such as the LE or the PLL internal output clocks. This phase-shift circuitry is used for DDR SDRAM and RLDRAM II interfaces. For best performance, turn off the input reference clock to the DQS phase-shift circuitry when reading from the DDR SDRAM or RLDRAM II. This is to avoid any DLL jitter incorrectly shifting the DQS signal while the FPGA is capturing data. 1 The I/O pins in I/O banks 1, 2, 5, and 6 can interface with the DDR SDRAM at up to 150 MHz. See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. A compensated delay element on each DQS pin allows for either a 90° or a 72° phase shift, which automatically centers input DQS signals with the data valid window of their corresponding DQ data signals. The DQS signals drive a local DQS bus within the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and clocks DQ input registers with the DQS signal. f Refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix Device Handbook for frequency limits regarding the 72 and 90° phase shift for DQS. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device. The phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device shift by the same degree amount. For example, all 10 DQS pins on the top of the device can be shifted by 90° and all 10 DQS pins on the bottom of the device can be shifted by 72°. The reference circuit requires a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. 1 This applies only to the initial phase calculation. Altera recommends that you enable the DLL during the refresh cycle of the DDR SDRAM. Enabling the DLL for the duration of the minimum refresh time is sufficient for recalculating the phase shift. Figure 3–8 shows the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. 3–16 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–8. DQS & DQSn Pins & the DQS Phase-Shift Circuitry Note (1) CLK[15..12] (2) DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin Compensated Delay Element Δt Δt Δt Δt Phase Shift Reference Circuit Δt Δt Δt Δt Δt Δt DQS Bus Notes to Figure 3–8: (1) (2) There are up to 10 DQS and DQSn pins available on the top or the bottom of the Stratix and Stratix GX devices. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. The reference clock can also be used in the logic array. The phase-shift circuitry is only used during read transactions where the DQS pins are acting as input clocks or strobes. The phase-shift circuitry can shift the incoming DQS signal by 0°, 72°, and 90°. The shifted DQS signal is then inverted and used as a clock or a strobe at the DQ IOE input registers. f Refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix Device Handbook for frequency limits regarding the 72 and 90° phase shift for DQS. The DQS phase-shift circuitry is bypassed when 0° shift is chosen. The routing delay between the pins and the IOE registers is matched with high precision for both the DQ and DQS signal when the 72° or 90° phase shift is used. With the 0° phase shift, the skew between DQ and the DQS signals at the IOE register has been minimized. See Table 3–4 for the Quartus II software reported number on the DQ and DQS path to the IOE when the DQS is set to 0° phase shift. Table 3–4. Quartus II Reported Number on the DQS Path to the IOE Note (1) Altera Corporation June 2006 Speed Grade DQ2IOE DQS2IOE Unit -5 0.908 1.008 ns -6 0.956 1.061 ns -7 1.098 1.281 ns 3–17 Stratix Device Handbook, Volume 2 DDR Memory Support Overview Table 3–4. Quartus II Reported Number on the DQS Path to the IOE Note (1) Speed Grade DQ2IOE DQS2IOE Unit -8 1.293 1.635 ns Note to Table 3–4: (1) These are reported by Quartus II version 4.0. Check the latest version of the Quartus II software for the most current information. To generate the correct phase shift, you must provide a clock signal of the same frequency as the DQS signal to the DQS phase-shift circuitry. Any of the CLK[15..12]p clock pins can feed the phase circuitry on the top of the device (I/O banks 3 and 4) and any of the CLK[7..4]p clock pins can feed the phase circuitry on the bottom of the device (I/O banks 7 and 8). Both the top and bottom phase-shift circuits need unique clock pins for the reference clock. You cannot use any internal clock sources to feed the phase-shift circuitry, but you can route internal clock sources off-chip and then back into one of the allowable clock input pins. DLL The DQS phase-shift circuitry uses a DLL to dynamically measure the clock period needed by the DQS pin (see Figure 3–9). The DQS phase-shift circuitry then uses the clock period to generate the correct phase shift. The DLL in the Stratix and Stratix GX devices DQS phaseshift circuitry can operate between 100 and 200 MHz. The phase-shift circuitry needs a maximum of 256 clock cycles to calculate the correct phase shift. Data sent during these clock cycles may not be properly captured. 1 3–18 Stratix Device Handbook, Volume 2 You can still use the DQS phase-shift circuitry for DDR SDRAM interfaces that are less than 100 MHz. The DQS signal is shifted by about 2.5 ns. This shifted DQS signal is not in the center of the DQ signals, but it is shifted enough to capture the correct data in this low-frequency application. Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–9. Simplified Diagram of the DQS Phase-Shift Circuitry Input Reference Clock Phase Comparator Up/Down Counter Delay Chains 6 Control Signals to DQS Pins The input reference clock goes into the DLL to a chain of delay elements. The phase comparator compares the signal coming out of the end of the delay element chain to the input reference clock. The phase comparator then issues the upndn signal to the up/down counter. This signal increments or decrements a six-bit delay setting (control signals to DQS pins) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. The shifted DQS signal then goes to the DQS bus to clock the IOE input registers of the DQ pins. It cannot go into the logic array for other purposes. For external memory interfaces that use a bidirectional read strobe like DDR SDRAM, the DQS signal is low before going to or coming from a high-impedance state (see Figure 3–1 on page 3–3). The state where DQS is low just after a high-impedance state is called the preamble and the state where DQS is low just before it returns to high-impedance state is called the postamble. There are preamble and postamble specifications for both read and write operations in DDR SDRAM. To ensure data is not lost when there is noise on the DQS line at the end of a read postamble time, you need to add soft postamble circuitry to disable the clocks at the DQ IOE registers. f Altera Corporation June 2006 For more information, the DQS Postamble soft logic is described in AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. The Altera DDR SDRAM controller MegaCore® generates this logic as open-source code. 3–19 Stratix Device Handbook, Volume 2 DDR Memory Support Overview DDR Registers Each Stratix and Stratix GX IOE contains six registers and one latch. Two registers and a latch are used for input, two registers are used for output, and two registers are used for output enable control. The second output enable register provides the write preamble for the DQS strobe in the DDR external memory interfaces. This negative-edge output enable register extends the high-impedance state of the pin by a half clock cycle to provide the external memory's DQS preamble time specification. Figure 3–10 shows the six registers and the latch in the Stratix and Stratix GX IOE and Figure 3–11 shows how the second OE register extends the DQS high impedance state by half a clock cycle during a write operation. 3–20 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–10. Bidirectional DDR I/O Path in Stratix & Stratix GX Devices Note (1) DFF OE (2) D Q OR2 OE Register AOE (3) 1 0 (4) DFF D Q OE Register BOE (5) DFF datain_l D Q 0 1 TRI (6) I/O Pin (7) Output Register AO DFF Logic Array datain_h D Q Output Register BO outclock combout DFF dataout_h Q D Input Register AI LatchTCHLA dataout_l Q D DFF neg_reg_out Q D ENA Latch C I Input Register BI inclock Notes to Figure 3–10: (1) (2) (3) (4) (5) (6) (7) All control signals can be inverted at the IOE. No programmable delay chains are shown in this diagram. The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an inverter before input to the AOE register during compilation. The AOE register generates the enable signal for general-purpose DDR I/O applications. This select line is to choose whether the OE signal should be delayed by half-a-clock cycle. The BOE register generates the delayed enable signal for the write strobes and write clock for memory interfaces. The tristate enable is active low by default. You can design it to be active high. The combinational control path for the tristate is not shown in this diagram. You can also have combinational output to the I/O pin; this path is not shown in the diagram. Altera Corporation June 2006 3–21 Stratix Device Handbook, Volume 2 DDR Memory Support Overview Figure 3–11. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction Note (1) System clock (outclock for DQS) OE for DQS (from logic array) 90˚ DQS Delay by Half a Clock Cycle Preamble Postamble Write Clock (outclock for DQ, −90° phase shifted from System Clock) datain_h (from logic array) D0 D2 datain_l (from logic array) D1 D3 OE for DQ (from logic array) D0 DQ D1 D2 D3 Note to Figure 3–11: (1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the Quartus II software implements this signal as an active high and automatically adds an inverter before the AOE register D input. Figures 3–12 and 3–13 summarize the IOE registers used for the DQ and DQS signals. 3–22 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE Note (1) DFF (2) D OE Q OE Register AOE DFF D datain_l Q 0 1 Output Register AO TRI DQ Pin DFF Logic Array D datain_h Q Output Register BO outclock (3) DFF Q D dataout_h Input Register AI Latch TCH LA Q dataout_l D DFF neg_reg_out Q D ENA Latch C I Input Register BI inclock (from DQS bus) (4) Notes to Figure 3–12: (1) (2) (3) (4) You can use the altdq megafunction to generate the DQ signals. The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an inverter before the OE register AOE during compilation. The outclock signal is phase shifted –90° from the system clock. The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq megafunction to generate the DQ signals. Altera Corporation June 2006 3–23 Stratix Device Handbook, Volume 2 DDR Memory Support Overview Figure 3–13. DQS Configuration in Stratix & Stratix GX IOE Note (1) DFF OE (2) D Q OE Register AOE OR2 1 0 (3) DFF D Q OE Register BOE DFF Logic Array datain_h (3) D Q 0 Output Register AO TRI DQS Pin (5) 1 DFF datain_l (4) system clock D Q Output Register BO undelayed DQS (6) combout (7) DQS Phase Shift Circuitry (8) Notes to Figure 3–13: (1) (2) (3) (4) (5) (6) (7) (8) You can use the altdqs megafunction to generate the DQS signals. The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an inverter before OE register AOE during compilation. The select line can be chosen in the altdqs MegaWizard Plug-In Manager. The datain_l and datain_h pins are usually connected to VCC and ground, respectively. DQS postamble handling is not shown in this diagram. For more information, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. This undelayed DQS signal goes to the LE for the soft postamble circuitry. You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction. DQS phase-shift circuitry is only available on DQS pins. 3–24 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices The Stratix and Stratix GX DDR IOE structure requires you to invert the incoming DQS signal by using a NOT gate to ensure proper data transfer. The altdq megafunction automatically adds the inverter when it generates the DQ signals. As shown in Figure 3–10, the inclock signal's rising edge clocks the AI register, inclock signal's falling edge clocks the BI register, and latch CI is opened when inclock is one. In a DDR memory read operation, the last data coincides with DQS being low. If you do not invert the DQS pin, you do not get this last data because the latch does not open until the next rising edge of the DQS signal. The NOT gate is inserted automatically if the altdg megafunction is used; otherwise you need to add the NOT gate manually. Figure 3–14 shows waveforms of the circuit shown in Figure 3–12. The second set of waveforms in Figure 3–14 shows what happens if the shifted DQS signal is not inverted; the last data, Dn, does not get latched into the logic array as DQS goes to tristate after the read postamble time. The third set of waveforms in Figure 3–14 shows a proper read operation with the DQS signal inverted after the 90° shift; the last data Dn does get latched. In this case the outputs of register AI and latch CI, which correspond to dataout_h and dataout_l ports, are now switched because of the DQS inversion. Altera Corporation June 2006 3–25 Stratix Device Handbook, Volume 2 DDR Memory Support Overview Figure 3–14. DQ Captures with Non-Inverted & Inverted Shifted DQS DQ & DQS Signals DQ at the pin Dn − 1 Dn DQS at the pin Shifted DQS Signal is Not Inverted DQS shifted by 90˚ Output of register A1 (dataout_h) Output of register B1 Output of latch C1 (dataout_l) Dn − 1 Dn − 2 Dn Dn − 2 Shifted DQS Signal is Inverted DQS inverted and shifted by 90˚ Output of register A1 (dataout_h) Output of register B1 Output of latch C1 (dataout_l) 3–26 Stratix Device Handbook, Volume 2 Dn − 2 Dn Dn − 1 Dn − 3 Dn − 1 Altera Corporation June 2006 External Memory Interfaces in Stratix & Stratix GX Devices PLL When using the Stratix and Stratix GX top and bottom I/O banks (I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL with two outputs is needed to generate the system clock and the write clock. The system clock generates the DQS write signals, commands, and addresses. The write clock is –90° shifted from the system clock and generates the DQ signals during writes. When using the Stratix and Stratix GX side I/O banks 1, 2, 5, or 6 to interface with DDR SDRAM devices, two PLLs may be needed per I/O bank for best performance. The side I/O banks do not have dedicated circuitry, so one PLL captures data from the DDR SDRAM and another PLL generates the write signals, commands, and addresses to the DDR SDRAM device. Stratix and Stratix GX devices side I/O banks can support DDR SDRAM up to 150 MHz. f Conclusion Altera Corporation June 2006 For more information, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. Stratix and Stratix GX devices support SDR SDRAM, DDR SDRAM, RLDRAM II, QDR SDRAM, QDRII SRAM, and ZBT SRAM external memories. Stratix and Stratix GX devices feature high-speed interfaces that transfer data between external memory devices at up to 200 MHz/400 Mbps. Phase-shift circuitry in the Stratix and Stratix GX devices allows you to ensure that clock edges are properly aligned. 3–27 Stratix Device Handbook, Volume 2 Conclusion 3–28 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Section III. I/O Standards This section provides information on Stratix® single-ended, voltagereferenced, and differential I/O standards. It contains the following chapters: Revision History ■ Chapter 4, Selectable I/O Standards in Stratix & Stratix GX Devices ■ Chapter 5, High-Speed Differential I/O Interfaces in Stratix Devices The table below shows the revision history for Chapters 4 and 5. Chapter Date/Version 4 June 2006, v3.4 ● Updated “AC Hot Socketing Specification” section. July 2005, v3.3 ● ● Updated “Non-Voltage-Referenced Standards” section. Minor change to Table 4–6. ● Updated content throughout. January 2005, v3.2 Altera Corporation Changes Made Comments Section III–1 I/O Standards Chapter Stratix Device Handbook, Volume 2 Date/Version September 2004, v3.1 Changes Made ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● April 2004, v3.0 ● ● ● November 2003, v2.2 ● ● October 2003, v2.1 ● ● July 2003, v2.0 ● ● ● ● ● ● Section III–2 Comments Table 4–1 on page 4–1: renamed table, updated table, and added Note 1. Deleted Figure named “1.5-V Differential HSTL Class II Termination.” Updated text describing “SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3” on page 4–11. Updated HyperTransport data rates on page 4–17. Changed HyperTransport device speed from 800 MHz to 400 MHz on page 4–17. Added four rows to Table 4–2 on page 4–18: 1.5V HSTL Class I, 1.8-V HSTL Class I, 1.5-V HSTL Class II, and 1.8-V HSTL Class II. Changed title of Table 4–3 on page 4–21. Updated Table 4–4 on page 4–22. Updated Figure 4–20 on page 4–29. Added description of which clock pins support differential on-chip termination on page 4–30. Updated description of flip-chip packages on page 4–31. Changed title of Figure 4–21 on page 4–31. Updated milliamps for non-thermally enhanced cavity up and non-thermally enhanced FineLine BGA packages on page 4–35. Updated equation for FineLine BGA package on page 4–35. Updated milliamps in non-thermally enhanced cavity up and non-thermally enhanced FineLine BGA packages onpage 4–37. Updated notes to Figure 4–18. New information added to the “Hot Socketing” section. New information added to the “Differential Pad Placement Guidelines” section. Removed support for series and parallel on-chip termination. Updated Figure 4–22. Added the Output Enable Group Logic Option in Quartus II and Toggle Rate Logic Option in Quartus II sections. Updated notes to Table 4–10. Renamed impedance matching to series termination throughout Chapter. Removed wide range specs for LVTTL and LVCMOS standards pages 4-3 to 4-5. Relaxed restriction of input pins next to differential pins for flipchip packages (pages 4-20, 4-35, and 4-36). Added Drive Strength section on page 4-26. Removed text “for 10 ns or less” from AC Hot socketing specification on page 4-27. Added Series Termination column to Table 4-9. Altera Corporation I/O Standards Chapter Date/Version 5 July 2005, v3.2 September 2004, v3.1 Changes Made Updated Table 5–14 on page 5–58. ● ● ● ● ● ● ● April 2004, v3.0 ● ● ● November 2003, v2.2 ● ● Updated Note 3 in Table 5–10 on page 5–54. Updated Table 5–7 on page 5–34. Updated Table 5–8 on page 5–36. Updated description of “RD Differential Termination” on page 5–46. Updated Note 5 in Table 5–14 on page 5–58. Updated Notes 2, 5, and 7 in Table 5–11 on page 5–56 through Table 5–14 on page 5–58. Added new text about spanning two I/O banks on page 5–60. Updated notes for Figure 5–17. Updated Table 5–7, 5–8, and 5–10. “Data Alignment with Clock” section, last sentence: change made from 90 degrees to 180 degrees. Removed support for series and parallel on-chip termination. Updated the number of channels per PLL in Tables 5-10 through 5-14. October 2003, v2.1 ● Added -8 speed grade device information, including Tables 5-7 and 5-8. July 2003, v2.0 ● Format changes throughout Chapter. Relaxed restriction of input pins next to differential pins for flip chip packages in Figure 5-1, Note 5. Wire bond package performance specification for “high” speed channels was increased to 624 Mbps from 462 Mbps throughout Chapter. Updated high-speed I/O specification for J=2 in Tables 5-7 and 5-8. Updated Tables 5-10 to 5-14 to reflect PLL cross-bank support for high-speed differential channels at full speed. Increased maximum output clock frequency to 462 to 500 MHz on page 5-66. ● ● ● ● ● Altera Corporation Comments Section III–3 I/O Standards Section III–4 Stratix Device Handbook, Volume 2 Altera Corporation 4. Selectable I/O Standards in Stratix & Stratix GX Devices S52004-3.4 Introduction The proliferation of I/O standards and the need for higher I/O performance have made it critical that devices have flexible I/O capabilities. Stratix® and Stratix GX programmable logic devices (PLDs) feature programmable I/O pins that support a wide range of industry I/O standards, permitting increased design flexibility. These I/O capabilities enable fast time-to-market and high-performance solutions to meet the demands of complex system designs. Additionally, Stratix and Stratix GX devices simplify system board design and make it easy to connect to microprocessors, peripherals, memories, gate arrays, programmable logic circuits, and standard logic functions. This chapter provides guidelines for using one or more industry I/O standards in Stratix and Stratix GX devices, including: ■ ■ ■ ■ ■ ■ ■ ■ Stratix & Stratix GX I/O Standards Stratix and Stratix GX I/O standards High-speed interfaces Stratix and Stratix GX I/O banks Programmable current drive strength Hot socketing Differential on-chip termination I/O pad placement guidelines Quartus® II software support Stratix and Stratix GX devices support a wide range of industry I/O standards as shown in the Stratix Device Family Data Sheet section in the Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1. Several applications that use these I/O standards are listed in Table 4–1. Table 4–1. I/O Standard Applications & Performance (Part 1 of 2) Note (1) I/O Standard Altera Corporation June 2006 Application Performance 3.3-V LVTTL/LVCMOS General purpose 350 MHz 2.5-V LVTTL/LVCMOS General purpose 350 MHz 1.8-V LVTTL/LVCMOS General purpose 250 MHz 1.5-V LVCMOS General purpose 225 MHz PCI/CompactPCI PC/embedded systems 66 MHz 4–1 Stratix & Stratix GX I/O Standards Table 4–1. I/O Standard Applications & Performance (Part 2 of 2) Note (1) I/O Standard Application Performance PCI-X 1.0 PC/embedded systems 133 MHz AGP 1× and 2× Graphics processors 66 to 133 MHz SSTL-3 Class I and II SDRAM 167 MHz SSTL-2 Class I and II DDR I SDRAM 160 to 400 Mbps HSTL Class I QDR SRAM/SRAM/CSIX 150 to 225 MHz HSTL Class II QDR SRAM/SRAM/CSIX 150 to 250 MHz Differential HSTL Clock interfaces 150 to 225 MHz GTL Backplane driver 200 MHz GTL+ Pentium processor interface 133 to 200 MHz LVDS Communications 840 Mbps HyperTransport technology Motherboard interfaces 800 Mbps LVPECL PHY interface 840 Mbps PCML Communications 840 Mbps Differential SSTL-2 DDR I SDRAM 160 to 400 Mbps CTT Back planes and bus interfaces 200 MHz Note to Table 4–1: (1) These performance values are dependent on device speed grade, package type (flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1. 3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) EIA/JEDEC Standard JESD8-B The 3.3-V LVTTL I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVTTL standard defines the DC interface parameters for digital circuits operating from a 3.0-V or 3.3-V power supply and driving or being driven by LVTTL-compatible devices. The LVTTL input standard specifies a wider input voltage range of –0.5 V ≤VI ≤ 3.8 V. Altera allows an input voltage range of –0.5 V ≤VI ≤ 4.1 V. The LVTTL standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels for 3.3-V LVTTL operation. 4–2 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices 3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B The 3.3-V low voltage complementary metal oxide semiconductor (LVCMOS) I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVCMOS standard defines the DC interface parameters for digital circuits operating from a 3.0-V or 3.3-V power supply and driving or being driven by LVCMOS-compatible devices. The LVCMOS standard specifies the same input voltage requirements as LVTTL (–0.5 V ≤VI ≤ 3.8 V). The output buffer drives to the rail to meet the minimum high-level output voltage requirements. The 3.3-V I/O standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels for 3.3-V LVCMOS operation. 2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V devices. The input and output voltage ranges are: ■ ■ The 2.5-V normal range input standards specify an input voltage range of – 0.3 V ≤ VI ≤ 3.0 V. The normal range minimum high-level output voltage requirement (VOH) is 2.1 V. Stratix and Stratix GX devices support both input and output levels for 2.5-V LVTTL operation. 2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V parts. The input and output voltage ranges are: ■ ■ Altera Corporation June 2006 The 2.5-V normal range input standards specify an input voltage range of – 0.5 V ≤ VI ≤ 3.0 V. The normal range minimum VOH requirement is 2.1 V. 4–3 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards Stratix and Stratix GX devices support both input and output levels for 2.5-V LVCMOS operation. 1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V parts. The input and output voltage ranges are: ■ ■ The 1.8-V normal range input standards specify an input voltage range of – 0.5 V ≤ VI ≤ 2.3 V. The normal range minimum VOH requirement is VCCIO – 0.45 V. Stratix and Stratix GX devices support both input and output levels for 1.8-V LVTTL operation. 1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V devices. The input and output voltage ranges are: ■ ■ The 1.8-V normal range input standards specify an input voltage range of – 0.5 V ≤ VI ≤ 2.5 V. The normal range minimum VOH requirement is VCCIO – 0.45 V. Stratix and Stratix GX devices support both input and output levels for 1.8-V LVCMOS operation. 1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard JESD8-11 The 1.5-V I/O standard is used for 1.5-V applications. This standard defines the DC interface parameters for high-speed, low-voltage, nonterminated digital circuits driving or being driven by other 1.5-V devices. The input and output voltage ranges are: ■ ■ The 1.5-V normal range input standards specify an input voltage range of – 0.5 V ≤ VI ≤ 2.0 V. The normal range minimum VOH requirement is 1.05 V. 4–4 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Stratix and Stratix GX devices support both input and output levels for 1.5-V LVCMOS operation. 1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6 The high-speed transceiver logic (HSTL) I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic switching range. This standard defines single ended input and output specifications for all HSTL-compliant digital integrated circuits. The single ended input standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Stratix and Stratix GX devices support both input and output levels specified by the 1.5-V HSTL I/O standard. The input clock is implemented using dedicated differential input buffers. Two singleended output buffers are automatically programmed to have opposite polarity so as to implement a differential output clock. Additionally, the 1.5-V HSTL I/O standard in Stratix and Stratix GX devices is compatible with the 1.8-V HSTL I/O standard in APEXTM 20KE and APEX 20KC devices because the input and output voltage thresholds are compatible. See Figures 4–1 and 4–2. Stratix and Stratix GX devices support both input and output levels with VREF and VTT. Figure 4–1. HSTL Class I Termination VTT = 0.75 V Output Buffer 50 Ω Z = 50 Ω Input Buffer VREF = 0.75 V Figure 4–2. HSTL Class II Termination VTT = 0.75 V VTT = 0.75 V Output Buffer 50 Ω 50 Ω Z = 50 Ω Input Buffer VREF = 0.75 V Altera Corporation June 2006 4–5 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards 1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6 The differential HSTL I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data rate (QDR) memory clock interfaces. The differential HSTL specification is the same as the single ended HSTL specification. The standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Differential HSTL does not require an input reference voltage, however, it does require a 50 Ω resistor termination resistor to VTT at the input buffer (see Figure 4–3). Stratix and Stratix GX devices support both input and output clock levels for 1.5-V differential HSTL. The input clock is implemented using dedicated differential input buffer. Two single-ended output buffers are automatically programmed to have opposite polarity so as to implement a differential output clock. Figure 4–3. 1.5-V Differential HSTL Class I Termination VTT = 0.75 V Differential Transmitter 50 Ω VTT = 0.75 V 50 Ω Differential Receiver Z0 = 50 Ω Z0 = 50 Ω 3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus Specification Rev. 2.3 The PCI local bus specification is used for applications that interface to the PCI local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The conventional PCI specification revision 2.3 defines the PCI hardware environment including the protocol, electrical, mechanical, and configuration specifications for the PCI devices and expansion boards. This standard requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant with the 3.3-V PCI Local Bus Specification Revision 2.3 and meet 64-bit/66-MHz operating frequency and timing requirements. The 3.3-V PCI standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels. 4–6 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices 3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus Specification Revision 1.0a The PCI-X 1.0 standard is used for applications that interface to the PCI local bus. The standard enables the design of systems and devices that operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. By using the PCI-X 1.0 standard, devices can be designed to meet PCI-X 1.0 requirements and operate as conventional 33- and 66-MHz PCI devices when installed in those systems. This standard requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133-MHz operating frequency and timing requirements. The 3.3-V PCI standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels. 3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification Revision 2.3 The Compact PCI local bus specification is used for applications that interface to the PCI local bus. It follows the PCI Local Bus Specification Revision 2.3 plus additional requirements in PCI Industrial Computers Manufacturing Group (PICMG) specifications PICMG 2.0 R3.0, CompactPCI specification, and the hot swap requirements in PICMG 2.1 R2.0, CompactPCI Hot Swap Specification. This standard has similar electrical requirements as LVTTL and requires 3.3-V VCCIO. Stratix and Stratix GX devices are compliant with the Compact PCI electrical requirements. The 3.3-V PCI standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels. 3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 The AGP interface is a platform bus specification that enables highperformance graphics by providing a dedicated high-speed port for the movement of large blocks of 3-dimensional texture data between a PC's graphics controller and system memory. The 1× AGP I/O standard is a single-ended standard used for 3.3-V graphics applications. The 1× AGP input standard specifies an input voltage range of – 0.5 V ≤ VI ≤ VCCIO + 0.5 V. The 1× AGP standard does not require input reference voltages or board terminations. Stratix and Stratix GX devices support both input and output levels. Altera Corporation June 2006 4–7 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards 3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 The 2× AGP I/O standard is a voltage-referenced, single-ended standard used for 3.3-V graphics applications. The 2× AGP input standard specifies an input voltage range of – 0.5V ≤ VI ≤ VCCIO + 0.5V. The 2× AGP standard does not require board terminations. Stratix and Stratix GX devices support both input and output levels. GTL - EIA/JEDEC Standard EIA/JESD8-3 The GTL I/O standard is a low-level, high-speed back plane standard used for a wide range of applications from ASICs and processors to interface logic devices. The GTL standard defines the DC interface parameters for digital circuits operating from power supplies of 2.5, 3.3, and 5.0 V. The GTL standard is an open-drain standard, and Stratix and Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this standard. GTL requires a 0.8-V VREF and open-drain outputs with a 1.2-V VTT (see Figure 4–4). Stratix and Stratix GX devices support both input and output levels. Figure 4–4. GTL Termination VTT = 1.2 V Output Buffer VTT = 1.2 V 50 Ω Z = 50 Ω 50 Ω Input Buffer VREF = 0.8 V GTL+ The GTL+ I/O standard is used for high-speed back plane drivers and Pentium processor interfaces. The GTL+ standard defines the DC interface parameters for digital circuits operating from power supplies of 2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain standard, and Stratix and Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this standard. GTL+ requires a 1.0-V VREF and open-drain outputs with a 1.5-V VTT (see Figure 4–5). Stratix and Stratix GX devices support both input and output levels. 4–8 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–5. GTL+ Termination VTT = 1.5 V VTT = 1.5 V Output Buffer 50 Ω 50 Ω Z = 50 Ω Input Buffer VREF = 1.0 V CTT - EIA/JEDEC Standard JESD8-4 The CTT I/O standard is used for backplanes and memory bus interfaces. The CTT standard defines the DC interface parameters for digital circuits operating from 2.5- and 3.3-V power supplies. The CTT standard does not require special circuitry to interface with LVTTL or LVCMOS devices when the CTT driver is not terminated. The CTT standard requires a 1.5-V VREF and a 1.5-V VTT (see Figure 4–6). Stratix and Stratix GX devices support both input and output levels. Figure 4–6. CTT Termination VTT = 1.5 V Output Buffer 50 Ω Z = 50 Ω Input Buffer VREF = 1.5 V SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8 The SSTL-3 I/O standard is a 3.3-V memory bus standard used for applications such as high-speed SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-3 requires a 1.5V VREF and a 1.5-V VTT to which the series and termination resistors are connected (see Figures 4–7 and 4–8). Stratix and Stratix GX devices support both input and output levels. Altera Corporation June 2006 4–9 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards Figure 4–7. SSTL-3 Class I Termination VTT = 1.5 V Output Buffer 50 Ω 25 Ω Z = 50 Ω Input Buffer VREF = 1.5 V Figure 4–8. SSTL-3 Class II Termination VTT = 1.5 V VTT = 1.5 V 50 Ω 50 Ω Output Buffer 25 Ω Z = 50 Ω Input Buffer VREF = 1.5 V SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A The SSTL-2 I/O standard is a 2.5-V memory bus standard used for applications such as high-speed DDR SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves operation in conditions where a bus must be isolated from large stubs. The SSTL-2 standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. SSTL-2 requires a 1.25-V VREF and a 1.25-V VTT to which the series and termination resistors are connected (see Figures 4–9 and 4–10). Stratix and Stratix GX devices support both input and output levels. Figure 4–9. SSTL-2 Class I Termination VTT = 1.25 V Output Buffer 50 Ω 25 Ω Z = 50 Ω Input Buffer VREF = 1.25 V 4–10 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–10. SSTL-2 Class II Termination VTT = 1.25 V VTT = 1.25 V Output Buffer 50 Ω 25 Ω 50 Ω Z = 50 Ω Input Buffer VREF = 1.25 V SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3 The SSTL-18 I/O standard is a 1.8-V memory bus standard. This standard is similar to SSTL-2 and defines input and output specifications for devices that are designed to operate in the SSTL-18 logic switching range 0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the series and termination resistors are connected. See Figures 4–11 and 4–12 for details on SSTL-18 Class I and II termination. Stratix and Stratix GX devices support both input and output levels. Figure 4–11. SSTL-18 Class I Termination VTT = 0.9 V Output Buffer 50 Ω 25 Ω Z = 50 Ω Input Buffer VREF = 0.9 V Figure 4–12. SSTL-18 Class II Termination VTT = 0.9 V VTT = 0.9 V 50 Ω 50 Ω Output Buffer 25 Ω Z = 50 Ω Input Buffer VREF = 0.9 V Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A The differential SSTL-2 I/O standard is a 2.5-V standard used for applications such as high-speed DDR SDRAM clock interfaces. This standard supports differential signals in systems using the SSTL-2 Altera Corporation June 2006 4–11 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards standard and supplements the SSTL-2 standard for differential clocks. The differential SSTL-2 standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. The differential SSTL-2 standard does not require an input reference voltage differential. See Figure 4–13 for details on differential SSTL-2 termination. Stratix and Stratix GX devices support output clock levels for differential SSTL-2 Class II operation. The output clock is implemented using two single-ended output buffers which are programmed to have opposite polarity. Figure 4–13. Differential SSTL-2 Class II Termination VTT = 1.25 V Differential Transmitter 50 Ω VTT = 1.25 V 50 Ω VTT = 1.25 V 50 Ω VTT = 1.25 V 50 Ω Differential Receiver 25 Ω Z0 = 50 Ω 25 Ω Z0 = 50 Ω LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644 The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard requiring a 3.3-V VCCIO. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 Mbps. However, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX devices meet the ANSI/TIA/EIA-644 standard. Due to the low voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than CMOS, TTL, and PECL. This low EMI makes LVDS ideal for applications with low EMI requirements or noise immunity requirements. The LVDS standard does not require an input reference voltage, however, it does require a 100 Ω termination resistor between the two signals at the input buffer. Stratix and Stratix GX devices include an optional differential LVDS termination resistor within the device using differential on-chip termination. Stratix and Stratix GX devices support both input and output levels. 4–12 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices f For more information on the LVDS I/O standard in Stratix devices, see the High-Speed Differential I/O Interfaces in Stratix Devices chapter. LVPECL The LVPECL I/O standard is a differential interface standard requiring a 3.3-V VCCIO. The standard is used in applications involving video graphics, telecommunications, data communications, and clock distribution. The high-speed, low-voltage swing LVPECL I/O standard uses a positive power supply and is similar to LVDS, however, LVPECL has a larger differential output voltage swing than LVDS. The LVPECL standard does not require an input reference voltage, but it does require a 100-Ω termination resistor between the two signals at the input buffer. See Figures 4–14 and 4–15 for two alternate termination schemes for LVPECL. Stratix and Stratix GX devices support both input and output levels. Figure 4–14. LVPECL DC Coupled Termination Output Buffer Input Buffer Z = 50 Ω 100 Ω Z = 50 Ω Figure 4–15. LVPECL AC Coupled Termination VCCIO VCCIO Output Buffer 10 to 100 nF Z = 50 Ω R1 R1 R2 R2 Input Buffer 100 Ω 10 to 100 nF Z = 50 Ω Pseudo Current Mode Logic (PCML) The PCML I/O standard is a differential high-speed, low-power I/O interface standard used in applications such as networking and telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O standard consumes less power than the LVPECL I/O standard. The Altera Corporation June 2006 4–13 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Standards PCML standard is similar to LVPECL, but PCML has a reduced voltage swing, which allows for a faster switching time and lower power consumption. The PCML standard uses open drain outputs and requires a differential output signal. See Figure 4–16 for details on PCML termination. Stratix and Stratix GX devices support both input and output levels. Additionally, Stratix GX devices support 1.5-V PCML as described in the Stratix GX Device Handbook, Volume 1. Figure 4–16. PCML Termination VTT Output Buffer 50 Ω 50 Ω Z = 50 Ω 50 Ω 50 Ω Input Buffer Z = 50 Ω HyperTransport Technology - HyperTransport Consortium The HyperTransport technology I/O standard is a differential highspeed, high-performance I/O interface standard requiring a 2.5-V VCCIO. This standard is used in applications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and Internet connectivity devices. The HyperTransport technology I/O standard is a point-to-point standard in which each HyperTransport technology bus consists of two point-to-point unidirectional links. Each link is 2 to 32 bits. The HyperTransport technology standard does not require an input reference voltage. However, it does require a 100-Ω termination resistor between the two signals at the input buffer. See Figure 4–17 for details on HyperTransport technology termination. Stratix and Stratix GX devices support both input and output levels. Figure 4–17. HyperTransport Technology Termination Output Buffer Input Buffer Z = 50 Ω 100 Ω Z = 50 Ω 4–14 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices f High-Speed Interfaces See the Stratix Device Family Data Sheet section in the Stratix Device Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O Interfaces in Stratix Devices chapter for more information on differential I/O standards. In addition to current industry physical I/O standards, Stratix and Stratix GX devices also support a variety of emerging high-speed interfaces. This section provides an overview of these interfaces. OIF-SPI4.2 This implementation agreement is widely used in the industry for OC-192 and 10-Gbps multi-service system interfaces. SONET and SDH are synchronous transmission systems over which data packets are transferred. POS-PHY Level 4 is a standard interface for switches and routers, and defines the operation between a physical layer (PHY) device and link layer devices (ATM, Internet protocol, and Gigabit Ethernet) for bandwidths of OC-192 ATM, POS, and 10-Gigabit Ethernet applications. Some key POS-PHY Level 4 system features include: ■ ■ ■ ■ ■ ■ ■ ■ ■ Large selection of POS-PHY Level 4-based PHYs Independent of data protocol Wide industry support LVDS I/O standard to improve signal integrity Inband addressing/control Out of band flow control Scalable architecture Over 622-Mbps operation Dynamic interface timing mode POS-PHY Level 4 operates at a wide range of frequencies. OIF-SFI4.1 This implementation agreement is widely used in the industry for interfacing physical layer (PHY) to the serializer-deserializer (SERDES) devices in OC-192 and 10 Gbps multi-service systems. The POS-PHY Level 4 interface standard defines the SFI-4 standard. POS-PHY Level 4: SFI-4 is a standardized 16-bit × 622-Mbps line-side interface for 10-Gbps applications. Internet LAN and WAN architectures use telecommunication SONET protocols for data transferring data over the PHY layer. SFI-4 interfaces between OC-192 SERDES and SONET framers. Altera Corporation June 2006 4–15 Stratix Device Handbook, Volume 2 High-Speed Interfaces 10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft Standard P802.3ae/D2.0 10 Gigabit Ethernet XSBI is an interface standard for LANs, metropolitan area networks (MANs), storage area networks (SANs), and WANs. 10 Gigabit Ethernet XSBI provides many features for efficient, effective high-speed networking, including easy migration to higher performance levels without disruption, lower cost of ownership including acquisition and support versus other alternatives, familiar management tools and common skills, ability to support new applications and data protocols, flexibility in network design, and multiple vendor sourcing and interoperability. Under the ISO Open Systems Interconnection (OSI) model, Ethernet is a Layer 2 protocol. 10 Gigabit Ethernet XSBI uses the IEEE 802.3 Ethernet media access control (MAC) protocol, Ethernet frame format, and the minimum/maximum frame size. An Ethernet PHY corresponding to OSI layer 1 connects the media to the MAC layer that corresponds to OSI layer 2. The PHY is divided into a physical media dependent (PMD) element, such as optical transceivers, and a physical coding sub-layer (PCS), which has coding and a serializer/multiplexor. This standard defines two PHY types, including the LAN PHY and the WAN PHY, which are distinguished by the PCS. The 10 Gigabit Ethernet XSBI standard is a full-duplex technology standard that can increase the speed and distance of Ethernet. RapidIO Interconnect Specification Revision 1.1 The RapidIO interface is a communications standard used to connect devices on a circuit board and circuit boards on a backplane. RapidIO is a packet-switched interconnect standard designed for embedded systems such as those used in networking and communications. The RapidIO interface standard is a high-performance interconnect interface used for transferring data and control information between microprocessors, DSPs, system memory, communications and network processors, and peripheral devices in a system. RapidIO replaces existing peripheral bus and processor technologies such as PCI. Some features of RapidIO include multiprocessing support, an open standard, flexible topologies, higher bandwidth, low latency, error management support in hardware, small silicon footprint, widely available process and I/O technologies, and transparency to existing applications and operating system software. The RapidIO standard provides 10-Gbps device bandwidth using 8-bit-wide input and output data ports. RapidIO uses LVDS technology, has the capability to be scaled to multi-GHz frequencies, and features a 10-bit interface. 4–16 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices HyperTransport Technology - HyperTransport Consortium The HyperTransport technology I/O standard is a differential high-speed, high performance I/O interface standard developed for communications and networking chip-to-chip communications. HyperTransport technology is used in applications such as highperformance networking, telecommunications, embedded systems, consumer electronics, and Internet connectivity devices. The HyperTransport technology I/O standard is a point-to-point (one source connected to exactly one destination) standard that provides a highperformance interconnect between integrated circuits in a system, such as on a motherboard. Stratix devices support HyperTransport technology at data rates up to 800 Mbps and 32 bits in each direction. HyperTransport technology uses an enhanced differential signaling technology to improve performance. HyperTransport technology supports data widths of 2, 4, 8, 16, or 32 bits in each direction. HyperTransport technology in Stratix and Stratix GX devices operates at multiple clock speeds up to 400 MHz. UTOPIA Level 4 – ATM Forum Technical Committee Standard AFPHY-0144.001 The UTOPIA Level 4 frame-based interface standard allows device manufacturers and network developers to develop components that can operate at data rates up to 10 Gbps. This standard increases interface speeds using LVDS I/O and advanced silicon technologies for fast data transfers. UTOPIA Level 4 provides new control techniques and a 32-, 16-, or 8-bit LVDS bus, a symmetric transmit/receive bus structure for easier application design and testability, nominal data rates of 10 Gbps, in-band control of cell delimiters and flow control to minimize pin count, sourcesynchronous clocking, and supports variable length packet systems. UTOPIA Level 4 handles sustained data rates for OC-192 and supports ATM cells. UTOPIA Level 4 also supports interconnections across motherboards, daughtercards, and backplane interfaces. Stratix & Stratix GX I/O Banks Altera Corporation June 2006 Stratix devices have eight I/O banks in addition to the four enhanced PLL external clock output banks, as shown in Table 4–2 and Figure 4–18. I/O banks 3, 4, 7, and 8 support all single-ended I/O standards. I/O banks 1, 2, 5, and 6 support differential HSTL (on input clocks), LVDS, LVPECL, PCML, and HyperTransport technology, as well as all single-ended I/O standards except HSTL Class II, GTL, SSTL-18 Class II, PCI/PCI-X 1.0, and 1× /2× AGP. The four enhanced PLL external clock output banks (I/O banks 9, 10, 11, and 12) support clock outputs all single-ended I/O 4–17 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Banks standards in addition to differential SSTL-2 and HSTL (both on the output clock only). Since Stratix devices support both non-voltage-referenced and voltage-referenced I/O standards, there are different guidelines when working with either separately or when working with both. Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 1 of 2) Enhanced PLL External Clock Output Banks I/O Bank I/O Standard 1 2 3 4 5 6 7 8 9 10 11 12 3.3-V LVTTL/LVCMOS v v v v v v v v v v v v 2.5-V LVTTL/LVCMOS v v v v v v v v v v v v 1.8-V LVTTL/LVCMOS v v v v v v v v v v v v 1.5-V LVCMOS v v v v v v v v v v v v PCI/PCIX//Compact PCI v v v v v v v v AGP 1× v v v v v v v v AGP 2× v v v v v v v v SSTL-3 Class I v v v v v v v v v v v v SSTL-3 Class II v v v v v v v v v v v v SSTL-2 Class I v v v v v v v v v v v v SSTL-2 Class II v v v v v v v v v v v v SSTL-18 Class I v v v v v v v v v v v v v v v v v v v v v v v v SSTL-18 Class II Differential SSTL-2 (output clocks) HSTL Class I v v v v v v v v v v v v 1.5-V HSTL Class I v v v v v v v v v v v v 1.8-V HSTL Class I v v v v v v v v v v v v HSTL Class II v v v v v v v v 1.5-V HSTL Class II v v v v v v v v 1.8-V HSTL Class II v v v v v v v v v v v v v v v v v v v v Differential HSTL (input clocks) v v v v Differential HSTL (output clocks) GTL 4–18 Stratix Device Handbook, Volume 2 v v v v Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 2 of 2) Enhanced PLL External Clock Output Banks I/O Bank I/O Standard 1 2 3 4 5 6 7 8 9 10 11 12 GTL+ v v v v v v v v v v v v CTT v v v v v v v v v v v v LVDS v v (1) (1) v v (1) (1) (2) (2) (2) (2) HyperTransport technology v v (1) (1) v v (1) (1) (2) (2) (2) (2) LVPECL v v (1) (1) v v (1) (1) (2) (2) (2) (2) PCML v v (1) (1) v v (1) (1) (2) (2) (2) (2) Notes to Table 4–2: (1) (2) This I/O standard is only supported on input clocks in this I/O bank. This I/O standard is only supported on output clocks in this I/O bank. Altera Corporation June 2006 4–19 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Banks Figure 4–18. Stratix I/O Banks Notes (1), (2), (3) DQS5T 9 DQS4T PLL11 (5) DQS1T DQS0T 10 Bank 4 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) (5) I/O Banks 1, 2, 5, and 6 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2× PLL2 Bank 1 DQS2T I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards PLL1 Bank 8 PLL3 DQS8B DQS7B DQS6B DQS5B (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) 11 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 DQS9B PLL4 I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) PLL8 DQS3T VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) Bank 2 VREF1B2 VREF2B2 VREF3B2 VREF4B2 Bank 3 VREF1B1 VREF2B1 VREF3B1 VREF4B1 PLL5 12 PLL6 Bank 5 DQS6T VREF4B5 VREF3B5 VREF2B5 VREF1B5 DQS7T Bank 6 DQS8T VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF4B6 VREF3B6 VREF2B6 VREF1B6 DQS9T PLL7 Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 DQS4B DQS3B DQS2B DQS1B PLL9 DQS0B Notes to Figure 4–18: (1) (2) (3) (4) (5) Figure 4–18 is a top view of the silicon die. This corresponds to a top-down view for non-flip-chip packages, but is a reverse view for flip-chip packages. Figure 4–18 is a graphic representation only. See the pin list and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2×. For guidelines on placing single-ended I/O pads next to differential I/O pads, see “I/O Pad Placement Guidelines” on page 4–30. 4–20 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Tables 4–3 and 4–4 list the I/O standards that Stratix GX enhanced and fast PLL pins support. Figure 4–19 shows the I/O standards that each Stratix GX I/O bank supports. Table 4–3. I/O Standards Supported in Stratix & Stratix GX Enhanced PLL Pins Input Output I/O Standard INCLK FBIN PLLENABLE EXTCLK LVTTL v v v v LVCMOS v v v v 2.5 V v v v 1.8 V v v v 1.5 V v v v 3.3-V PCI v v v 3.3-V PCI-X 1.0 v v v LVPECL v v v 3.3-V PCML v v v LVDS v v v HyperTransport technology v v v Differential HSTL v v v Differential SSTL 3.3-V GTL v v v 3.3-V GTL+ v v v 1.5-V HSTL Class I v v v 1.5-V HSTL Class II v v v SSTL-18 Class I v v v SSTL-18 Class II v v v SSTL-2 Class I v v v SSTL-2 Class II v v v SSTL-3 Class I v v v SSTL-3 Class II v v v AGP (1× and 2×) v v v CTT v v v Altera Corporation June 2006 4–21 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Banks Table 4–4. I/O Standards Supported in Stratix & Stratix GX Fast PLL Pins Input I/O Standard INCLK PLLENABLE LVTTL v v LVCMOS v v 2.5 V v 1.8 V v 1.5 V v 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL v 3.3-V PCML v LVDS v HyperTransport technology v Differential HSTL v Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5V HSTL Class I v 1.5V HSTL Class II SSTL-18 Class I v SSTL-18 Class II SSTL-2 Class I v SSTL-2 Class II v SSTL-3 Class I v SSTL-3 Class II v AGP (1× and 2×) CTT 4–22 Stratix Device Handbook, Volume 2 v Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–19. Stratix GX I/O Banks I/O Bank 2 I/O Banks 1 & 2 Support: ■ Differential I/O Standards - True LVDS - LVPECL - 3.3-V PCML - HyperTransport Technology ■ Single-Ended I/O Standard - 3.3 -, 2.5 -, 1.8 -V LVTTL - GTL+ - CTT - SSTL-18 Class I - SSTL-2 Class I and II - SSTL-3 Class I and II - 1.5 -, 1.8 -V HSTL Class I I/O Bank 1 I/O Bank 3 I/O Bank 4 I/O Banks 3, 4, 6 & 7 Support: ■ 3.3-, 2.5-, 1.8-V LVTTL ■ 3.3-V PCI, PCI-X 1.0 ■ GTL ■ GTL+ ■ AGP ■ CTT ■ SSTL-18 Class I and II ■ SSTL-2 Class I and II ■ SSTL-3 Class I and II ■ HSTL Class I and II Individual Power Bus I/O Bank 7 I/O Bank 6 I/O Bank 5 I/O Bank 5 Contains Transceiver Blocks There is some flexibility with the number of I/O standards each Stratix I/O bank can simultaneously support. The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in Stratix devices. Altera Corporation June 2006 4–23 Stratix Device Handbook, Volume 2 Stratix & Stratix GX I/O Banks Non-Voltage-Referenced Standards Each Stratix I/O bank has its own VCCIO pins and supports only one VCCIO, either 1.5, 1.8, 2.5 or 3.3 V. A Stratix I/O bank can simultaneously support any number of input signals with different I/O standard assignments, as shown in Table 4–5. Table 4–5. Acceptable Input Levels for LVTTL/LVCMOS Acceptable Input Levels Bank VCCIO 3.3 V 2.5 V 1.8 V 1.5 V 3.3 V v v 2.5 V v v 1.8 V v (2) v (2) v v (1) 1.5 V v (2) v (2) v v Notes to Table 4–5: (1) (2) Because the input signal will not drive to the rail, the input buffer does not completely shut off, and the I/O current will be slightly higher than the default value. These input values overdrive the input buffer, so the pin leakage current will be slightly higher than the default value. For output signals, a single I/O bank can only support non-voltagereferenced output signals driving at the same voltage as VCCIO. A Stratix I/O bank can only have one VCCIO value, so it can only drive out that one value for non-voltage referenced signals. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs, HyperTransport technology inputs and outputs, and 3.3-V LVCMOS inputs (not output or bidirectional pins). 1 If the output buffer overdrives the input buffer, you must turn on the Allow voltage overdrive for LVTTL/LVCMOS option in the Quartus II software. To see this option, click the Device & Pin Options button in the Device page of the Settings dialog box (Assignments menu). Then click the Pin Placement tab in the Device & Pin Options dialog box. Voltage-Referenced Standards To accommodate voltage-referenced I/O standards, each Stratix I/O bank supports multiple VREF pins feeding a common VREF bus. The number of available VREF pins increases as device density increases. If these pins are not used as VREF pins, they can not be used as generic I/O pins. 4–24 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices An I/O bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same VREF setting. For example, although one I/O bank can implement both SSTL-3 and SSTL-2 I/O standards, I/O pins using these standards must be in different banks since they require different VREF values For voltage-referenced inputs, the receiver compares the input voltage to the voltage reference and does not take into account the VCCIO setting. Therefore, the VCCIO setting is irrelevant for voltage referenced inputs. Voltage-referenced bidirectional and output signals must be the same as the I/O bank’s VCCIO voltage. For example, although you can place an SSTL-2 input pin in any I/O bank with a 1.25-V VREF level, you can only place SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO. Mixing Voltage Referenced & Non-Voltage Referenced Standards Non-voltage referenced and voltage referenced pins can safely be mixed in a bank by applying each of the rule-sets individually. For example, on I/O bank can support SSTL-3 inputs and 1.8-V LVCMOS inputs and outputs with a 1.8-V VCCIO and a 1.5-V VREF. Similarly, an I/O bank can support 1.5-V LVCMOS, 3.3-V LVTTL (inputs, but not outputs), and HSTL I/O standards with a 1.5-V VCCIO and 0.75-V VREF. For the voltage-referenced examples, see the “I/O Pad Placement Guidelines” section. For details on how the Quartus II software supports I/O standards, see the “Quartus II Software Support”section. Altera Corporation June 2006 4–25 Stratix Device Handbook, Volume 2 Drive Strength Drive Strength Each I/O standard supported by Stratix and Stratix GX devices drives out a minimum drive strength. When an I/O is configured as LVTTL or LVCMOS I/O standards, you can specify the current drive strength, as summarized in Table 4–7. Standard Current Drive Strength Each I/O standard supported by Stratix and Stratix GX devices drives out a minimum drive strength. Table 4–6 summarizes the minimum drive strength of each I/O standard. Table 4–6. Minimum Current Drive Strength of Each I/O Standard I/O Standard Current Strength, IOL/IOH (mA) GTL 40 (1) GTL+ 34 (1) SSTL-3 Class I 8 SSTL-3 Class II 16 SSTL-2 Class I 8.1 SSTL-2 Class II 16.4 SSTL-18 Class I 6.7 SSTL-18 Class II 13.4 1.5-V HSTL Class I 8 1.5-V HSTL Class II 16 CTT 8 AGP 1× IOL = 1.5, IOH = –0.5 Note to Table 4–6: (1) Because this I/O standard uses an open drain buffer, this value refers to IOL. When the SSTL-2 Class I and II I/O standards are implemented on top or bottom I/O pins, the drive strength is designed to be higher than the drive strength of the buffer when implemented on side I/O pins. This allows the top or bottom I/O pins to support 200-MHz operation with the standard 35-pF load. At the same time, the current consumption when using top or bottom I/O pins is higher than the side I/O pins. The high current strength may not be necessary for certain applications where the value of the load is less than the standard test load (e.g., DDR interface). The Quartus II software allows you to reduce the drive strength when the I/O pins are used for the SSTL-2 Class I or Class II I/O standard and being implemented on the top or bottom I/O through the Current Strength setting. Select the minimum strength for lower drive strength. 4–26 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Programmable Current Drive Strength The Stratix and Stratix GX device I/O pins support various output current drive settings as shown in Table 4–7. These programmable drive strength settings help decrease the effects of simultaneously switching outputs (SSO) in conjunction with reducing system noise. The supported settings ensure that the device driver meets the IOH and IOL specifications for the corresponding I/O standard. Table 4–7. Programmable Drive Strength I/O Standard IOH / IOL Current Strength Setting (mA) 3.3-V LVTTL 24 (1), 16, 12, 8, 4 3.3-V LVCMOS 24 (2), 12 (1), 8, 4, 2 2.5-V LVTTL/LVCMOS 16 (1), 12, 8, 2 1.8-V LVTTL/LVCMOS 12 (1), 8, 2 1.5-V LVCMOS 8 (1), 4, 2 Notes to Table 4–7: (1) (2) This is the Quartus II software default current setting. I/O banks 1, 2, 5, and 6 do not support this setting. These drive-strength settings are programmable on a per-pin basis (for output and bidirectional pins only) using the Quartus II software. To modify the current strength of a particular pin, see “Programmable Drive Strength Settings” on page 4–40. Hot Socketing Stratix devices support hot socketing without any external components. In a hot socketing situation, a device’s output buffers are turned off during system power-up or power-down. Stratix and Stratix GX devices support any power-up or power-down sequence (VCCIO and VCCINT) to simplify designs. For mixed-voltage environments, you can drive signals into the device before or during power-up or power-down without damaging the device. Stratix and Stratix GX devices do not drive out until the device is configured and has attained proper operating conditions. Even though you can power up or down the VCCIO and VCCINT power supplies in any sequence you should not power down any I/O bank(s) that contains the configuration pins while leaving other I/O banks powered on. For power up and power down, all supplies (VCCINT and all VCCIO power planes) must be powered up and down within 100 ms of one another. This prevents I/O pins from driving out. Altera Corporation June 2006 4–27 Stratix Device Handbook, Volume 2 I/O Termination You can power up or power down the VCCIO and VCCINT pins in any sequence. The power supply ramp rates can range from 100 ns to 100 ms. During hot socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. DC Hot Socketing Specification The hot socketing DC specification is | IIOPIN | < 300 μ A. AC Hot Socketing Specification The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less. This specification takes into account the pin capacitance, but not board trace and external loading capacitance. Additional capacitance for trace, connector, and loading must be considered separately. IIOPIN is the current at any user I/O pin on the device. The DC specification applies when all VCC supplies to the device are stable in the powered-up or powered-down conditions. For the AC specification, the peak current duration because of power-up transients is 10 ns or less. For more information, refer to the Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices white paper. I/O Termination Although single-ended, non-voltage-referenced I/O standards do not require termination, Altera recommends using external termination to improve signal integrity where required. The following I/O standards do not require termination: ■ ■ ■ ■ ■ ■ ■ ■ LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI/Compact PCI 3.3-V PCI-X 1.0 3.3-V AGP 1× Voltage-Referenced I/O Standards Voltage-referenced I/O standards require both an input reference voltage, VREF, and a termination voltage, VTT. Off-chip termination on the board should be used for series and parallel termination. 4–28 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices For more information on termination for voltage-referenced I/O standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device Handbook, Volume 2. Differential I/O Standards Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the bus. Stratix and Stratix GX devices provide an optional differential termination on-chip resistor when using LVDS. See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for more information on differential I/O standards and their interfaces. For differential I/O standards, I/O banks support differential termination when VCCIO equals 3.3 V. Differential Termination (RD) Stratix devices support differential on-chip termination for sourcesynchronous LVDS signaling. The differential termination resistors are adjacent to the differential input buffers on the device. This placement eliminates stub effects, improving the signal integrity of the serial link. Using differential on-chip termination resistors also saves board space. Figure 4–20 shows the differential termination connections for Stratix and Stratix GX devices. Figure 4–20. Differential Termination Differential Transmitter Stratix LVDS Receiver Buffer with Differential On-Chip Termination Z0 RD Z0 Altera Corporation June 2006 4–29 Stratix Device Handbook, Volume 2 I/O Pad Placement Guidelines Differential termination for Stratix devices is supported for the left and right I/O banks. Differential termination for Stratix GX devices is supported for the left, source-synchronous I/O bank. Some of the clock input pins are in the top and bottom I/O banks, which do not support differential termination. Clock pins CLK[1,3,8,10] support differential on-chip termination. Clock pins CLK[0,2,9,11], CLK[4-7], and CLK[12-15] do not support differential on-chip termination. Transceiver Termination Stratix GX devices feature built-in on-chip termination within the transceiver at both the transmit and receive buffers. This termination improves signal integrity and provides support for the 1.5-V PCML I/O standard. I/O Pad Placement Guidelines This section provides pad placement guidelines for the programmable I/O standards supported by Stratix and Stratix GX devices and includes essential information for designing systems using the devices' selectable I/O capabilities. These guidelines will reduce noise problems so that FPGA devices can maintain an acceptable noise level on the line from the VCCIO supply. Since Altera FPGAs require that a separate VCCIO power each bank, these noise issues do not have any effect when crossing bank boundaries and these guidelines do not apply. Although pad placement rules need not be considered between I/O banks, some rules must be considered if you are using a VREF signal in a PLLOUT bank. Note that the signals in the PLLOUT banks share the VREF supply with neighboring I/O banks and, therefore, must adhere to the VREF rules discussed in “VREF Pad Placement Guidelines”. Differential Pad Placement Guidelines To avoid cross coupling and maintain an acceptable noise level on the VCCIO supply, there are restrictions on the placement of single-ended I/O pads in relation to differential pads. Use the following guidelines for placing single-ended pads with respect to differential pads in Stratix devices. These guidelines apply for LVDS, HyperTransport technology, LVPECL, and PCML I/O standards. The differential pad placement guidelines do not apply for differential HSTL and differential SSTL output clocks since each differential output clock is essentially implemented using two single-ended output buffers. These rules do not apply to differential HSTL input clocks either even though the dedicated input buffers are used. However, both differential HSTL and differential SSTL output standards must adhere to the single-ended (VREF) pad placement restrictions discussed in “VREF Pad Placement Guidelines”. 4–30 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices ■ ■ For flip-chip packages, there are no restrictions for placement of single-ended input signals with respect to differential signals (see Figure 4–21). For wire-bond packages, single ended input pads may only be placed four or more pads away from a differential pad. Single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad (see Figure 4–21), regardless of package type. Figure 4–21. Legal Pin Placement Note (1) Wirebond Input Input, Output, Bidirectional Differential Pin FlipChip Input Input Input, Output, Bidirectional Note to Figure 4–21: (1) Input pads on a flip-chip packages have no restrictions. VREF Pad Placement Guidelines Restrictions on the placement of single-ended voltage-referenced I/O pads with respect to VREF pads help maintain an acceptable noise level on the VCCIO supply and to prevent output switching noise from shifting the VREF rail. The following guidelines are for placing single-ended pads in Stratix devices. Input Pins Each VREF pad supports a maximum of 40 input pads with up to 20 on each side of the VREF pad. Output Pins When a voltage referenced input or bidirectional pad does not exist in a bank, there is no limit to the number of output pads that can be implemented in that bank. When a voltage referenced input exists, each VREF pad supports 20 outputs for thermally enhanced FineLine BGA® and thermally enhanced BGA cavity up packages or 15 outputs for Nonthermally enhanced cavity up and non-thermally enhanced FineLine BGA packages. Altera Corporation June 2006 4–31 Stratix Device Handbook, Volume 2 I/O Pad Placement Guidelines Bidirectional Pins Bidirectional pads must satisfy input and output guidelines simultaneously. If the bidirectional pads are all controlled by the same OE and there are no other outputs or voltage referenced inputs in the bank, then there is no case where there is a voltage referenced input active at the same time as an output. Therefore, the output limitation does not apply. However, since the bidirectional pads are linked to the same OE, the bidirectional pads act as inputs at the same time. Therefore, the input limitation of 40 input pads (20 on each side of the VREF pad) applies. If any of the bidirectional pads are controlled by different output enables (OE) and there are no other outputs or voltage referenced inputs in the bank, then there may be a case where one group of bidirectional pads is acting as inputs while another group is acting as outputs. In such cases, apply the formulas shown in Table 4–8. Table 4–8. Input-Only Bidirectional Pin Limitation Formulas Package Type Formula Thermally enhanced FineLine BGA and – ≤20 (per VREF pad) Non-thermally enhanced cavity up and – ≤15 (per VREF pad). Consider a thermally enhanced FineLine BGA package with eight bidirectional pads controlled by OE1, eight bidirectional pads controlled by OE2, and six bidirectional pads controlled by OE3. While this totals 22 bidirectional pads, it is safely allowable because there would be a maximum of 16 outputs per VREF pad possible assuming the worst case where OE1 and OE2 are active and OE3 is inactive. This is particularly relevant in DDR SDRAM applications. When at least one additional voltage referenced input and no other outputs exist in the same VREF bank, then the bidirectional pad limitation must simultaneously adhere to the input and output limitations. See the following equation. + ≤40 (20 on each side of the VREF pad) 4–32 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices The previous equation accounts for the input limitations, but you must apply the appropriate equation from Table 4–9 to determine the output limitations. Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist) Package Type Formula Thermally enhanced FineLine BGA and ≤20 (per VREF pad) thermally enhanced BGA cavity up Non-thermally enhanced cavity up and ≤15 (per VREF pad) non-thermally enhanced FineLine BGA When at least one additional output exists but no voltage referenced inputs exist, apply the appropriate formula from Table 4–10. Table 4–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist) Package Type Formula Thermally enhanced FineLine BGA and + – ≤20 (per VREF pad) Non-thermally enhanced cavity up and + – ≤15 (per VREF pad) When additional voltage referenced inputs and other outputs exist in the same VREF bank, then the bidirectional pad limitation must again simultaneously adhere to the input and output limitations. See the following equation. + ≤40 (20 on each side of the VREF pad) Altera Corporation June 2006 4–33 Stratix Device Handbook, Volume 2 I/O Pad Placement Guidelines The previous equation accounts for the input limitations, but you must apply the appropriate equation from Table 4–9 to determine the output limitations. Table 4–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs) Package Type Formula Thermally enhanced FineLine BGA and + ≤20 (per VREF pad) non-thermally enhanced cavity up and + ≤15 (per VREF pad) In addition to the pad placement guidelines, use the following guidelines when working with VREF standards: ■ ■ Each bank can only have a single VCCIO voltage level and a single VREF voltage level at a given time. Pins of different I/O standards can share the bank if they have compatible VCCIO values (see Table 4–12 for more details). In all cases listed above, the Quartus II software generates an error message for illegally placed pads. Output Enable Group Logic Option in Quartus II The Quartus II software can check a design to make sure that the pad placement does not violate the rules mentioned above. When the software checks the design, if the design contains more bidirectional pins than what is allowed, the Quartus II software returns a fitting error. When all the bidirectional pins are either input or output but not both (for example, in a DDR memory interface), you can use the Output Enable Group Logic option. Turning on this option directs the Quartus II Fitter to view the specified nodes as an output enable group. This way, the Fitter does not violate the requirements for the maximum number of pins driving out of a VREF bank when a voltaged-referenced input pin or bidirectional pin is present. In a design that implements DDR memory interface with dq, dqs and dm pins utilized, there are two ways to enable the above logic options. You can enable the logic options through the Assignment Editor or by adding the following assignments to your project’s ESF file: OPTIONS_FOR_INDIVIDUAL_NODES_ONLY { dq : OUTPUT_ENABLE_GROUP 1; dqs : OUTPUT_ENABLE_GROUP 1; 4–34 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices dm : OUTPUT_ENABLE_GROUP 1; } As a result, the Quartus II Fitter does not count the bidirectional pin potential outputs, and the number of VREF bank outputs remains in the legal range. Toggle Rate Logic Option in Quartus II You should specify the pin’s output toggling rate in order to perform a stricter pad placement check in the Quartus II software. Specify the frequency at which a pin toggles in the Quartus II Assignment Editor. This option is useful for adjusting the pin toggle rate in order to place them closer to differential pins. The option directs the Quartus II Fitter toggle-rate checking while allowing you to place a single-ended pin closer to a differential pin. DC Guidelines Variables affecting the DC current draw include package type and desired termination methods. This section provides information on each of these variables and also shows how to calculate the DC current for pin placement. 1 The Quartus II software automatically takes these variables into account during compilation. For any 10 consecutive output pads in an I/O bank, Altera recommends a maximum current of 200 mA for thermally enhanced FineLine BGA and thermally enhanced BGA cavity up packages and 164 mA for non-thermally enhanced cavity up and non-thermally enhanced FineLine BGA packages. The following equation shows the current density limitation equation for thermally enhanced FineLine BGA and thermally enhanced BGA cavity up packages: pin + 9 Σ Ipin < 200 mA pin The following equation shows the current density limitation equation for non-thermally enhanced cavity up and non-thermally enhanced FineLine BGA packages: Altera Corporation June 2006 4–35 Stratix Device Handbook, Volume 2 I/O Pad Placement Guidelines pin + 9 Σ Ipin < 164 mA pin Table 4–12 shows the DC current specification per pin for each I/O standard. I/O standards not shown in the table do not exceed these current limitations. Table 4–12. I/O Standard DC Specification Note (1) IPIN (mA) Pin I/O Standard 3.3-V VCCIO 2.5-V VCCIO 1.5-V VCCIO GTL 40 40 - GTL+ 34 34 - SSTL-3 Class I 8 - - SSTL-3 Class II 16 - - CTT 8 - - SSTL-2 Class I - 8.1 - SSTL-2 Class II - 16.4 - HSTL Class I - - 8 HSTL Class II - - 16 Note to Table 4–12: (1) f The current rating on a VREF pin is less than 10μA. For more information on Altera device packaging, see the Package Information for Stratix Devices chapter in the Stratix Device Handbook, Volume 2. 4–36 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–22. Current Draw Limitation Guidelines I/O Pin Sequence of an I/O Bank Any 10 Consecutive I/O Pins, VCC GND Any 10 consecutive I/O pads cannot exceed 200 mA in thermally enhanced FineLine BGA and thermally enhanced BGA cavity up packages or 164 mA in non-thermally enhanced cavity up and nonthermally enhanced FineLine BGA packages. For example, consider a case where a group of 10 consecutive pads are configured as follows for a thermally enhanced FineLine BGA and thermally enhanced BGA cavity up package: ■ ■ ■ Number of SSTL-3 Class I output pads = 3 Number of GTL+ output pads = 4 The rest of the surrounding I/O pads in the consecutive group of 10 are unused In this case, the total current draw for these 10 consecutive I/O pads would be: (# of SSTL-3 Class I pads × 8 mA) + (# of GTL+ output pads × 34 mA) = (3 × 8 mA) + (4 × 34 mA) = 160 mA In the above example, the total current draw for all 10 consecutive I/O pads is less than 200 mA. Altera Corporation June 2006 4–37 Stratix Device Handbook, Volume 2 Power Source of Various I/O Standards Power Source of Various I/O Standards For Stratix and Stratix GX devices, the I/O standards are powered by different power sources. To determine which source powers the input buffers, see Table 4–13. All output buffers are powered by VCCIO. Table 4–13. The Relationships Between Various I/O Standards and the Power Sources I/O Standard Quartus II Software Support Power Source 2.5V/3.3V LVTTL VCCIO PCI/PCI-X 1.0 VCCIO AGP VCCIO 1.5V/1.8V VCCIO GTL VCCINT GTL+ VCCINT SSTL VCCINT HSTL VCCINT CTT VCCINT LVDS VCCINT LVPECL VCCINT PCML VCCINT HyperTransport VCCINT You specify which programmable I/O standards to use for Stratix and Stratix GX devices with the Quartus II software. This section describes Quartus II implementation, placement, and assignment guidelines, including ■ ■ ■ ■ ■ ■ Compiler Settings Device & Pin Options Assign Pins Programmable Drive Strength Settings I/O Banks in the Floorplan View Auto Placement & Verification Compiler Settings You make Compiler settings in the Compiler Settings dialog box (Processing menu). Click the Chips & Devices tab to specify the device family, specific device, package, pin count, and speed grade to use for your design. 4–38 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Device & Pin Options Click Device & Pin Options in the Compiler Settings dialog box to access the I/O pin settings. For example, in the Voltage tab you can select a default I/O standard for all pins for the targeted device. I/O pins that do not have a specific I/O standard assignment default this standard. Click OK when you are done setting I/O pin options to return to the Compiler Settings dialog box. Assign Pins Click Assign Pins in the Compiler Settings dialog box to view the device’s pin settings and pin assignments (see Figure 4–23). You can view the pin settings under Available Pins & Existing Assignments. The listing does not include VREF pins because they are dedicated pins. The information for each pin includes: ■ ■ ■ ■ ■ ■ ■ ■ Number Name I/O Bank I/O Standard Type (e.g., row or column I/O and differential or control) SignalProbe Source Name Enabled (that is, whether SignalProbe routing is enabled or disabled Status Figure 4–23. Assign Pins Altera Corporation June 2006 4–39 Stratix Device Handbook, Volume 2 Quartus II Software Support When you assign an I/O standard that requires a reference voltage to an I/O pin, the Quartus II software automatically assigns VREF pins. See the Quartus II Help for instructions on how to use an I/O standard for a pin. Programmable Drive Strength Settings To make programmable drive strength settings, perform the following steps: 1. In the Tools menu, choose Assignment Organizer. 2. Choose the Edit specific entity & node settings for: setting, then select the output or bidirectional pin to specify the current strength for. 3. In the Assignment Categories dialog box, select Options for Individual Nodes Only. 4. Select Click here to add a new assignment. 5. In the Assignment dialog box, set the Name field to Current Strength and set the Setting field to the desired, allowable value. 6. Click Add. 7. Click Apply, then OK. I/O Banks in the Floorplan View You can view the arrangement of the device I/O banks in the Floorplan View (View menu) as shown in Figure 4–24. You can assign multiple I/O standards to the I/O pins in any given I/O bank as long as the VCCIO of the standards is the same. Pins that belong to the same I/O bank must use the same VCCIO signal. Each device I/O pin belongs to a specific, numbered I/O bank. The Quartus II software color codes the I/O bank to which each I/O pin and VCCIO pin belong. Turn on the Show I/O Banks option to display the I/O bank color and the bank numbers for each pin. 4–40 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices Figure 4–24. Floorplan View Window Auto Placement & Verification of Selectable I/O Standards The Quartus II software automatically verifies the placement for all I/O and VREF pins and performs the following actions. ■ ■ ■ ■ ■ Altera Corporation June 2006 Automatically places I/O pins of different VREF standards without pin assignments in separate I/O banks and enables the VREF pins of these I/O banks. Verifies that voltage-referenced I/O pins requiring different VREF levels are not placed in the same bank. Reports an error message if the current limit is exceeded for a Stratix or Stratix GX power bank, as determined by the equation documented in “DC Guidelines” on page 4–35. Reserves the unused high-speed differential I/O channels and regular user I/O pins in the high-speed differential I/O banks when any of the high-speed differential I/O channels are being used. Automatically assigns VREF pins and I/O pins such that the current requirements are met and I/O standards are placed properly. 4–41 Stratix Device Handbook, Volume 2 Conclusion Conclusion Stratix and Stratix GX devices provide the I/O capabilities to allow you to work with current and emerging I/O standards and requirements. Today’s complex designs demand increased flexibility to work with the wide variety of available I/O standards and to simplify board design. With Stratix and Stratix GX device features, such as hot socketing and differential on-chip termination, you can reduce board design interface costs and increase your development flexibility. More Information For more information, see the following sources: ■ ■ ■ ■ References The Stratix Device Family Data Sheet section in the Stratix Device Handbook, Volume 1 The Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 The High-Speed Differential I/O Interfaces in Stratix Devices chapter AN 224: High-Speed Board Layout Guidelines For more information, see the following references: ■ ■ ■ ■ ■ ■ ■ ■ Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9B, Electronic Industries Association, December 2000. High-Speed Transceiver Logic (HSTL) – A 1.5-V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, EIA/JESD8-6, Electronic Industries Association, August 1995. 1.5-V +/- 0.1 V (Normal Range) and 0.9 V – 1.6 V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-11, Electronic Industries Association, October 2000. 1.8-V +/- 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-7, Electronic Industries Association, February 1997. Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits, JESD8-9A, Electronic Industries Association, November 1993. 2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-5, Electronic Industries Association, October 1995. Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated Circuits, JESD8-B, Electronic Industries Association, September 1999. Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits, JESD8-3, Electronic Industries Association, November 1993. 4–42 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 Selectable I/O Standards in Stratix & Stratix GX Devices ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation June 2006 Accelerated Graphics Port Interface Specification 2.0, Intel Corporation. Stub Series Terminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3, Electronic Industries Association. PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 1998. PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest Group. UTOPIA Level 4, AF-PHY-0144.001, ATM Technical Committee. POS-PHY Level 4: SPI-4, OIF-SPI4-02.0, Optical Internetworking Forum. POS-PHY Level 4: SFI-4, OIF-SFI4-01.0, Optical Internetworking Forum. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunications Industry/Electronic Industries Association, October 1995. 4–43 Stratix Device Handbook, Volume 2 References 4–44 Stratix Device Handbook, Volume 2 Altera Corporation June 2006 5. High-Speed Differential I/O Interfaces in Stratix Devices S52005-3.2 Introduction To achieve high data transfer rates, Stratix® devices support TrueLVDSTM differential I/O interfaces which have dedicated serializer/deserializer (SERDES) circuitry for each differential I/O pair. Stratix SERDES circuitry transmits and receives up to 840 megabits per second (Mbps) per channel. The differential I/O interfaces in Stratix devices support many high-speed I/O standards, such as LVDS, LVPECL, PCML, and HyperTransportTM technology. Stratix device highspeed modules are designed to provide solutions for many leading protocols such as SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO, HyperTransport technology, and UTOPIA-4. The SERDES transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide words and transmit them across either a cable or printed circuit board (PCB). The SERDES receiver takes the serialized data and reconstructs the bits into a 4-, 7-, 8-, or 10-bit-wide parallel word. The SERDES contains the necessary high-frequency circuitry, multiplexer, demultiplexer, clock, and data manipulation circuitry. You can use double data rate I/O (DDRIO) circuitry to transmit or receive differential data in by-one (×1) or by-two (×2) modes. 1 Contact Altera Applications for more information on other B values that the Stratix devices support and using ×7-mode in the Quartus® II software. Stratix devices currently only support B = 1 and B = 7 in ×7 mode. This chapter describes the high-speed differential I/O capabilities of Stratix programmable logic devices (PLDs) and provides guidelines for their optimal use. You should use this document in conjunction with the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. Consideration of the critical issues of controlled impedance of traces and connectors, differential routing, termination techniques, and DC balance gets the best performance from the device. Therefore, an elementary knowledge of high-speed clock-forwarding techniques is also helpful. Stratix I/O Banks Altera Corporation July 2005 Stratix devices contain eight I/O banks, as shown in Figure 5–1. The two I/O banks on each side contain circuitry to support high-speed LVDS, LVPECL, PCML, HSTL Class I and II, SSTL-2 Class I and II, and HyperTransport inputs and outputs. 5–1 Stratix I/O Banks Figure 5–1. Stratix I/O Banks Notes (1), (2), (3) DQS5T 9 DQS4T PLL11 (5) DQS1T DQS0T 10 Bank 4 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) (5) I/O Banks 1, 2, 5, and 6 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2× PLL2 Bank 1 DQS2T I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards PLL1 Bank 8 PLL3 DQS8B DQS7B DQS6B DQS5B (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) 11 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 DQS9B PLL4 I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) PLL8 DQS3T VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10 LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) Bank 2 VREF1B2 VREF2B2 VREF3B2 VREF4B2 Bank 3 VREF1B1 VREF2B1 VREF3B1 VREF4B1 PLL5 12 PLL6 Bank 5 DQS6T VREF4B5 VREF3B5 VREF2B5 VREF1B5 DQS7T Bank 6 DQS8T VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF4B6 VREF3B6 VREF2B6 VREF1B6 DQS9T PLL7 Bank 7 PLL12 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 DQS4B DQS3B DQS2B DQS1B PLL9 DQS0B Notes to Figure 5–1: (1) (2) (3) (4) (5) Figure 5–1 is a top view of the Stratix silicon die, which corresponds to a top-down view of non-flip-chip packages and a bottom-up view of flip-chip packages. Figure 5–1 is a graphic representation only. See the pin list and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1× /2× . See “Differential Pad Placement Guidelines” on page 4–30. You can only place single-ended output/bidirectional pads five or more pads away from a differential pad. Use the Show Pads view in the Quartus II Floorplan Editor to locate these pads. The Quartus II software gives an error message for illegal output or bidirectional pin placement next to a high-speed differential I/O pin. Stratix Differential I/O Standards Stratix devices provide a multi-protocol interface that allows communication between a variety of I/O standards, including LVDS, HyperTransport technology, LVPECL, PCML, HSTL Class I and II, and 5–2 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices SSTL-2 Class I and II. This feature makes the Stratix device family ideal for applications that require multiple I/O standards, such as a protocol translator. f For more information on termination for Stratix I/O standards, see “Differential I/O Termination” on page 5–46. Figure 5–2 compares the voltage levels between differential I/O standards supported in all the Stratix devices. Figure 5–2. Differential I/O Standards Supported by Stratix Devices 4.0 3.3 V PCML 3.0 V 3.0 2.1 V Voltage (V) 2.0 LVPECL 1.7 V 1.4 V LVDS 1.0 1.0 V 0.9 V HyperTransport 0.3 V 0.0 Technology Altera Corporation July 2005 5–3 Stratix Device Handbook, Volume 2 Stratix I/O Banks LVDS The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard requiring a 3.3-V VCCIO. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 Mbps. However, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 Gbps. Stratix devices meet the ANSI/TIA/EIA-644 standard. Due to the low voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than CMOS, transistor-to-transistor logic (TTL), and PECL. This low EMI makes LVDS ideal for applications with low EMI requirements or noise immunity requirements. The LVDS standard specifies a differential output voltage range of 0.25 V × VOD ≤ 0.45 V. The LVDS standard does not require an input reference voltage, however, it does require a 100-Ω termination resistor between the two signals at the input buffer. Stratix devices include an optional differential termination resistor within the device. See Section I, Stratix Device Family Data Sheet of the Stratix Device Handbook, Volume 1 for the LVDS parameters. HyperTransport Technology The HyperTransport technology I/O standard is a differential highspeed, high-performance I/O interface standard requiring a 2.5-V VCCIO. This standard is used in applications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and Internet connectivity devices. The HyperTransport technology I/O standard is a point-to-point standard in which each HyperTransport technology bus consists of two point-to-point unidirectional links. Each link is 2 to 32 bits. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the HyperTransport parameters. LVPECL The LVPECL I/O standard is a differential interface standard requiring a 3.3-V VCCIO. The standard is used in applications involving video graphics, telecommunications, data communications, and clock distribution. The high-speed, low-voltage swing LVPECL I/O standard uses a positive power supply and is similar to LVDS, however, LVPECL has a larger differential output voltage swing than LVDS. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the LVPECL signaling characteristics. 5–4 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices PCML The PCML I/O standard is a differential high-speed, low-power I/O interface standard used in applications such as networking and telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O standard achieves better performance and consumes less power than the LVPECL I/O standard. The PCML standard is similar to LVPECL, but PCML has a reduced voltage swing, which allows for a faster switching time and lower power consumption.See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the PCML signaling characteristics. Differential HSTL (Class I & II) The differential HSTL I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data rate (QDR) memory clock interfaces. The differential HSTL specification is the same as the single ended HSTL specification. The standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. The differential HSTL I/O standard is only available on the input and output clocks. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the HSTL signaling characteristics Differential SSTL-2 (Class I & II) The differential SSTL-2 I/O standard is a 2.5-V memory bus standard used for applications such as high-speed double data rate (DDR) SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves operation in conditions where a bus must be isolated from large stubs. The SSTL-2 standard specifies an input voltage range of – 0.3 V ≤ VI ≤ VCCIO + 0.3 V. Stratix devices support both input and output levels. The differential SSTL-2 I/O standard is only available on output clocks. See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics. Stratix Differential I/O Pin Location The differential I/O pins are located on the I/O banks on the right and left side of the Stratix device. Table 5–1 shows the location of the Stratix device high-speed differential I/O buffers. When the I/O pins in the I/O banks that support differential I/O standards are not used for high-speed Altera Corporation July 2005 5–5 Stratix Device Handbook, Volume 2 Principles of SERDES Operation signaling, you can configure them as any of the other supported I/O standards. DDRIO capabilities are detailed in “SERDES Bypass DDR Differential Signaling” on page 5–42. Table 5–1. I/O Pin Locations on Each Side of Stratix Devices Differential Input Differential Output DDRIO Left Device Side (1) v v v Right v v v Top v Bottom v Note to Table 5–1: (1) Principles of SERDES Operation Device sides are relative to pin A1 in the upper left corner of the device (top view of the package). Stratix devices support source-synchronous differential signaling up to 840 Mbps. Serial data is transmitted and received along with a lowfrequency clock. The PLL can multiply the incoming low-frequency clock by a factor of 1 to 10. The SERDES factor J can be 4, 7, 8, or 10 and does not have to equal the clock multiplication value. ×1 and ×2 operation is also possible by bypassing the SERDES; it is explained in “SERDES Bypass DDR Differential Interface Review” on page 5–42. On the receiver side, the high-frequency clock generated by the PLL shifts the serial data through a shift register (also called deserializer). The parallel data is clocked out to the logic array synchronized with the lowfrequency clock. On the transmitter side, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then transmitted out by the output buffers. There are four dedicated fast PLLs in EP1S10 to EP1S25 devices, and eight in EP1S30 to EP1S80 devices. These PLLs are used for the SERDES operations as well as general-purpose use. The differential channels and the high-speed PLL layout in Stratix devices are described in the “Differential I/O Interface & Fast PLLs” section on page 5–16. 5–6 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Stratix Differential I/O Receiver Operation You can configure any of the Stratix differential input channels as a receiver channel (see Figure 5–3). The differential receiver deserializes the incoming high-speed data. The input shift register continuously clocks the incoming data on the negative transition of the high-frequency clock generated by the PLL clock (×W). The data in the serial shift register is shifted into a parallel register by the RXLOADEN signal generated by the fast PLL counter circuitry on the third falling edge of the high-frequency clock. However, you can select which falling edge of the high frequency clock loads the data into the parallel register, using the data-realignment circuit. For more information on the data-realignment circuit, see “Data Realignment Principles of Operation” on page 5–25. In normal mode, the enable signal RXLOADEN loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock. You can also load data to the parallel register through the TXLOADEN signal when using the data-realignment circuit. Figure 5–3 shows the block diagram of a single SERDES receiver channel. Figure 5–4 shows the timing relationship between the data and clocks in Stratix devices in ×10 mode. W is the low-frequency multiplier and J is data parallelization division factor. Altera Corporation July 2005 5–7 Stratix Device Handbook, Volume 2 Principles of SERDES Operation Figure 5–3. Stratix High-Speed Interface Deserialized in ×10 Mode Receiver Circuit Serial Shift Registers RXIN+ RXIN− Parallel Registers PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 ×W RXCLKIN+ RXCLKIN− Parallel Registers PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 Stratix Logic Array ×W/J (1) Fast RXLOADEN PLL (2) TXLOADEN Notes to Figure 5–3: (1) (2) W = 1, 2, 4, 7, 8, or 10. J = 4, 7, 8, or 10. W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers. This figure does not show additional circuitry for clock or data manipulation. Figure 5–4. Receiver Timing Diagram Internal ×1 clock Internal ×10 clock RXLOADEN Receiver data input n–1 n–0 9 8 7 6 5 4 3 2 1 0 n–1 n–0 9 8 7 6 5 4 3 2 1 0 Internal ×1 clock Internal ×10 clock RXLOADEN Receiver data input 5–8 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Stratix Differential I/O Transmitter Operation You can configure any of the Stratix differential output channels as a transmitter channel. The differential transmitter is used to serialize outbound parallel data. The logic array sends parallel data to the SERDES transmitter circuit when the TXLOADEN signal is asserted. This signal is generated by the high-speed counter circuitry of the logic array low-frequency clock’s rising edge. The data is then transferred from the parallel register into the serial shift register by the TXLOADEN signal on the third rising edge of the high-frequency clock. Figure 5–5 shows the block diagram of a single SERDES transmitter channel and Figure 5–6 shows the timing relationship between the data and clocks in Stratix devices in ×10 mode. W is the low-frequency multiplier and J is the data parallelization division factor. Figure 5–5. Stratix High-Speed Interface Serialized in ×10 Mode Transmitter Circuit Stratix Logic Array PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Parallel Register PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Serial Register TXOUT+ TXOUT− ×W Fast PLL Altera Corporation July 2005 TXLOADEN 5–9 Stratix Device Handbook, Volume 2 Principles of SERDES Operation Figure 5–6. Transmitter Timing Diagram Internal ×1 clock Internal ×10 clock TXLOADEN Receiver data input n–1 n–0 9 8 7 6 5 4 3 2 1 0 Transmitter Clock Output Different applications and protocols call for various clocking schemes. Some applications require you to center-align the rising or falling clock edge with the data. Other applications require a divide version of the transmitted clock, or the clock and data to be at the same high-speed frequency. The Stratix device transmitter clock output is versatile and easily programmed for all such applications. Stratix devices transmit data using the source-synchronous scheme, where the clock is transmitted along with the serialized data to the receiving device. Unlike APEXTM 20KE and APEX II devices, Stratix devices do not have a fixed transmitter clock output pin. The Altera® Quartus II software generates the transmitter clock output by using a fast clock to drive a transmitter dataout channel. Therefore, you can place the transmitter clock pair close to the data channels, reducing clock-todata skew and increasing system margins. This approach is more flexible, as any channel can drive a clock, not just specially designated clock pins. Divided-Down Transmitter Clock Output You can divide down the high-frequency clock by 2, 4, 8, or 10, depending on the system requirements. The various options allow Stratix devices to accommodate many different types of protocols. The divided-down clock is generated by an additional transmitting data channel. 5–10 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–2 shows the divided-down version of the high-frequency clock and the selected serialization factor J (described in pervious sections). The Quartus II software automatically generates the data input to the additional transmitter data channel. Table 5–2. Differential Transmitter Output Clock Division J Data Input Output Clock Divided By (1) 4 1010 2 4 0011 4 8 10101010 2 8 00110011 4 8 11000011 8 10 1010101010 2 10 1110000011 10 Note to Table 5–2: (1) This value is usually referred to as B. Center-Aligned Transmitter Clock Output A negative-edge-triggered D flipflop (DFF) register is located between the serial register of each data channel and its output buffer, as show in Figure 5–7. The negative-edge-triggered DFF register is used when center-aligned data is required. For center alignment, the DFF only shifts the output from the channel used as the transmitter clock out. The transmitter data channels bypass the negative-edge DFF. When you use the DFF register, the data is transmitted at the negative edge of the multiplied clock. This delays the transmitted clock output relative to the data channels by half the multiplied clock cycle. This is used for HyperTransport technology, but can also be used for any interface requiring center alignment. Altera Corporation July 2005 5–11 Stratix Device Handbook, Volume 2 Principles of SERDES Operation Figure 5–7. Stratix Programmable Transmitter Clock Transmitter Circuit Stratix Logic Array PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Parallel Register PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Serial Register TXOUT+ TXOUT− ×W Fast PLL TXLOADEN SDR Transmitter Clock Output You can route the high-frequency clock internally generated by the PLL out as a transmitter clock output on any of the differential channels. The high-frequency clock output allows Stratix devices to support applications that require a 1-to-1 relationship between the clock and data. The path of the high-speed clock is shown in Figure 5–8. A programmable inverter allows you to drive the signal out on either the negative edge of the clock or 180º out of phase with the streaming data. 5–12 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–8. High-Speed 1-to-1 Transmitter Clock Output Transmitter Circuit Stratix Logic Array PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Parallel Register PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Serial Register Inverter TXOUT+ TXOUT− ×W Fast PLL (1) TXLOADEN Note to Figure 5–8: (1) This figure does not show additional circuitry for clock or data manipulation. Using SERDES to Implement DDR Some designs require a 2-to-1 data-to-clock ratio. These systems are usually based on Rapid I/O, SPI-4 Phase 2 (POS_PHY Level 4), or HyperTransport interfaces, and support various data rates. Stratix devices meet this requirement for such applications by providing a variable clock division factor. The SERDES clock division factor is set to 2 for double data rate (DDR). An additional differential channel (as described in “Transmitter Clock Output” on page 5–10) is automatically configured to produce the transmitter clock output signal with half the frequency of the data. For example, when a system is required to transmit 6.4 Gbps with a 2-to-1 clock-to-data ratio, program the SERDES with eight high-speed channels running at 800 Mbps each. When you set the output clock division factor (2 for this example), the Quartus II software automatically assigns a ninth channel as the transmitter clock output. You can edge- or center-align the transmitter clock by selecting the default PLL phase or selecting the negative-edge transmitter clock output. On the receiver side, the clock signal is connected to the receiver PLL's clock. The multiplication factor W is also calculated automatically. The data rate divides by the input clock frequency to calculate the W factor. The deserialization factor (J) may be 4, 7, 8, or 10. Altera Corporation July 2005 5–13 Stratix Device Handbook, Volume 2 Using SERDES to Implement SDR Figure 5–9 shows a DDR clock-to-data timing relationship with the clock center-aligned with respect to data. Figure 5–10 shows the connection between the receiver and transmitter circuits. Figure 5–9. DDR Clock-to-Data Relationship inclock DDR XX B0 A0 B1 A1 B2 A2 B3 A3 Figure 5–10. DDR Receiver & Transmitter Circuit Connection Stratix SERDES DDR Receiver rx_d[0] Channel 0 Serial-to-Parallel Register Stratix SERDES DDR Transmitter Parallel Register 8 8 Parallel Register Parallel-to-Serial Register Parallel Register Parallel-to-Serial Register Parallel Register Parallel-to-Serial Register Channel 0 tx_d[0] data rate = 800 Mbps Stratix Logic Array rx_d[15] data rate = 800 Mbps Channel 15 Serial-to-Parallel Register Parallel Register rxclk LVDS PLL 8 8 input clock × W 400 MHz 8 rxloadena Channel 15 Channel 16 ÷2 txclk_out 800 Mbps txclk_out 400 MHz txloaden LVDS PLL input clock × W txclk_in 100 MHz Using SERDES to Implement SDR Stratix devices support systems based on single data rate (SDR) operations applications by allowing you to directly transmit out the multiplied clock (as described in “SDR Transmitter Clock Output” on page 5–12). These systems are usually based on Utopia-4, SFI-4, or XSBI interfaces, and support various data rates. An additional differential channel is automatically configured to produce the transmitter clock output signal and is transmitted along with the data. For example, when a system is required to transmit 10 Gbps with a 1-to1 clock-to-data ratio, program the SERDES with sixteen high-speed channels running at 624 Mbps each. The Quartus II software 5–14 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices automatically assigns a seventeenth channel as the transmitter clock output. You can edge- or center-align the transmitter clock output by selecting the default PLL phase or selecting the 90° phase of the PLL output. On the receiver side, the clock signal is connected to the receiver PLL's clock input, and you can assign identical clock-to-data alignment. The multiplication factor W is calculated automatically. The data rate is dividing by the input clock frequency to calculate the W factor. The deserialization factor J may be 4, 7, 8, or 10. Figure 5–11 shows an SDR clock-to-data timing relationship, with clock center aligned with respect to data. Figure 5–12 shows the connection between the receiver and transmitter circuits. Figure 5–11. SDR Clock-to-Data Relationship inclock SDR XX B0 B1 B2 B3 Figure 5–12. SDR Receiver & Transmitter Circuit Connection Stratix SERDES SDR Receiver rx_d[0] Channel 0 Serial-to-Parallel Register Stratix SERDES SDR Transmitter Parallel Register 8 8 Parallel Register Parallel-to-Serial Register Parallel Register Parallel-to-Serial Register Channel 0 tx_d[0] data rate = 624 Mbps Stratix Logic Array rx_d[15] data rate = 624 Mbps Channel 15 Serial-to-Parallel Register Parallel Register 8 8 input clock × W Channel 15 Channel 16 txloaden tx_d[15] txclk_out 624 MHz rxclk 624 MHz LVDS PLL rxloaden LVDS PLL input clock × W txclk_in 624 MHz Altera Corporation July 2005 5–15 Stratix Device Handbook, Volume 2 Differential I/O Interface & Fast PLLs Differential I/O Interface & Fast PLLs Stratix devices provide 16 dedicated global clocks, 8 dedicated fast regional I/O pins, and up to 16 regional clocks (four per device quadrant) that are fed from the dedicated global clock pins or PLL outputs. The 16 dedicated global clocks are driven either by global clock input pins that support all I/O standards or from enhanced and fast PLL outputs. Stratix devices use the fast PLLs to implement clock multiplication and division to support the SERDES circuitry. The input clock is either multiplied by the W feedback factor and/or divided by the J factor. The resulting clocks are distributed to SERDES, local, or global clock lines. Fast PLLs are placed in the center of the left and right sides for EP1S10 to EP1S25 devices. For EP1S30 to EP1S80 devices, fast PLLs are placed in the center of the left and right sides, as well as the device corners (see Figure 5–13). These fast PLLs drive a dedicated clock network to the SERDES in the rows above and below or top and bottom of the device as shown in Figure 5–13. 5–16 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–13. Stratix Fast PLL Positions & Clock Naming Convention Note (1) CLK[15..12] 5 11 FPLLCLK0 7 10 FPLLCLK3 CLK[3..0] 1 2 4 3 CLK[11..8] 8 9 FPLLCLK2 PLLs FPLLCLK1 6 12 CLK[7..4] Notes to Figure 5–13: (1) (2) Dedicated clock input pins on the right and left sides do not support PCI or PCI-X 1.0. PLLs 7, 8, 9, and 10 are not available on the EP1S30 device in the 780-pin FineLine BGA® package. Altera Corporation July 2005 5–17 Stratix Device Handbook, Volume 2 Differential I/O Interface & Fast PLLs Clock Input & Fast PLL Output Relationship Table 5–3 summarizes the PLL interface to the input clocks and the enable signal (ENA). Table 5–4 summarizes the clock networks each fast PLL can connect to across all Stratix family devices. Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables Note (1) All Stratix Devices EP1S30 to EP1S80 Devices Only Input Pin PLL 1 CLK0 (2) v CLK1 v PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10 v (3) CLK2 (2) v CLK3 v v (3) CLK4 CLK5 CLK6 CLK7 CLK8 v CLK9 (2) v v (3) CLK10 v CLK11 (2) v v (3) CLK12 CLK13 CLK14 CLK15 v ENA v FPLL7CLK FPLL8CLK FPLL9CLK FPLL10CLK v v v v v v v v v v Notes to Table 5–3: (1) (2) (3) PLLs 5, 6, 11, and 12 are not fast PLLs. Clock pins CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip termination. Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode. 5–18 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 1 of 2) Notes (1), (2) All Stratix Devices EP1S30 to EP1S80 Devices Only Output Signal PLL 1 GCLK0 v GCLK1 v PLL 2 GCLK2 v GCLK3 v PLL 3 GCLK4 v GCLK9 v PLL 4 GCLK10 v GCLK11 v PLL 7 PLL 8 RCLK1 v v v RCLK2 v v v RCLK3 v v v RCLK4 v v v PLL 9 PLL 10 RCLK9 v v v RCLK10 v v v RCLK11 v v v RCLK12 v v v DIFFIOCLK1 v DIFFIOCLK2 v DIFFIOCLK3 v DIFFIOCLK4 v DIFFIOCLK5 v DIFFIOCLK6 v DIFFIOCLK7 v DIFFIOCLK8 v DIFFIOCLK9 v DIFFIOCLK10 v DIFFIOCLK11 v DIFFIOCLK12 v DIFFIOCLK13 Altera Corporation July 2005 v 5–19 Stratix Device Handbook, Volume 2 Differential I/O Interface & Fast PLLs Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2) Notes (1), (2) All Stratix Devices EP1S30 to EP1S80 Devices Only Output Signal PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10 v DIFFIOCLK14 DIFFIOCLK15 v DIFFIOCLK16 v Notes to Table 5–4: (1) (2) PLLs 5, 6, 11, and 12 are not fast PLLs. The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be driven by a dedicated clock pin (CLK[3..0] and CLK[8..11]) or the corner pins that clock the corner PLLs (FPLL[10..7]CLK). Fast PLL Specifications You can drive the fast PLLs by an external pin or any one of the sectional clocks [21..0]. You can connect the clock input directly to local or global clock lines, as shown in Figure 5–14. You cannot use the sectional-clock inputs to the fast PLL’s input multiplexer for the receiver PLL. You can only use the sectional clock inputs in the transmitter only mode or as a general purpose PLL. 5–20 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–14. Fast PLL Block Diagram Post-Scale Counters DIFFIOCLK1 (1) ÷k Regional clock TXLOADEN (2) VCO Phase Selection Selectable at each PLL Output Port RXLOADEN (2) ÷v Global or regional clock Clock Input Phase Frequency Detector Charge Pump 8 Loop Filter Regional clock DIFFIOCLK2 (1) VCO ÷l Global or regional clock rxclkin ÷m Notes to Figure 5–14: (1) (2) In high-speed differential I/O mode, the high-speed PLL clock feeds the SERDES. Stratix devices only support one rate of data transfer per fast PLL in high-speed differential I/O mode. Control signal for high-speed differential I/O SERDES. You can multiply the input clock by a factor of 1 to 16. The multiplied clock is used for high-speed serialization or deserialization operations. Fast PLL specifications are shown in the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. The voltage controlled oscillators (VCOs) are designed to operate within the frequency range of 300 to 840 MHz, to provide data rates of up to 840 Mbps. High-Speed Phase Adjust There are eight phases of the multiplied clock at the PLL output, each delayed by 45° from the previous clock and synchronized with the original clock. The three multiplexers (shown in Figure 5–14) select one of the delayed, multiplied clocks. The PLL output drives the three counters k, v, and l. You can program the three individual post scale counters (k, v, and l) independently for division ratio or phase. The selected PLL output is used for the serialization or deserialization process in SERDES. Altera Corporation July 2005 5–21 Stratix Device Handbook, Volume 2 Differential I/O Interface & Fast PLLs Counter Circuitry The multiplied clocks bypass the counter taps k and v to directly feed the SERDES serial registers. These two taps also feed to the quadrant local clock network and the dedicated RXLOADENA or TXLOADENA pins, as shown in Figure 5–15. Both k and v are utilized simultaneously during the data-realignment procedure. When the design does not use the data realignment, both TXLOADEN and RXLOADEN pins use a single counter. Figure 5–15. Fast PLL Connection to Logic Array Counter Circuitry Post-Scale Counters VCO Phase Selection Selectable at each PLL Output Port ÷k CLK1 SERDES Circuitry ×1 CLK1 to logic array or local clocks TXLOADEN RXLOADEN 8 ÷v PLL Output Clock Distribution Circuitry ×1 CLK2 to logic array or local clocks CLK2 SERDES Circuitry ÷l Regional clock clkin The Stratix device fast PLL has another GCLK connection for generalpurpose applications. The third tap l feeds the quadrant local clock as well as the global clock network. You can use the l counter's multiplexer for applications requiring the device to connect the incoming clock directly to the local or global clocks. You can program the multiplexer to connect the RXCLKIN signal directly to the local or global clock lines. Figure 5–15 shows the connection between the incoming clock, the l tap, and the local or global clock lines. The differential clock selection is made per differential bank. Since the length of the clock tree limits the performance, each fast PLL should drive only one differential bank. 5–22 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Fast PLL SERDES Channel Support The Quartus II MegaWizard Plug-In Manager only allows you to implement up to 20 receiver or 20 transmitter channels for each fast PLL. These channels operate at up to 840 Mbps. For more information on implementing more than 20 channels, see “Fast PLLs” on page 5–52. The receiver and transmitter channels are interleaved such that each I/O bank on the left and right side of the device has one receiver channel and one transmitter channel per row. Figure 5–16 shows the fast PLL and channel layout in EP1S10, EP1S20, and EP1S25 devices. Figure 5–17 shows the fast PLL and channel layout in EP1S30 to EP1S80 devices. f For more the number of channels in each device, see Tables 5–10 through 5–14. Figure 5–16. Fast PLL & Channel Layout in EP1S10, EP1S20 & EP1S25 Devices Note (1) Up to 20 Receiver and Transmitter Channels (2) Transmitter Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver Receiver CLKIN Fast PLL 1 CLKIN Fast PLL 2 (3) Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2) Fast PLL 4 CLKIN Fast PLL 3 CLKIN (3) Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2) Notes to Figure 5–16: (1) (2) (3) Wire-bond packages only support up to 624 Mbps until characterization shows otherwise. See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps. Altera Corporation July 2005 5–23 Stratix Device Handbook, Volume 2 Differential I/O Interface & Fast PLLs Figure 5–17. Fast PLL & Channel Layout in EP1S30 to EP1S80 Devices Note (1) FPLL7CLK Fast PLL 7 Fast PLL 10 Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter FPLL10CLK Transmitter Receiver Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter Transmitter Receiver CLKIN CLKIN Receiver Fast PLL 1 (3) (3) Fast PLL 2 Fast PLL 4 CLKIN Fast PLL 3 CLKIN Transmitter Transmitter Receiver Receiver Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Transmitter Transmitter Receiver FPLL8CLK Receiver Fast PLL 8 Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2) Fast PLL 9 FPLL9CLK Notes to Figure 5–17: (1) (2) (3) Wire-bond packages only support up to 624-Mbps until characterization shows otherwise. See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps. 5–24 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Advanced Clear & Enable Control There are several control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and to gate PLL output clocks for low-power applications. The PLLENABLE pin is a dedicated pin that enables and disables Stratix device enhanced and fast PLLs. When the PLLENABLE pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the PLLENABLE pin goes high again, the PLLs relock and resynchronize to the input clocks. The reset signals are reset/resynchronization inputs for each enhanced PLL. Stratix devices can drive these input signals from an input pin or from LEs. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. When driven low again, the PLL resynchronizes to its input as it relocks. Receiver Data Realignment Most systems using serial differential I/O data transmission require a certain data-realignment circuit. Stratix devices contain embedded datarealignment circuitry. While normal I/O operation guarantees that data is captured, it does not guarantee the parallelization boundary, as this point is randomly determined based on the power-up of both communicating devices. The data-realignment circuitry corrects for bit misalignments by shifting, or delaying, data bits. Data Realignment Principles of Operation Stratix devices use a realignment and clock distribution circuitry (described in “Counter Circuitry” on page 5–22) for data realignment. Set the internal rx_data_align node end high to assert the datarealignment circuitry. When this node is switched from a low to a high state, the realignment circuitry is activated and the data is delayed by one bit. To ensure the rising edge of the rx_data_align node end is latched into the PLL, the rx_data_align node end should stay high for at least two low-frequency clock cycles. An external circuit or an internal custom-made state machine using LEs can generate the signal to pull the rx_data_align node end to a high state. When the data realignment circuitry is activated, it generates an internal pulse Sync S1 or Sync S2 that disables one of the two counters used for the SERDES operation (described in “Counter Circuitry” on page 5–22). One counter is disabled for one high-frequency clock cycle, delaying the Altera Corporation July 2005 5–25 Stratix Device Handbook, Volume 2 Receiver Data Realignment RXLOADEN signal and dropping the first incoming bit of the serial input data stream located in the first serial register of the SERDES circuitry (shown in Figure 5–3 on page 5–8). Figure 5–18 shows the function-timing diagram of a Stratix SERDES in normal ×8 mode, and Figure 5–19 shows the function-timing diagrams of a Stratix SERDES when data realignment is used. Figure 5–18. SERDES Function Timing Diagram in Normal Operation ×8 clock Serial data D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 ×1 clock PD7 D2 D2 D2 PD6 D3 D3 D3 PD5 D4 D4 D4 PD4 D5 D5 D5 PD3 D6 D6 D6 PD2 D7 D7 D7 PD1 D0 D0 D0 PD0 D1 D1 D1 5–26 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–19. SERDES Function Timing Diagram with Data-Realignment Operation ×8 clock Serial data D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 ×1 clock PD7 D2 D3 D3 PD6 D3 D4 D4 PD5 D4 D5 D5 PD4 D5 D6 D6 PD3 D6 D7 D7 PD2 D7 D0 D0 PD1 D0 D1 D1 PD0 D1 D2 D2 Generating the TXLOADEN Signal The TXLOADEN signal controls the transfer of data between the SERDES circuitry and the logic array when data realignment is used. To prevent the interruption of the TXLOADEN signal during data realignment, both k and v counter are used. In normal operation the TXLOADEN signal is generated by the k counter. However, during the data-realignment operation this signal is generated by either counter. When the k counter is used for realignment, the Altera Corporation July 2005 5–27 Stratix Device Handbook, Volume 2 Receiver Data Realignment TXLOADEN signal is generated by the v counter, and when the v counter is used for realignment, the TXLOADEN signal is generated by the k counter, as shown in Figure 5–20. Figure 5–20. Realignment Circuit TXLOADEN Signal Control Note (1) Counter Circuitry Clock Distribution Circuitry CLK1 LVDS Circuitry ×1 CLK1 to logic array ÷k TXLOADEN Sync S1 Data Realignment Circuit Realignment CLK 8 PLL Output SYNC Realignment CLK Data Realignment Circuit Sync S2 RXLOADEN ÷v ×1 CLK2 to logic array CLK2 LVDS Circuitry ÷l GCLK/LCLK Note to Figure 5–20: (1) This figure does not show additional realignment circuitry. Realignment Implementation The realignment signal (SYNC) is used for data realignment and reframing. An external pin (RX_DATA_ALIGN) or an internal signal controls the rx_data_align node end. When the rx_data_align node end is asserted high for at least two low-frequency clock cycles, the RXLOADEN signal is delayed by one high-frequency clock period and the parallel bits shift by one bit. Figure 5–21 shows the timing relationship between the high-frequency clock, the RXLOADEN signal, and the parallel data. 5–28 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–21. Realignment by rx_data_align Node End 10× clock 1× clock SYNC rxloaden 6 datain receiver A receiver B 5 7 6 8 7 9 8 0 9 1 0 2 1 3 2 0123456789 4 3 5 4 6 5 7 6 8 7 9 8 0 9 1 0 2 1 0123456789 3 2 4 3 5 4 6 5 7 6 8 7 9 8 0 9 1 0 1234567890 2 1 3 2 4 3 4 1234567890 A state machine can generate the realignment signal to control the alignment procedure. Figure 5–22 shows the connection between the realignment signal and the rx_data_align node end. Figure 5–22. SYNC Signal Path to Realignment Circuit Stratix Logic Array Receiver Circuit PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 Parallel Register PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 Register Array SYNC Out 10 Pattern Detection State Machine Hold Register TXLOADEN ×1 ×W/J Realignment Circuit SYNC To guarantee that the rx_data_align signal generated by a user state machine is latched correctly by the counters, the user circuit must meet certain requirements. ■ Altera Corporation July 2005 The design must include an input synchronizing register to ensure that data is synchronized to the ×1 clock. 5–29 Stratix Device Handbook, Volume 2 Source-Synchronous Timing Budget ■ ■ ■ ■ SourceSynchronous Timing Budget After the pattern detection state machine, use another synchronizing register to capture the generated SYNC signal and synchronize it to the ×1 clock. Since the skew in the path from the output of this synchronizing register to the PLL is undefined, the state machine must generate a pulse that is high for two ×1 clock periods. Since the SYNC generator circuitry only generates a single fast clock period pulse for each SYNC pulse, you cannot generate additional SYNC pulses until the comparator signal is reset low. To guarantee the pattern detection state machine does not incorrectly generate multiple SYNC pulses to shift a single bit, the state machine must hold the SYNC signal low for at least three ×1 clock periods between pulses. This section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in Stratix devices. LVDS, LVPECL, PCML, and HyperTransport I/O standards enable high-speed data transmission. This high data-transmission rate results in better overall system performance. To take advantage of fast system performance, you must understand how to analyze timing for these high-speed signals. Timing analysis for the differential block is different from traditional synchronous timing analysis techniques. Rather than focusing on clock-to-output and setup times, sourcesynchronous timing analysis is based on the skew between the data and the clock signals. High-speed differential data transmission requires you to use timing parameters provided by IC vendors and to consider board skew, cable skew, and clock jitter. This section defines the sourcesynchronous differential data orientation timing parameters, and timing budget definitions for Stratix devices, and explains how to use these timing parameters to determine a design's maximum performance. Differential Data Orientation There is a set relationship between an external clock and the incoming data. For operation at 840 Mbps and W = 10, the external clock is multiplied by 10 and phase-aligned by the PLL to coincide with the sampling window of each data bit. The third falling edge of highfrequency clock is used to strobe the incoming high-speed data. Therefore, the first two bits belong to the previous cycle. Figure 5–23 shows the data bit orientation of the ×10 mode as defined in the Quartus II software. 5–30 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–23. Bit Orientation in the Quartus II Software inclock/outclock 10 LVDS Bits MSB data in n-1 n-0 9 8 7 6 5 4 LSB 3 2 1 0 high-frequency clock Differential I/O Bit Position Data synchronization is necessary for successful data transmission at high frequencies. Figure 5–24 shows the data bit orientation for a receiver channel operating in ×8 mode. Similar positioning exists for the most significant bits (MSBs) and least significant bits (LSBs) after deserialization, as listed in Table 5–5. Figure 5–24. Bit Order for One Channel of Differential Data inclock/outclock Previous Cycle Data in/ Data out Current Cycle D7 MSB D6 D5 0 0 D4 D3 Next Cycle D2 D1 D0 LSB 1 0 Example: Sending the Data 10010110 Previous Cycle Data in/ Data out Current Cycle 1 MSB Altera Corporation July 2005 1 0 Next Cycle 1 LSB 5–31 Stratix Device Handbook, Volume 2 Source-Synchronous Timing Budget Table 5–5 shows the conventions for differential bit naming for 18 differential channels. However, the MSB and LSB are increased with the number of channels used in a system. Table 5–5. LVDS Bit Naming Receiver Data Channel Number Internal 8-Bit Parallel Data MSB Position LSB Position 1 7 0 2 15 8 3 23 16 4 31 24 5 39 32 6 47 40 7 55 48 8 63 56 9 71 64 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136 Timing Definition The specifications used to define high-speed timing are described in Table 5–6. Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2) High-Speed Timing Specification Terminology tC High-speed receiver/transmitter input and output clock period. fHSCLK High-speed receiver/transmitter input and output clock frequency. tRISE Low-to-high transmission time. 5–32 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2) High-Speed Timing Specification Terminology tFALL High-to-low transmission time. Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = tC/w). fHSDR Maximum LVDS data transfer rate (fHSDR = 1/TUI). Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. Sampling window (SW) The period of time during which the data must be valid in order for you to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) – tSW (min). Input jitter (peak-to-peak) Peak-to-peak input jitter on high-speed PLLs. Output jitter (peak-to-peak) Peak-to-peak output jitter on high-speed PLLs. tDUTY Duty cycle on high-speed transmitter output clock. tLOCK Lock time for high-speed transmitter and receiver PLLs. Altera Corporation July 2005 5–33 Stratix Device Handbook, Volume 2 Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3) Notes (1), (2) -5 Speed Grade Symbol fHSDR Device operation (LVDS, LVPECL, HyperTransport technology) 5–34 Stratix Device Handbook, Volume 2 fHSCLK (Clock frequency) (PCML) fHSCLK = fHSDR / W -7 Speed Grade -8 Speed Grade Unit Min fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology) fHSCLK = fHSDR / W -6 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max Min Typ Max W = 4 to 30 10 210 10 210 10 156 10 115.5 MHz W = 2 (Serdes bypass) 50 231 50 231 50 231 50 231 MHz W = 2 (Serdes used) 150 420 150 420 150 312 150 231 MHz W = 1 (Serdes bypass) 100 462 100 462 100 462 100 462 MHz W = 1 (Serdes used) 300 717 300 717 300 624 300 462 MHz J = 10 300 840 300 840 300 640 300 462 Mbps J=8 300 840 300 840 300 640 300 462 Mbps J=7 300 840 300 840 300 640 300 462 Mbps J=4 300 840 300 840 300 640 300 462 Mbps J=2 100 462 100 462 100 640 100 462 Mbps J = 1 (LVDS and LVPECL only) 100 462 100 462 100 640 100 462 Mbps W = 4 to 30 (Serdes used) 10 100 10 100 10 77.75 10 77.75 MHz W = 2 (Serdes bypass) 50 200 50 200 50 150 50 150 MHz W = 2 (Serdes used) 150 200 150 200 150 155.5 150 155.5 MHz W = 1 (Serdes bypass) 100 250 100 250 100 200 100 200 MHz W = 1 (Serdes used) 300 400 300 400 300 311 300 311 MHz Source-Synchronous Timing Budget Altera Corporation July 2005 Tables 5–7 and 5–8 show the high-speed I/O timing for Stratix devices -5 Speed Grade Symbol -7 Speed Grade -8 Speed Grade Unit Min fHSDR Device operation (PCML) -6 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max Min Typ Max J = 10 300 400 300 400 300 311 300 311 Mbps J=8 300 400 300 400 300 311 300 311 Mbps J=7 300 400 300 400 300 311 300 311 Mbps J=4 300 400 300 400 300 311 300 311 Mbps J=2 100 400 100 400 100 300 100 300 Mbps J=1 100 250 100 250 100 200 100 200 Mbps 300 ps TCCS All SW PCML (J = 4, 7, 8, 10) 200 750 200 300 750 800 800 ps 5–35 Stratix Device Handbook, Volume 2 PCML (J = 2) 900 900 1,200 1,200 ps PCML (J = 1) 1,500 1,500 1,700 1,700 ps LVDS and LVPECL (J = 1) 500 500 550 550 ps LVDS, LVPECL, HyperTransport technology (J = 2 through 10) 440 440 500 500 ps Input jitter tolerance All (peak-to-peak) 250 250 250 250 ps Output jitter (peakto-peak) All 160 160 200 200 ps Output tRISE LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 120 170 200 120 170 200 ps LVPECL 90 130 150 90 130 150 100 135 150 100 135 150 ps PCML 80 110 135 80 110 135 80 110 135 80 110 135 ps Source-Synchronous Timing Budget Altera Corporation July 2005 Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 3) Notes (1), (2) -5 Speed Grade Symbol Output tFALL tDUTY -7 Speed Grade -8 Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 110 170 200 110 170 200 110 170 200 110 170 200 ps LVPECL 90 130 160 90 130 160 100 135 160 100 135 160 ps PCML 105 140 175 105 140 175 110 145 175 110 145 175 ps LVDS (J = 2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % 45 50 55 45 50 55 45 50 55 45 50 55 % 100 μs LVDS (J =1) and LVPECL, PCML, HyperTransport technology tLOCK -6 Speed Grade Conditions All 100 100 100 Notes to Table 5–7: (1) (2) When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed. Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 3) -6 Speed Grade Symbol -8 Speed Grade Unit Min Altera Corporation July 2005 fHSCLK (Clock frequency) (LVDS,LVPECL, HyperTransport technology) fHSCLK = fHSDR / W -7 Speed Grade Conditions W = 4 to 30 (Serdes used) 10 Typ Max Min 156 Typ Max Min Typ Max 10 115.5 10 115.5 MHz W = 2 (Serdes bypass) 50 231 50 231 50 231 MHz W = 2 (Serdes used) 150 312 150 231 150 231 MHz W = 1 (Serdes bypass) 100 311 100 270 100 270 MHz W = 1 (Serdes used) 300 624 300 462 300 462 MHz Source-Synchronous Timing Budget 5–36 Stratix Device Handbook, Volume 2 Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3) Notes (1), (2) -6 Speed Grade Symbol fH S C L K (Clock frequency) (PCML) fHSCLK = fHSDR / W Device operation, fH S D R (PCML) -8 Speed Grade Unit Min fHSDR Device operation, (LVDS,LVPECL, HyperTransport technology) -7 Speed Grade Conditions Typ Max Min Typ Max Min Typ Max J = 10 300 624 300 462 300 462 Mbps J=8 300 624 300 462 300 462 Mbps J=7 300 624 300 462 300 462 Mbps J=4 300 624 300 462 300 462 Mbps J=2 100 462 100 462 100 462 Mbps J = 1 (LVDS and LVPECL only) 100 311 100 270 100 270 Mbps W = 4 to 30 (Serdes used) 10 77.75 W = 2 (Serdes bypass) 50 150 W = 2 (Serdes used) 150 155.5 W = 1 (Serdes bypass) 100 200 W = 1 (Serdes used) 300 311 MHz 50 77.5 50 77.5 MHz MHz 100 155 100 155 MHz MHz 5–37 Stratix Device Handbook, Volume 2 J = 10 300 311 Mbps J=8 300 311 Mbps J=7 300 311 Mbps J=4 300 311 Mbps J=2 100 300 100 155 100 155 Mbps J=1 100 200 100 155 100 155 Mbps TCCS All SW PCML (J = 4, 7, 8, 10) only 400 400 400 ps 800 800 800 ps PCML (J = 2) only 1,200 1,200 1,200 ps PCML (J = 1) only 1,700 1,700 1,700 ps LVDS and LVPECL (J = 1) only 550 550 550 ps LVDS, LVPECL, HyperTransport technology (J = 2 through 10) only 500 500 500 ps Source-Synchronous Timing Budget Altera Corporation July 2005 Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 3) -6 Speed Grade Symbol -7 Speed Grade -8 Speed Grade Conditions Unit Min Typ Max Min Typ Max Min Typ Max Input jitter tolerance (peak-topeak) All 250 250 250 ps Output jitter (peak-to-peak) All 200 200 200 ps Output tR I S E LVDS 80 110 120 80 110 120 80 110 120 ps HyperTransport technology 120 170 200 120 170 200 120 170 200 ps LVPECL 100 135 150 100 135 150 100 135 150 ps PCML 80 110 135 80 110 135 80 110 135 ps Output tFA L L tD U T Y LVDS 80 110 120 80 110 120 80 110 120 ps HyperTransport 110 170 200 110 170 200 110 170 200 ps LVPECL 100 135 160 100 135 160 100 135 160 ps PCML 110 145 175 110 145 175 110 145 175 ps LVDS (J =2..10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % 45 50 55 45 50 55 45 50 55 % 100 μs LVDS (J =1) and LVPECL, PCML, HyperTransport technology tL O C K All 100 100 Source-Synchronous Timing Budget Altera Corporation July 2005 Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 3 of 3) 5–38 Stratix Device Handbook, Volume 2 High-Speed Differential I/O Interfaces in Stratix Devices Input Timing Waveform Figure 5–25 illustrates the essential operations and the timing relationship between the clock cycle and the incoming serial data. For a functional description of the SERDES, see “Principles of SERDES Operation” on page 5–6. Figure 5–25. Input Timing Waveform Note (1) Input Clock (Differential Signal) Previous Cycle bit 0 Input Data Next Cycle Current Cycle bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 tsw0 (min) MSB tsw0 (max) tsw1 (min) tsw1 (max) tsw2 (min) tsw2 (max) tsw3 (min) tsw3 (max) tsw4 (min) tsw4 (max) tsw5 (min) tsw5 (max) tsw6 (min) tsw6 (max) tsw7 (min) tsw7 (max) bit 7 LSB Note to Figure 5–25: (1) The timing specifications are referenced at a 100-mV differential voltage. Altera Corporation July 2005 5–39 Stratix Device Handbook, Volume 2 Source-Synchronous Timing Budget Output Timing The output timing waveform in Figure 5–26 illustrates the relationship between the output clock and the serial output data stream. Figure 5–26. Output Timing Waveform Note (1) Output Clock (Differential Signal) Previous Cycle Output Data bit 0 Next Cycle Current Cycle bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TPPos0 (min) MSB TPPos0 (max) LSB TPPos1 (min) TPPos1 (max) TPPos2 (min) TPPos2 (max) TPPos3 (min) TPPos3 (max) TPPos4 (min) TPPos4 (max) TPPos5 (min) TPPos5 (max) TPPos6 (min) TPPos6 (max) TPPos7 (min) TPPos7 (max) Note to Figure 5–26: (1) The timing specifications are referenced at a 250-mV differential voltage. Receiver Skew Margin Change in system environment, such as temperature, media (cable, connector, or PCB) loading effect, a receiver's inherent setup and hold, and internal skew, reduces the sampling window for the receiver. The timing margin between receiver’s clock input and the data input sampling window is known as RSKM. Figure 5–27 illustrates the relationship between the parameter and the receiver’s sampling window. 5–40 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget Timing Diagram External Input Clock Time Unit Interval (TUI) Internal Clock TCCS TCCS Receiver Input Clock Sampling Window (SW) RSKM RSKM TPPos (max) Bit n + 1 TPPos (max) Bit n tSW (min) Bit n TPPos (min) Bit n Timing Budget Internal tSW (max) Clock Bit n Falling Edge TPPos (min) Bit n + 1 TUI External Clock Clock Placement Internal Clock Synchronization Transmitter Output Data RSKM RSKM TCCS TCCS 2 TSWEND Receiver Input Data TSWBEGIN Altera Corporation July 2005 Sampling Window 5–41 Stratix Device Handbook, Volume 2 SERDES Bypass DDR Differential Signaling Switching Characteristics Timing specifications for Stratix devices are listed in Tables 5–7 and 5–8. You can also find Stratix device timing information in the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. Timing Analysis Differential timing analysis is based on skew between data and the clock signals. For static timing analysis, the timing characteristics of the differential I/O standards are guaranteed by design and depend on the frequency at which they are operated. Use the values in the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 to calculate system timing margins for various I/O protocols. For detailed descriptions and implementations of these protocols, see the Altera web site at www.altera.com. SERDES Bypass DDR Differential Signaling Each Stratix device high-speed differential I/O channel can transmit or receive data in by-two (×2) mode at up to 624 Mbps using PLLs. These pins do not require dedicated SERDES circuitry and they implement serialization and deserialization with minimal logic. SERDES Bypass DDR Differential Interface Review Stratix devices use dedicated DDR circuitry to implement ×2 differential signaling. Although SDR circuitry samples data only at the positive edge of the clock, DDR captures data on both the rising and falling edges for twice the transfer rate of SDR. Stratix device shift registers, internal global PLLs, and I/O cells can perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. SERDES Clock Domains The SERDES bypass differential signaling can use any of the many clock domains available in Stratix devices. These clock domains fall into four categories: global, regional, fast regional, and internally generated. General-purpose PLLs generate the global clock domains. The fast PLLs can generate additional global clocks domains. Each PLL features two taps that directly drive two unique global clock networks. A dedicated clock pin drives each general-purpose PLL. These clock lines are utilized when designing for speeds up to 420 Mbps. Tables 5–3 and 5–4 on page 5–19, respectively, show the available clocks in Stratix devices. 5–42 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices SERDES Bypass DDR Differential Signaling Receiver Operation The SERDES bypass differential signaling receiver uses the Stratix device DDR input circuitry to receive high-speed serial data. The DDR input circuitry consists of a pair of shift registers used to capture the high-speed serial data, and a latch. One register captures the data on the positive edge of the clock (generated by PLL) and the other register captures the data on the negative edge of the clock. Because the data captured on the negative edge is delayed by one-half of the clock cycle, it is latched before it interfaces with the system logic. Figure 5–28 shows the DDR timing relationship between the incoming serial data and the clock. In this example, the inclock signal is running at half the speed of the incoming data. However, other combinations are also possible. Figure 5–29 shows the DDR input and the other modules used in a Flexible-LVDS receiver design to interface with the system logic. Figure 5–28. ×2 Timing Relation between Incoming Serial Data & Clock clock datain B0 neg_reg_out XX Altera Corporation July 2005 A0 B1 B0 A1 B2 B1 A2 B3 B2 A3 B3 dataout_l XX B0 B1 B2 dataout_h XX A0 A1 A2 5–43 Stratix Device Handbook, Volume 2 SERDES Bypass DDR Differential Signaling Figure 5–29. ×2 Data Rate Receiver Channel with Deserialization Factor of 8 DDR IOE datain Shift Register DFF D0, D2, D4, D6 Register D1, D3, D5, D7 Stratix Logic Array Latch DFF Shift Register inclock PLL ×4 Clock ×1 SERDES Bypass DDR Differential Signaling Transmitter Operation The ×2 differential signaling transmitter uses the Stratix device DDR output circuitry to transmit high-speed serial data. The DDR output circuitry consists of a pair of shift registers and a multiplexer. The shift registers capture the parallel data on the clock’s rising edge (generated by the PLL), and a multiplexer transmits the data in sync with the clock. Figure 5–30 shows the DDR timing relation between the parallel data and the clock. In this example, the inclock signal is running at half the speed of the data. However, other combinations are possible. Figure 5–31 shows the DDR output and the other modules used in a ×2 transmitter design to interface with the system logic. 5–44 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–30. ×2 Timing Relation between Parallel Data & Clock outclock datain_l XX B0 B1 B2 B3 datain_h XX A0 A1 A2 A3 dataout XX A0 B0 A1 B1 A2 B2 A3 Figure 5–31. ×2 Data Rate Transmitter Channel with Serialization Factor of 8 DDR IOE DFF D0, D2, D4, D6 Stratix Logic Array Shift Register dataout DFF D1, D3, D5, D7 Shift Register ×1 PLL ×4 ×1 inclock High-Speed Interface Pin Locations Stratix high-speed interface pins are located at the edge of the package to limit the possible mismatch between a pair of high-speed signals. Stratix devices have eight programmable I/O banks. Figure 5–32 shows the I/O pins and their location relative to the package. Altera Corporation July 2005 5–45 Stratix Device Handbook, Volume 2 Differential I/O Termination Figure 5–32. Differential I/O Pin Locations Differential I/O Pins (LVDS, LVPECL, PCML, HyperTransport) Regular I/O Pins Differential I/O Pins (LVDS, LVPECL, PCML, HyperTransport) A B C D E F G H J K L M N P R T U V W Y AA 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Regular I/O Pins Differential I/O Termination Stratix devices implement differential on-chip termination to reduce reflections and maintain signal integrity. On-chip termination also minimizes the number of external resistors required. This simplifies board design and places the resistors closer to the package, eliminating small stubs that can still lead to reflections. RD Differential Termination Stratix devices support differential on-chip termination for the LVDS I/O standard. External termination is required on output pins for PCML transmitters. HyperTransport, LVPECL, and LVDS receivers require 100 ohm termination at the input pins. Figure 5–33 shows the device with differential termination for the LVDS I/O standard. f For more information on differential on-chip termination technology, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter. 5–46 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–33. LVDS Differential On-Chip Termination LVDS Receiver with On-Chip 100-Ω Termination LVDS Transmitter Z0 = 50 Ω RD Z0 = 50 Ω HyperTransport & LVPECL Differential Termination HyperTransport and LVPECL I/O standards are terminated by an external 100-Ω resistor on the input pin. Figure 5–34 shows the device with differential termination for the HyperTransport or LVPECL I/O standard. Figure 5–34. HyperTransport & LVPECL Differential Termination Differential Transmitter Differential Receiver Z0 = 50 Ω RD Z0 = 50 Ω PCML Differential Termination The PCML I/O technology is an alternative to the LVDS I/O technology, and use an external voltage source (VTT), a pair of 100-Ω resistors on the input side and a pair of 50-Ω resistors on the output side. Figure 5–35 shows the device with differential termination for PCML I/O standard. Altera Corporation July 2005 5–47 Stratix Device Handbook, Volume 2 Differential I/O Termination Figure 5–35. PCML Differential Termination VTT Differential Transmitter 50 Ω 50 Ω 50 Ω Differential Receiver 50 Ω Z0 = 50 Ω Z0 = 50 Ω Differential HSTL Termination The HSTL Class I and II I/O standards require a 0.75-V VREF and a 0.75V VTT. Figures 5–36 and 5–37 show the device with differential termination for HSTL Class I and II I/O standard. Figure 5–36. Differential HSTL Class I Termination VTT = 0.75 V Differential Transmitter 50 Ω VTT = 0.75 V 50 Ω Differential Receiver Z0 = 50 Ω Z0 = 50 Ω 5–48 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–37. Differential HSTL Class II Termination VTT = 0.75 V Differential Transmitter 50 Ω VTT = 0.75 V VTT = 0.75 V 50 Ω 50 Ω VTT = 0.75 V Differential Receiver 50 Ω Z0 = 50 Ω Z0 = 50 Ω Differential SSTL-2 Termination The SSTL-2 Class I and II I/O standards require a 1.25-V VREF and a 1.25-V VTT. Figures 5–37 and 5–38 show the device with differential termination for SSTL-2 Class I and II I/O standard. Figure 5–38. Differential SSTL-2 Class I Termination VTT = 1.25 V Differential Transmitter 50 Ω VTT = 1.25 V 50 Ω Differential Receiver 25 Ω Z0 = 50 Ω 25 Ω Z0 = 50 Ω Altera Corporation July 2005 5–49 Stratix Device Handbook, Volume 2 Board Design Consideration Figure 5–39. Differential SSTL-2 Class II Termination VTT = 1.25 V Differential Transmitter 50 Ω VTT = 1.25 V 50 Ω VTT = 1.25 V 50 Ω VTT = 1.25 V 50 Ω Differential Receiver 25 Ω Z0 = 50 Ω 25 Ω Z0 = 50 Ω Board Design Consideration This section is a brief explanation of how to get the optimal performance from the Stratix high-speed I/O block and ensure first-time success in implementing a functional design with optimal signal quality. For more information on detailed board layout recommendation and I/O pin terminations see AN 224: High-Speed Board Layout Guidelines. You must consider the critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques to get the best performance from the IC. For more information, use this chapter and the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1. The Stratix high-speed module generates signals that travel over the media at frequencies as high as 840 Mbps. Board designers should use the following general guidelines: ■ ■ ■ ■ ■ ■ ■ Baseboard designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces. Place external reference resistors as close to receiver input pins as possible. Use surface mount components. Avoid 90° or 45° corners. Use high-performance connectors such as HS-3 connectors for backplane designs. High-performance connectors are provided by Teradyne Corp (www.teradyne.com) or Tyco International Ltd. (www.tyco.com). Design backplane and card traces so that trace impedance matches the connector’s and/or the termination’s impedance. Keep equal number of vias for both signal traces. 5–50 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices ■ ■ ■ ■ ■ Software Support Create equal trace lengths to avoid skew between signals. Unequal trace lengths also result in misplaced crossing points and system margins as the TCCS value increases. Limit vias because they cause discontinuities. Use the common bypass capacitor values such as 0.001 µF, 0.01 µF, and 0.1 µF to decouple the fast PLL power and ground planes. Keep switching TTL signals away from differential signals to avoid possible noise coupling. Do not route TTL clock signals to areas under or above the differential signals. This section provides information on using the Quartus II software to create Stratix designs with LVDS transmitters or receivers. You can use the altlvds megafunction in the Quartus II software to implement the SERDES circuitry. You must bypass the SERDES circuitry in ×1 and ×2 mode designs and use the altddio megafunction to implement the deserialization instead. You can use either the logic array or the M512 RAM blocks closest to the differential pins for deserialization in SERDES bypass mode. Differential Pins in Stratix Stratix device differential pins are located in I/O banks 1, 2, 5, and 6 (see Figure 5–1 on page 5–2). Each bank has differential transmitter and differential receiver pin pairs. You can use each differential transmitter pin pair as either a differential data pin pair or a differential clock pin pair because Stratix devices do not have dedicated LVDS tx_outclock pin pairs. The differential receiver pin pairs can only function as differential data pin pairs. You can use these differential pins as regular user I/O pins when not used as differential pins. When using differential signaling in an I/O bank, you cannot place non-differential output or bidirectional pads within five I/O pads of either side of the differential pins to avoid a decrease in performance on the LVDS signals. You only need to make assignments to the positive pin of the pin-pair. The Quartus II software automatically reserves and makes the same assignment to the negative pin. If you do not assign any differential I/O standard to the differential pins, the Quartus II software sets them as LVDS differential pins during fitting, if the design uses the SERDES circuitry. Additionally, if you bypass the SERDES circuitry, you can still use the differential pins by assigning a differential I/O standard to the pins in the Quartus II software. However, when you bypass the SERDES circuitry in the ×1 and ×2 mode, you must assign the correct differential I/O standard to the associated pins in the Assignment Organizer. For more information on how to use the Assignment Organizer, see the Quartus II On-Line Help. Altera Corporation July 2005 5–51 Stratix Device Handbook, Volume 2 Software Support Stratix devices can drive the PLL_LOCK signal to both output pins and internal logic. As a result, you do not need a dedicated LOCK pin for your PLLs. In addition, there is only one PLL_ENABLE pin that enables all the PLLs on the device, including the fast PLLs. You must use either the LVTTL or LVCMOS I/O standard with this pin. Table 5–9 displays the LVDS pins in Stratix devices. Table 5–9. LVDS Pin Names Pin Names Functions DIFFIO_TX#p Transmitter positive data or output clock pin DIFFIO_TX#n Transmitter negative data or output clock pin DIFFIO_RX#p Receiver positive data pin DIFFIO_RX#n Receiver negative data pin FPLLCLK#p Positive input clock pin to the corner fast PLLs (1), (2) FPLLCLK#n Negative input clock pin to the corner fast PLLs (1), (2) CLK#p Positive input clock pin (2) CLK#n Negative input clock pin (2) Notes to Table 5–9: (1) (2) The FPLLCLK pin-pair is only available in EP1S30, EP1S40, EP1S60, EP1S80 devices. Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode. Fast PLLs Each fast PLL features a multiplexed input path from a global or regional clock net. A clock pin or an output from another PLL in the device can drive the input path. The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be driven by a dedicated clock pin (CLK[3..0,8..11]) or the corner pins that clock the corner PLLs (FPLL[10..7]CLK). EP1S10, EP1S20, and EP1S25 devices have a total of four fast PLLs located in the center of both sides of the device (see Figure 5–16 on page 5–23). EP1S30 and larger devices have two additional fast PLLs per side at the top and bottom corners of the device. As shown in Figure 5–17 on page 5–24, the corner fast PLL shares an I/O bank with the closest center fast PLL (e.g., PLLs 1 and 7 share an I/O bank). The maximum input clock frequency for enhanced PLLs is 684 MHz and 717 MHz for fast PLLs. f For more information on Stratix PLLs, see the General-Purpose PLLs in Stratix & Stratix GX Devices chapter. 5–52 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices One fast PLL can drive the 20 transmitter channels and 20 receiver channels closest to it with data rates of up to 840 Mbps. Wire-bond packages support a data rate of 624 Mbps. The corner fast PLLs in EP1S80 devices support data rates of up to 840 Mbps. See Tables 5–10 through 5–14 for the number of high-speed differential channels in a particular Stratix device density and package. Since the fast PLL drives the 20 closest differential channels, there are coverage overlaps in the EP1S30 and larger devices that have two fast PLLs per I/O bank. In these devices, either the center fast PLL or the corner fast PLL can drive the differential channels in the middle of the I/O bank. Fast PLLs can drive more than 20 transmitter and 20 receiver channels (see Tables 5–10 through 5–14 and Figures 5–16, and 5–17 for the number of channels each PLL can drive). In addition, the center fast PLLs can drive either one I/O bank or both I/O banks on the same side (left or right) of the device, while the corner fast PLLs can only drive the differential channels in its I/O bank. Neither fast PLL can drive the differential channels in the opposite side of the device. The center fast PLLs can only drive two I/O at 840 Mbps. For example, EP1S20 device fast PLL 1 can drive all 33 differential channels on its side (17 channels from I/O bank 2 and 16 channels from I/O bank 1) running at 840 Mbps in 4× mode. When a center fast PLL drives the opposite bank on the same side of the device, the other center fast PLL cannot drive any differential channels on the device. See Tables 5–10 through 5–14 for the maximum number of channels that one fast PLL can drive. The number of channels is also listed in the Quartus II software. The Quartus II software gives an error message if you try to compile a design exceeding the maximum number of channels. f Altera Corporation July 2005 Additional high-speed DIFFIO pin information for Stratix devices is available in Volume 3 of the Stratix Device Handbook. 5–53 Stratix Device Handbook, Volume 2 Software Support Table 5–10 shows the number of channels and fast PLLs in EP1S10, EP1S20, and EP1S25 devices. Tables 5–11 through 5–14 show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices. Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1) Device EP1S10 Package Transmitter/ Receiver 484-pin FineLine BGA Transmitter (2) Receiver 672-pin FineLine BGA Transmitter 672-pin BGA (2) Receiver 780-pin FineLine BGA Transmitter (2) Receiver EP1S20 484-pin FineLine BGA Transmitter (2) Receiver 672-pin FineLine BGA Transmitter 672-pin BGA (2) Receiver 780-pin FineLine BGA Transmitter (2) Receiver 5–54 Stratix Device Handbook, Volume 2 Total Channels 20 20 36 36 44 44 24 20 48 50 66 66 Maximum Speed (Mbps) Center Fast PLLs PLL 1 PLL 2 PLL 3 PLL 4 840 5 5 5 5 840 (3) 10 10 10 10 840 5 5 5 5 840 (3) 10 10 10 10 624 (4) 9 9 9 9 624 (3) 18 18 18 18 624 (4) 9 9 9 9 624 (3) 18 18 18 18 840 11 11 11 11 840 (3) 22 22 22 22 840 11 11 11 11 840 (3) 22 22 22 22 840 6 6 6 6 840 (3) 12 12 12 12 840 5 5 5 5 840 (3) 10 10 10 10 624 (4) 12 12 12 12 624 (3) 24 24 24 24 624 (4) 13 12 12 13 624 (3) 25 25 25 25 840 17 16 16 17 840 (3) 33 33 33 33 840 17 16 16 17 840 (3) 33 33 33 33 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1) Device EP1S25 Package Transmitter/ Receiver 672-pin FineLine BGA Transmitter 672-pin BGA (2) Receiver 780-pin FineLine BGA Transmitter (2) Receiver 1,020-pin FineLine BGA Total Channels Maximum Speed (Mbps) PLL 1 PLL 2 PLL 3 PLL 4 56 624 (4) 14 14 14 14 624 (3) 28 28 28 28 624 (4) 14 15 15 14 624 (3) 29 29 29 29 58 70 66 Transmitter (2) 78 Receiver 78 Center Fast PLLs 840 18 17 17 18 840 (3) 35 35 35 35 840 17 16 16 17 840 (3) 33 33 33 33 840 19 20 20 19 840 (3) 39 39 39 39 840 19 20 20 19 840 (3) 39 39 39 39 Notes to Table 5–10: (1) (2) (3) (4) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at 840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design requires a DDR clock, it can use an extra data channel. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock crossbank channels simultaneously if, for example, PLL_1 is clocking all RX channels and PLL_2 is clocking all TX channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank RX channels or two adjacent PLLs simultaneously clocking TX channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. These values show the channels available for each PLL without crossing another bank. Altera Corporation July 2005 5–55 Stratix Device Handbook, Volume 2 Software Support Table 5–11. EP1S30 Differential Channels Note (1) Package 780-pin FineLine BGA 956-pin FineLine BGA 1,020-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) 70 Receiver 66 Transmitter (4) 80 (7) Receiver 80 (7) Transmitter (4) 80 (2) (7) Receiver 80 (2) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 17 17 18 (6) (6) (6) (6) 840 (5) 35 35 35 35 (6) (6) (6) (6) 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 840 19 20 20 19 20 20 20 20 840 (5) 39 39 39 39 20 20 20 20 840 20 20 20 20 19 20 20 19 840 (5) 40 40 40 40 19 20 20 19 840 19 (1) 20 20 19 (1) 20 20 20 20 840 (5),(8) 39 (1) 39 (1) 39 (1) 39 (1) 20 20 20 20 840 20 20 20 20 19 (1) 20 20 19 (1) 840 (5),(8) 40 40 40 40 19 (1) 20 20 19 (1) Table 5–12. EP1S40 Differential Channels (Part 1 of 2) Note (1) Package 780-pin FineLine BGA 956-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) 68 Receiver 66 Transmitter (4) 80 Receiver 80 5–56 Stratix Device Handbook, Volume 2 Maximum Speed (Mbps) Center Fast PLLs Corner Fast PLLs (2), (3) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 16 16 18 (6) (6) (6) (6) 840 (5) 34 34 34 34 (6) (6) (6) (6) 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 840 18 17 17 18 20 20 20 20 840 (5) 35 35 35 35 20 20 20 20 840 20 20 20 20 18 17 17 18 840 (5) 40 40 40 40 18 17 17 18 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–12. EP1S40 Differential Channels (Part 2 of 2) Note (1) Package 1,020-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) Receiver 1,508-pin FineLine BGA Transmitter (4) Receiver 80 (10) (7) 80 (10) (7) 80 (10) (7) 80 (10) (7) Maximum Speed (Mbps) Center Fast PLLs Corner Fast PLLs (2), (3) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5), (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5), (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5), (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5), (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) Table 5–13. EP1S60 Differential Channels (Part 1 of 2) Note (1) Package 956-pin FineLine BGA 1,020-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) 80 Receiver 80 Transmitter (4) 80 (12) (7) Receiver Altera Corporation July 2005 80 (10) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 12 10 10 12 20 20 20 20 840 (5), (8) 22 22 22 22 20 20 20 20 840 20 20 20 20 12 10 10 12 840 (5), (8) 40 40 40 40 12 10 10 12 840 12 (2) 10 (4) 10 (4) 12 (2) 20 20 20 20 840 (5), (8) 22 (6) 22 (6) 22 (6) 22 (6) 20 20 20 20 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5), (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) 5–57 Stratix Device Handbook, Volume 2 Software Support Table 5–13. EP1S60 Differential Channels (Part 2 of 2) Note (1) Package 1,508-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) Receiver 80 (36) (7) 80 (36) (7) Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 12 (8) 10 (10) 10 (10) 12 (8) 20 20 20 20 840 (5),(8) 22 (18) 22 (18) 22 (18) 22 (18) 20 20 20 20 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5),(8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) Table 5–14. EP1S80 Differential Channels (Part 1 of 2) Note (1) Package 956-pin FineLine BGA 1,020-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) 80 (40) (7) Receiver 80 Transmitter (4) 80 (12) (7) Receiver 80 (10) (7) 5–58 Stratix Device Handbook, Volume 2 Maximum Center Fast PLLs Corner Fast PLLs (2) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 10 10 10 10 20 20 20 20 840 (5),(8) 20 20 20 20 20 20 20 20 840 20 20 20 20 10 10 10 10 840 (5),(8) 40 40 40 40 10 10 10 10 840 10 (2) 10 (4) 10 (4) 10 (2) 20 20 20 20 840 (5),(8) 20 (6) 20 (6) 20 (6) 20 (6) 20 20 20 20 840 20 20 20 20 10 (2) 10 (3) 10 (3) 10 (2) 840 (5),(8) 40 40 40 40 10 (2) 10 (3) 10 (3) 10 (2) Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Table 5–14. EP1S80 Differential Channels (Part 2 of 2) Note (1) Package 1,508-pin FineLine BGA Transmitter Total /Receiver Channels Transmitter (4) Receiver 80 (72) (7) 80 (56) (7) Maximum Center Fast PLLs Corner Fast PLLs (2) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 840 10 (10) 10 (10) 10 (10) 10 (10) 20 (8) 20 (8) 20 (8) 20 (8) 840 (5),(8) 20 (20) 20 (20) 20 (20) 20 (20) 20 (8) 20 (8) 20 (8) 20 (8) 840 20 20 20 20 10 (14) 10 (14) 10 (14) 10 (14) 840 (5),(8) 40 40 40 40 10 (14) 10 (14) 10 (14) 10 (14) Notes to Tables 5–11 through 5–14. (1) (2) (3) (4) (5) (6) (7) (8) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and 4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap, see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com). The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device pin tables. The numbers of channels listed include the transmitter clock output (tx_outclock) channel. You can use an extra data channel if you need a DDR clock. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. PLLs 7, 8, 9, and 10 are not available in this device. The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These channels are independent of the high-speed differential channels. For the location of these channels, see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com). See device pin-outs channels marked “high” speed are 840 Mbps and “low” speed channels are 462 MBps. The Quartus II software may also merge transmitter and receiver PLLs when a receiver block is driving a transmitter block if the Use Common PLLs for Rx and Tx option is set for both modules. The Quartus II software does not merge the PLLs in multiple transmitter-only or multiple receiver-only modules fed by the same clock. Altera Corporation July 2005 5–59 Stratix Device Handbook, Volume 2 Software Support When you span two I/O banks using cross-bank support, you can route only two load enable signals total between the plls. When you enable rx_data_align, you use both rxloadena and txloadena of a PLL. That leaves no loadena for the second PLL. The only way you can use the rx_data_align is if one of the following is true: ■ ■ The RX PLL is only clocking RX channels (no resources for TX) If all channels can fit in one I/O bank LVDS Receiver Block You only need to enter the input clock frequency, deserialization factor, and the input data rate to implement an LVDS receiver block. The Quartus II software then automatically sets the clock boost (W) factor for the receiver. In addition, you can also indicate the clock and data alignment for the receiver or add the pll_enable, rx_data_align, and rx_locked output ports. Table 5–15 explains the function of the available ports in the LVDS receiver block. Table 5–15. LVDS Receiver Ports Port Name Direction rx_in[number_of_channels - 1..0] Input Function Input Port Source/Output Port Destination Input data channel Pin rx_inclock Input Reference input clock Pin or output from a PLL rx_pll_enable Input Enables fast PLL Pin (1), (2), (3) rx_data_align Input Control for the data realignment circuitry Pin or logic array (1), (3), (4) rx_locked Output Fast PLL locked pin Pin or logic array (1), (3) rx_out[Deserialization_factor * number_of_channels -1..0] Output De-serialized data Logic array rx_outclock Output Internal reference clock Logic array Notes to Table 5–15: (1) (2) (3) (4) This is an optional port. Only one rx_pll_enable pin is necessary to enable all the PLLs in the device. This is a non-differential pin. See “Realignment Implementation” on page 5–28 for more information. For guaranteed performance and data alignment, you must synchronize rx_data_align with rx_outclock. 5–60 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Use the altlvds MegaWizard Plug-In Manager to create an LVDS receiver block. The following sections explain the parameters available in the Plug-In Manager when creating an LVDS receiver block. Page 3 of the altlvds_rx MegaWizard Plug-In Manager On page 3 of the altlvds MegaWizard Plug-In Manager, you can choose to create either an LVDS transmitter or receiver. Depending on what you select, the MegaWizard Plug-In Manager provides you with different options. Figure 5–40 shows page 3 of the altlvds MegaWizard Plug-In Manager with options for creating an LVDS receiver. Figure 5–40. Page 3 of the altlvds_rx MegaWizard Plug-In Manager Number of Channels The What is the number of channels? parameter specifies the number of receiver channels required and the width of rx_out port. To set a fast PLL to drive over 20 channels, type the required number in the Quartus II window instead of choosing a number from the drop-down menu, which only has selections of up to 20 channels. Altera Corporation July 2005 5–61 Stratix Device Handbook, Volume 2 Software Support Deserialization Factor Use the What is the deserialization factor? parameter to specify the number of bits per channel. The Stratix LVDS receiver supports 4, 7, 8, and 10 for deserialization factor (J) values. Based on the factor specified, the Quartus II software determines the multiplication and/or division factor for the LVDS PLL to deserialize the data. See Table 5–5 for the differential bit naming convention. The parallel data for the nth channel spans from the MSB (rx_out bit [(J × n) – 1]) to the LSB (rx_out bit [J × (n – 1)]), where J is the deserialization factor. The total width of the receiver rx_out port is equal to the number of channels multiplied by your deserialization factor. Input Data Rate The What is the inclock boost(W)? parameter sets the data rate coming into the receiver and is usually the deserialization factor (J) multiplied by the inclock frequency. This parameter’s value must be larger than the input clock frequency and has a maximum input data rate of 840 Mbps for Stratix devices. You do not have to provide a value for the inclock boost (W) when designing with Stratix devices because the Quartus II software can calculate it automatically from this parameter and the clock frequency or clock period. The rx_outclock frequency is (W/J) × input frequency. The parallel data coming out of the receiver has the same frequency as the rx_outclock port. The clock-to-data alignment of the parallel data output from the receiver depends on the What is the alignment of data with respect to rx_inclock? parameter. Data Alignment with Clock The What is the alignment of data with respect to rx_inclock? parameter adjusts the clock-to-data skew. For most applications, the data is source synchronous to the clock. However, there are applications where you must center-align the data with respect to the clock. You can use the What is the alignment of data with respect to rx_inclock? parameter to align the input data with respect to the rx_inclock port. The MegaWizard Plug-In automatically calculates the phase for the fast PLL outputs from the What is the alignment of data with respect to rx_inclock? parameter. This parameter’s default value is EDGE_ALIGNED, and other values available from the pull-down menu are EDGE_ALIGNED, CENTER_ALIGNED, 45_DEGREES, 135_DEGREES, 180_DEGREES, 225_DEGREES, 270_DEGREES, and 315_DEGREES. CENTER_ALIGNED is the same as 90 degrees aligned and is useful for applications like HyperTransport technology. 5–62 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Clock Frequency or Clock Period The fields in the Specify the input clock rate by box specify the input frequency or the period of the input clock going into the fast PLL. When using the same input clock to feed a transmitter and receiver simultaneously, the Quartus II software can use one fast PLL for both the transmitter and receiver. Page 4 of the altlvds_rx MegaWizard Plug-In Manager This section describes the parameters found on page 4 of the altlvds_rx MegaWizard Plug-In Manager (see Figure 5–41). Figure 5–41. Page 4 of the altlvds_rx MegaWizard Plug-In Manager Altera Corporation July 2005 5–63 Stratix Device Handbook, Volume 2 Software Support Data Realignment Check the Use the “rx_data_align” input port box within the Input Ports box to add the rx_data_align output port and enable the data realignment circuitry in Stratix SERDES. See “Receiver Data Realignment” on page 5–25 for more information. If necessary, you can create a state machine to send a pulse to the rx_data_align port to realign the data coming in the LVDS receiver. You need to assert the port for at least two clock cycles to enable the data realignment circuitry. Go to the Altera web site at www.altera.com for a sample design written in Verilog HDL. For guaranteed performance when using data realignment, check the Add Extra registers for rx_data_align input box when using the rx_data_align port. The Quartus II software places one synchronization register in the LE closest to the rx_data_align port. Register Outputs Check the Register outputs box to register the receiver’s output data. The register acts as the module’s register boundary. If the module fed by the receiver does not have a register boundary for the data, turn this option on. The number of registers used is proportional to the deserialization factor (J). The Quartus II software places the synchronization registers in the LEs closest to the SERDES circuitry. Use Common PLL for Both Transmitter & Receiver Check the Use Common PLLs for Rx and Tx box to place both the LVDS transmitter and the LVDS receiver in the same Stratix device I/O bank. The Quartus II software allows the transmitter and receiver to share the same fast PLL when they use the same input clock. Although you must separate the transmitter and receiver modules in your design, the Quartus II software merges the fast PLLs when appropriate and give you the following message: Receiver fast PLL and transmitter fast PLL are merged together The Quartus II software provides the following message when it cannot merge the fast PLLs for the LVDS transmitter and receiver pair in the design: Can't merge transmitter-only fast PLL and receiveronly fast PLL rx_outclock Resource You can use either the global or regional clock for the rx_outclock signal. If you select Auto in the Quartus II software, the tool uses any available lines. 5–64 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices LVDS Transmitter Module The Quartus II software calculates the inclock boost (W) factor for the LVDS transmitter based on input data rate, input clock frequency, and the deserialization factor. In addition to setting the data and clock alignment, you can also set the outclock divide factor (B) for the transmitter output clock and add the pll_enable, tx_locked, and tx_coreclock ports. Table 5–16 explains the function of the available ports in the LVDS transmitter block. Table 5–16. LVDS Transmitter Ports Port Name Direction Function Input port Source/Output port Destination tx_in[Deserialization_factor * number_of_channels - 1..0] Input Input data Logic array tx_inclock Input Reference input clock Pin or output clock from a PLL tx_pll_enable Input tx_out[number_of_channels - 1..0] Output Fast PLL enable Pin (1), (2), (3) Serialized LVDS data signal Pin tx_outclock Output External reference clock Pin tx_coreclock Output Internal reference clock Pin, logic array, or input clock to a fast PLL (1) tx_locked Output Fast PLL locked pin Pin or logic array (1), (2), (3) Notes to Table 5–16: (1) (2) (3) This is an optional port. Only one tx_pll_enable pin is necessary to enable all the PLLs in the device. This is a non-differential pin. You can also use the altlvds MegaWizard Plug-In Manager to create an LVDS transmitter block. The following sections explain the parameters available in the Plug-In Manager when creating an LVDS transmitter block. Page 3 of the altlvds_tx MegaWizard Plug-In Manager This section describes the parameters found on page 3 of the altlvds_tx MegaWizard Plug-In Manager (see Figure 5–42). Altera Corporation July 2005 5–65 Stratix Device Handbook, Volume 2 Software Support Figure 5–42. Page 3 of the Transmitter altlvds MegaWizard Plug-In Manager Number of Channels The What is the number of channels? parameter specifies the number of transmitter channels required and the width of the tx_in port. You can have more than 20 channels in a transmitter or receiver module by typing in the required number instead of choosing a number from the drop down menu, which only has selections of up to 20 channels. Deserialization Factor The What is the deserialization factor? parameter specifies the number of bits per channel. The transmitter block supports deserialization factors of 4, 7, 8, and 10. Based on the factor specified, the Quartus II software determines the multiplication and/or division factor for the LVDS PLL in order to serialize the data. Table 5–5 on page 5–32 lists the differential bit naming convention. The parallel data for the nth channel spans from the MSB (rx_out bit [(J × n) – 1]) to the LSB (rx_out bit [J × (n – 1)]), where J is the 5–66 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices deserialization factor. The total width of the tx_in port of the transmitter is equal to the number of channels multiplied by the deserialization factor. Outclock Divide Factor The What is the Output data rate? parameter specifies the ratio of the tx_outclock frequency compared to the data rate. The default value for this parameter is the value of the deserialization factor parameter. The tx_outclock frequency is equal to [W/B] x input clock frequency. There is also an optional tx_coreclock port which has the same frequency as the [W/J] × input frequency. The outclock divide factor is useful for applications that do not require the data rate to be the same as the clock frequency. For example, HyperTransport technology uses a half-clock data rate scheme where the clock frequency is half the data rate. Table 5–17 shows the supported outclock divide factor for a given deserialization factor. Table 5–17. Deserialization Factor (J) vs. Outclock Divide Factor (B) Deserialization Factor (J) Outclock Divide Factor (B) 4 1, 2, 4 7 1, 7(1) 8 1, 2, 4, 8 10 1, 2, 10 Note to Table 5–17: (1) The clock does not have a 50% duty cycle when b=7 in x7 mode. Output Data Rate The What is the Output data rate parameter specifies the data rate out of the fast PLL and determines the input clock boost/multiplication factor needed for the transmitter. This parameter must be larger than the input clock frequency and has a maximum rate of 840 Mbps for Stratix devices. The input clock boost factor (W) is the output data rate divided by the input clock frequency. The Stratix SERDES circuitry supports input clock boost factors of 4, 7, 8, or 10. The maximum output data rate is 840 Mbps, while the clock has a maximum output of 500 MHz. Data Alignment with Clock Use the What is the alignment of data with respect to tx_inclock? parameter and the What is the alignment of tx_outclock? to align the input and output data, respectively, with the clock. For most applications, the data is edge-aligned with the clock. However, there are applications where the data must be center-aligned with respect to the clock. With Altera Corporation July 2005 5–67 Stratix Device Handbook, Volume 2 Software Support Stratix devices, you can align the input data with respect to the tx_inclock port and align the output data with respect to the tx_outclock port. The MegaWizard Plug-In Manager uses the alignment of input and output data to automatically calculate the phase for the fast PLL outputs. Both of these parameters default to EDGE_ALIGNED, and other values are CENTER_ALIGNED, 45_DEGREES, 135_DEGREES, 180_DEGREES, 225_DEGREES, 270_DEGREES, and 315_DEGREES. CENTER_ALIGNED is the same as 180 degrees aligned and is required for the HyperTransport technology I/O standard. Clock Frequency & Clock Period The fields in the Specify the input clock rate by box specify either the frequency or the period of the input clock going into the fast PLL. However, you cannot specify both. If your design uses the same input clock to feed a transmitter and a receiver module simultaneously, the Quartus II software can merge the fast PLLs for both the transmitter and receiver when the Use common PLLs for Tx & Rx option is turned on. Page 4 of the altlvds_tx MegaWizard Plug-In Manager This section describes the parameters found on page 4 of the altlvds_tx MegaWizard Plug-In Manager (see Figure 5–43). 5–68 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–43. Page 4 of the Transmitter altlvds MegaWizard Plug-In Manager Registered Inputs Check the Register inputs box if the input data to the transmitter is not registered just before it feeds the transmitter module. You can choose either tx_clkin or tx_coreclk to clock the transmitter data (tx_in[]) signal. This serves as the register boundary. The number of registers used is proportional to the deserialization factor (J). The Quartus II software places the synchronization registers with the LEs in the same row and closest to the SERDES circuitry. Use Common PLL for Transmitter & Receiver Check the Use Common PLLs for Rx and Tx box to place both the LVDS transmitter and receiver in the same I/O bank in Stratix devices. The Quartus II software also allows the transmitter and receiver to share the PLL when the same input clock is used for both. Although you must Altera Corporation July 2005 5–69 Stratix Device Handbook, Volume 2 Software Support separate the transmitter and receiver in your design, the Quartus II software merges the fast PLLs when appropriate and gives you the following message: Receiver fast PLL and transmitter fast PLL are merged together The Quartus II software gives the following message when it cannot merge the fast PLLs for the LVDS transmitter and receiver pair in the design: Can't merge transmitter-only fast PLL and receiver-only fast PLL tx_outclock Resource You can use either the global or regional clock for the tx_outclock signal. If you select Auto in the Quartus II software, the tool uses any available lines. SERDES Bypass Mode You can bypass the SERDES block if your data rate is less than 624 Mbps, and you must bypass the SERDES block for the ×1 and ×2 LVDS modules. Since you cannot route the fast PLL output to an output pin, you must create additional DDR I/O circuitry for the transmitter clock output. To create an ×J transmitter output clock, instantiate an alt_ddio megafunction clocked by the ×J clock with datain_h connected to VCC and datain_l connected to GND. ×1 Mode For ×1 mode, you only need to specify the I/O standard of the pins to tell the Quartus II software that you are using differential signaling. However, Altera recommends using the DDRIO circuitry when the input or output data rate is higher than 231 Mbps. The maximum output clock frequency for ×1 mode is 420 MHz. ×2 Mode You must use the DDRIO circuitry for ×2 mode. The Quartus II software provides the altddio_in and altddio_out megafunctions to use for ×2 receiver and ×2 transmitter, respectively. The maximum data rate in ×2 mode is 624 Mbps. Figure 5–44 shows the schematic for using DDR circuitry in ×2 mode. 5–70 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–44. LVDS x2 Mode Schematic Using DDR I/O Circuitry DDIO In RXp RXn datain[0] inclock DDIO Out dataout_h[0] dataout_l[0] datain_h[0] dataout[0] TXp TXn datain_l[0] Custom Logic outclock DDIO Out RX_PLL rx_inclk inclock /1 clock1 VCC datain_h[0] /2 clock0 GND datain_l[0] dataout[0] tx_outclk outclock The transmitter output clock requires extra DDR output circuitry that has the input high and input low connected to VCC and GND respectively. The output clock frequency is the same as the input frequency of the DDR output circuitry. Other Modes For other modes, you can still to use the DDR circuitry for better frequency performance. You can use either the LEs or the M512 RAM block for the deserialization. M512 RAM Block as Serializer/Deserializer Interface In addition to using the DDR circuitry and the M512 RAM block, you need two extra counters per memory block to provide the address for the memory: a fast counter powering up at 0 and a slow counter powering up at 2. The M512 RAM block is configured as a simple dual-port memory block, where the read enable and the write enable signals are always tied high. Figures 5–45 and 5–46 show the block diagram for the SERDES bypass receiver and SERDES bypass transmitter, respectively. Altera Corporation July 2005 5–71 Stratix Device Handbook, Volume 2 Software Support Figure 5–45. SERDES Bypass LVDS Receiver Using M512 RAM Block as the Deserializer waddr[7..5] Simple Dual Port RX_SESB 512 Bits DDIO In RXp datain[0] RXn inclock dataout_h[0] datain[1..0] dataout_l[0] waddr[7..0] dataout[7..0] Core data wclock clock q[4..0] raddr[5..0] rclock W-UpCounter RX_PLL rx_inclk inclock ÷1 clock1 ÷2 clock0 clock raddr[5..3] q[2..0] R-UpCounter Core clock Figure 5–46. SERDES Bypass LVDS Transmitter Using M512 RAM Block as Deserializer waddr[7..5] Simple Dual Port ×2×8 TX_SESB 512 Bits core_data datain[7..0] clock q[2..0] DDIO Out dataout[7..0] datain_h[0] dataout_h[0] waddr[5..0] datain_l[0] dataout_l[0] wclock outclock TXp TXn raddr[7..0] rclock W-UpCounter RX_PLL core_clk inclock ÷1 clock1 ×2 clock0 clock q[5..0] R-UpCounter raddr[5..3] RX_PLL VCC datain_h[0] /1 clock1 GND datain_l[0] /2 clock0 tx_outclk outclock 5–72 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices For the transmitter, the read counter is the fast counter and the write counter is the slow counter. For the receiver, the write counter is the fast counter and the read counter is the slow counter. Tables 5–18 and 5–19 provide the address counter configurations for the transmitter and the receiver, respectively. Table 5–18. Address Counters for SERDES Bypass LVDS Receiver M512 Mode Deserialization Factor Write Up-Counter (Fast Counter) Read Up-Counter (Slow Counter) Width Starts at Width Starts at Write Read Invalid Initial Cycles ×2×4 4 4 0 3 2 12 6 ×2×8 8 5 0 3 2 24 6 ×4×16 8 5 0 3 2 24 6 ×2×16 16 6 0 3 2 48 6 Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter M512 Mode Deserialization Factor Write Up-Counter (Fast Counter) Read Up-Counter (Slow Counter) Width Starts at Width Starts at Write Read Invalid Initial Cycles ×2×4 4 4 0 3 2 2 4 ×2×8 8 5 0 3 2 2 8 ×4×16 8 5 0 3 2 2 8 ×2×16 16 6 0 3 2 2 16 In different M512 memory configurations, the counter width is smaller than the address width, so you must ground some of the most significant address bits. Table 5–20 summarizes the address width, the counter width, and the number of bits to be grounded. Table 5–20. Address & Counter Width M512 Mode Number of Grounded Bits Write Counter Read Counter Write Address Read Address Width Width Width Width Write Address Read Address ×2×4 4 3 8 7 4 4 ×2×8 5 3 8 6 3 3 ×4×16 6 3 7 5 1 2 ×2×16 5 3 8 5 3 2 Altera Corporation July 2005 5–73 Stratix Device Handbook, Volume 2 Software Support Logic Array as Serializer/Deserializer Interface The design can use the lpm_shift_reg megafunction instead of a simple dual port memory block to serialize/deserialize data. The receiver requires an extra flip-flop clocked by the slow clock to latch on to the deserialized data. The transmitter requires a counter to generate the enable signal for the shift register to indicate the times to load and serialize the data. Figures 5–47 and 5–48 show the schematic of the ×8 LVDS receiver and ×8 LVDS transmitter, respectively, with the logic array performing the deserialization. This scheme can also be used for APEX II and Mercury device flexible LVDS solutions. Figure 5–47. SERDES Bypass LVDS Receiver with Logic Array as Deserializer clock Shift Register Serial data in ×4 clock0 Clock PLL data_h data data[1, 3, 5, 7] data[7..0] D DDR Input DFF[7..0] Q Data to logic array ÷2 clock1 data_l data data[0, 2, 4, 6] Shift Register CLK clock rx_clk 5–74 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 High-Speed Differential I/O Interfaces in Stratix Devices Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer Counter Shift Register clock load data Data[7..0] data_l ×4 clock Clock PLL ×1 clock DDR Output Shift Register data Serial data out data_h load clock tx_clk Summary Altera Corporation July 2005 The Stratix device family of flexible, high-performance, high-density PLDs delivers the performance and bandwidth necessary for complex system-on-a-programmable-chip (SOPC) solutions. Stratix devices support multiple I/O protocols to interface with other devices within the system. Stratix devices can easily implement processing-intensive datapath functions that are received and transmitted at high speeds. The Stratix family of devices combines a high-performance enhanced PLD architecture with dedicated I/O circuitry in order to provide I/O standard performances of up to 840 Mbps. 5–75 Stratix Device Handbook, Volume 2 Summary 5–76 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 Section IV. Digital Signal Processing (DSP) This section provides information for design and optimization of digital signal processing (DSP) functions and arithmetic operations in the onchip DSP blocks. It contains the following chapters: Revision History ■ Chapter 6, DSP Blocks in Stratix & Stratix GX Devices ■ Chapter 7, Implementing High Performance DSP Functions in Stratix & Stratix GX Devices The table below shows the revision history for Chapters 6 and 7. Chapter Date/Version 6 July 2005, v2.2 ● Changed Stratix GX FPGA Family data sheet reference to Stratix GX Device Handbook, Volume 1. Changes Made September 2004, v2.1 ● Updated “Software Support” on page 6–28. Deleted “Quartus II DSP Megafunctions” section. It was replaced by the updated “Software Support” on page 6–28 Replaced references to AN 193 and AN 194 with a new reference on page 6–28. ● ● 7 July 2003, v2.0 ● Minor content change. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. September 2004, v1.1 ● Corrected spelling error. April 2003, v1.0 ● No new changes in Stratix Device Handbook v2.0. Altera Corporation Section IV–1 Digital Signal Processing (DSP) Section IV–2 Stratix Device Handbook, Volume 2 Altera Corporation 6. DSP Blocks in Stratix & Stratix GX Devices S52006-2.2 Introduction Traditionally, designers had to make a trade-off between the flexibility of off-the-shelf digital signal processors and the performance of custombuilt devices. Altera® Stratix® and Stratix GX devices eliminate the need for this trade-off by providing exceptional performance combined with the flexibility of programmable logic devices (PLDs). Stratix and Stratix GX devices have dedicated digital signal processing (DSP) blocks, which have high-speed parallel processing capabilities, that are optimized for DSP applications. DSP blocks are ideal for implementing DSP applications that need high data throughput. The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions, and correlators. These functions are the building blocks for more complex systems such as wideband code division multiple access (W-CDMA) basestations, voice over Internet protocol (VoIP), and highdefinition television (HDTV). Although these functions are complex, they all use similar building blocks such as multiply-adders and multiply-accumulators. Stratix and Stratix GX DSP blocks combine five arithmetic operations— multiplication, addition, subtraction, accumulation, and summation—to meet the requirements of complex functions and to provide improved performance. This chapter describes the Stratix and Stratix GX DSP blocks, and explains how you can use them to implement high-performance DSP functions. It addresses the following topics: ■ ■ ■ f Altera Corporation July 2005 Architecture Operational Modes Software Support See the Stratix Device Family Data Sheet section of the Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 for more information on Stratix and Stratix GX devices, respectively. 6–1 DSP Block Overview DSP Block Overview Each Stratix and Stratix GX device has two columns of DSP blocks that efficiently implement multiplication, multiply accumulate (MAC), and filtering functions. Figure 6–1 shows one of the columns with surrounding LAB rows. You can configure each DSP block to support: ■ ■ ■ Eight 9 × 9 bit multipliers Four 18 × 18 bit multipliers One 36 × 36 bit multiplier Figure 6–1. DSP Blocks Arranged in Columns DSP Block Column 8 LAB Rows DSP Block The multipliers can then feed an adder or an accumulator block, depending on the DSP block operational mode. Additionally, you can use the DSP block input registers as shift registers to implement applications such as FIR filters efficiently. The number of DSP blocks per column 6–2 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices increases with device density. Tables 6–1 and 6–2 describe the number of DSP blocks in each Stratix and Stratix GX device, respectively, and the multipliers that you can implement. Table 6–1. Number of DSP Blocks in Stratix Devices Note (1) Device DSP Blocks 9 × 9 Multipliers 18 × 18 Multipliers 36 × 36 Multipliers EP1S10 6 48 24 6 EP1S20 10 80 40 10 EP1S25 10 80 40 10 EP1S30 12 96 48 12 EP1S40 14 112 56 14 EP1S60 18 144 72 18 EP1S80 22 176 88 22 Table 6–2. Number of DSP Blocks in Stratix GX Devices Note (1) Device DSP Blocks 9 × 9 Multipliers EP1SGX10C 6 48 18 × 18 Multipliers 36 × 36 Multipliers 24 6 EP1SGX10D 6 48 24 6 EP1SGX25C 10 80 40 10 EP1SGX25D 10 80 40 10 EP1SGX25F 10 80 40 10 EP1SGX40D 14 112 56 14 EP1SGX40G 14 112 56 14 Note to Tables 6–1 and 6–2: (1) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers shown.The total number of multipliers for each device is not the sum of all the multipliers. Altera Corporation July 2005 6–3 Stratix Device Handbook, Volume 2 DSP Block Overview Figure 6–2 shows the DSP block operating as an 18 × 18 multiplier. Figure 6–2. DSP Block in 18 × 18 Mode Optional Serial Shift Register Inputs from Previous DSP Block From the Row Interface Block D PRN Q ENA CLRN D PRN Q Multiplier Block D Adder Output Block Output Register PRN Q ENA CLRN ENA CLRN Adder/ Subtractor/ Accumulator D PRN Q ENA CLRN D PRN Q D PRN Q ENA CLRN Summation Block ENA CLRN Adder D PRN Q ENA CLRN D PRN Q D PRN Q ENA CLRN ENA CLRN Adder/ Subtractor/ Accumulator D PRN Q ENA CLRN D PRN Q Pipeline Register D PRN Q ENA CLRN ENA CLRN 6–4 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Architecture The DSP block consists of the following elements: ■ ■ ■ ■ ■ ■ A multiplier block An adder/subtractor/accumulator block A summation block An output interface Output registers Routing and control signals Multiplier Block Each multiplier block has input registers, a multiplier stage, and a pipeline register. See Figure 6–3. Figure 6–3. Multiplier Block Architecture signa signb aclr[3..0] clock[3..0] ena[3..0] shiftinb shiftina D Data A Q ENA CLRN D Q ENA Data Out to Adder Blocks CLRN D Data B Q ENA CLRN shiftoutb Altera Corporation July 2005 shiftouta 6–5 Stratix Device Handbook, Volume 2 Architecture Input Registers Each operand feeds an input register or the multiplier directly. The DSP block has the following signals (one of each controls every input and output register): ■ ■ ■ clock[3..0] ena[3..0] aclr[3..0] The input registers feed the multiplier and drive two dedicated shift output lines, shiftouta and shiftoutb. The shift outputs from one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block), as shown in Figure 6–4 on page 6–7, to form a shift register chain. This chain can terminate in any block, i.e., you can create any length of shift register chain up to 224 registers. A shift register is useful in DSP applications such as FIR filters. When implementing 9 × 9 and 18 × 18 multipliers, you do not need external logic to create the shift register chain because the input shift registers are internal to the DSP block. This implementation greatly reduces the required LE count and routing resources, and produces repeatable timing. 6–6 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Figure 6–4. Shift Register Chain DSP Block 0 Data A D Q ENA A[n] × B[n] CLRN Data B D Q Q D ENA CLRN ENA CLRN shiftoutb shiftouta D Q ENA A[n - 1] × B[n - 1] CLRN D Q D Q ENA CLRN ENA CLRN shiftoutb shiftouta DSP Block 1 D Q ENA A[n - 2] × B[n - 2] CLRN D Q D Q ENA CLRN ENA CLRN shiftoutb Altera Corporation July 2005 shiftouta 6–7 Stratix Device Handbook, Volume 2 Architecture Multiplier Stage The multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multiplication. (The multiplier stage also support smaller multipliers. See “Operational Modes” on page 6–18 for details.) Based on the data width, a single DSP block can perform many multiplications in parallel. The multiplier operands can be signed or unsigned numbers. Two signals, signa and signb, indicate the representation of the two operands. For example, a logic 1 on the signa signal indicates that data A is a signed number; a logic 0 indicates an unsigned number. The result of the multiplication is signed if any one of the operands is a signed number, as shown in Table 6–3. Table 6–3. Multiplier Signed Representation Data A Data B Result Unsigned Unsigned Unsigned Unsigned Signed Signed Signed Unsigned Signed Signed Signed Signed The signa and signb signals affect the entire DSP block. Therefore, all of the data A inputs feeding the same DSP block must have the same sign representation. Similarly, all of the data B inputs feeding the same DSP block must have the same sign representation. The multiplier offers full precision regardless of the sign representation. 1 By default, the Altera Quartus® II software sets the multiplier to perform unsigned multiplication when the signa and signb signals are not used. Pipeline Registers The output from the multiplier can feed a pipeline register or be bypassed. You can use pipeline registers for any multiplier size; pipelining is useful for increasing the DSP block performance, particularly when using subsequent adder stages. 1 6–8 Stratix Device Handbook, Volume 2 In the DSP block, pipelining improves the performance of 36 × 36 multipliers. For 18 × 18 multipliers and smaller, pipelining adds latency but does not improve performance. Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Adder/Output Block The adder/output block has the following elements (See Figure 6–5 on page 6–10): ■ ■ ■ ■ An adder/subtractor/accumulator block A summation block An output select multiplexer Output registers You can configure the adder/output block as: ■ ■ ■ ■ ■ A pure output interface An accumulator A simple one-level adder A two-level adder with dynamic addition/subtraction control on the first-level adder The final stage of a 36-bit multiplier The output select multiplexer sets the output of the DSP block. You can register the adder/output block’s output using the output registers. 1 Altera Corporation July 2005 You cannot use the adder/output block independently of the multiplier. 6–9 Stratix Device Handbook, Volume 2 Architecture Figure 6–5. Adder/Output Block Accumulator Feedback Output Select Multiplexer accum_sload0 Result A Output Registers overflow0 Adder/ Subtractor/ Accumulator 0 addnsub1 Result B signa Adder signb Result C Adder/ Subtractor/ Accumulator 1 addnsub3 overflow1 Result D Accumulator Feedback accum_sload1 Adder/Subtractor/Accumulator Block The adder/subtractor/accumulator is the first level of the adder/output block. You can configure the block as an accumulator or as an adder/subtractor. Accumulator When the adder/subtractor/accumulator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in Figure 6–5. You can use the 6–10 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices accum_sload[1..0] signals to clear the accumulator asynchronously. This action is not the same as resetting the output registers. You can clear the accumulation and begin a new one without losing any clock cycles. The overflow signal goes high on the positive edge of the clock when the accumulator overflows or underflows. In the next clock cycle, however, the overflow signal resets to zero even though an overflow (or underflow) occurred in the previous clock cycle. Use a latch to preserve the overflow condition indefinitely (until the latch is cleared). Adder/Subtractor The addnsub[1..0] signals select addition or subtraction: high for addition and low for subtraction. You can control the addnsub[1..0] signals using external logic; therefore, the first-level block can switch from an adder to a subtractor dynamically, simply by changing the addnsub[1..0] signals. If the first stage is configured as a subtractor, the output is A - B and C - D. The adder/subtractor also uses two signals, signa and signb, like the multiplier block. These signals indicate the sign representation of both operands together. You can register the signals with a latency of 1 or 2 clock cycles. Summation Block The output from the adder/subtractor feeds to an optional summation block, which is an adder block that sums the outputs of the adder/subtractor. The summation block is important in applications such as FIR filters. Output Select Multiplexer The outputs from the various elements of the adder/output block are routed through an output select multiplexer. Based on the DSP block operational mode, the outputs of the multiplier block, adder/subtractor/accumulator, or summation block feed straight to the output, bypassing the remaining blocks in the DSP block. 1 The output select multiplier configuration is configured automatically by software. Output Registers You can use the output registers to register the DSP block output. Like the input registers, the output registers are controlled by the four clock[3..0], aclr[3..0], and ena[3..0] signals. You can use the output registers in any DSP block operational mode. Altera Corporation July 2005 6–11 Stratix Device Handbook, Volume 2 Architecture 1 The output registers form part of the accumulator in the multiply-accumulate mode. Routing Structure & Control Signals This section describes the interface between the DSP blocks and the row interface blocks. It also describes how the DSP block generates control signals and how the signals route from the row interface to the DSP block. DSP Block Interface The DSP blocks are organized in columns, which provides efficient horizontal communication between the blocks and the column-based memory blocks. The DSP block communicates with other parts of the device through an input and output interface. Each DSP block, including the input and output interface, is 8 logic array blocks (LABs) long. The DSP block and row interface blocks consist of eight blocks that connect to eight adjacent LAB rows on the left and right. Each of the eight blocks has two regions: right and left, one per row. The DSP block receives 144 data input signals and 18 control signals for a total of 162 input signals. This block drives out 144 data output signals; 2 of the data signals can be used as overflow signals (overflow). Figure 6–6 provides an overview of the DSP block and its interface to adjacent LABs. Figure 6–6. DSP Block Interface to Adjacent LABs DSP Block & Row Interface 144 8 LAB 162 Rows Row Interfaces 0 through 7 Data DSP Block 144 8 LAB Rows 18 Control DSP Block Input Interface DSP Block Output Interface Input Interface The DSP block input interface has 162 input signals from adjacent LABs; 18 data signals per row and 18 control signals per block. Output Interface The DSP block output interface drives 144 outputs to adjacent LABs, 18 signals per row from 8 rows. 6–12 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Because the DSP block outputs communicate horizontally, and because each DSP block row has more outputs than an LAB (18 from the DSP block compared to 10 from an LAB), the DSP block has double the number of row channel drivers compared to an LAB. The DSP block has the same number of row channels, but the row channels are staggered as if there were two LABs within each block. The DSP blocks have the same number of column channels as LABs because DSP blocks communicate primarily through row channels. Row Interface Block Each row interface block connects to the DSP block row structure with 21 signals. Because each DSP block has eight row interface blocks, this block receives 162 signals from the eight row interfaces. Of the 162 signals, 144 are data inputs and 18 are control signals. Figure 6–7 on page 6–14 shows one row block within the DSP block. Altera Corporation July 2005 6–13 Stratix Device Handbook, Volume 2 Architecture Figure 6–7. DSP Row Interface Block C4 and C8 Interconnects DirectLink Interconnect from Adjacent LAB R4 and R8 Interconnects Nine DirectLink Outputs to Adjacent LABs DirectLink Interconnect from Adjacent LAB 18 DSP Block Row Structure LAB 10 LAB 9 9 10 3 Control 18 18 [17..0] [17..0] Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row Control Signals in the Row Interface Block The DSP block has a set of input registers, a pipeline register, and an output register. Each register is grouped in banks that share the same clock and clear resources: ■ ■ ■ 1- to 9-bit banks for the input register 1- to 18-bit banks for the pipeline register 18 bits for the output register 6–14 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices The row interface block generates the control signals and routes them to the DSP block. Each DSP block has 18 control signals: ■ ■ ■ ■ ■ ■ Four clock signals (clock[3..0]), which are available to each bank of DSP blocks Four clear signals (aclr[3..0]), which are available to each bank of DSP blocks Four clock enable signals (ena[3..0]), which the whole DSP block can use signa and signb, which are specific to each DSP block addnsub[1..0] signals accum_sload[1..0] signals The signa, signb, and addnsub[1..0], accum_sload[1..0] signals have independent clocks and clears and can be registered individually. When each 18 × 18 multiplier in the DSP block splits in half to two 9 × 9 multipliers, each 9 × 9 multiplier has independent control signals. Figure 6–8 shows the DSP block row interface and shows how it generates the data and control signals. Figure 6–8. DSP Block Row Interface 30 Local Interconnect Signals 21 Signals for Data to Input Register DSP Row LAB Row Clocks Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 DSP Block Row Interface Bit 8 DSP Row 2 DSP Row 1 DSP Row 3 DSP Row Unit Control Block DSP Row Bit 9 Bit 10 3 Detail of 1 DSP Row DSP Row 4 DSP Row 5 Input Registers DSP Block DSP Row 6 DSP Row 7 DSP Row 8 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Altera Corporation July 2005 6–15 Stratix Device Handbook, Volume 2 Architecture The DSP block interface generates the clock signals from LAB row clocks or the local interconnect. The clear signals are generated from the local interconnects within each DSP block row interface or from LAB row clocks. The four clock enable signals are generated from the 30 local interconnects from the same LAB rows that generate the clock signals. The clock enable is paired with the clock because the enable logic is implemented at the interface. Figure 6–9 shows the signal distribution within the row interface block. Figure 6–9. DSP Block Row Interface Signal Distribution aclr[3..0] ena[3..0] data[17..0] 18 4 4 clock[3..0] 4 Input 18 Registers 18-Bit Data Routed from 30 Local Interconnects 18 A1 Four Clock Enable Signals Routed from 30 Local Interconnects 18 × 18 Multiplier Row 1 B1 18 Four Clear Signals Routed from 30 Local Interconnects or LAB Row Clock Four Clock Signals Routed from LAB Row Clock or Local Interconnect 18 Row 2 18 18 A4 18 × 18 Multiplier Row 7 B4 18 18 Row 8 6–16 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Each row block provides 18 bits of data to the multiplier (i.e., one of the operands to the multiplier), which are routed through the 30 local interconnects within each DSP row interface block. Any signal in the device can be the source of the 18-bit multiplier data, by connecting to the local row interconnect through any row or column. Each control signal routes through one of the eight rows of the DSP block. Table 6–4 shows the 18 control signals and the row to which each one routes. Table 6–4. Control Signals in DSP Block Signal Name Row signa 1 signb 6 addnsub1 3 addnsub3 7 accum_sload0 2 accum_sload1 7 Description DSP block-wide signed and unsigned control signals for all multipliers. The multiplier outputs are unsigned only if both signa and signb are low. Controls addition or subtraction of the two one-level adders. The addnsub0 signal controls the top two one-level adders; the addnsub1 signal controls the bottom two one-level adders. A high indicates addition; a low indicates subtraction. Resets the feedback input to the accumulator. The signal asynchronously clears the accumulator and allows new accumulation to begin without losing any clock cycles. The accum_sload0 controls the top two one-level adders, and the accum_sload1 controls the bottom two one-level adders. A low is for normal accumulation operations and a high is for zeroing the accumulator. clock0 3 clock1 4 DSP block-wide clock signals. clock2 5 clock3 6 aclr0 1 aclr1 4 aclr2 5 aclr3 7 ena[3..0] Same rows as the DSP block-wide clock enable signals. Clock Signals DSP block-wide clear signals. Input/Output Data Interface Routing The 30 local interconnects generate the 18 inputs to the row interface blocks. The 21 outputs of the row interface block are the inputs to the DSP row block (see Figure 6–7 on page 6–14). Altera Corporation July 2005 6–17 Stratix Device Handbook, Volume 2 Operational Modes The row interface block has DirectLink™ connections that connect the DSP block input or output signals to the left and right adjacent LABs at each row. (The DirectLink connections provide interconnects between LABs and adjacent blocks.) The DirectLink connection reduces the use of row and column interconnects, providing higher performance and flexibility. Each row interface block receives 10 DirectLink connections from the right adjacent LABs and 10 from the left adjacent LABs. Additionally, the row interface block receives signals from the DSP block, making a total of 30 local interconnects for each row interface block. All of the row and column resources within the DSP block can access this interconnect region (see Figure 6–7 on page 6–14). A DSP block has nine outputs that drive the right adjacent LAB and nine that drive the left adjacent LAB through DirectLink interconnects. All 18 outputs drive any row or column. Operational Modes You can use the DSP block in one of four operational modes, depending on your application needs (see Table 6–4). The Quartus II software has built-in megafunctions that you can use to control the mode. After you have made your parameter settings using the megafunction’s MegaWizard® Plug-In, the Quartus II software automatically configures the DSP block. Table 6–5. DSP Block Operational Modes 9× 9 Mode 18 × 18 36 × 36 Simple multiplier Eight multipliers with eight Four multipliers with four product outputs product outputs One multiplier Multiply accumulator Two 34-bit multiplyaccumulate blocks – Two-multiplier adder Four two-multiplier adders Two two-multiplier adders – Four-multiplier adder Two four-multiplier adders One four-multiplier adder – Two 52-bit multiplyaccumulate blocks Simple Multiplier Mode In simple multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers and for applications such as equalizer coefficient updates that require many individual multiplication operations. 6–18 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices 9- & 18-Bit Multipliers You can configure each DSP block multiplier for 9 or 18 bits. A single DSP block can support up to 8 individual 9-bit or smaller multipliers, or up to 4 individual multipliers with operand widths between 10- and 18-bits. Figure 6–10 shows the simple multiplier mode. Figure 6–10. Simple Multiplier Mode signa Adder Output Block A Q D A ENA CLRN B Q D ENA CLRN Q D ENA CLRN shiftoutb shiftouta signb The multiplier operands can accept signed integers, unsigned integers, or a combination. The signa and signb signals are dynamic and can be registered in the DSP block. Additionally, you can register the multiplier inputs and results independently. Pipelining the result, using the pipeline registers in the block, increases the performance of the DSP block. 36-Bit Multiplier The 36-bit multiplier is a subset of the simple multiplier mode. It uses the entire DSP block to implement one 36 × 36-bit multiplier. The four 18-bit multipliers are fed part of each input, as shown in Figure 6–11 on page 6–21. The adder/output block adds the partial products using the Altera Corporation July 2005 6–19 Stratix Device Handbook, Volume 2 Operational Modes summation block. You can use pipeline registers between the multiplier stage and the summation block. The 36 × 36-bit multiplier supports signed and unsigned operation. The 36-bit multiplier is useful when your application needs more than 18-bit precision, for example, for mantissa multiplication of precision floating-point arithmetic applications. 6–20 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Figure 6–11. 36-Bit Multiplier signa signb A[17..0] D Q ENA CLRN Q D ENA CLRN B[17..0] D Q ENA A CLRN A[35..18] D Q B ENA CLRN D Q ENA Partial Product Summation Block CLRN B[35..18] D D Q ENA Q Data Out CLRN ENA CLRN A[35..18] D Q C ENA CLRN D Q ENA CLRN B[17..0] D D Q ENA CLRN A[17..0] D Q ENA CLRN D Q ENA CLRN B[35..18] D Q ENA CLRN Altera Corporation July 2005 6–21 Stratix Device Handbook, Volume 2 Operational Modes Multiply Accumulator Mode In multiply accumulator mode, the output of the multiplier stage feeds the adder/output block, which is configured as an accumulator or subtractor (see Figure 6–12). You can implement up to two independent 18-bit multiply accumulators in one DSP block. The Quartus II software implements smaller multiplier-accumulators by tying the unused loworder bits of an 18-bit multiplier to ground. Figure 6–12. Multiply Accumulator Mode signa (1) signb (1) aclr clock ena shiftina shiftinb D Data A Q D ENA D Q Q Data Out ENA ENA CLRN Accumulator CLRN CLRN D Data B Q D ENA Q overflow ENA CLRN CLRN shiftoutb addnsub1 signa shiftouta signb accum_sload1 Note to Figure 6–12: (1) The signa and signb signals are the same in the multiplier stage and the adder/output block. The multiply accumulator output can be up to 52 bits wide for a maximum 36-bit result with 16-bits of accumulation. In this mode, the DSP block uses output registers and the accum_sload and overflow signals. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. The DSP block can then begin a new accumulation without losing any clock cycles. The overflow signal indicates an overflow or underflow in the accumulator. This signal is 6–22 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices cleared for the next accumulation cycle, and you can use an external latch to preserve the signal. You can use the addnsub[1..0] signals to perform accumulation or subtraction dynamically. 1 If you want to use DSP blocks and your design only has an accumulator, you can use a multiply by one followed by an accumulator to force the software to implement the logic in the DSP block. Two-Multiplier Adder Mode The two-multiplier adder mode uses the adder/output block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. Additionally, in this mode, the DSP block outputs two sums or differences for multipliers up to 18 bits, or 4 sums or differences for 9-bit or smaller multipliers. A single DSP block can implement one 18 × 18-bit complex multiplier or two 9 × 9-bit complex multipliers. A complex multiplication can be written as: (a + jb) × (c + jd) = (a × c – b × d) + j × (a × d + b × c) In this mode, a single DSP block calculates the real part (a × c – b × d) using one adder/subtractor/accumulator and the imaginary part (a × d + b × c) using another adder/subtractor/accumulator for data up to 18 bits. Figure 6–13 shows an 18-bit complex multiplication. For data widths up to 9 bits, the DSP block can perform two complex multiplications using four one-level adders. Resources outside of the DSP block route each input to the two multiplier inputs. 1 Altera Corporation July 2005 You can only use the adder block if it follows multiplication operations. 6–23 Stratix Device Handbook, Volume 2 Operational Modes Figure 6–13. Complex Multiplier Implemented Using Two-Multiplier Adder Mode 18 DSP Block 18 A 36 18 C 37 A×C-B×D (Real Part) Subtractor 18 B 36 18 D 18 A 36 18 D 37 Adder 18 B A×D+B×C (Imaginary Part) 36 18 C Four-Multiplier Adder Mode In the four-multiplier adder mode, which you can use for 1-dimensional and 2-dimensional filtering applications, the DSP block adds the results of two adder/subtractor/accumulators in a final stage (the summation block). 1 You can only use the adder block if it follows multiplication operations. 9- & 18-Bit Summation Blocks A single DSP block can implement one 18 × 18 or two 9 × 9 summation blocks (see Figure 6–14 on page 6–25). The multiplier product widths must be the same size. 6–24 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Figure 6–14. Four-Multiplier Adder Mode signa signb aclr clock ena shiftina shiftinb D Data A Q ENA CLRN D Q ENA Adder/ Subtractor CLRN D Data B Q ENA CLRN D Data A Q Q D ENA ENA CLRN D Q ENA CLRN D Data B Q addnsub0 signa signb addnsub1 Data Out Adder CLRN ENA CLRN D Data A Q ENA CLRN D Q ENA Adder/ Subtractor CLRN D Data B Q ENA CLRN D Data A Q ENA CLRN Q D ENA CLRN D Data B Q ENA CLRN shiftoutb Altera Corporation July 2005 shiftouta 6–25 Stratix Device Handbook, Volume 2 Operational Modes FIR Filters The four-multiplier adder mode can be used for FIR filter and complex FIR filter applications. The DSP block combines a four-multiplier adder with the input registers configured as shift registers. One set of shift inputs contains the filter data, while the other holds the coefficients, which can be loaded serially or in parallel (see Figure 6–15). The input shift register eliminates the need for shift registers external to the DSP block (e.g., implemented in device logic elements). This architecture simplifies filter design and improves performance because the DSP block implements all of the filter circuitry. 1 Serial shift inputs in 36-bit simple multiplier mode require external registers. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, you can cascade DSP blocks with additional adder stages implemented in logic elements. 6–26 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 DSP Blocks in Stratix & Stratix GX Devices Figure 6–15. Input Shift Registers Configured for a FIR Filter Data A D Q ENA A[n] × B[n] (to adder) CLRN Data B D Q Q D ENA CLRN ENA CLRN Data B Data A D Q ENA A[n - 1] × B[n - 1] (to adder) CLRN D Q D Q ENA CLRN ENA CLRN Data B Data A D Q ENA A[n - 2] × B[n - 2] (to adder) CLRN D Q Q D ENA CLRN ENA CLRN Altera Corporation July 2005 6–27 Stratix Device Handbook, Volume 2 Software Support Software Support Altera provides two distinct methods for implementing various modes of the DSP block in your design: instantiation and inference. Both methods use the following three Quartus II megafunctions: ■ ■ ■ lpm_mult altmult_add altmult_accum You can instantiate the megafunctions in the Quartus II software to use the DSP block. Alternatively, with inference, you can create a HDL design an synthesize it using a third-party synthesis tool like LeonardoSpectrum or Synplify or Quartus II Native Synthesis that infers the appropriate megafunction by recognizing multipliers, multiplier adders, and multiplier accumulators. Using either method, the Quartus II software maps the functionality to the DSP blocks during compilation. Conclusion f See the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device Handbook, Volume 2 for more information on using DSP blocks to implement high-performance DSP functions such as FIR filters, IIR filters, and discreet cosine transforms (DCTs). f See Quartus II On-Line Help for instructions on using the megafunctions and the MegaWizard Plug-In Manager. f For more information on DSP block inference support, see the Recommended HDL Coding Styles chapter of the Quartus II Development Software Handbook v4.1, Volume 1. The Stratix and Stratix GX device DSP blocks are optimized to support DSP applications that need high data throughput, such as FIR filters, FFT functions, and encoders. These DSP blocks are flexible and can be configured in one of four operational modes to suit any application need. The DSP block’s adder/subtractor/accumulator and the summation blocks minimize the amount of logic resources used and provide efficient routing. This efficiency results in improved performance and data throughput for DSP applications. The Quartus II software, together with the LeonardoSpectrum and Synplify software, provides a complete and easy-to-use flow for implementing functionality in the DSP block. 6–28 Stratix Device Handbook, Volume 2 Altera Corporation July 2005 7. Implementing High Performance DSP Functions in Stratix & Stratix GX Devices S52007-1.1 Introduction Digital signal processing (DSP) is a rapidly advancing field. With products increasing in complexity, designers face the challenge of selecting a solution with both flexibility and high performance that can meet fast time-to-market requirements. DSP processors offer flexibility, but they lack real-time performance, while application-specific standard products (ASSPs) and application-specific integrated circuits (ASICs) offer performance, but they are inflexible. Only programmable logic devices (PLDs) offer both flexibility and high performance to meet advanced design challenges. The mathematical theory underlying basic DSP building blocks—such as the finite impulse response (FIR) filter, infinite impulse response (IIR) filter, fast fourier transform (FFT), and direct cosine transform (DCT)—is computationally intensive. Altera® Stratix® and Stratix GX devices feature dedicated DSP blocks optimized for implementing arithmetic operations, such as multiply, multiply-add, and multiply-accumulate. In addition to DSP blocks, Stratix and Stratix GX devices have TriMatrix™ embedded memory blocks that feature various sizes that can be used for data buffering, which is important for most DSP applications. These dedicated hardware features make Stratix and Stratix GX devices an ideal DSP solution. This chapter describes the implementation of high performance DSP functions, including filters, transforms, and arithmetic functions, using Stratix and Stratix GX DSP blocks. The following topics are discussed: ■ ■ ■ ■ ■ Stratix & Stratix GX DSP Block Overview Altera Corporation September 2004 FIR filters IIR filters Matrix manipulation Discrete Cosine Transform Arithmetic functions Stratix and Stratix GX devices feature DSP blocks that can efficiently implement DSP functions, including multiply, multiply-add, and multiply-accumulate. The DSP blocks also have three built-in registers sets: the input registers, the pipeline registers at the multiplier output, and the output registers. Figure 7–1 shows the DSP block operating in the 18 × 18-bit mode. 7–1 Stratix & Stratix GX DSP Block Overview Figure 7–1. DSP Block Diagram for 18 x 18-bit Mode Optional Serial Shift Register Inputs from Previous DSP Block Multiplier Stage D Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor Q ENA CLRN D D ENA CLRN Q Output Selection Multiplexer Q ENA CLRN Adder/ Subtractor/ Accumulator 1 D Q ENA CLRN D D ENA CLRN Q Q ENA CLRN Summation D Q ENA CLRN D D ENA CLRN Q Q Summation Stage for Adding Four Multipliers Together Optional Output Register Stage ENA CLRN Adder/ Subtractor/ Accumulator 2 D Optional Serial Shift Register Outputs to Next DSP Block in the Column Q ENA CLRN D D ENA CLRN Q ENA CLRN 7–2 Stratix Device Handbook, Volume 2 Q Optional Pipeline Register Stage Optional Input Register Stage with Parallel Input or Shift Register Configuration to MultiTrack Interconnect Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices The DSP blocks are organized into columns enabling efficient horizontal communication with adjacent TriMatrix memory blocks. Tables 7–1 and 7–2 show the DSP block resources in Stratix and Stratix GX devices, respectively. Table 7–1. DSP Block Resources in Stratix Devices DSP Blocks Maximum 9 × 9 Multipliers Maximum 18 × 18 Multipliers EP1S10 6 48 24 6 EP1S20 10 80 40 10 EP1S25 10 80 40 10 EP1S30 12 96 48 12 EP1S40 14 112 56 14 EP1S60 18 144 72 18 EP1S80 22 176 88 22 Device Maximum 36 × 36 Multipliers Table 7–2. DSP Block Resources in Stratix GX Devices DSP Blocks Maximum 9 × 9 Multipliers Maximum 18 × 18 Multipliers Maximum 36 × 36 Multipliers EP1SGX10C 6 48 24 6 EP1SGX10D 6 48 24 6 EP1SGX25C 10 80 40 10 EP1SGX25D 10 80 40 10 EP1SGX25F 10 80 40 10 EP1SGX40D 14 112 56 14 EP1SGX40G 14 112 56 14 Device Altera Corporation September 2004 7–3 Stratix Device Handbook, Volume 2 TriMatrix Memory Overview Each DSP block supports either eight 9 × 9-bit multipliers, four 18-bit multipliers, or one 36 × 36-bit multiplier. These multipliers can feed an adder or an accumulator unit based on the operation mode. Table 7–3 shows the different operation modes for the DSP blocks. Table 7–3. Operation Modes for DSP Blocks Number & Size of Multipliers per DSP Block DSP Block Mode 9 x 9-bit 18 x 18-bit 36 x 36-bit Simple multiplier Eight multipliers with eight product outputs Four multipliers with four product outputs Multiply-accumulate Two multiply and accumulate (34 bit) Two multiply and accumulate (52 bit) Two-multipliers adder 4 two-multipliers adders 2 two-multipliers adders Four-multipliers adder 2 four-multipliers adder 1 four-multipliers adder One multiplier with one product output Implementing multipliers, multiply-adders, and multiply-accumulators in the DSP blocks has a performance advantage over logic cell implementation. Using DSP blocks also reduces logic cell and routing resource consumption. To achieve higher performance, register each stage of the DSP block to allow pipelining. For implementing applications, such as FIR filters, efficiently use the input registers of the DSP block as shift registers. f TriMatrix Memory Overview For more information on DSP blocks, see the DSP Blocks in Stratix & Stratix GX Devices chapter. Stratix and Stratix GX devices feature the TriMatrix memory structure, composed of three sizes of embedded RAM blocks. These include the 512-bit size M512 block, the 4-Kbit size M4K block, and the 512-Kbit size M-RAM block. Each block is configurable to support a wide range of features. Tables 7–4 and 7–5 show the number of memory blocks in each Stratix and Stratix GX device, respectively. Table 7–4. TriMatrix Memory Resources in Stratix Devices (Part 1 of 2) Device M512 M4K M-RAM EP1S10 94 60 1 EP1S20 194 82 2 EP1S25 224 138 2 7–4 Stratix Device Handbook, Volume 2 Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Table 7–4. TriMatrix Memory Resources in Stratix Devices (Part 2 of 2) Device M512 M4K M-RAM EP1S30 295 171 4 EP1S40 384 183 4 EP1S60 574 292 6 EP1S80 767 364 9 Table 7–5. TriMatrix Memory Resources in Stratix GX Devices Device M512 M4K M-RAM EP1SGX10C 94 60 1 EP1SGX10D 94 60 1 EP1SGX25C 224 138 2 EP1SGX25D 224 138 2 EP1SGX25F 224 138 2 EP1SGX40D 384 183 4 EP1SGX40G 384 183 4 Most DSP applications require local data storage for intermediate buffering or for filter storage. The TriMatrix memory blocks enable efficient use of available resources for each application. The M512 and M4K memory blocks can implement shift registers for applications, such as multi-channel filtering, auto-correlation, and crosscorrelation functions. Implementing shift registers in embedded memory blocks reduces logic cell and routing resource consumption. f For more information on TriMatrix memory blocks, see the TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices chapter. DSP Function Overview The following sections describe commonly used DSP functions. Each section illustrates the implementation of a basic DSP building block, including FIR and IIR filters, in Stratix and Stratix GX devices using DSP blocks and TriMatrix memory blocks. Finite Impulse Response (FIR) Filters This section describes the basic theory and implementation of basic FIR filters, time-domain multiplexed (TDM) FIR filters, and interpolation and decimation polyphase FIR filters. An introduction to the complex FIR filter is also presented in this section. Altera Corporation September 2004 7–5 Stratix Device Handbook, Volume 2 Finite Impulse Response (FIR) Filters FIR Filter Background Digital communications systems use FIR filters for a variety of functions, including waveform shaping, anti-aliasing, band selection, decimation/interpolation, and low pass filtering. The basic structure of a FIR filter consists of a series of multiplications followed by an addition. The following equation represents an FIR filter operation: y( n) = x( n) ⊗ h(n ) L–1 y( n) = ∑ x ( n – i )h ( i ) i=0 where: x(n) represents the sequence of input samples h(n) represents the filter coefficients L is the number of filter taps A sample FIR filter with L=8 is shown in Figure 7–2. Figure 7–2. Basic FIR Filter x(n) h(0) h(1) h(2) h(3) h(5) h(4) h(6) h(7) y(n) This example filter in Figure 7–2 uses the input values at eight different time instants to produce an output. Hence, it is an 8-tap filter. Each register provides a unit sample delay. The delayed inputs are multiplied with their respective filter coefficients and added together to produce the output. The width of the output bus depends on the number of taps and the bit width of the input and coefficients. 7–6 Stratix Device Handbook, Volume 2 Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Basic FIR Filter A basic FIR filter is the simplest FIR filter type. As shown in Figure 7–2, a basic FIR filter has a single input channel and a single output channel. Basic FIR Filter Implementation Stratix and Stratix GX devices’ dedicated DSP blocks can implement basic FIR filters. Because these DSP blocks have closely integrated multipliers and adders, filters can be implemented with minimal routing resources and delays. For implementing FIR filters, the DSP blocks are configured in the four-multipliers adder mode. f See the DSP Blocks in Stratix & Stratix GX Devices chapter for more information on the different modes of the DSP blocks. This section describes the implementation of an 18-bit 8-tap FIR filter. Because Stratix and Stratix GX devices support modularity, cascading two 4-tap filters can implement an 8-tap filter. Larger FIR filters can be designed by extending this concept. Users can also increase the number of taps available per DSP block if 18 bits of resolution are not required. For example, by using only 9 bits of resolution for input samples and coefficient values, 8 multipliers are available per DSP block. Therefore, a 9-bit 8-tap filter can be implemented in a single DSP block provided an external adder is implemented in logic cells. The four-multipliers adder mode, shown in Figure 7–3, provides four 18 × 18-bit multipliers and three adders in a single DSP block. Hence, it can implement a 4-tap filter. The data width of the input and the coefficients is 18 bits, which results in a 38-bit output for a 4-tap filter. Altera Corporation September 2004 7–7 Stratix Device Handbook, Volume 2 Finite Impulse Response (FIR) Filters Figure 7–3. Hardware View of a DSP Block in Four-Multipliers Adder Mode Notes (1). (2), (3) shiftout input from previous block shiftout input from previous block CLK2 CLR2 Data from row 18 interface block Coefficients 18 from row interface block CLK1 CLR1 D D Q Multiplier A 36 D Q D Q h(0) Q Data from row interface block 18 x(n) 18 18 D Q x(n-1) 18 37 36 Coefficients from row 18 interface block Multiplier B h(1) D Q 18 38 38 D Data from row interface block 18 D Q Output y(n) x(n-2) 18 Multiplier C 36 Coefficients from row 18 interface block D D Q D Q 37 h(2) Q Data from row interface block 18 Q 18 D Q x(n-3) 18 36 Coefficients from row 18 interface block D Q shiftin input to next block Multiplier D h(3) 18 shiftin input to next block Notes to Figure 7–3: (1) (2) (3) The input registers feed the multiplier blocks. These registers can increase the DSP block performance, but are optional. These registers can also function as shift registers if the dedicated shiftin/shiftout signals are used. The pipeline registers are fed by the multiplier blocks. These registers can increase the DSP block performance, but are optional. The output registers register the DSP block output. These registers can increase the DSP block performance, but are optional. 7–8 Stratix Device Handbook, Volume 2 Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–4. Quartus II Software View of MegaWizard Implementation of a DSP Block in Four-Multipliers Adder Mode Each input register of the DSP block provides a shiftout output that connects to the shiftin input of the adjacent input register of the same DSP block. The registers on the boundaries of a DSP block also connect to the registers of adjacent DSP blocks through the use of shiftin/shiftout connections. These connections create register chains spanning multiple DSP blocks, which makes it easy to increase the length of FIR filters. Figure 7–5 shows two DSP blocks connected to create an 8-tap FIR filter. Filters with more taps can be implemented by connecting DSP blocks in a similar manner, provided sufficient DSP blocks are available in the device. 1 Adding the outputs of the two DSP blocks requires an external adder which can be implemented using logic cells. The input data can be fed directly or by using the shiftout/shiftin chains, which allow a single input to shift down the register chain inside the DSP block. The input to each of the registers has a multiplexer, hence, the data can be fed either from outside the DSP block or the preceding register. This can be selected from the MegaWizard® in the Quartus® II software, as shown in Figure 7–4. The example in Figure 7–5 uses the shiftout/shiftin flip-flop chains where the multiplexers are configured to use these chains. In this example, the flip-flops inside the DSP blocks serve as the taps of the FIR filter. Altera Corporation September 2004 7–9 Stratix Device Handbook, Volume 2 Finite Impulse Response (FIR) Filters When the coefficients are loaded in parallel, they can be fed directly from memory elements or any other muxing scheme. This facilitates the implementation of an adaptive (variable) filter. Further, if the user wants to implement the shift register chains external to the DSP block, this can be done by using the altshift_taps megafunction. In this case, the coefficient and data shifting is done external to the DSP block. The DSP block is only used to implement the multiplications and the additions. Parallel vs. Serial Implementation The fastest implementations are fully parallel, but consume more logic resources than serial implementations. To trade-off performance for logic resources, implement a serial scheme with a specified number of taps. To facilitate this, Altera provides the FIR Compiler core through its MegaCore program. The FIR Compiler is an easy-to-use, fully-integrated graphical user interface (GUI) based FIR filter design software. f For more information on the FIR Compiler MegaCore, visit the Altera web site at www.altera.com and search for “FIR compiler” in the “Intellectual Property” page. It is important to note that the four-multipliers adder mode allows a DSP block to be configured for parallel or serial input. When it is configured for parallel input, as shown in Figure 7–6, the data input and the coefficients can be loaded directly without the need for shiftin/shiftout chains between adjacent registers in the DSP block. When the DSP block is configured for serial input, as shown in Figure 7–5, the shiftin/shiftout chains create a register cascade both within the DSP block and also between adjacent DSP blocks. 7–10 Stratix Device Handbook, Volume 2 Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Figure 7–5. Serial Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks Notes (1), (2), (3) Data input x(n) D Q D Q D Q D Q D Q D Q D Q D Q DSP block 1 Filter coefficients h(0) x x(n-1) h(1) x x(n-2) h(2) x x(n-3) h(3) Filter output y(n) x x(n-4) D Q D Q D Q D Q D Q D Q D Q D Q DSP block 2 h(4) x x(n-5) h(5) x x(n-6) h(6) x x(n-7) h(7) Notes to Figure 7–5: (1) (2) (3) Altera Corporation September 2004 Unused ports grayed out. The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading and should be ignored here. This indexing is retained in this figure for consistency with other figures in this chapter. To increase the DSP block performance, include the pipeline and output registers. See Figure 7–3 on page 7–8 for the details. 7–11 Stratix Device Handbook, Volume 2 Finite Impulse Response (FIR) Filters Figure 7–6. Parallel Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks Notes (1), (2) Data input x(n) D Q D Q D Q D Q D Q D Q D Q D Q DSP block 1 Filter coefficients h(0) x(n-1) h(1) x(n-2) h(2) x(n-3) h(3) Filter output y(n) x(n-4) D Q D Q D Q D Q D Q D Q D Q D Q DSP block 2 h(4) x(n-5) h(5) x(n-6) h(6) x(n-7) h(7) Notes to Figure 7–6: (1) (2) The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading. To increase the DSP block performance, include the input, pipeline, and output registers. See Figure 7–3 on page 7–8 for the details. 7–12 Stratix Device Handbook, Volume 2 Altera Corporation September 2004 Implementing High Performance DSP Functions in Stratix & Stratix GX Devices Basic FIR Filter Implementation Results Table 7–6 shows the results of the serial implementation of an 18-bit 8 tap FIR filter as shown in Figure 7–5 on page 7–11 Table 7–6. Basic FIR Filter Implementation Results Part EP1S10F780 Utilization LCELL: 130/10570 (1%) DSP Block 9-bit elements: 16/48 (33%) Memory bits: 288/920448 (