Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIV5V4-5.9
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
ISO
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Section I. Device Datasheet and Addendum for Stratix IV Devices
Chapter 1. DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Transceiver Datapath PCS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–48
DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–50
TriMatrix Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–51
Configuration and JTAG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52
Temperature Sensing Diode Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–53
Chip-Wide Reset (Dev_CLRn) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61
Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62
Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63
Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–64
Chapter 2. Addendum to the Stratix IV Device Handbook
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
iv
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Contents
September 2014 Altera Corporation
Chapter Revision Dates
The chapters in this document, Stratix IV Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1.
DC and Switching Characteristics for Stratix IV Devices
Revised:
September 2014
Part Number: SIV54001-5.9
Chapter 2.
Addendum to the Stratix IV Device Handbook
Revised:
February 2011
Part Number: SIV54002-1.5
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
vi
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter Revision Dates
September 2014 Altera Corporation
Section I. Device Datasheet and
Addendum for Stratix IV Devices
This section includes the following chapters:
■
Chapter 1, DC and Switching Characteristics for Stratix IV Devices
■
Chapter 2, Addendum to the Stratix IV Device Handbook
Revision History
Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
I–2
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Section I: Device Datasheet and Addendum for Stratix IV Devices
September 2014 Altera Corporation
1. DC and Switching Characteristics for
Stratix IV Devices
September 2014
SIV54001-5.9
SIV54001-5.9
This chapter contains the following sections:
■
“Electrical Characteristics”
■
“Switching Characteristics”
■
“I/O Timing”
■
“Glossary”
Electrical Characteristics
This chapter covers the electrical and switching characteristics for Stratix® IV devices.
Electrical characteristics include operating conditions and power consumption.
Switching characteristics include transceiver specifications, core, and periphery
performance. This chapter also describes I/O timing, including programmable I/O
element (IOE) delay and programmable output buffer delay.
f For information regarding the densities and packages of devices in the Stratix IV
family, refer to the Stratix IV Device Family Overview chapter.
Operating Conditions
When you use Stratix IV devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of the
Stratix IV devices, you must consider the operating requirements described in this
chapter.
Stratix IV devices are offered in commercial, industrial, and military grades.
Commercial devices are offered in –2 (fastest), –2×, –3, and –4 speed grades. Industrial
devices are offered in –1, –2, –3, and –4 speed grades. Military devices are offered in –3
speed grade.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix IV
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014
Feedback Subscribe
1–2
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
c Conditions other than those listed in Table 1–1, Table 1–2, and Table 1–3 may cause
permanent damage to the device. Additionally, device operation at the absolute
maximum ratings for extended periods of time may have adverse effects on the
device.
Table 1–1. Absolute Maximum Ratings for Stratix IV Devices
Symbol
Description
Minimum
Maximum
Unit
VCC
Core voltage and periphery circuitry power supply
-0.5
1.35
V
VCCPT
Power supply for programmable power technology
-0.5
1.8
V
VCCPGM
Configuration pins power supply
-0.5
3.75
V
VCCAUX
Auxiliary supply for the programmable power technology
-0.5
3.75
V
VCCBAT
Battery back-up power supply for design security volatile key register
-0.5
3.75
V
VCCPD
I/O pre-driver power supply
-0.5
3.75
V
VCCIO
I/O power supply
-0.5
3.9
V
VCC_CLKIN
Differential clock input power supply
-0.5
3.75
V
VCCD_PLL
PLL digital power supply
-0.5
1.35
V
VCCA_PLL
PLL analog power supply
-0.5
3.75
V
VI
DC input voltage
-0.5
4.0
V
IOUT
DC output current per pin
-25
40
mA
TJ
Operating junction temperature
-55
125
°C
TSTG
Storage temperature (No bias)
-65
150
°C
Minimum
Maximum
Unit
Table 1–2. Transceiver Power Supply Absolute Maximum Ratings for Stratix IV GX Devices
Symbol
Description
VCCA_L
Transceiver high voltage power (left side)
-0.5
3.75
V
VCCA_R
Transceiver high voltage power (right side)
-0.5
3.75
V
VCCHIP_L
Transceiver HIP digital power (left side)
-0.5
1.35
V
VCCHIP_R
Transceiver HIP digital power (right side)
-0.5
1.35
V
VCCR_L
Receiver power (left side)
-0.5
1.35
V
VCCR_R
Receiver power (right side)
-0.5
1.35
V
VCCT_L
Transmitter power (left side)
-0.5
1.35
V
VCCT_R
Transmitter power (right side)
-0.5
1.35
V
VCCL_GXBLn
(1)
Transceiver clock power (left side)
-0.5
1.35
V
VCCL_GXBRn
(1)
Transceiver clock power (right side)
-0.5
1.35
V
VCCH_GXBLn
(1)
Transmitter output buffer power (left side)
-0.5
1.8
V
VCCH_GXBRn
(1)
Transmitter output buffer power (right side)
-0.5
1.8
V
Note to Table 1–2:
(1) n = 0, 1, 2, or 3.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–3
Table 1–3. Transceiver Power Supply Absolute Maximum Ratings for Stratix IV GT Devices (1)
Symbol
Description
Minimum
Maximum
Unit
VCCA_L
Transceiver high voltage power (left side)
-0.5
3.75
V
VCCA_R
Transceiver high voltage power (right side)
-0.5
3.75
V
VCCHIP_L
Transceiver HIP digital power (left side)
-0.5
1.35
V
VCCHIP_R
Transceiver HIP digital power (right side)
-0.5
1.35
V
VCCR_L
Receiver power (left side)
-0.5
1.35
V
VCCR_R
Receiver power (right side)
-0.5
1.35
V
VCCT_L
Transmitter power (left side)
-0.5
1.35
V
VCCT_R
Transmitter power (right side)
-0.5
1.35
V
VCCL_GXBLn
(2)
Transceiver clock power (left side)
-0.5
1.35
V
VCCL_GXBRn
(2)
Transceiver clock power (right side)
-0.5
1.35
V
VCCH_GXBLn
(2)
Transmitter output buffer power (left side)
-0.5
1.8
V
VCCH_GXBRn
(2)
Transmitter output buffer power (right side)
-0.5
1.8
V
Notes to Table 1–3:
(1) For the absolute maximum ratings for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) n = 0, 1, 2, or 3.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–4
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 1–4 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Table 1–4 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% duty cycle. For example, a signal that
overshoots to 4.3 V can only be at 4.3 V for ~5% over the lifetime of the device; for a
device lifetime of 10 years, this amounts to half of a year.
Table 1–4. Maximum Allowed Overshoot During Transitions
Symbol
Vi (AC)
Description
Condition (V)
Overshoot Duration as
% of High Time
Unit
4.0
100.000
%
4.05
79.330
%
4.1
46.270
%
4.15
27.030
%
AC input voltage
4.2
15.800
%
4.25
9.240
%
4.3
5.410
%
4.35
3.160
%
4.4
1.850
%
4.45
1.080
%
4.5
0.630
%
4.55
0.370
%
4.6
0.220
%
Temperature Overshoot Above Maximum Allowed Temperature
The maximum allowed operating temperature for Stratix IV industrial grade devices
is 100 °C. It is recommended that the operating temperature of the device is
maintained below 100 °C at all times. The temperature excursions over 100 °C due to
internal heating of the device should not exceed the number of cycles as specified in
the Table 1–5. Exceeding the recommended number of cycles may cause solder
interconnect failures. Altera® recommends using the Stratix IV military grade devices
if the application requires operating temperatures over 100 °C.
Table 1–5. Temperature Overshoot Above Maximum Allowed Temperature
Description
Device operating
temperature (°C)
September 2014
Altera Corporation
Operating Temperature (°C)
Number of Cycles Over 100 °C
100
3200
105
768
110
640
115
480
120
320
125
160
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–5
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Stratix IV devices. Table 1–6 lists the steady-state voltage and current values expected
from Stratix IV devices. Power supply ramps must all be strictly monotonic, without
plateaus.
f For power supply ripple requirements, refer to the Device-Specific Power Delivery
Network (PDN) Tool User Guide.
Table 1–6. Recommended Operating Conditions for Stratix IV Devices (Part 1 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum
Unit
VCC (Stratix IV GX
and Stratix IV E)
Core voltage and periphery circuitry power
supply
—
0.87
0.90
0.93
V
VCC
(Stratix IV GT)
Core voltage and periphery circuitry power
supply
—
0.92
0.95
0.98
V
VCCPT
Power supply for programmable power
technology
—
1.45
1.5
1.55
V
VCCAUX
Auxiliary supply for the programmable
power technology
—
2.375
2.5
2.625
V
I/O pre-driver (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O pre-driver (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O buffers (2.5 V) power supply
—
2.375
2.5
2.625
V
VCCPD
(2)
I/O buffers (1.8 V) power supply
—
1.71
1.8
1.89
V
I/O buffers (1.5 V) power supply
—
1.425
1.5
1.575
V
I/O buffers (1.2 V) power supply
—
1.14
1.2
1.26
V
Configuration pins (3.0 V) power supply
—
2.85
3.0
3.15
V
Configuration pins (2.5 V) power supply
—
2.375
2.5
2.625
V
Configuration pins (1.8 V) power supply
—
1.71
1.8
1.89
V
VCCA_PLL
PLL analog voltage regulator power supply
—
2.375
2.5
2.625
V
VCCD_PLL
(Stratix IV GX
and Stratix IV E)
PLL digital voltage regulator power supply
—
0.87
0.90
0.93
V
VCCD_PLL
(Stratix IV GT)
PLL digital voltage regulator power supply
—
0.92
0.95
0.98
V
VCC_CLKIN
Differential clock input power supply
—
2.375
2.5
2.625
V
Battery back-up power supply (For design
security volatile key register)
—
1.2
—
3.3
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
Output voltage
VCCIO
VCCPGM
VCCBAT
(1)
TJ (Stratix IV GX
and Stratix IV E)
TJ (Stratix IV GT)
September 2014
Operating junction temperature
Operating junction temperature
Altera Corporation
—
0
—
VCCIO
V
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
Military
–55
—
125
°C
Industrial
0
—
100
°C
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–6
Table 1–6. Recommended Operating Conditions for Stratix IV Devices (Part 2 of 2)
Symbol
Description
tRAMP
Power supply ramp time
Condition
Minimum
Typical
Maximum
Unit
Normal POR
(PORSEL=0)
0.05
—
100
ms
Fast POR
(PORSEL=1)
0.05
—
4
ms
Notes to Table 1–6:
(1) If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
(2) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
Table 1–7 lists the transceiver power supply recommended operating conditions for
Stratix IV GX devices.
Table 1–7. Transceiver Power Supply Operating Conditions for Stratix IV GX Devices
Symbol
Description
(1)
Minimum
Typical
Maximum
Unit
2.85/2.375
3.0/2.5 (2)
3.15/2.625
V
VCCA_L
Transceiver high voltage power (left side)
VCCA_R
Transceiver high voltage power (right side)
VCCHIP_L
Transceiver HIP digital power (left side)
0.87
0.9
0.93
V
VCCHIP_R
Transceiver HIP digital power (right side)
0.87
0.9
0.93
V
VCCR_L
Receiver power (left side)
1.045
1.1
1.155
V
VCCR_R
Receiver power (right side)
1.045
1.1
1.155
V
VCCT_L
Transmitter power (left side)
1.045
1.1
1.155
V
VCCT_R
Transmitter power (right side)
1.045
1.1
1.155
V
VCCL_GXBLn
(3)
Transceiver clock power (left side)
1.05
1.1
1.15
V
VCCL_GXBRn
(3)
Transceiver clock power (right side)
1.05
1.1
1.15
V
VCCH_GXBLn
(3)
Transmitter output buffer power (left side)
VCCH_GXBRn
(3)
Transmitter output buffer power (right side)
1.33/1.425
1.4/1.5 (4)
1.47/1.575
V
Notes to Table 1–7:
(1) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(2) VCCA_L/R must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR),
or both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect VCCA_L/R to either 3.0 V or 2.5 V.
(3) n = 0, 1, 2, or 3.
(4) VCCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can
connect VCCH_GXBL/R to either 1.4 V or 1.5 V.
Table 1–8 lists the recommended operating conditions for the Stratix IV GT
transceiver power supply.
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 1 of 2) (1),
Symbol
Description
(2)
Minimum
Typical
Maximum
Unit
VCCA_L
Transceiver high voltage power (left side)
3.17
3.3
3.43
V
VCCA_R
Transceiver high voltage power (right side)
3.17
3.3
3.43
V
VCCHIP_L
Transceiver HIP digital power (left side)
0.92
0.95
0.98
V
VCCHIP_R
Transceiver HIP digital power (right side)
0.92
0.95
0.98
V
VCCR_L
Receiver power (left side)
1.15
1.2
1.25
V
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–7
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2) (1),
Symbol
Description
(2)
Minimum
Typical
Maximum
Unit
VCCR_R
Receiver power (right side)
1.15
1.2
1.25
V
VCCT_L
Transmitter power (left side)
1.15
1.2
1.25
V
VCCT_R
Transmitter power (right side)
1.15
1.2
1.25
V
VCCL_GXBLn
(3)
Transceiver clock power (left side)
1.15
1.2
1.25
V
VCCL_GXBRn
(3)
Transceiver clock power (right side)
1.15
1.2
1.25
V
VCCH_GXBLn
(3)
Transmitter output buffer power (left side)
1.33
1.4
1.47
V
VCCH_GXBRn
(3)
Transmitter output buffer power (right side)
1.33
1.4
1.47
V
Notes to Table 1–8:
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(3) n = 0, 1, 2, or 3.
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
I/O Pin Leakage Current
Table 1–9 lists the Stratix IV I/O pin leakage current specifications.
Table 1–9. I/O Pin Leakage Current for Stratix IV Devices
Symbol
Description
Conditions
(1)
Min
Typ
Max
Unit
II
Input pin
VI = 0V to VCCIOMAX
-20
—
20
µA
IOZ
Tri-stated I/O pin
VO = 0V to VCCIOMAX
-20
—
20
µA
Note to Table 1–9:
(1) VREF current refers to the input pin leakage current.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–8
Bus Hold Specifications
Table 1–10 lists the Stratix IV device family bus hold specifications.
Table 1–10. Bus Hold Parameters
VCCIO
Parameter Symbol
1.2 V
Conditions
1.5 V
1.8 V
2.5 V
3.0 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
22.5
—
25.0
—
30.0
—
50.0
—
70.0
—
µA
-22.5
—
-25.0
—
-30.0
—
-50.0
—
-70.0
—
µA
Low
sustaining
current
ISUSL
High
sustaining
current
ISUSH
Low
overdrive
current
IODL
0V < VIN <
VCCIO
—
120
—
160
—
200
—
300
—
500
µA
High
overdrive
current
IODH
0V < VIN <
VCCIO
—
-120
—
-160
—
-200
—
-300
—
-500
µA
Bus-hold
trip point
VTRIP
—
0.45
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
2.00
V
VIN > VIL
(maximum)
VIN < VIH
(minimum)
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 1–11 lists the Stratix IV OCT
termination calibration accuracy specifications.
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 1 of 2)
(1)
Calibration Accuracy
Symbol
25- RS
Description
(2)
3.0, 2.5, 1.8, 1.5, 1.2
50- RS
3.0, 2.5, 1.8, 1.5, 1.2
50- RT
2.5, 1.8, 1.5, 1.2
20- , 40- , and
60- RS (3)
3.0, 2.5, 1.8, 1.5, 1.2
September 2014
Conditions
Unit
C2
C3,I3, M3
C4,I4
Internal series termination
with calibration (25-
setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
±8
±8
±8
%
Internal series termination
with calibration (50-
setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
±8
±8
±8
%
Internal parallel termination
with calibration (50-
setting)
VCCIO = 2.5, 1.8, 1.5,
1.2 V
± 10
± 10
± 10
%
Expanded range for internal
series termination with
calibration (20- , 40- and
60- RS setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
± 10
± 10
± 10
%
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–9
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 2 of 2)
(1)
Calibration Accuracy
Symbol
Description
25- RS_left_shift
3.0, 2.5, 1.8, 1.5, 1.2
Internal left shift series
termination with calibration
(25- RS_left_shift setting)
Conditions
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
Unit
C2
C3,I3, M3
C4,I4
± 10
± 10
± 10
%
Notes to Table 1–11:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25- RS is not supported for 1.5 V and 1.2 V in Row I/O.
(3) 20- RS is not supported for 1.5 V and 1.2 V in Row I/O.
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change. Table 1–12 lists the Stratix IV OCT
without calibration resistance tolerance to PVT changes.
Table 1–12. OCT Without Calibration Resistance Tolerance Specifications for Stratix IV Devices
Resistance Tolerance
Symbol
25- RS
3.0 and 2.5
25- RS
1.8 and 1.5
25- RS
1.2
50- RS
3.0 and 2.5
50- RS
1.8 and 1.5
50- RS
1.2
100- RD
2.5
September 2014
Description
Conditions
Unit
C2
C3,I3, M3
C4,I4
Internal series termination
without calibration (25-
setting)
VCCIO = 3.0 and 2.5 V
± 30
± 40
± 40
%
Internal series termination
without calibration (25-
setting)
VCCIO = 1.8 and 1.5 V
± 30
± 40
± 40
%
Internal series termination
without calibration (25-
setting)
VCCIO = 1.2 V
± 35
± 50
± 50
%
Internal series termination
without calibration (50-
setting)
VCCIO = 3.0 and 2.5 V
± 30
± 40
± 40
%
Internal series termination
without calibration (50-
setting)
VCCIO = 1.8 and 1.5 V
± 30
± 40
± 40
%
Internal series termination
without calibration (50-
setting)
VCCIO = 1.2 V
± 35
± 50
± 50
%
Internal differential
termination (100- setting)
VCCIO = 2.5 V
± 25
± 25
± 25
%
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–10
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–13 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 1–13 to determine the OCT variation after power-up calibration
and Equation 1–1 to determine the OCT variation without re-calibration.
Equation 1–1. OCT Variation Without Re-Calibration (1),
(2), (3), (4), (5), (6)
dR
dR
R OCT = R SCAL 1 + ------- T ------- V
dT
dV
Notes to Equation 1–1:
(1) The ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 1–13 lists the OCT variation after the power-up calibration.
Table 1–13. OCT Variation after Power-Up Calibration
Symbol
dR/dV
dR/dT
Description
(1)
VCCIO (V)
Typical
3.0
0.0297
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
3.0
0.189
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
OCT variation with voltage without
re-calibration
OCT variation with temperature
without re-calibration
Unit
%/mV
%/°C
Note to Table 1–13:
(1) Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
Pin Capacitance
Table 1–14 lists the Stratix IV device family pin capacitance.
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 1 of 2)
Symbol
Description
Value
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
4
pF
CIOLR
Input capacitance on the left and right I/O pins
4
pF
CCLKTB
Input capacitance on the top and bottom non-dedicated clock input pins
4
pF
CCLKLR
Input capacitance on the left and right non-dedicated clock input pins
4
pF
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–11
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Value
Unit
COUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
CCLK1, CCLK3, CCLK8,
and CCLK10
Input capacitance for dedicated clock input pins
2
pF
Hot Socketing
Table 1–15 lists the hot socketing specifications for Stratix IV devices.
Table 1–15. Hot Socketing Specifications for Stratix IV Devices
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300 A
IIOPIN (AC)
AC current per I/O pin
8 mA
IXCVR-TX (DC)
DC current per transceiver TX pin
100 mA
IXCVR-RX (DC)
DC current per transceiver RX pin
50 mA
(1)
Note to Table 1–15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Internal Weak Pull-Up Resistor
Table 1–16 lists the weak pull-up resistor values for Stratix IV devices.
Table 1–16. Internal Weak Pull-Up Resistor for Stratix IV Devices
Symbol
RPU
Description
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if the programmable pull-up resistor
option is enabled.
(1), (3)
Conditions (V)
Value
(4)
Unit
VCCIO = 3.0 ±5%
(2)
25
k
VCCIO = 2.5 ±5%
(2)
25
k
VCCIO = 1.8 ±5%
(2)
25
k
VCCIO = 1.5 ±5%
(2)
25
k
VCCIO = 1.2 ±5%
(2)
25
k
Notes to Table 1–16:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(4) These specifications are valid with ±10% tolerances to cover changes over PVT.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–12
I/O Standard Specifications
Table 1–17 through Table 1–22 list the input voltage (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Stratix IV devices. These tables also show the Stratix IV
device family I/O standard specifications. VOL and VOH values are valid at the
corresponding IOH and IOL, respectively.
For an explanation of terms used in Table 1–17 through Table 1–22, refer to “Glossary”
on page 1–64.
Table 1–17. Single-Ended I/O Standards
I/O
Standard
VCCIO (V)
Min
VIL (V)
Typ
Max
Min
VIH (V)
Max
Min
VOL (V)
VOH (V)
Max
Min
Max
IOL
(mA)
IOH
(mA)
LVTTL
2.85
3
3.15
-0.3
0.8
1.7
3.6
0.4
2.4
2
-2
LVCMOS
2.85
3
3.15
-0.3
0.8
1.7
3.6
0.2
VCCIO - 0.2
0.1
-0.1
2.5 V
2.375
2.5
2.625
-0.3
0.7
1.7
3.6
0.4
2
1
-1
1.8 V
1.71
1.8
1.89
-0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.45
VCCIO 0.45
2
-2
1.5 V
1.425
1.5
1.575
-0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
-2
1.2 V
1.14
1.2
1.26
-0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
-2
3.0-V PCI
2.85
3
3.15
—
0.3 *
VCCIO
0.5 *
VCCIO
3.6
0.1 *
VCCIO
0.9 * VCCIO
1.5
-0.5
3.0-V
PCI-X
2.85
3
3.15
—
0.35 *
VCCIO
0.5 *
VCCIO
—
0.1 *
VCCIO
0.9 * VCCIO
1.5
-0.5
Table 1–18. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
VCCIO (V)
I/O Standard
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
VREF 0.04
VREF
VREF +
0.04
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF 0.04
VREF
VREF +
0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.47 *
VCCIO
0.5 *
VCCIO
0.53 *
VCCIO
0.47 *
VCCIO
VREF
0.53 *
VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 *
VCCIO
0.5 *
VCCIO
0.53 *
VCCIO
—
VCCIO/2
—
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–13
Table 1–19. Single-Ended SSTL and HSTL I/O Standards Signal Specifications
VIL(DC) (V)
I/O Standard
VIH(DC) (V)
VIL(AC)
(V)
VIH(AC)
(V)
VOL (V)
VOH (V)
Iol (mA)
Ioh (mA)
Min
Max
Min
Max
Max
Min
Max
Min
SSTL-2
Class I
-0.3
VREF 0.15
VREF +
0.15
VCCIO +
0.3
VREF 0.31
VREF +
0.31
VTT 0.57
VTT +
0.57
8.1
-8.1
SSTL-2
Class II
-0.3
VREF 0.15
VREF +
0.15
VCCIO +
0.3
VREF 0.31
VREF +
0.31
VTT 0.76
VTT +
0.76
16.2
-16.2
SSTL-18
Class I
-0.3
VREF 0.125
VREF +
0.125
VCCIO +
0.3
VREF 0.25
VREF +
0.25
VTT 0.475
VTT +
0.475
6.7
-6.7
SSTL-18
Class II
-0.3
VREF 0.125
VREF +
0.125
VCCIO +
0.3
VREF 0.25
VREF +
0.25
0.28
VCCIO 0.28
13.4
-13.4
SSTL-15
Class I
—
VREF 0.1
VREF +
0.1
—
VREF 0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
8
-8
SSTL-15
Class II
—
VREF 0.1
VREF +
0.1
—
VREF 0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
16
-16
HSTL-18
Class I
—
VREF -0.1
VREF +
0.1
—
VREF 0.2
VREF +
0.2
0.4
VCCIO 0.4
8
-8
HSTL-18
Class II
—
VREF 0.1
VREF +
0.1
—
VREF 0.2
VREF +
0.2
0.4
VCCIO 0.4
16
-16
HSTL-15
Class I
—
VREF 0.1
VREF +
0.1
—
VREF 0.2
VREF +
0.2
0.4
VCCIO 0.4
8
-8
HSTL-15
Class II
—
VREF 0.1
VREF +
0.1
—
VREF 0.2
VREF +
0.2
0.4
VCCIO 0.4
16
-16
HSTL-12
Class I
-0.15
VREF 0.08
VREF +
0.08
VCCIO +
0.15
VREF 0.15
VREF +
0.15
0.25*
VCCIO
0.75*
VCCIO
8
-8
HSTL-12
Class II
-0.15
VREF 0.08
VREF +
0.08
VCCIO +
0.15
VREF 0.15
VREF +
0.15
0.25*
VCCIO
0.75*
VCCIO
16
-16
Table 1–20. Differential SSTL I/O Standards
I/O
Standard
VCCIO (V)
VSWING(DC) (V)
Min
Typ
Max
Min
SSTL-2
Class I, II
2.375
2.5
2.625
0.3
SSTL-18
Class I, II
1.71
1.8
1.89
0.25
SSTL-15
Class I, II
1.425
1.5
1.575
0.2
September 2014
Altera Corporation
Max
VX(AC) (V)
Min
VSWING(AC) (V)
VOX(AC) (V)
Typ
Max
Min
Max
Min
Typ
Max
VCCIO + VCCIO/2
0.6
- 0.2
—
VCCIO/2
+ 0.2
0.62
VCCIO
+ 0.6
VCCIO/2
- 0.15
—
VCCIO/2
+ 0.15
VCCIO +
0.6
VCCIO/2
0.175
—
VCCIO/2
+ 0.175
0.5
VCCIO
+ 0.6
VCCIO/2
0.125
—
VCCIO/2
+
0.125
—
—
VCCIO/2
—
0.35
—
—
VCCIO/2
—
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
1–14
Table 1–21. Differential HSTL I/O Standards
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I
1.71
1.8
1.89
0.2
—
0.78
—
1.12
0.78
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.68
—
0.9
0.68
—
0.9
0.4
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
—
0.5*
VCCIO
—
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
0.3
VCCIO
+ 0.48
Table 1–22. Differential I/O Standard Specifications
I/O
Standard
PCML
2.5 V LVDS
(HIO)
VCCIO (V) (3)
Min
Typ
Max
(1), (2)
(Part 1 of 2)
VID (mV)
VICM(DC) (V)
Min Condition Max Min
Condition
VOD (V)
Max
Min
(4)
VOCM (V)
Typ Max
Min
Typ
(4)
Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 1–23 on page 1–16 and Table 1–24 on
page 1–25.
2.375 2.5 2.625 100
VCM =
1.25 V
—
—
0.05
(5)
1.05
(5)
DMAX
700 Mbps
1.8
0.247
—
0.6
1.125 1.25 1.375
DMAX >
1.55 (
0.247
5)
700 Mbps
—
0.6
1.125 1.25 1.375
(5)
—
0.05
DMAX
700 Mbps
1.8
0.247
—
0.6
1
1.25
1.5
—
1.05
DMAX>
700 Mbps
1.55
0.247
—
0.6
1
1.25
1.5
VCM =
1.25 V
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.4
2.375 2.5 2.625 100
VCM =
1.25 V
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.5
Mini-LVDS
(HIO)
2.375 2.5 2.625 200
—
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.4
Mini-LVDS
(VIO)
2.375 2.5 2.625 200
—
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.5
2.375 2.5 2.625 300
—
—
0.6
DMAX
700 Mbps
1.8
—
—
—
—
—
—
2.375 2.5 2.625 300
—
—
DMAX >
700 Mbps
1.6
—
—
—
—
—
—
2.5 V LVDS
(VIO)
2.375 2.5 2.625 100
RSDS
(HIO)
2.375 2.5 2.625 100
RSDS
(VIO)
VCM =
1.25 V
LVPECL (7)
September 2014
Altera Corporation
(6)
1
(6)
(6)
(6)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–22. Differential I/O Standard Specifications
I/O
Standard
BLVDS (8)
VCCIO (V) (3)
Min
Typ
Max
(1), (2)
1–15
(Part 2 of 2)
VID (mV)
VICM(DC) (V)
Min Condition Max Min
2.375 2.5 2.625 100
—
—
—
VOD (V)
(4)
VOCM (V)
(4)
Condition
Max
Min
Typ Max
Min
Typ
Max
—
—
—
—
—
—
—
—
Notes to Table 1–22:
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–16.
(3) Differential clock inputs in column I/O are powered by VCC_CLKIN which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are
powered by VCCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by VCCPD which requires 2.5V.
(4) RL range: 90 RL 110 .
(5) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 1.0 V VIN 1.6 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is zero V VIN 1.85 V.
(6) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 0.85 V VIN 1.75 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is 0.45 V VIN 1.95 V.
(7) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
(8) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interfaces in Supported Altera Device
Families.
Power Consumption
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
1
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix IV core and periphery
blocks for commercial, industrial, and military grade devices.
The final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. There are no designations on finalized
tables.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–16
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1–23 lists the Stratix IV GX transceiver specifications.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min
Typ
Max
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
Typ
Max
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL
Input frequency
from REFCLK input
pins
—
50
—
697
50
—
697
50
—
637.5
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
—
50
—
425
50
—
325
50
—
325
MHz
Absolute VMAX for a
REFCLK pin
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Operational VMAX for
a REFCLK pin
—
—
—
1.5
—
—
1.5
—
—
1.5
V
Absolute VMIN for a
REFCLK pin
—
-0.4
—
—
-0.4
—
—
-0.4
—
—
V
—
—
—
0.2
—
—
0.2
—
—
0.2
UI
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
—
33
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
—
On-chip termination
resistors
—
—
—
—
—
—
—
VICM (AC coupled)
—
VICM (DC coupled)
HCSL I/O
standard for
PCIe reference
clock
Rise/fall time
September 2014
(21)
Altera Corporation
0 to
-0.5%
100
1100 ± 10%
250
—
550
0 to
-0.5%
100
1100 ± 10%
250
—
(4),
LVDS, HCSL
0 to
-0.5%
100
1100 ± 10%
550
250
—
mV
550
mV
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–17
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 2 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
10 Hz
—
—
-50
—
—
-50
—
—
-50
dBc/Hz
100 Hz
—
—
-80
—
—
-80
—
—
-80
dBc/Hz
1 KHz
—
—
-110
—
—
-110
—
—
-110
dBc/Hz
10 KHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
100 KHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
1 MHz
—
—
-130
—
—
-130
—
—
-130
dBc/Hz
10 KHz to
20 MHz
—
—
3
—
—
3
—
—
3
ps
—
—
2000
± 1%
—
—
2000 ±
1%
—
—
2000
± 1%
—
Calibration block
clock frequency
—
10
—
125
10
—
125
10
—
125
MHz
fixedclk clock
frequency
PCIe Receiver
Detect
—
125
—
—
125
—
—
125
—
MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
—
50
2.5/
37.5
—
50
2.5/
37.5
—
50
—
—
—
—
2
—
—
2
—
—
2
ms
—
1
—
—
1
—
—
1
—
—
µs
3750
Mbps
Transmitter REFCLK
Phase Noise
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
REFCLK (3)
RREF
Transceiver Clocks
Delta time between
reconfig_clks
(5)
(5)
(5)
(19)
Transceiver block
minimum
power-down
(gxb_powerdown)
pulse width
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width, non-PMA
Direct) (23)
—
600
—
3750
600
—
3750
600
—
Data rate (Double
width, non-PMA
Direct) (23)
—
1000
—
8500
1000
—
6500
1000
—
—
600
—
3250
600
—
3250
600
—
Data rate (Single
width, PMA Direct)
6375
(22)
Mbps
3250
Mbps
(23)
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–18
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 3 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Data rate (Double
width, PMA
Direct) (23)
—
1000
—
6500
1000
—
6500
1000
—
6375
Mbps
Absolute VMAX for a
receiver pin (6)
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Operational VMAX for
a receiver pin
—
—
—
1.5
—
—
1.5
—
—
1.5
V
Absolute VMIN for a
receiver pin
—
-0.4
—
—
-0.4
—
—
-0.4
—
—
V
Maximum
peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
VICM = 0.82 V
setting
—
—
2.7
—
—
2.7
—
—
2.7
V
VICM =1.1 V
setting (7)
—
—
1.6
—
—
1.6
—
—
1.6
V
100
—
—
100
—
—
165
—
—
mV
165
—
—
165
—
—
165
—
—
mV
Maximum peak-topeak differential
input voltage VID
(diff p-p) after
device configuration
Data Rate =
600 Mbps to
5 Gbps
Minimum
differential eye
opening at receiver
serial input pins (20)
Equalization = 0
DC gain = 0 dB
Data Rate
> 5 Gbps
Equalization = 0
DC gain = 0 dB
VICM
Receiver DC
Coupling Support
Differential on-chip
termination
resistors
September 2014
VICM = 0.82 V
setting
820 ± 10%
820 ± 10%
820 ± 10%
mV
VICM = 1.1 V
setting (7)
1100 ± 10%
1100 ± 10%
1100 ± 10%
mV
—
For more information about receiver DC coupling support, refer to the “DCCoupled Links” section in the Transceiver Architecture in Stratix IV Devices chapter.
85 setting
85 ± 20%
85 ± 20%
85 ± 20%
100 setting
100 ± 20%
100 ± 20%
100 ± 20%
120 setting
120 ± 20%
120 ± 20%
120 ± 20%
150- setting
150 ± 20%
150 ± 20%
150 ± 20%
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–19
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 4 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min
Differential and
common mode
return loss
Typ
Max
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
Serial RapidIO
SR/LR,
Typ
Max
Min
Typ
Unit
Max
Compliant
—
CPRI LV/HV,
OBSAI,
SATA
± 62.5, 100, 125, 200,
Programmable PPM
detector (8)
—
Run length
—
—
—
200
—
—
200
—
—
200
UI
Programmable
equalization (18)
—
—
—
16
—
—
16
—
—
16
dB
—
—
—
75
—
—
75
—
—
75
µs
—
15
—
—
15
—
—
15
—
—
µs
—
—
—
4000
—
—
4000
—
—
4000
ns
—
4000
—
—
4000
—
—
4000
—
—
ns
tLTR
(9)
tLTR_LTD_Manual
tLTD_Manual
tLTD_Auto
(10)
(11)
(12)
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD)
mode
Receiver buffer and
CDR offset
cancellation time
(per channel)
September 2014
ppm
250, 300, 500, 1000
PCIe Gen1
20 - 35
MHz
PCIe Gen2
40 - 65
MHz
(OIF) CEI PHY
at 6.375 Gbps
20 - 35
MHz
XAUI
10 - 18
MHz
Serial RapidIO
1.25 Gbps
10 - 18
MHz
Serial RapidIO
2.5 Gbps
10 - 18
MHz
Serial RapidIO
3.125 Gbps
6 - 10
MHz
GIGE
6 - 10
MHz
SONET OC12
3-6
MHz
SONET OC48
14 - 19
—
Altera Corporation
—
—
1850
0
—
—
MHz
1850
0
—
—
18500
recon
fig_
clk
cycles
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–20
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 5 of 9)
Symbol/
Description
Conditions
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–2 Commercial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
DC Gain Setting
=0
—
0
—
—
0
—
—
0
—
dB
DC Gain Setting
=1
—
3
—
—
3
—
—
3
—
dB
DC Gain Setting
=2
—
6
—
—
6
—
—
6
—
dB
DC Gain Setting
=3
—
9
—
—
9
—
—
9
—
dB
DC Gain Setting
=4
—
12
—
—
12
—
—
12
—
dB
EyeQ Data Rate
—
600
—
3250
600
—
3250
600
—
3250
Mbps
AEQ Data Rate
min VID
(diff p-p)
outer envelope
= 600 mV
8B/10B
encoded data
2500
—
6500
2500
—
6500
—
—
—
Mbps
Decision Feedback
Equalizer (DFE) Data
Rate
min VID
(diff p-p)
outer envelope
= 500 mV
3125
—
6500
3125
—
6500
—
—
—
Mbps
3750
Mbps
Programmable DC
gain
Transmitter
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML
Data rate (Single
width, non-PMA
Direct)
—
Data rate (Double
width, non-PMA
Direct)
—
Data rate (Single
width, PMA Direct)
—
Data rate (Double
width, PMA Direct)
—
(13)
VOCM
0.65 V setting
Differential on-chip
termination
resistors
September 2014
600
—
1000
600
—
1000
—
—
—
3750
8500
3250
6500
650
—
600
—
3750
600
—
1000
—
6500
1000
—
600
—
3250
600
1000
—
6500
—
650
—
6375
(22)
Mbps
—
3250
Mbps
1000
—
6375
Mbps
—
650
—
mV
85 setting
85 ± 15%
85 ± 15%
85 ± 15%
100 setting
100 ± 15%
100 ± 15%
100 ± 15%
120 setting
120 ± 15%
120 ± 15%
120 ± 15%
150- setting
150 ± 15%
150 ± 15%
150 ± 15%
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–21
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 6 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min
Differential and
common mode
return loss
Rise time
(14)
Typ
Max
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
PCIe Gen1 and
Gen2 (TX
VOD=4),
XAUI (TX
VOD=6),
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
Serial RapidIO
SR (VOD=6),
Serial RapidIO
LR (VOD=8),
CPRI LV
(VOD=6),
CPRI HV
(VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
Typ
Max
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Min
Typ
Unit
Max
Compliant
—
—
50
—
200
50
—
200
50
—
200
ps
—
50
—
200
50
—
200
50
—
200
ps
XAUI rise time
—
60
—
130
60
—
130
60
—
130
ps
XAUI fall time
—
60
—
130
60
—
130
60
—
130
ps
Intra-differential pair
skew
—
—
—
15
—
—
15
—
—
15
ps
Intra-transceiver
block transmitter
channel-to-channel
skew
×4 PMA and
PCS bonded
mode Example:
XAUI, PCIe ×4,
Basic ×4
—
—
120
—
—
120
—
—
120
ps
Inter-transceiver
block transmitter
channel-to-channel
skew
×8 PMA and
PCS bonded
mode Example:
PCIe ×8,
Basic ×8
—
—
500
—
—
500
—
—
500
ps
Fall time
(14)
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–22
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 7 of 9)
Symbol/
Description
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode (15)
Conditions
–2 Commercial
Speed Grade
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
—
—
400
—
—
400
—
—
400
ps
N 18 channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
—
—
650
—
—
650
—
—
650
ps
600
—
8500
600
—
6500
600
—
6375
Mbps
CMU0 PLL and CMU1 PLL
Supported Data
Range
—
pll_powerdown
minimum pulse
width
(tpll_powerdown)
—
CMU PLL lock time
from
pll_powerdown
de-assertion
—
September 2014
Altera Corporation
s
1
—
—
100
—
—
100
—
—
100
s
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–23
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 8 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min
-3 dB Bandwidth
Typ
Max
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
Min
Typ
Max
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Min
Typ
Unit
Max
PCIe Gen1
2.5 - 3.5
MHz
PCIe Gen2
6-8
MHz
(OIF) CEI PHY
at 4.976 Gbps
7 - 11
MHz
(OIF) CEI PHY
at 6.375 Gbps
5 - 10
MHz
XAUI
2-4
MHz
Serial RapidIO
1.25 Gbps
3 - 5.5
MHz
Serial RapidIO
2.5 Gbps
3 - 5.5
MHz
Serial RapidIO
3.125 Gbps
2-4
MHz
GIGE
2.5 - 4.5
MHz
SONET OC12
1.5 - 2.5
MHz
SONET OC48
3.5 - 6
MHz
ATX PLL (6G)
Supported Data
Range (16)
-3 dB Bandwidth
/L = 1
4800-5400 and
6000-6500
4800-5400 and
6000-6500
4800-5400 and
6000-6375
Mbps
/L = 2
2400-2700 and
3000-3250
2400-2700 and
3000-3250
2400-2700 and
3000-3187.5
Mbps
/L = 4
1200-1350 and
1500-1625
1200-1350 and
1500-1625
1200-1350 and
1500-1593.75
Mbps
PCIe Gen 2
1.5
1.5
—
MHz
(OIF) CEI PHY
at 6.375 Gbps
3 - 4.5
3 - 4.5
—
MHz
Transceiver-FPGA Fabric Interface
Interface speed
(non-PMA Direct)
Interface speed
(PMA Direct)
September 2014
—
25
—
325
25
—
325
25
—
250
MHz
—
50
—
325
50
—
325
50
—
325
MHz
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–24
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 9 of 9)
Symbol/
Description
Conditions
Min
Digital reset pulse
width
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–2 Commercial
Speed Grade
Typ
—
Max
Min
Typ
Max
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Min
Typ
Unit
Max
Minimum is two parallel clock cycles
—
Notes to Table 1–23:
(1) The –2× speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29,
EP4SGX110FF35, EP4SGX230DF29, EP4SGX110FF35, EP4SGX180DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX180FF35,
EP4SGX290FH29, EP4SGX360FF35, and EPSGX360FH29.
(2) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK
rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(5) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more
information, refer to the Dynamic Reconfiguration in Stratix IV Devices chapter.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS.
(8) The rate matcher supports only up to ± 300 parts per million (ppm).
(9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–2 on page 1–33.
(10) Time for which the CDR must be kept in lock-to-reference (LTR) mode after rx_pll_locked goes high and before rx_locktodata is asserted
in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(12) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(13) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right
PLL Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(14) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(15) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the
link. You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about
clocking requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices
chapter.
(16) The Quartus II software automatically selects the appropriate /L divider depending on the configured data.
(17) The maximum transceiver-FPGA fabric interface speed of 265.625 MHz is allowed only in Basic low-latency PCS mode with a 32-bit interface
width. For more information, refer to the “Basic Double-Width Mode Configurations” section in the Transceiver Architecture in Stratix IV Devices
chapter.
(18) Figure 1–1 shows the AC gain curves for each of the 16 available equalization settings.
(19) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the
delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
(20) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
(21) The rise and fall time transition is specified from 20% to 80%.
(22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These
configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the Transceiver Architecture in Stratix IV Devices chapter.
(23) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–25
Figure 1–1 shows the top-to-bottom AC gain curve for equalization settings 0 to 15.
Figure 1–1. AC Gain Curves for Equalization Settings 0 to 15 (Bottom to Top)
Table 1–24 lists the Stratix IV GT transceiver specifications.
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 1 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
Min
Typ
Max
–2 Industrial Speed
Grade
Min
Typ
Max
–3 Industrial Speed
Grade
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL
(3),
LVDS
Input frequency
from REFCLK input
pins
—
50
—
706.25
50
—
706.25
50
—
706.25
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
—
50
—
425
50
—
425
50
—
425
MHz
Absolute VMAX for a
REFCLK pin
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Operational VMAX for
a REFCLK pin
—
—
—
1.5
—
—
1.5
—
—
1.5
V
Absolute VMIN for a
REFCLK pin
—
-0.3
—
—
-0.3
—
—
-0.3
—
—
V
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–26
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 2 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Rise/fall time
—
—
—
0.2
—
—
0.2
—
—
0.2
UI
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak
differential input
voltage
—
200
—
1200
200
—
1200
200
—
1200
mV
On-chip termination
resistors
—
—
100
—
—
100
—
—
100
—
VICM
—
1200 ± 10%
1200 ± 10%
1200 ± 10%
mV
10 Hz
—
—
-50
—
—
-50
—
—
-50
dBc/Hz
100 Hz
—
—
-80
—
—
-80
—
—
-80
dBc/Hz
1 KHz
—
—
-110
—
—
-110
—
—
-110
dBc/Hz
10 KHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
100 KHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
1 MHz
—
—
-130
—
—
-130
—
—
-130
dBc/Hz
10 KHz to
20 MHz
—
—
3
—
—
3
—
—
3
ps
—
—
—
2000
± 1%
—
2000
± 1%
—
—
2000
± 1%
—
Calibration block
clock frequency
—
10
—
125
10
—
125
10
—
125
MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
—
—
2.5/
37.5
—
50
2.5/
37.5
—
50
MHz
fixedclk clock
frequency
PCIe Receiver
Detect
—
125
—
—
125
—
—
125
—
MHz
—
—
—
2
—
—
2
—
—
2
ms
—
—
1
—
—
1
—
—
1
—
µs
3750
Mbps
Transmitter REFCLK
Phase Noise
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
REFCLK (2)
RREF
Transceiver Clocks
Delta time between
reconfig_clks
(1)
(1)
(1)
(15)
Transceiver block
minimum
(gxb_powerdown)
power-down pulse
width
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width,
non-PMA Direct) (16)
September 2014
—
Altera Corporation
600
—
3750
600
—
3750
600
—
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–27
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 3 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
Min
Typ
Max
Min
Typ
Max
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
10312.5 1000
—
8500
Mbps
Data rate (Double
width,
non-PMA Direct) (16)
—
1000
—
11300
1000
-
Data rate (Single
width,
PMA Direct) (16)
—
600
-
3250
600
-
3250
600
—
3250
Mbps
Data rate (Double
width,
PMA Direct) (16)
—
1000
-
6500
1000
-
6500
1000
—
6500
Mbps
Absolute VMAX for a
receiver pin (4)
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Operational VMAX for
a receiver pin
—
—
—
1.5
—
—
1.5
—
—
1.5
V
Absolute VMIN for a
receiver pin
—
—
-0.4
—
-0.4
—
—
-0.4
—
—
V
Maximum
peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
VICM = 0.82 V
setting
—
—
2.7
—
—
2.7
—
—
2.7
V
VICM = 1.2 V
setting (5)
—
—
1.2
—
—
1.2
—
—
1.2
V
85
—
—
85
—
—
85
—
—
mV
165
—
—
—
—
—
—
—
—
mV
Maximum
peak-to-peak
differential input
voltage VID (diff p-p)
after device
configuration
Minimum
differential eye
opening at the
receiver serial input
pins for data rates
10.3125 Gbps.
Minimum
differential eye
opening at the
receiver serial input
pins for data rates
> 10.3125 Gbps.
VICM
September 2014
Equalization = 0
(6)
DC gain = 0 dB
Equalization = 0
(6)
DC gain = 0 dB
VICM = 0.82 V
setting
820 ± 10%
820 ± 10%
820 ± 10%
mV
VICM = 1.2 V
setting (5)
1200 ± 10%
1200 ± 10%
1200 ± 10%
mV
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–28
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 4 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
Min
Differential on-chip
termination
resistors
Differential and
common mode
return loss
Typ
Max
–2 Industrial Speed
Grade
Min
Typ
Max
–3 Industrial Speed
Grade
Min
Typ
Unit
Max
85 setting
85 ± 20%
85 ± 20%
85 ± 20%
100 setting
100 ± 20%
100 ± 20%
100 ± 20%
120 setting
120 ± 20%
120 ± 20%
120 ± 20%
150- setting
150 ± 20%
150 ± 20%
150 ± 20%
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
Serial RapidIO
SR/LR,
Compliant
—
CPRI LV/HV,
OBSAI,
SATA
± 62.5, 100, 125, 200,
Programmable PPM
detector (7)
—
—
Run length
—
—
—
200
—
—
200
—
—
200
UI
Programmable
equalization
—
—
—
16
—
—
16
—
—
16
dB
—
—
—
75
—
—
75
—
—
75
µs
—
15
—
—
15
—
—
15
—
—
µs
tLTR
(8)
tLTR_LTD_Manual
tLTD_Manual
(9)
(10)
ppm
250, 300, 500, 1000
—
—
—
4000
—
—
4000
—
—
4000
ns
(11)
—
4000
—
—
4000
—
—
4000
—
—
ns
Receiver buffer and
CDR offset
cancellation time
(per channel)
—
—
—
17000
—
—
17000
—
—
17000
reconfig_clk
DC Gain Setting
=0
—
0
—
—
0
—
—
0
—
dB
DC Gain Setting
=1
—
3
—
—
3
—
—
3
—
dB
DC Gain Setting
=2
—
6
—
—
6
—
—
6
—
dB
DC Gain Setting
=3
—
9
—
—
9
—
—
9
—
dB
DC Gain Setting
=4
—
12
—
—
12
—
—
12
—
dB
—
—
—
4.0
—
—
4.0
—
—
4.0
Gbps
tLTD_Auto
Programmable DC
gain
EyeQ Max Data Rate
September 2014
Altera Corporation
cycles
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–29
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 5 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
AEQ Data Rate
min VID
(diff p-p)
outer envelope
= 600 mV
8B/10B
encoded data
2500
—
6500
2500
—
6500
—
—
—
Mbps
Decision Feedback
Equalizer (DFE) Data
Rate
min VID
(diff p-p)
outer envelope
= 600 mV
3125
—
6500
3125
—
6500
—
—
—
Mbps
3750
600
—
3750
Mbps
10312.5 1000
—
8500
Mbps
Transmitter
Supported I/O
Standards
1.4 V PCML
Data rate (Single
width,
non-PMA Direct)
—
600
—
3750
600
—
Data rate (Double
width,
non-PMA Direct)
—
1000
—
11300
1000
—
Data rate (Single
width,
PMA Direct)
—
600
—
3250
600
—
3250
600
—
3250
Mbps
Data rate (Double
width,
PMA Direct) (12)
—
1000
—
6500
1000
—
6500
1000
—
6500
Mbps
0.65 V setting
—
650
—
—
650
—
—
650
—
mV
VOCM
Differential on-chip
termination
resistors
September 2014
85 setting
85 ± 15%
85 ± 15%
85 ± 15%
100 setting
100 ± 15%
100 ± 15%
100 ± 15%
120 setting
120 ± 15%
120 ± 15%
120 ± 15%
150- setting
150 ± 15%
150 ± 15%
150 ± 15%
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–30
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 6 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
Min
Differential and
common mode
return loss
Rise time
(13)
Typ
Max
–2 Industrial Speed
Grade
Min
PCIe Gen1 and
Gen2 (TX
VOD=4),
XAUI
(TX VOD=6),
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
Serial RapidIO
SR (VOD=6),
Serial RapidIO
LR (VOD=8),
CPRI LV
(VOD=6),
CPRI HV
(VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
Typ
Max
–3 Industrial Speed
Grade
Min
Typ
Unit
Max
Compliant
—
—
50
—
200
50
—
200
50
—
200
ps
—
50
—
200
50
—
200
50
—
200
ps
XAUI rise time
—
60
—
130
60
—
130
60
—
130
ps
XAUI fall time
—
60
—
130
60
—
130
60
—
130
ps
Intra-differential
pair skew
—
—
—
15
—
—
15
—
—
15
ps
Intra-transceiver
block transmitter
channel-to-channel
skew
×4 PMA and
PCS bonded
mode Example:
XAUI, PCIe, ×4,
Basic ×4
—
—
120
—
—
120
—
—
120
ps
Inter-transceiver
block transmitter
channel-to-channel
skew
×8 PMA and
PCS bonded
mode Example:
PCIe ×8,
Basic ×8
—
—
500
—
—
500
—
—
500
ps
Fall time
(13)
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–31
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 7 of 8)
Symbol/
Description
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode (14)
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
—
—
400
—
—
400
—
—
400
ps
N 18
channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
—
—
650
—
—
650
—
—
650
ps
CMU PLL0 and CMU PLL1
Supported data
range
—
600
—
11300
600
—
10312.5
600
—
8500
Mbps
CMU PLL lock time
from
pll_powerdown
de-assertion
—
—
—
100
—
—
100
—
—
100
s
ATX PLL (6G)
Supported Data
Range
/L = 1
4800-5400 and
6000-6500
4800-5400 and
6000-6500
4800-5400 and
6000-6500
Mbps
/L = 2
2400-2700 and
3000-3250
2400-2700 and
3000-3250
2400-2700 and
3000-3250
Mbps
/L = 4
1200-1350 and
1500-1625
1200-1350 and
1500-1625
1200-1350 and
1500-1625
Mbps
—
Mbps
ATX PLL (10G)
Supported Data
Range
—
9900
—
11300
9900
—
10312.5
—
25
—
325
25
—
325
25
—
265.625
MHz
—
50
—
325
50
—
325
50
—
325
MHz
Transceiver-FPGA Fabric Interface
Interface speed
(non-PMA Direct)
Interface speed
(PMA Direct)
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–32
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 8 of 8)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
Min
Digital reset pulse
width
—
Typ
Max
–2 Industrial Speed
Grade
Min
Typ
Max
–3 Industrial Speed
Grade
Min
Typ
Unit
Max
Minimum is two parallel clock cycles
—
Notes to Table 1–24:
(1) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk
frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to the
Dynamic Reconfiguration in Stratix IV Devices chapter.
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase
jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) You must use the 1.2-V RXVICM setting if the input serial data standard is LVDS.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive
the minimum eye opening requirement with Receiver Equalization enabled.
(7) The rate matcher supports only up to ± 300 ppm.
(8) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–2 on page 1–33.
(9) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual
mode. Refer to Figure 1–2 on page 1–33.
(10) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right PLL
Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the link.
You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about clocking
requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices chapter.
(15) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta
time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
(16) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–33
Figure 1–2 shows the lock time parameters in manual mode.
1
LTD = Lock-To-Data; LTR = Lock-To-Reference
Figure 1–2. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data
Valid data
r x_dataout
t
t
LTR
LTD_Manual
t LTR_LTD_Manual
Figure 1–3 shows the lock time parameters in automatic mode.
Figure 1–3. Lock Time Parameters for Automatic Mode
CDR status
LTR
LTD
r x_freqlocked
r x_dataout
Invalid
Valid
data
t
September 2014
Altera Corporation
data
LTD_Auto
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–34
Table 1–25 through Table 1–28 lists the typical differential VOD termination settings for
Stratix IV GX and GT devices.
Table 1–25. Typical VOD Setting, TX Term = 85
VOD Setting (mV)
Symbol
VOD differential
peak-to-peak Typical (mV)
0
1
2
3
4
5
6
7
170 ±
20%
340 ±
20%
510 ±
20%
595 ±
20%
680 ±
20%
765 ±
20%
850 ±
20%
1020 ±
20%
6
7
Table 1–26. Typical VOD Setting, TX Term = 100
VOD Setting (mV)
Symbol
VOD differential
peak-to-peak Typical (mV)
0
1
2
3
4
5
200 ±
20%
400 ±
20%
600 ±
20%
700 ±
20%
800 ±
20%
900 ±
20%
1000
1200
± 20% ± 20%
Table 1–27. Typical VOD Setting, TX Term = 120
VOD Setting (mV)
Symbol
VOD differential
peak-to-peak Typical (mV)
0
1
2
3
4
5
6
240 ±
20%
480 ±
20%
720 ±
20%
840 ±
20%
960 ±
20%
1080 ±
20%
1200 ±
20%
Table 1–28. Typical VOD Setting, TX Term = 150
VOD Setting (mV)
Symbol
VOD differential
peak-to-peak Typical (mV)
0
1
2
3
4
5
300 ±
20%
600 ±
20%
900 ±
20%
1050 ±
20%
1200 ±
20%
1350 ±
20%
Table 1–29 lists typical transmitter pre-emphasis levels in dB for the first post tap
under the following conditions (low-frequency data pattern [five 1s and five 0s] at
6.25 Gbps). The levels listed in Table 1–29 are a representation of possible
pre-emphasis levels under the specified conditions only and that the pre-emphasis
levels may change with data pattern and data rate.
f To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Stratix IV HSSI HSPICE models.
Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part 1 of 2)
VOD Setting
Pre-Emphasis 1st
Post-Tap Setting
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
1
N/A
0.7
0
0
0
0
0
0
2
N/A
1
0.3
0
0
0
0
0
3
N/A
1.5
0.6
0
0
0
0
0
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–35
Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part 2 of 2)
VOD Setting
Pre-Emphasis 1st
Post-Tap Setting
0
1
2
3
4
5
6
7
4
N/A
2
0.7
0.3
0
0
0
0
5
N/A
2.7
1.2
0.5
0.3
0
0
0
6
N/A
3.1
1.3
0.8
0.5
0.2
0
0
7
N/A
3.7
1.8
1.1
0.7
0.4
0.2
0
8
N/A
4.2
2.1
1.3
0.9
0.6
0.3
0
9
N/A
4.9
2.4
1.6
1.2
0.8
0.5
0.2
10
N/A
5.4
2.8
1.9
1.4
1
0.7
0.3
11
N/A
6
3.2
2.2
1.7
1.2
0.9
0.4
12
N/A
6.8
3.5
2.6
1.9
1.4
1.1
0.6
13
N/A
7.5
3.8
2.8
2.1
1.6
1.2
0.6
14
N/A
8.1
4.2
3.1
2.3
1.7
1.3
0.7
15
N/A
8.8
4.5
3.4
2.6
1.9
1.5
0.8
16
N/A
N/A
4.9
3.7
2.9
2.2
1.7
0.9
17
N/A
N/A
5.3
4
3.1
2.4
1.8
1.1
18
N/A
N/A
5.7
4.4
3.4
2.6
2
1.2
19
N/A
N/A
6.1
4.7
3.6
2.8
2.2
1.4
20
N/A
N/A
6.6
5.1
4
3.1
2.4
1.5
21
N/A
N/A
7
5.4
4.3
3.3
2.7
1.7
22
N/A
N/A
8
6.1
4.8
3.8
3
2
23
N/A
N/A
9
6.8
5.4
4.3
3.4
2.3
24
N/A
N/A
10
7.6
6
4.8
3.9
2.6
25
N/A
N/A
11.4
8.4
6.8
5.4
4.4
3
26
N/A
N/A
12.6
9.4
7.4
5.9
4.9
3.3
27
N/A
N/A
N/A
10.3
8.1
6.4
5.3
3.6
28
N/A
N/A
N/A
11.3
8.8
7.1
5.8
4
29
N/A
N/A
N/A
12.5
9.6
7.7
6.3
4.3
30
N/A
N/A
N/A
N/A
11.4
9
7.4
N/A
31
N/A
N/A
N/A
N/A
12.9
10
8.2
N/A
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–36
Table 1–30 lists the Stratix IV GX transceiver jitter specifications for all supported
protocols. For protocols supported by Stratix IV GT industrial speed grade devices,
refer to the Stratix IV GX –2 commercial speed grade column in Table 1–30.
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
SONET/SDH Transmit Jitter Generation
–2 Commercial
Speed Grade
(2)
(Part 1 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min Typ
Max
Min
Typ
Max
Min Typ
Max
Unit
(4)
Peak-to-peak jitter at
622.08 Mbps
Pattern = PRBS15
—
—
0.1
—
—
0.1
—
—
0.1
UI
RMS jitter at
622.08 Mbps
Pattern = PRBS15
—
—
0.01
—
—
0.01
—
—
0.01
UI
Peak-to-peak jitter at
2488.32 Mbps
Pattern = PRBS15
—
—
0.1
—
—
0.1
—
—
0.1
UI
RMS jitter at
2488.32 Mbps
Pattern = PRBS15
—
—
0.01
—
—
0.01
—
—
0.01
UI
SONET/SDH Receiver Jitter Tolerance
(4)
Jitter frequency =
0.03 KHz
> 15
> 15
> 15
UI
> 1.5
> 1.5
> 1.5
UI
> 0.15
> 0.15
> 0.15
UI
> 15
> 15
> 15
UI
> 1.5
> 1.5
> 1.5
UI
> 0.15
> 0.15
> 0.15
UI
> 0.15
> 0.15
> 0.15
UI
Pattern = PRBS15
Jitter tolerance at
622.08 Mbps
Jitter frequency =
25 KHZ
Pattern = PRBS15
Jitter frequency =
250 KHz
Pattern = PRBS15
Jitter frequency =
0.06 KHz
Pattern = PRBS15
Jitter frequency =
100 KHZ
Jitter tolerance at
2488.32 Mbps
Pattern = PRBS15
Jitter frequency = 1 MHz
Pattern = PRBS15
Jitter frequency =
10 MHz
Pattern = PRBS15
Fibre Channel Transmit Jitter Generation
(5), (13)
Total jitter FC-1
Pattern = CRPAT
—
—
0.23
—
—
0.23
—
—
0.23
UI
Deterministic jitter FC-1
Pattern = CRPAT
—
—
0.11
—
—
0.11
—
—
0.11
UI
Total jitter FC-2
Pattern = CRPAT
—
—
0.33
—
—
0.33
—
—
0.33
UI
Deterministic jitter FC-2
Pattern = CRPAT
—
—
0.2
—
—
0.2
—
—
0.2
UI
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–37
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
Max
(2)
(Part 2 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Typ
Max
Unit
Max
Total jitter FC-4
Pattern = CRPAT
—
—
0.52
—
—
0.52
—
—
0.52
UI
Deterministic jitter FC-4
Pattern = CRPAT
—
—
0.33
—
—
0.33
—
—
0.33
UI
Fibre Channel Receiver Jitter Tolerance
(5), (14)
Deterministic jitter FC-1
Pattern = CJTPAT
> 0.37
> 0.37
> 0.37
UI
Random jitter FC-1
Pattern = CJTPAT
> 0.31
> 0.31
> 0.31
UI
Fc/25000
> 1.5
> 1.5
> 1.5
UI
Fc/1667
> 0.1
> 0.1
> 0.1
UI
Pattern = CJTPAT
> 0.33
> 0.33
> 0.33
UI
Sinusoidal jitter FC-1
Deterministic jitter FC-2
Random jitter FC-2
Pattern = CJTPAT
> 0.29
> 0.29
> 0.29
UI
Fc/25000
> 1.5
> 1.5
> 1.5
UI
Fc/1667
> 0.1
> 0.1
> 0.1
UI
Deterministic jitter FC-4
Pattern = CJTPAT
> 0.33
> 0.33
> 0.33
UI
Random jitter FC-4
Pattern = CJTPAT
> 0.29
> 0.29
> 0.29
UI
Fc/25000
> 1.5
> 1.5
> 1.5
UI
Fc/1667
> 0.1
> 0.1
> 0.1
UI
Sinusoidal jitter FC-2
Sinusoidal jitter FC-4
XAUI Transmit Jitter Generation
(6)
Total jitter at 3.125 Gbps Pattern = CJPAT
—
—
0.3
—
—
0.3
—
—
0.3
UI
Deterministic jitter at
3.125 Gbps
—
—
0.17
—
—
0.17
—
—
0.17
UI
Pattern = CJPAT
XAUI Receiver Jitter Tolerance
(6)
Total jitter
—
> 0.65
> 0.65
> 0.65
UI
Deterministic jitter
—
> 0.37
> 0.37
> 0.37
UI
Peak-to-peak jitter
Jitter frequency =
22.1 KHz
> 8.5
> 8.5
> 8.5
UI
Peak-to-peak jitter
Jitter frequency =
1.875 MHz
> 0.1
> 0.1
> 0.1
UI
Peak-to-peak jitter
Jitter frequency =
20 MHz
> 0.1
> 0.1
> 0.1
UI
PCIe Transmit Jitter Generation
(7)
Total jitter at 2.5 Gbps
(Gen1)
Compliance pattern
—
—
0.25
—
—
0.25
—
—
0.25
UI
Total jitter at 5 Gbps
(Gen2) (15)
Compliance pattern
—
—
0.25
—
—
0.25
—
—
—
UI
PCIe Receiver Jitter Tolerance
Total jitter at 2.5 Gbps
(Gen1)
September 2014
(7)
Compliance pattern
Altera Corporation
> 0.6
> 0.6
> 0.6
UI
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–38
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
Total jitter at 5 Gbps
(Gen2)
Compliance pattern
Max
(2)
(Part 3 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Compliant
Typ
Max
Compliant
Unit
Max
—
UI
PCIe (Gen 1) Electrical Idle Detect Threshold
VRX-IDLE-DETDIFFp-p
(16)
Compliance pattern
(peak-to-peak)
—
175
65
—
175
65
—
175
UI
—
—
0.17
—
—
0.17
—
—
0.17
UI
—
—
0.35
—
—
0.35
—
—
0.35
UI
(8)
Serial RapidIO Transmit Jitter Generation
Deterministic jitter
65
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
Data Rate = 1.25, 2.5,
3.125 Gbps
Total jitter
(peak-to-peak)
Pattern = CJPAT
Serial RapidIO Receiver Jitter Tolerance
Deterministic jitter
tolerance (peak-to-peak)
Combined deterministic
and random jitter
tolerance (peak-to-peak)
(8)
Data Rate = 1.25, 2.5,
3.125 Gbps
> 0.37
> 0.37
> 0.37
UI
> 0.55
> 0.55
> 0.55
UI
> 8.5
> 8.5
> 8.5
UI
> 0.1
> 0.1
> 0.1
UI
> 0.1
> 0.1
> 0.1
UI
Pattern = CJPAT
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
Jitter Frequency = 22.1
KHz Data Rate = 1.25,
2.5, 3.125 Gbps
Pattern = CJPAT
Jitter Frequency = 1.875
MHz
Sinusoidal jitter
tolerance (peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
Jitter Frequency =
20 MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
GIGE Transmit Jitter Generation
(9)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
—
—
0.14
—
—
0.14
—
—
0.14
UI
Total jitter
(peak-to-peak)
Pattern = CRPAT
—
—
0.279
—
—
0.279
—
—
0.279
UI
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–39
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
GIGE Receiver Jitter Tolerance
Max
(2)
(Part 4 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Typ
Max
Unit
Max
(9)
Deterministic jitter
tolerance (peak-to-peak)
Pattern = CJPAT
> 0.4
> 0.4
> 0.4
UI
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
UI
HiGig Transmit Jitter Generation
(10)
Deterministic jitter
(peak-to-peak)
Data Rate = 3.75 Gbps
Total jitter
(peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT
Pattern = CJPAT
HiGig Receiver Jitter Tolerance
—
—
0.17
—
—
—
—
—
—
UI
—
—
0.35
—
—
—
—
—
—
UI
> 0.37
—
—
—
—
—
—
UI
> 0.65
—
—
—
—
—
—
UI
> 8.5
—
—
—
—
—
—
UI
> 0.1
—
—
—
—
—
—
UI
> 0.1
—
—
—
—
—
—
UI
—
—
0.3
—
—
0.3
UI
—
—
>0.675
UI
(10)
Deterministic jitter
tolerance (peak-to-peak)
Data Rate = 3.75 Gbps
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT
Pattern = CJPAT
Jitter Frequency = 22.1
KHz
Data Rate = 3.75 Gbps
Pattern = CJPAT
Sinusoidal jitter
tolerance (peak-to-peak)
Jitter Frequency =
1.875MHz
Data Rate = 3.75 Gbps
Pattern = CJPAT
Jitter Frequency =
20 MHz
Data Rate = 3.75 Gbps
Pattern = CJPAT
(OIF) CEI Transmitter Jitter Generation
Data Rate = 6.375 Gbps
Total jitter
(peak-to-peak)
Pattern = PRBS15 BER =
10-12
(OIF) CEI Receiver Jitter Tolerance
Deterministic jitter
tolerance (peak-to-peak)
September 2014
(11)
—
—
0.3
(11)
Data Rate = 6.375 Gbps
Pattern = PRBS31 BER =
10-12
Altera Corporation
> 0.675
> 0.675
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–40
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Data Rate = 6.375 Gbps
Pattern=PRBS31
Max
(2)
(Part 5 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Typ
Max
Unit
Max
> 0.988
> 0.988
—
—
>0.988
UI
>5
>5
—
—
>5
UI
> 0.05
> 0.05
—
—
> 0.05
UI
> 0.05
> 0.05
—
—
> 0.05
UI
BER = 10-12
Jitter Frequency = 38.2
KHz
Data Rate = 6.375 Gbps
Pattern = PRBS31 BER =
10-12
Jitter Frequency = 3.82
MHz
Sinusoidal jitter
tolerance (peak-to-peak)
Data Rate = 6.375 Gbps
Pattern = PRBS31 BER =
10-12
Jitter Frequency =
20 MHz
Data Rate= 6.375 Gbps
Pattern = PRBS31 BER =
10-12
SDI Transmitter Jitter Generation
Alignment jitter
(peak-to-peak)
(12)
Data Rate = 1.485 Gbps
(HD) Pattern = Color Bar
Low-Frequency Roll-Off
= 100 KHz
0.2
—
—
0.2
—
—
0.2
—
—
UI
Data Rate = 2.97 Gbps
(3G) Pattern = Color Bar
Low-Frequency Roll-Off
= 100 KHz
0.3
—
—
0.3
—
—
0.3
—
—
UI
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–41
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
SDI Receiver Jitter Tolerance
Max
(2)
(Part 6 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Typ
Max
Unit
Max
(12)
Jitter Frequency =
15 KHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Sinusoidal jitter
tolerance (peak-to-peak)
>2
>2
>2
UI
> 0.3
> 0.3
> 0.3
UI
> 0.3
> 0.3
> 0.3
UI
>1
>1
>1
UI
> 0.2
> 0.2
> 0.2
UI
> 0.2
> 0.2
> 0.2
UI
Jitter Frequency =
100 KHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Jitter Frequency =
148.5 MHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Jitter Frequency =
20 KHz
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
Sinusoidal jitter
tolerance (peak-to-peak)
Jitter Frequency = 100
KHz Data Rate = 1.485
Gbps (HD) Pattern =
75% Color Bar
Jitter Frequency = 148.5
MHz
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
SAS Transmit Jitter Generation
(17)
Total jitter at 1.5 Gbps
(G1)
Pattern = CJPAT
—
—
0.55
—
—
0.55
—
—
0.55
UI
Deterministic jitter at
1.5 Gbps (G1)
Pattern = CJPAT
—
—
0.35
—
—
0.35
—
—
0.35
UI
Total jitter at 3.0 Gbps
(G2)
Pattern = CJPAT
—
—
0.55
—
—
0.55
—
—
0.55
UI
Deterministic jitter at
3.0 Gbps (G2)
Pattern = CJPAT
—
—
0.35
—
—
0.35
—
—
0.35
UI
Total jitter at 6.0 Gbps
(G3)
Pattern = CJPAT
—
—
0.25
—
—
0.25
—
—
0.25
UI
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–42
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Random jitter at
6.0 Gbps (G3)
Conditions
Pattern = CJPAT
SAS Receiver Jitter Tolerance
–2 Commercial
Speed Grade
(2)
(Part 7 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min Typ
Max
Min
Typ
Max
Min Typ
Max
—
0.15
—
—
0.15
—
0.15
—
—
Unit
UI
(17)
Total Jitter tolerance at
1.5 Gbps (G1)
Pattern = CJPAT
> 0.65
> 0.65
> 0.65
UI
Deterministic Jitter
tolerance at 1.5 Gbps
(G1)
Pattern = CJPAT
> 0.35
> 0.35
> 0.35
UI
> 0.1
> 0.1
> 0.1
UI
Sinusoidal Jitter
tolerance at 1.5 Gbps
(G1)
Jitter Frequency = 900
KHz to 5 MHz
Pattern = CJTPAT BER =
1E-12
CPRI Transmit Jitter Generation
(18)
E.6.HV, E.12.HV
Pattern = CJPAT
Total Jitter
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
—
—
0.279
—
—
0.279
—
—
0.279
UI
—
—
0.35
—
—
0.35
—
—
0.35
UI
—
—
0.14
—
—
0.14
—
—
0.14
UI
—
—
0.17
—
—
0.17
—
—
0.17
UI
Pattern = CJTPAT
E.6.HV, E.12.HV
Pattern = CJPAT
Deterministic Jitter
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
CPRI Receiver Jitter Tolerance
Total jitter tolerance
Deterministic jitter
tolerance
Total jitter tolerance
(18)
E.6.HV, E.12.HV
Pattern = CJPAT
E.6.HV, E.12.HV
Pattern = CJPAT
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
> 0.66
> 0.66
> 0.66
UI
> 0.4
> 0.4
> 0.4
UI
> 0.65
> 0.65
> 0.65
UI
> 0.37
> 0.37
> 0.37
UI
> 0.55
> 0.55
> 0.55
UI
Pattern = CJTPAT
Deterministic jitter
tolerance
Combined deterministic
and random jitter
tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–43
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
OBSAI Transmit Jitter Generation
(Part 8 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min Typ
Max
Min
Typ
Max
Min Typ
Max
—
—
0.35
—
—
0.35
—
—
0.35
UI
—
—
0.17
—
—
0.17
—
—
0.17
UI
(19)
Total jitter at 768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6MHz
Deterministic jitter at
768 Mbps, 1536 Mbps,
and 3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT
Pattern = CJPAT
OBSAI Receiver Jitter Tolerance
–2 Commercial
Speed Grade
(2)
(19)
Deterministic jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.37
> 0.37
> 0.37
UI
Combined deterministic
and random jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.55
> 0.55
> 0.55
UI
Jitter Frequency =
5.4 KHz
> 8.5
> 8.5
> 8.5
UI
> 0.1
> 0.1
> 0.1
UI
> 8.5
> 8.5
> 8.5
UI
> 0.1
> 0.1
> 0.1
UI
Sinusoidal Jitter
tolerance at 768 Mbps
Pattern = CJPAT
Jitter Frequency =
460 MHz to 20 MHz
Pattern = CJPAT
Jitter Frequency =
10.9 KHz
Sinusoidal Jitter
tolerance at 1536 Mbps
Pattern = CJPAT
Jitter Frequency =
921.6 MHz to 20 MHz
Pattern = CJPAT
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–44
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1),
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
Min Typ
Jitter Frequency = 21.8
KHz
Sinusoidal Jitter
tolerance at 3072 Mbps
Max
(2)
(Part 9 of 9)
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Min
Min Typ
Typ
Max
Unit
Max
> 8.5
> 8.5
> 8.5
UI
> 0.1
> 0.1
> 0.1
UI
Pattern = CJPAT
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
Notes to Table 1–30:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(4) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(5) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(6) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(7) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(8) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(9) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(10) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(11) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The fibre channel transmitter jitter generation numbers are compliant to the specification at T interoperability point.
(14) The fibre channel receiver jitter tolerance numbers are compliant to the specification at R interoperability point.
(15) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(16) Stratix IV PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50mV.
(17) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(18) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(19) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–45
Table 1–31 lists the transceiver jitter specifications for protocols supported by
Stratix IV GT devices.
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 1 of 2)
Symbol/
Description
–1 Industrial Speed
Grade
Conditions
XLAUI/CAUI Transmit Jitter Generation
Total Jitter
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
0.30
—
—
0.30
—
—
0.30
UI
—
—
0.17
—
—
0.17
—
—
0.17
UI
(1), (3)
Pattern = PRBS-31
VOD = 800 mV
REFCLK = 644.53 MHz
Deterministic
Jitter
4 (XLAUI)/
10 (CAUI) channels in
Basic ×1 mode
XLAUI/CAUI Receiver Jitter Tolerance
Total Jitter
tolerance
(1)
Pattern = PRBS-31
> 0.62
> 0.62
—
UI
>5
>5
—
UI
> 0.05
> 0.05
—
UI
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
Sinusoidal Jitter
tolerance
BER = 1E-12
Jitter Frequency 4 MHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
XFI Transmitter Jitter Generation
(2), (3)
Pattern =
PRBS-31
Vod = 800 mV
Total jitter at
10.3125 Gbps
REFCLK =
644.53 MHz
—
—
0.3
—
—
0.3
—
—
—
UI
—
—
0.30
—
—
0.30
—
—
0.30
UI
—
—
0.17
—
—
0.17
—
—
0.17
UI
10 channels in Basic ×1 mode
OTL 4.10
(1), (3)
Total Jitter at
11.18 Gbps
Pattern = PRBS-31
Deterministic
Jitter
REFCLK = 698.75 MHz
September 2014
VOD = 800 mV
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–46
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
Min
Typ
Max
–2 Industrial Speed
Grade
Min
Typ
Max
–3 Industrial Speed
Grade
Min
Typ
Unit
Max
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
Sinusoidal Jitter
tolerance
>5
>5
—
UI
> 0.05
> 0.05
—
UI
BER = 1E-12
Jitter Frequency 4 MHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
Notes to Table 1–31:
(1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
(2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
(3) Contact Altera for board and link best practices at BER = 1E-15.
Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices
Symbol/Description
Conditions
(1), (2)
-1 Industrial
Speed Grade
-2 Industrial
Speed Grade
-3 Industrial
Speed Grade
Mean
Mean
Mean
—
—
Unit
Pattern = PRBS-31
Total Transmitter jitter at
11.3 Gbps (4)
Vod = 800 mV
REFCLK = 706.25 MHz
0.23 UI
(3)
UI
12 channels in Basic ×1 mode
Notes to Table 1–32:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for stated conditions only.
(3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
characterized was 0.30 UI.
(4) Contact Altera for board and link best practices at BER = 1E-15.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–47
Transceiver Datapath PCS Latency
f For more information about:
■
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
Architecture in Stratix IV Devices chapter.
■
PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
Architecture in Stratix IV Devices chapter.
■
SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
■
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Architecture in Stratix IV Devices chapter.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1–33 lists the clock tree specifications for Stratix IV devices.
Table 1–33. Clock Tree Performance for Stratix IV Devices
Performance
Unit
Symbol
September 2014
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Global clock and
Regional clock
800
700
500
MHz
Periphery clock
550
500
500
MHz
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–48
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
PLL Specifications
Table 1–34 lists the Stratix IV PLL specifications when operating in the commercial
(0° to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction
temperature ranges.
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)
Symbol
Parameter
Input clock frequency (–2/–2x speed grade)
fIN
fINPFD
fVCO
(2)
tEINDUTY
fOUT
fOUT_EXT
Min
5
Typ
—
Max
Unit
800
(1)
MHz
MHz
MHz
Input clock frequency (–3 speed grade)
5
—
717
(1)
Input clock frequency (–4 speed grade)
5
—
717
(1)
Input frequency to the PFD
5
—
325
MHz
PLL VCO operating range (–2 speed grade)
600
—
1600
MHz
PLL VCO operating range (–3 speed grade)
600
—
1300
MHz
PLL VCO operating range (–4 speed grade)
600
—
1300
MHz
Input clock or external feedback clock input duty cycle
40
—
60
%
Output frequency for internal global or regional clock
(–2/–2x speed grade)
—
—
800
(3)
MHz
Output frequency for internal global or regional clock
(–3 speed grade)
—
—
717
(3)
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
—
—
717
(3)
MHz
Output frequency for external clock output (–2 speed grade)
—
—
800
(3)
MHz
717
(3)
MHz
717
(3)
MHz
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
—
—
—
—
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
10
ns
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
Time required to reconfigure phase shift
—
1
—
scanclk
cycles
fSCANCLK
scanclk frequency
—
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
de-assertion of areset
—
—
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
—
0.3
—
MHz
—
1.5
—
MHz
—
4
—
MHz
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
(8)
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
—
ns
tINCCJ
(4), (5)
tOUTPJ_DC
(6)
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
—
—
0.15
UI (p-p)
Input clock cycle to cycle jitter (FREF < 100 MHz)
—
—
±750
ps (p-p)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
—
—
17.5
mUI (p-p)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–49
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)
Symbol
tOUTCCJ_DC
tOUTPJ_IO
(6)
(6),
(9)
tOUTCCJ_IO
(6),
(9)
tCASC_OUTPJ_DC
(6), (7)
fDRIFT
Parameter
Min
Typ
Max
Unit
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
—
17.5
mUI (p-p)
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
600
ps (p-p)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
60
mUI (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
600
ps (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
60
mUI (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
—
—
250
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
—
—
25
mUI (p-p)
Frequency drift after PFDENA is disabled for duration of
100 us
—
—
±10
%
Notes to Table 1–34:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–51 on page 1–62.
(7) The cascaded PLL specification is only applicable with the following condition:
A. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz
B. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–49 on
page 1–61.
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–50
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
DSP Block Specifications
Table 1–35 lists the Stratix IV DSP block performance specifications.
Table 1–35. Block Performance Specifications for Stratix IV DSP Devices
(1)
Resources
Used
Performance
Number of
Multipliers
–1 Industrial
and–2/–2×
Commercial/
Industrial
Speed Grade
9×9-bit multiplier (A, C, E, G) (2)
1
520
460
460
400
400
MHz
9×9-bit multiplier (B, D, F, H) (2)
1
520
460
460
400
400
MHz
1
540
500
500
440
440
MHz
1
540
500
500
440
430
MHz
18×18-bit multiplier
1
600
550
550
480
480
MHz
36×36-bit multiplier
1
480
440
440
380
380
MHz
18×18-bit multiply accumulator
4
490
440
440
380
380
MHz
18×18-bit multiply adder
4
510
470
470
410
400
MHz
18×18-bit multiply adder-signed full
precision
2
490
450
440
390
390
MHz
18×18-bit multiply adder with
loopback (4)
2
390
350
350
310
300
MHz
36-bit shift (32-bit data)
1
490
440
440
380
380
MHz
Double mode
1
480
440
440
380
370
MHz
Mode
12×12-bit multiplier (A,
E) (3)
12×12-bit multiplier (B, D, F,
H) (3)
–3
–3
–4
–4
Commercial Industrial Commercial Industrial
Speed
Speed
Speed
Speed
Grade
Grade
Grade
Grade
Unit
Notes to Table 1–35:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements eight independent 9b´9b multiplies using A, B, C, D for the top DSP half block and E, F, G, H for the bottom DSP half block
multipliers.
(3) The DSP block implements six independent 12b´12b multiplies using A, B, D for the top DSP half block and E, F, H for the bottom DSP half block
multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–51
TriMatrix Memory Block Specifications
Table 1–36 lists the Stratix IV TriMatrix memory block specifications.
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices (1) (Part 1 of 2)
Resources Used
Memory
MLAB
(3)
M9K
Block
(3)
Mode
Performance
–3
–1 Industrial
–3
–4
–4
Industrial/
and –2 /–2× Commercial/
Industrial
Commercial/ Military
TriMatrix
ALUTs
Commercial/ Industrial/
Speed
Industrial
Speed
Memory
Industrial
Military
Grade
Grade
Speed Grade
(2)
Speed Grade Speed Grade
(2)
Unit
Single port
64×10
0
1
600
500
450
500
450
MHz
Simple dual-port
32×20
0
1
600
500
450
500
450
MHz
Simple dual-port
64×10
0
1
600
500
450
500
450
MHz
ROM 64×10
0
1
600
500
450
500
450
MHz
ROM 32×20
0
1
600
500
450
500
450
MHz
Single-port
256×36
0
1
600
540
475
540
475
MHz
Simple dual-port
256×36
0
1
550
490
420
490
420
MHz
Simple dual-port
256×36, with the
read-during-write
option set to Old
Data
0
1
375
340
300
340
300
MHz
True dual port
512×18
0
1
490
430
370
430
370
MHz
True dual-port
512×18, with the
read-during-write
option set to Old
Data
0
1
375
335
290
335
290
MHz
ROM 1 Port
0
1
600
540
475
540
475
MHz
ROM 2 Port
0
1
600
540
475
540
475
MHz
Min Pulse Width
(clock high time)
—
—
750
800
850
800
850
ps
Min Pulse Width
(clock low time)
—
—
500
625
690
625
690
ps
September 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–52
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices (1) (Part 2 of 2)
Resources Used
Memory
M144K
Block
(3)
Performance
–3
–4
–1 Industrial
–3
–4
Industrial/
Industrial
and –2 /–2× Commercial/
TriMatrix
Commercial/ Military
Speed
ALUTs
Commercial/ Industrial/
Memory
Industrial
Speed
Grade
Industrial
Military
Speed Grade
Grade
(2)
Speed Grade Speed Grade
(2)
Mode
Unit
Single-port
4K×36
0
1
475
440
380
400
350
MHz
Simple dual-port
2K×72
0
1
465
435
385
375
325
MHz
Simple dual-port
2K×72, with the
read-during-write
option set to Old
Data
0
1
260
240
205
225
200
MHz
Simple dual-port
2K×64 (with
ECC)
0
1
335
300
255
295
250
MHz
True dual-port
4K×36
0
1
400
375
330
350
310
MHz
True dual-port
4K×36, with the
read-during-write
option set to Old
Data
0
1
245
230
205
225
200
MHz
ROM 1 Port
0
1
540
500
435
450
420
MHz
ROM 2 Port
0
1
500
465
400
425
400
MHz
Min Pulse Width
(clock high time)
—
—
700
755
860
860
950
ps
Min Pulse Width
(clock low time)
—
—
500
625
690
690
690
ps
Notes to Table 1–36:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set
to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) This is only applicable to the Stratix IV E and GX devices.
(3) When you use the error detection CRC feature, there is no degradation in FMAX.
Configuration and JTAG Specifications
Table 1–37 lists the Stratix IV configuration mode specifications.
Table 1–37. Configuration Mode Specifications for Stratix IV Devices
DCLK FMAX
Programming Mode
Passive serial
Fast passive parallel
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
(1)
Unit
Min
Typ
Max
—
—
125
MHz
—
—
125
MHz
September 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–53
Table 1–37. Configuration Mode Specifications for Stratix IV Devices
DCLK FMAX
Programming Mode
Unit
Min
Typ
Max
17
26
40
Fast active serial
MHz
Note to Table 1–37:
(1) This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for
each device may vary depending on device density. For more information, refer to the Configuration, Design
Security, and Remote System Upgrades in Stratix IV Devices chapter.
Table 1–38 lists the JTAG timing parameters and values for Stratix IV devices.
Table 1–38. JTAG Timing Parameters and Values for Stratix IV Devices
Symbol
Description
Min
Max
Unit
tJCP
TCK clock period
30
—
ns
tJCH
TCK clock high time
14
—
ns
tJCL
TCK clock low time
14
—
ns
tJPSU (TDI)
TDI JTAG port setup time
1
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
JTAG port clock to output
—
tJPZX
JTAG port high impedance to valid output
tJPXZ
—
JTAG port valid output to high impedance
—
11
(1)
ns
14
(1)
ns
14
(1)
ns
Note to Table 1–38:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Temperature Sensing Diode Specifications
Table 1–39 lists the specifications for the Stratix IV temperature sensing diode.
Table 1–39. External Temperature Sensing Diode Specifications for Stratix IV Devices
Description
Min
Typ
Max
Unit
Ibias, diode source current
8
—
500
A
Vbias, voltage across diode
0.3
—
0.9
V
Series resistance
—
—
工商网监
湘ICP备2023018690号
