EP4S40G2F40I2N

Errata Sheet for Stratix IV E Devices ES-01024-3.0 Errata Sheet This errata sheet provides updated information about known device issues affecting Stratix® IV E devices. Production Device Issues for Stratix IV E Devices Table 1 lists the issues and affected Stratix IV E production devices. Table 1. Production Device Issues for Stratix IV E Devices (Part 1 of 2) Issue Affected Devices Planned Fix All Stratix IV E devices (ES and production) Quartus II software version 12.0 and later. All Stratix IV GX (ES and production) devices Quartus II software version 9.1 and later. All production devices — EP4SE360, EP4SE530, EP4SE820 EP4SE360 Rev B, EP4SE530 Rev E, EP4SE820 Rev B All production devices — All production devices — All production devices — “PLL phasedone Signal Stuck at Low” In some cases, the Stratix IV phase-locked loop (PLL) blocks exhibit the phasedone signal stuck at low during the PLL dynamic phase shift. “Remote System Upgrade” The remote system upgrade feature fails when loading an invalid configuration image. “EDCRC False Errors” The error detection CRC (SEU detection) feature may falsely assert the CRC_ERROR signal when no SEU event has occurred. “I/O Jitter” Affected Stratix IV E production devices may exhibit higher than expected jitter on general purpose I/O pins. “Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK Frequency” Stratix IV E configuration might fail in FPP mode when the DCLK frequency is set to 125 MHz with a 60/40 or 40/60 duty cycle. “FPP Mode Configuration Failures When the Minimum Hold Time (tDH) is set to 0 ns or 24 ns” Stratix IV E configuration fails in FPP mode when the minimum data hold time (tDH) is set to 0 ns for uncompressed and unencrypted configuration data or 24 ns for compressed and/or encrypted data. “M144K RAM Block Lock-Up” M144K RAM blocks may lock up if there is a glitch in the clock source. 101 Innovation Drive San Jose, CA 95134 www.altera.com June 2012 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe Page 2 Production Device Issues for Stratix IV E Devices Table 1. Production Device Issues for Stratix IV E Devices (Part 2 of 2) Issue Affected Devices Planned Fix All production devices — All production devices Refer to “Higher Power Supply Current During Power-Up for VCCPD” “Stratix IV E Power-up Sequencing on Production Devices” The device fails to power up and exit POR at low temperatures when VCC is powered after VCCAUX. “Higher Power Supply Current During Power-Up for VCCPD” Higher power-up current requirements are needed for VCCPD power supply. PLL phasedone Signal Stuck at Low In some cases, the Stratix IV PLL blocks exhibit the phasedone signal stuck at low during the PLL dynamic phase shift. When the PLL phasedone signal is stuck at low, the intended phase shift does not happen. You can recover from the PLL phasedone signal being stuck at low by resetting the PLL or by restarting the phase shift operation by asserting the phasestep signal. Solution To resolve the PLL phasedone signal stuck at low issue, the Altera PLL megafunction is enhanced to automatically restart the phase shift operation internally in the Altera PLL megafunction whenever the PLL phasedone signal is stuck at low. Restarting the phase shift operation compensates for the missing phase shift operation and also recovers the phasedone signal. This Altera PLL megafunction solution will be implemented in the Quartus II software version 12.0 and later. Altera recommends upgrading to the latest Quartus II software, regenerating the PLL megafunction, and recompiling your design. Additionally, software patches are available for the Quartus II software versions 9.1 SP2 and 10.1 SP1 to upgrade the PLL megafunction with the solution. To download and install the Quartus II software patch, refer to the PLL Phasedone Stuck at Low Solution. f If you need additional support, file a service request using mySupport. Remote System Upgrade The remote system upgrade feature does not operate correctly when you initiate a reconfiguration cycle that goes from a factory configuration image to an invalid application configuration image. In this scenario, the device fails to revert back to the factory configuration image after a configuration error is detected while loading the invalid application configuration image. The failure is indicated by a continuous toggling of the nSTATUS pin. In correct operation, the device reverts to the factory configuration image after a configuration error is detected with the invalid configuration image. June 2012 Altera Corporation Errata Sheet for Stratix IV E Devices Production Device Issues for Stratix IV E Devices 1 Page 3 An invalid application configuration image is classified as one of the following: ■ A partially programmed application image ■ A blank application image ■ An application image assigned with a wrong start address The remote system upgrade feature works correctly with all other reconfiguration trigger conditions. This issue is addressed by enabling the Reconfig POF Checking feature in the updated ALTREMOTE_UPDATE megafunction and is available in the Quartus® II software version 9.1 and later. For more information about how to enable the Reconfig POF Checking feature, refer to AN 603: Active Serial Remote System Upgrade Reference Design. EDCRC False Errors The error detection cyclic redundancy check (CRC) (single event upset [SEU] detection) feature may falsely assert the CRC_ERROR signal when no SEU event has occurred. The falsely asserted CRC_ERROR signal happens because the configuration RAM is incorrectly read for the EDCRC checks. In this scenario, the configuration RAM data and the functionality of the device are not affected. ■ If EDCRC is not critical to your system, turn it off. ■ If EDCRC is required, insert a soft IP in your design. f For more support and to request the soft IP, file a service request using mySupport. I/O Jitter Affected Stratix IV E production devices (refer to Table 1) may exhibit up to ±50 ps higher than expected jitter on general purpose I/O pins. I/O pins in LVDS mode (including dynamic phase alignment [DPA] and soft clock data recovery [CDR]) are not affected. The actual amount of additional jitter depends on the device switching activity. The EP4SE230 production ordering code is not affected. Altera is fixing this issue in the next revision of production devices, which will meet all current jitter specifications. f For further support, file a service request using mySupport. Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK Frequency Stratix IV E devices might fail to configure in FPP mode if the DCLK frequency is set to 125 MHz with a 60/40 or 40/60 duty cycle. When the device fails to configure in FPP mode, the device pulls the nSTATUS pin low and the configuration host may initiate a reconfiguration. This problem affects all Stratix IV E devices. Errata Sheet for Stratix IV E Devices June 2012 Altera Corporation Page 4 Production Device Issues for Stratix IV E Devices For successful FPP configuration at 125 MHz for devices with the density of the EP4SE360 and lower, set the duty cycle to 45/55, 55/45, or higher. These settings correspond to a minimum DCLK high time (tCH) and a minimum DCLK low time (tCL) of 3.6 ns. For EP4SE530 devices, reduce the DCLK frequency to 100 MHz or lower and set the duty cycle to 45/55, 55/45, or higher. These settings correspond to a minimum DCLK high time (tCH) and a minimum DCLK low time (tCL) of 4.5 ns. For EP4SE820 devices, reduce the DCLK frequency to 80 MHz or lower and set the duty cycle to 45/55, 55/45, or higher. These settings correspond to a minimum DCLK high time (tCH) and a minimum DCLK low time (tCL) of 5.6 ns. FPP Mode Configuration Failures When the Minimum Hold Time (tDH) is set to 0 ns or 24 ns Stratix IV E devices might fail to configure in FPP mode if the minimum hold time (tDH) for the configuration data is set to 0 ns for uncompressed and unencrypted configuration data, or 24 ns for compressed and/or encrypted data. When the configuration fails, the device pulls the nSTATUS pin low and the configuration host may initiate a reconfiguration. This problem affects all Stratix IV E devices. You can successfully configure the Stratix IV E devices in FPP mode by setting the minimum hold time (tDH) for the uncompressed and unencrypted configuration data to 1 ns or higher. For compressed and/or encrypted data, set the minimum hold time (tDH) to 3 * 1/fDCLK + 1 ns or higher (fDCLK is your DCLK frequency setting). Alternatively, you can drive the configuration data out on the falling edge of the DCLK. 1 The MAX II Parallel Flash Loader drives out configuration data on the falling edge of the DCLK. This issue does not affect you if you use the Max II Parallel Flash Loader as the configuration controller. M144K RAM Block Lock-Up M144K blocks may lock up if there is a glitch in the clock source when rden equals 1. In the lock-up state, the RAM block does not respond to read or write operations and requires an FPGA reconfiguration to restore operation. The lock-up occurs within the M144K RAM in the Read Timer Trigger circuitry. A clock glitch may inadvertently freeze the Read Timer Trigger circuitry, locking the RAM block in its last operation. MLABs and M9K RAM blocks are not affected. The workaround is to add clock-enable logic, an internal phase-locked loop (PLL), or clock-generation logic (for example, a clock divider). You can add clock-enable logic (internal or external) to disable RAM block operation until the clock is stable. You can also gate the clock internally or externally. If FPGA resources permit, you can use an internal PLL or clock-generation logic to ensure a stable clock source at the RAM block input. June 2012 Altera Corporation Errata Sheet for Stratix IV E Devices Production Device Issues for Stratix IV E Devices Page 5 The Read Timer circuitry makes RAM block operation independent of the input clock duty cycle, thus maximizing design performance. If you cannot provide a stable clock, use the DCD option in the Quartus II software version 9.1 or later to work around this problem. When the M144K block uses the DCD option, the block does not exhibit the lock-up behavior, but clock high-time requirements are increased and fMAX performance is degraded. If you cannot provide a stable clock input without glitches, to enable the DCD option in the Quartus II software, perform the following steps: 1. On the Assignments menu, click Settings. 2. In the Category list, select Fitter Settings. 3. Click More Settings. 4. Under Existing option settings, set M144K Block Read Clock Duty Cycle Dependency to On. 5. Click OK. 6. Compile your design. Use the .qsf variable instead of the previous instructions to make a global assignment. DCD is on globally by adding the following line to the project’s .qsf (the default is Off): set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY ON Alternatively, you can also apply this setting to individual M144K blocks with the Assignment Editor. The global and per instance assignments can be mixed. For example, you can set DCD to On globally, but set it to Off for an instance. You can also set it to On for an instance. Stratix IV E Power-up Sequencing on Production Devices Stratix IV E devices might fail to power up correctly at low temperatures when the VCC (0.9 V) power supply powers up after the VCCAUX (2.5 V) power supply. The power-up issue occurs because the FPGA device fails to exit power-on reset (POR), as indicated by the nSTATUS pin being stuck low. Configuration cannot begin when the nSTATUS pin is low. The problem affects all Stratix IV E devices. Engineering sample devices are not affected. Production devices must use the power-up sequence board design modifications to successfully power-up and exit POR on production devices, by fully powering VCC before VCCAUX begins to ramp. There is no dependency on the ramp rate for VCC and VCCAUX. The published ramp rate specifications still apply. 1 You can successfully use the hot socketing feature if you use the VCC before VCCAUX power sequence board design modification. Contact Altera for Technical Support if you require assistance with implementing these board design changes. Errata Sheet for Stratix IV E Devices June 2012 Altera Corporation Page 6 Stratix IV E ES Device Issues Stratix IV E ES Device Issues Table 2 lists the issues and which Stratix IV E ES devices are affected by each issue. Table 2. Issues for Stratix IV E ES Devices Issue EDCRC False Errors The error detection CRC (SEU detection) feature may falsely assert the CRC_ERROR signal when no SEU event has occurred. Remote System Upgrade Remote System Upgrade fails when loading an invalid configuration image. M9K/M144K RAM Block Lock-up M9K/M144K RAM blocks may lock up if there is a glitch in the clock source. CRC Error Injection Feature The CRC Error Injection feature may not operate correctly. Higher Power Supply Current During Power-Up for VCCPD Higher power-up current requirements are needed for VCCPD power supply. M144K Write with Dual-Port Dual-Clock Modes M144K RAM blocks may not operate correctly in dual-port dual-clock modes. Automatic Clock Switchover Automatic clock switchover feature may not operate correctly. CRC Error Detection Feature MLAB RAM blocks may not operate correctly with the CRC Error Detection feature enabled. Higher VCC Power Supply Levels Stratix IV E ES devices require higher VCC power supply levels. I/O Jitter Stratix IV E ES devices may exhibit higher than expected jitter on all I/O pins. Higher Minimum fINPFD Setting Stratix IV E ES devices may exhibit higher than expected PLL jitter at low fINPFD settings. High I/O pin leakage current Top and bottom I/O banks show higher leakage than the published Stratix IV Data Sheet version 2.1 specifications. Higher standby current for VCC power supply Higher than specified standby current on the VCC supply. Reduced M9K/M144K performance Reduced M9K/M144K performance for Stratix IV E ES devices. Affected Devices Planned Fix EP4SE530 ES devices — EP4SE530 ES devices Production devices EP4SE530 ES devices None EP4SE530 ES devices Production devices EP4SE530 ES devices None EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices (all speed grades) Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices Production devices EP4SE530 ES devices For more information, refer to “DPA Misalignment” on page 11. DPA misalignment Dynamic phase alignment (DPA) circuitry in Stratix IV E ES devices might get stuck at the initial configured phase or move to the optimum phase after a longer than expected period of time. June 2012 Altera Corporation Errata Sheet for Stratix IV E Devices Stratix IV E ES Device Issues Page 7 EDCRC False Errors The error detection cyclic redundancy check (CRC) (single event upset [SEU] detection) feature may falsely assert the CRC_ERROR signal when no SEU event has occurred. The falsely asserted CRC_ERROR signal happens because the configuration RAM is incorrectly read for the EDCRC checks. In this scenario, the configuration RAM data and the functionality of the device are not affected. ■ If EDCRC is not critical to your system, turn it off. ■ If EDCRC is required, insert a soft IP in your design. f For more support and to request the soft IP, file a service request using mySupport. Remote System Upgrade The remote system upgrade feature does not operate correctly when you initiate a reconfiguration cycle from a factory configuration image to an invalid application configuration image. In this scenario, Stratix IV GX and Stratix IV E devices fail to revert to the factory configuration image after a configuration error is detected while loading the invalid application configuration image. The failure is indicated by a continuous toggling of the nSTATUS pin. In correct operation, Stratix IV GX and Stratix IV E devices revert to the factory configuration image after a configuration error is detected with the invalid configuration image. 1 An invalid application configuration image is classified as one of the following: ■ A partially programmed application image ■ A blank application image ■ An application image assigned with a wrong start address The remote system upgrade feature works correctly with all other reconfiguration trigger conditions. The remote system upgrade feature issue is addressed by using the updated ALTREMOTE_UPDATE megafunction and is available in the Quartus II software version 9.1 or later, or contact Altera technical support for the software patch available with the Quartus II software version 9.0 SP2. Errata Sheet for Stratix IV E Devices June 2012 Altera Corporation Page 8 Stratix IV E ES Device Issues M9K/M144K RAM Block Lock-up The M9K and M144K blocks can lock up if the clock source glitches when rden=1, which can occur if the clock source is not from a PLL. In this state, a RAM block no longer responds to read or write operations and requires an FPGA reconfiguration to restore operation. The issue occurs in the Read Timer Trigger circuitry, where a glitch-prone non-PLL clock may inadvertently freeze the Read Timer Trigger circuitry, locking the RAM block in its last operation. All RAM block modes are affected. MLABs are not affected. The workaround is to add clock-enable logic, an internal PLL, or clock generation logic (for example, a clock divider). You can add clock-enable logic (internal or external) to disable RAM block operation until the clock is stable. You can also gate the clock internally or externally. If FPGA resources permit, you can use an internal PLL or clock generation logic to ensure a stable clock source at the RAM block input. CRC Error Injection Feature The CRC Error Injection feature on Stratix IV E ES devices may not operate correctly when running the EDERROR_INJECT JTAG instruction. The CRC_ERROR output status pin may remain low, incorrectly indicating no CRC errors. The CRC Error Injection feature issue only occurs with the error injection block and is fixed in production devices. The CRC Error Detection feature operates correctly as expected, and is not affected by this issue. If you need to use the CRC Error Injection feature with Stratix IV E ES devices, contact Altera® Technical Support. Higher Power Supply Current During Power-Up for VCCPD Stratix IV E ES devices require higher power-up current levels for the VCCPD power supply than previously specified. The PowerPlay Early Power Estimator (EPE) version 9.0.1 correctly shows the VCCPD power-on current for Stratix IV E ES devices. The Quartus II software and PowerPlay EPE version 9.1 and later versions correctly show the VCCPD power-on current for production devices. Stratix IV E ES and production device functionality is not affected by this issue, even if your VCCPD power supply is designed with output current levels below what the Quartus II software and/or EPE specify. Stratix IV E ES and production devices will power-up and operate correctly as expected, provided the supplies power up monotonically and the minimum voltage requirement is met. VCCPD must meet the minimum power supply voltage requirement for the device to exit power-on reset (POR). After the device exits POR, the VCCPD current requirements return to what is reported by Altera’s power estimation tools. Overall thermal power and operating current levels are not affected by this issue. If there are other devices on the board that share the VCCPD power supply, you can use the Quartus II software and/or the EPE to estimate power supply current requirements. This analysis may be needed if the other devices on the board have stringent power supply integrity requirements. There is no planned fix for the higher power-up current requirements. June 2012 Altera Corporation Errata Sheet for Stratix IV E Devices Stratix IV E ES Device Issues Page 9 M144K Write with Dual-Port Dual-Clock Modes M144K RAM blocks in dual-port dual-clock modes may fail to operate correctly, affecting applications such as DCFIFO memories, where data is transferred between two separate clock domains. If you are using Stratix IV E ES devices with the Quartus II software version 9.0, you must recompile your design and manually avoid all use of M144K RAM blocks in dual-port dual-clock modes. The Quartus II software version 9.0 SP1 automatically disables use of dual-port dual-clock modes in all M144K RAM blocks. In both cases, your design’s usage of M9K RAM blocks may increase as a result. This issue is fixed in production devices. f You can download a software patch to help with M144K RAM blocks in dual-port dual-clock mode failure at: http://www.altera.com/support/kdb/solutions/rd04092009_699.html Automatic Clock Switchover The PLL Automatic Clock Switchover feature may fail to operate correctly on Stratix IV E ES devices when the two clocks are running different frequencies. If both clocks are running at the same frequency, there is no impact to your design. The following modes are affected: ■ Automatic ■ Automatic with Manual Override You may observe two possible issues: 1 ■ Switchover from inclk0 to inclk1, even though inclk0 is active (and vice-versa) ■ clkbad[0,1] status signals may glitch, even if the input clocks are active Manual clock switchover mode operates correctly as expected and is not affected. This issue is fixed in production devices. CRC Error Detection Feature The CRC Error Detection feature, when you enable single event upset (SEU) detection, may cause the MLAB RAM blocks to operate incorrectly in Stratix IV E ES devices. Write operations in MLAB RAM blocks are affected with all CRC Error Detection divisor settings. 1 The CRC Error Detection feature operates correctly as expected. FPGA configuration bits are not affected by this issue. Disabling the CRC Error Detection feature in your design compilation with the Quartus II software prevents this issue from occurring in Stratix IV E ES devices. This issue is fixed in production devices. f You can download a software patch to help with the CRC Error Detection feature issue at: http://www.altera.com/support/kdb/solutions/rd04092009_699.html Errata Sheet for Stratix IV E Devices June 2012 Altera Corporation Page 10 Stratix IV E ES Device Issues Higher VCC Power Supply Levels Stratix IV E ES devices require higher VCC power supply levels (Table 3). Table 3. Power Supply Levels for Stratix IV E ES Devices Power Supply Power Supply Level (V) Description VCC 0.95 Core voltage and periphery circuitry power supply VCCD_PLL 0.95 PLL digital power supply EP4SE530 ES devices require VCC and VCCD_PLL power supplies set to 0.95 V ±0.03 V for all speed grades. Use the Stratix IV E PowerPlay EPE version 9.0.1 or later to estimate current and power/thermal requirements for Stratix IV E ES devices with the required higher power supply levels. The Stratix IV E PowerPlay EPE version 9.0 reflects current and power estimates for production devices at data sheet specifications only. Production devices will not operate at these higher power supply levels. If needed, design your power supplies to support dropping power supply levels back to data sheet specification for production devices. There are no reliability issues with Stratix IV E ES devices at these higher power supply levels. I/O Jitter Stratix IV E ES devices may exhibit ± ~100 ps higher than expected jitter on all I/O pins. The actual amount of additional jitter is application and toggle-rate dependent. Altera fixed the issue in production devices, which meet all current jitter specifications. If you are using Stratix IV E ES devices, you need to account for this additional timing uncertainty in all I/O timing closure budgets. Higher Minimum fINPFD Setting Stratix IV E ES devices may exhibit higher than expected PLL jitter at low fINPFD settings. Raising the minimum fINPFD to 25 MHz removes the additional PLL jitter in Stratix IV E ES devices. Altera fixed the issue in production devices, which meet the current fINPFD minimum of 5 MHz. If you are using Stratix IV E ES devices, review your fINPFD settings by searching under “Nominal PFD Frequency” in each PLL section of your .fit.rpt compilation report file. If needed, recompile your design in the Quartus II software with modified PLL settings to achieve the higher minimum fINPFD. f For more information about the ALTPLL megafunction, refer to the Quartus II Handbook or the Phase-Locked Loops (ALTPLL) Megafunction User Guide. June 2012 Altera Corporation Errata Sheet for Stratix IV E Devices Stratix IV E ES Device Issues Page 11 High I/O Pin Leakage Current Top and bottom I/O pin leakage current is higher for Stratix IV E ES devices than production devices. Side I/O banks are not affected. For Stratix IV E ES device I/O pin leakage current on top and bottom I/O banks, refer to Table 4. Table 4. I/O Pin Leakage Current for Top and Bottom I/O Banks I/O Bank Voltage (V) Temperature Units 3.0 2.5 1.8 1.5 1.2 25°C 35 25 15 11 9 A 85°C 140 100 60 45 35 A These I/O pin leakage current values apply to Stratix IV E ES silicon only and not to production silicon. Higher Standby Current for VCC Power Supply You can expect to see higher standby ICC values on the VCC power supply for Stratix IV E ES devices than indicated in the Quartus II software version 9.0 and the Stratix IV E PowerPlay EPE version 9.0. The higher standby ICC current for the VCC power supply is fixed in production devices. Use the Stratix IV E PowerPlay EPE version 9.0.1 or later to estimate current and power/thermal requirements for the Stratix IV E ES device. The Stratix IV E PowerPlay EPE version 9.0 will not be updated with these higher standby current values. Reduced M9K/M144K Performance M9K/M144K fMAX and tCO performance for Stratix IV E ES devices may be lower than indicated in the Quartus II software version 8.1. Compile your design in the Quartus II software version 9.0 or later to estimate the impact on your design. DPA Misalignment Stratix IV E DPA circuitry for Stratix IV E ES devices occasionally become stuck at the initial configured phase or take significantly longer than expected to select the optimum phase. A non-ideal phase may result in data bit errors, even after the DPA lock signal has gone high. Resetting the DPA circuit may not alleviate the problem; in fact, resetting the DPA circuit might trigger the problem. LVDS receivers configured in DPA mode are affected. LVDS receivers configured in soft CDR mode with 0 parts-per-million (ppm) difference (synchronous interface) are also affected. For applications with flexibility in the choice of training patterns, Altera recommends choosing bit sequences with more data transitions and a non-cyclical pattern similar to a PRBS or K28.5 code sequence. For applications using a fixed, cyclical, or data transition sparse training pattern (for example, if you are using the SPI 4.2 protocol, which specifies a training pattern of ten 0s and ten 1s), turn on the DPA PLL Calibration option (available in the Quartus II software version 9.0 and later) in the ALTLVDS MegaWizard™ Plug-In Manager. Errata Sheet for Stratix IV E Devices June 2012 Altera Corporation Page 12 Document Revision History 1 There are two caveats when enabling the DPA PLL Calibration option: ■ PLL merging (merging receiver [RX] and RX or merging RX and transmitter [TX] PLL) is not automatically supported by the ALTLVDS megafunction; use the external PLL option to handle PLL merging separately. ■ Timing for all PLL outputs is pulled in by 1/4 of the voltage controlled oscillator (VCO) phase during the PLL calibration process. This different timing must be taken into account for external I/O pin timing interfaces and for clock domain transfers (without a FIFO) when the clocks are not all from this same PLL. f For more information about the DPA PLL Calibration option, refer to the LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide planned release corresponding to the Quartus II software version 9.0. Until the User Guide is updated, in the interim, file a service request using mySupport. Document Revision History Table 5 lists the revision history for this Errata Sheet. Table 5. Document Revision History (Part 1 of 2) Date Version Changes June 2012 3.0 Changed Table 2 wording to list “Production devices” only in Planned Fixed column. February 2012 2.9 Changed Stratix V reference to Stratix IV in Table 1. December 2011 2.8 Added the “PLL phasedone Signal Stuck at Low” section. September 2011 2.7 June 2011 2.6 Added the “EDCRC False Errors” section. March 2011 2.5 Update the “I/O Jitter” section of Table 1. January 2011 2.4 May 2010 April 2010 January 2010 June 2012 Altera Corporation 2.3 ■ Added the “Remote System Upgrade” section. ■ Minor text edits. ■ Updated the “Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK Frequency” section. ■ Converted to the new template. ■ Added the “I/O Jitter” section. ■ Added “Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK Frequency” ■ Added “FPP Mode Configuration Failures When the Minimum Hold Time (tDH) is set to 0 ns or 24 ns” ■ Updated “DPA Misalignment” and removed this issue from Production devices section ■ Updated “Higher Power Supply Current During Power-Up for VCCPD” ■ Updated “Stratix IV E Power-up Sequencing on Production Devices”. ■ Added “DPA Misalignment” section to production devices. 2.2 2.1 Errata Sheet for Stratix IV E Devices Document Revision History Page 13 Table 5. Document Revision History (Part 2 of 2) Date Version Changes Added: November 2009 2.0 ■ “Stratix IV E Production Device Issues” ■ “M144K RAM Block Lock-Up” ■ “Stratix IV E Power-up Issue on Production Devices” Updated the following with link to software patch: ■ “M144K Write with Dual-Port Dual-Clock Modes” ■ “CRC Error Detection Feature” Updated with fix in “Automatic Clock Switchover”. August 2009 June 2009 1.1 1.0 Errata Sheet for Stratix IV E Devices Added “Remote System Upgrade” ■ M9K/M144K RAM Block Lock-up ■ CRC Error Injection Feature ■ Higher Power Supply Current During Power-Up for VCCPD ■ M144K Write with Dual-Port Dual-Clock Modes ■ Automatic Clock Switchover ■ CRC Error Detection Feature ■ Higher VCC Power Supply Levels ■ I/O Jitter ■ Higher Minimum fINPFD Setting ■ High I/O Pin Leakage Current ■ Higher Standby Current for VCC Power Supply ■ Reduced M9K/M144K Performance ■ DPA Misalignment June 2012 Altera Corporation Page 14 June 2012 Document Revision History Altera Corporation Errata Sheet for Stratix IV E Devices