EP53A8HQI

EP53A8LQI/EP53A8HQI 1000mA Synchronous Buck Regulator with Integrated Inductor RoHS Compliant; Halogen Free Description Features The EP53A8LQI and EP53A8HQI are a 1000mA PowerSOC. The device integrates MOSFET switches, control, compensation, and the Inductor in an advanced 3mm x 3mm QFN Package. • Integrated Inductor Technology • 3mm x 3mm x 1.1mm QFN package • Total Solution Footprint ~ 21mm2 • Low VOUT ripple for RF compatibility Integrated inductor ensures the complete power solution is fully characterized with the inductor carefully matched to the silicon and compensation network. . It enables a tiny solution footprint, low output ripple, low part-count, and high reliability, while maintaining high efficiency. The complete solution can be implemented in as little as 21mm2. • High efficiency, up to 94% • 1000mA continuous output current • Less than 1µA standby current • 5 MHz switching frequency • 3 pin VID for glitch free voltage scaling • VOUT Range 0.6V to VIN – 0.5V The EP53A8xQI uses a 3-pin VID to easily select the output voltage setting. Output voltage settings are available in 2 optimized ranges providing coverage for typical VOUT settings. • Short circuit and over current protection • UVLO and thermal protection • IC level reliability in a PowerSOC solution The VID pins can be changed on the fly for fast dynamic voltage scaling. EP53A8LQI further has the option to use an external voltage divider. 3.5mm 4.7uF Application • Portable wireless and RF applications • Wireless broad band data cards • Solid state storage applications • Noise and space sensitive applications 100 Ohm 100 ohm VIN 6mm EP53A8xQI PVIN VOUT AVIN VSENSE ENABLE 4.7µF 0603 VFB VS0 VOUT 10µF 0805 VS1 VS2 PGND AGND 10uF Figure 1: Total Solution Footprint. Figure 2: Typical Application Circuit. www.enpirion.com 03651 12/16/2009 Rev:B EP53A8LQI/EP53A8HQI Ordering Information Part Number Comment Package EP53A8LQI LOW VID Range 16-pin QFN T&R EP53A8HQI HIGH VID Range 16-pin QFN T&R EP53A8LQI-E EP53A8LQI Evaluation Board EP53A8HQI-E EP53A8HQI Evaluation Board Pin Assignments (Top View) Figure 3: EP53A8LQI Pin Out Diagram (Top View) PIN NAME 1, 15, 16 NC(SW) 2,3 PGND 4 VFB 5 VSENSE 6 AGND 7, 8 VOUT 9, 10, 11 VS2, VS1, VS0 12 13 14 ENABLE AVIN PVIN FUNCTION NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device. Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors. EP53A8LQI: Feed back pin for external divider option. EP53A8HQI: No Connect Sense pin for preset output voltages. Refer to application section for proper configuration. Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider Regulated Output Voltage. Refer to application section for proper layout and decoupling. Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11. EP53A8LQI: Selects one of seven preset output voltages or an external resistor divider. EP53A8HQI: Selects one of eight preset output voltages. (Refer to section on output voltage select for more details.) Output Enable. Enable = logic high; Disable = logic low Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor. Input Voltage for the MOSFET switches. ©Enpirion 2009 all rights reserved, E&OE 03651 Figure 4: EP53A8HQI Pin Out Diagram (Top View)Pin Description 2 12/16/2009 www.enpirion.com Rev:B EP53A8LQI/EP53A8HQI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS VIN -0.3 6.0 V Voltages on: ENABLE, VSENSE, VSO – VS2 -0.3 VIN+ 0.3 V Voltages on: VFB (EP53A8LQI) -0.3 2.7 V 150 °C 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C 260 °C ESD Rating (based on Human Body Mode) 2000 V Input Supply Voltage Maximum Operating Junction Temperature TJ-ABS Storage Temperature Range TSTG -65 Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range VIN 2.4 5.5 V Operating Ambient Temperature TA - 40 +85 °C Operating Junction Temperature TJ - 40 +125 °C Thermal Characteristics PARAMETER Thermal Resistance: Junction to Ambient –0 LFM (Note 1) Thermal Overload Trip Point Thermal Overload Trip Point Hysteresis SYMBOL TYP UNITS θJA 85 °C/W TJ-TP +155 °C 25 °C Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards ©Enpirion 2009 all rights reserved, E&OE 03651 3 12/16/2009 www.enpirion.com Rev:B EP53A8LQI/EP53A8HQI Electrical Characteristics NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V. CIN = -4.7µF 0603 MLCC, COUT = 10µF 0805 MLCC PARAMETER SYMBOL Operating Input Voltage VIN Under Voltage Lock-out – VIN Rising VUVLO_R 2.0 V Under Voltage Lock-out – VIN Falling VUVLO_F 1.9 V Drop Out Resistance RDO Input to Output Resistance Output Voltage Range VOUT EP53A8LQI (VDO = ILOAD X RDO) EP53A8HQI Dynamic Voltage Slew Rate VSLEW EP53A8HQI EP53A8LQI ∆VOUT TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V -2 Feedback Pin Voltage Initial Accuracy VFB TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V .588 Line Regulation ∆VOUT_LINE 2.4V ≤ VIN ≤ 5.5V 0.03 %/V Load Regulation ∆VOUT_LOAD 0A ≤ ILOAD ≤ 1000mA 0.6 %/A Temperature Variation ∆VOUT_TEMPL -40°C ≤ TA ≤ +85°C 30 ppm/°C Output Current IOUT Shut-down Current ISD Enable = Low OCP Threshold ILIM 2.4V ≤ VIN ≤ 5.5V 0.6V ≤ VOUT ≤ 3.3V VS0-VS2, Pin Logic Low VVSLO 0.0 0.3 V VS0-VS2, Pin Logic High VVSHI 1.4 VIN V VS0-VS2, Pin Input Current IVSX Enable Pin Logic Low VENLO Enable Pin Logic High VENHI Enable Pin Current IENABLE Note 1