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AN822: Intel® FPGA Configuration Device Migration Guideline Subscribe Send Feedback AN-822 | 2018.03.30 Latest document on the web: PDF | HTML Contents Contents 1 Intel® FPGA Configuration Device Migration Guideline.....................................................3 1.1 Migration Considerations..........................................................................................3 1.2 Software Migration Guidelines.................................................................................. 5 1.2.1 IP Core Compatibility.................................................................................. 5 1.2.2 Programming File Compatibility.................................................................... 6 1.2.3 IP Core and Programming File Migration Guideline...........................................7 1.2.4 Software Support for EPCQ-A Devices............................................................9 1.3 Specification Comparison.........................................................................................9 1.3.1 Operating Conditions................................................................................. 10 1.3.2 Timing Specifications.................................................................................10 1.3.3 Operation Codes....................................................................................... 13 1.3.4 Pin Information.........................................................................................15 1.3.5 Package Dimensions..................................................................................17 1.3.6 Status Register......................................................................................... 20 1.4 Evaluating Data Setup and Hold Timing Slack........................................................... 23 1.5 Document Revision History for AN 822: Intel FPGA Configuration Device Migration Guideline......................................................................................................... 25 AN822: Intel® FPGA Configuration Device Migration Guideline 2 AN-822 | 2018.03.30 1 Intel® FPGA Configuration Device Migration Guideline This document describes the guidelines for migrating from the Serial Configuration (EPCS) and Quad-Serial Configuration (EPCQ) devices to the Quad-Serial Configuration (EPCQ-A) devices. Related Links • Serial Configuration (EPCS) Devices Datasheet • Quad-Serial Configuration (EPCQ) Devices Datasheet • Quad-Serial Configuration (EPCQ-A) Devices Datasheet 1.1 Migration Considerations The EPCQ-A devices are conditionally compatible for a direct migration from EPCQ and EPCS devices. You must consider the following items to determine the compatibility and the next step of action for a successful device migration. IP Cores If you are using Intel® IP cores, you may need to regenerate and recompile your design. In certain conditions, the programming files can be reused without recompilation. Refer to IP Core Compatibility on page 5 for more information about IP core compatibility. Refer to Table 3 on page 6 if you are not using IP cores that interface with the configuration device. Pins, Package and Capacity Migration can only be done to an EPCQ-A device that has sufficient capacity for the programming file and have the same pin count package. Pin 3 (nRESET) on the EPCQ64A and EPCQ128A devices act as a reset pin. This pin has an internal pull-up, and if you do not use the reset function, connect the nRESET pin to either VCC or leave it unconnected. Refer to Pin Information on page 15 for more information about the pin-outs and descriptions. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered 1 Intel® FPGA Configuration Device Migration Guideline AN-822 | 2018.03.30 Figure 1. EPCS to EPCQ Migration Pin Package and Capacity Summary To EPCQ-A Variant From EPCS From EPCQ EPCQ4A1 EPCQ16A EPCQ32A EPCQ64A EPCQ128A EPCS1 Yes Yes Yes No No EPCS4 Yes Yes Yes No No EPCS16 Yes 2 Yes Yes No No EPCS64 No No No Yes Yes EPCS128 No No No Yes 2 Yes EPCQ16 No Yes Yes No No EPCQ32 No Yes 2 Yes No No EPCQ64 No No No Yes Yes EPCQ128 No No No Yes 2 Yes Note: 1. EPCQ4A devices support Active Serial x1 configuration only. 2. Migration is compatible only if the destination EPCQ-A device has the sufficient capacity for the programming file. Operation Commands The dummy clock requirement of the fast read (0Bh) and extended quad input fast read (EBh) commands: • EPCQ—the dummy clock is configurable with the non-volatile configuration register (NVCR). When the EPCQ is used with a Cyclone® V, Arria® V or Stratix® V device, the dummy clock is configured to be 4, 10 or 12, depending on the byteaddressing mode and ASx1 or ASx4 configuration. However, in EPCQ-A devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you must regenerate the programming files, such as .pof, .jic, and .rpd. • EPCS—the dummy clock is fixed at 8 for fast read, therefore you do not have to regenerate the programming files if all other conditions are met. Table 3 on page 6 defines the need to regenerate the programming files. Refer to IP Core and Programming File Migration Guideline on page 7 for more information about the conditions. Status Register Status Register contains the Top/Bottom (TB) bit (bit 5), Block Protect (BP) bits (bit 4, bit 3, bit 2) for sector protection bits. EPCS devices do not have TP bit and some EPCQ device densities have BP3 (bit 6), while bit 6 is reserved in EPCQ-A devices. Due to this differences, you may need to recompile the programming file if your design uses the sector protect feature. Refer to Status Register on page 20 for more information about status registers and sector protect bits. AN822: Intel® FPGA Configuration Device Migration Guideline 4 1 Intel® FPGA Configuration Device Migration Guideline AN-822 | 2018.03.30 Sector Size All of the EPCS, EPCQ and EPCQ-A devices have the sector size of 512kb except for EPCS128 which has 2Mb. This impacts the sector erase operation. If the design is erasing the flash during user mode, you must update your design to comply the sector size when migrating from EPCS128 to EPCQ128A. After updating your design, regenerate a new programming file for the EPCQ-A device. 1.2 Software Migration Guidelines 1.2.1 IP Core Compatibility Table 1. EPCS to EPCQ-A Device Migration IP Core Compatibility IP Core Compatibility Condition ASMI Parallel Yes/No • Serial Flash Controller Yes/No • Serial Flash Loader (SFL) Yes/No • • Remote Update Table 2. If sector protect is used, refer to Sector Protect on page 20 to determine compatibility. EPCS128 has different sector size than EPCQ128A, not compatible if sector erase is used. Compatible for Cyclone V, Arria V and Stratix V devices. For devices earlier than Cyclone V, Arria V and Stratix V, it is compatible if the Enhanced SFL(1) is enabled. Yes EPCQ to EPCQ-A Device Migration IP Core Compatibility IP Core Compatibility ASMI Parallel Yes/No Condition • • ASMI Parallel II No — Serial Flash Controller No — Serial Flash Controller II No — Generic QSPI Controller No — Generic QSPI Controller II No — Yes/No • • Yes — Serial Flash Loader Remote Update If sector protect is used, refer to sector protect table comparison to determine compatibility. Not compatible if read dummy clock is enabled. Compatible for Cyclone V, Arria V and Stratix V devices. For devices earlier than Cyclone V, Arria V and Stratix V, it is compatible if the Enhanced SFL(1) is enabled. Related Links (1) • Altera Remote Update IP Core User Guide • Altera ASMI Parallel IP Core User Guide • Converting .sof to .jic Files in the Quartus Prime Software Enhanced SFL is an option available in the Serial Flash Loader IP core when using with devices earlier than Cyclone V, Arria V and Stratix V. AN822: Intel® FPGA Configuration Device Migration Guideline 5 1 Intel® FPGA Configuration Device Migration Guideline AN-822 | 2018.03.30 • Programming Serial Configuration Devices Using the Quartus Prime Programmer and .jic Files 1.2.2 Programming File Compatibility Note: This section describes programming file compatibility for designs without Intel FPGA IP cores. List of supported programming files: Table 3. • Programmer Object File (.pof) • JTAG Indirect Configuration File (.jic) • Raw Programming Data (.rpd) • STAPL File (.jam/.jbc) • Serial Vector Format (.svf) Programming File Compatibility Guide Note: Device Family Legacy FPGA devices For designs that do not contain IP cores which interface with the configuration device, depending upon the FPGA family and configuration scheme implemented, the existing programming files may be compatible with EPCQ-A devices without the need to regenerate the programming files. Original Configuration Device EPCS Configuration Device Density 64Mb & below 128Mb EPCQ Any Programming Files supported Disable EPCS/ EPCQ ID check Setting Compatible with EPCQA(2)(3) .pof/.jic/.rpd/.jam/.jbc Any Yes .svf Any Yes(4) .pof/.jic/.rpd Any Yes(5) .svf Any Yes(4) .jam/.jbc Any No(6) .pof/.jic/.rpd/.jam/.jbc On(7) Yes continued... (2) Table assumes other compatibility considerations are satisfied. (3) Table assumes the programming files do not contain any ASMI Parallel IP or Serial Flash Loader IP. (4) Only supported for .svf files generated for EPCS devices to be used to program an EPCQ-A, and not the other way round. (5) In .rpd file, the binary data is the same between EPCS128 and EPCQ128A. However due to different sector size, a proper erasing procedure is required when programming each device. (6) Due to different sector size, the .jam/.jbc file is different between EPCS and EPCQ. (7) In Intel Quartus® Prime version 15.1 or later, automatic mode turns on this option automatically. AN822: Intel® FPGA Configuration Device Migration Guideline 6 1 Intel® FPGA Configuration Device Migration Guideline AN-822 | 2018.03.30 Device Family Original Configuration Device Cyclone V, Arria V, and Stratix V devices EPCS Configuration Device Density 64Mb & below 128Mb EPCQ(9) Any Programming Files supported Disable EPCS/ EPCQ ID check Setting Compatible with EPCQA(2)(3) .svf On(7) Yes(4) .pof/.jic/.rpd/.jam/.jbc On(8) Yes .svf On(8) Yes(4) .pof/.jic/.rpd On(8) Yes(5) .svf On(8) Yes(4) .jam/.jbc Any No(6) Any Any No Refer to IP Core and Programming File Migration Guideline on page 7 for more information about guidelines on incompatible programming files. 1.2.3 IP Core and Programming File Migration Guideline Note: This section describes programming file compatibility for designs with Intel FPGA IP cores that interface with the configuration device. Refer to the following diagram to determine the subsequent tasks and guidelines for migration: • IP core and programming file are incompatible—regenerate IP core and programming file shown in IP Core Regeneration Guideline on page 8. • Programming file is incompatible—regenerate programming file shown in Programming File Regeneration Guideline on page 9. • IP core and programming file are compatible—no additional task required and you can reuse the existing programming file. (2) Table assumes other compatibility considerations are satisfied. (3) Table assumes the programming files do not contain any ASMI Parallel IP or Serial Flash Loader IP. (8) Other than Intel Quartus Prime version 13.0 to 15.0, automatic mode turns on this option automatically. (9) EPCQ programming files are not compatible with EPCQ-A in AS x1 or AS x4 modes. AN822: Intel® FPGA Configuration Device Migration Guideline 7 1 Intel® FPGA Configuration Device Migration Guideline AN-822 | 2018.03.30 Figure 2. IP Core and Programming File Compatibility Flow Chart Start IP core is compatible?1 No Yes EPCS EPCQ Cyclone V, Arria V or Stratix V? Yes Regenerate IP core and programming file No Yes Use sector protect? Size