DataSheeT – enpirion® power solutions
EZ6301QI Triple Output Module
1.5A DC-DC Buck Module with 2 x 300mA LDOs
DESCRIPTION
FEATURES
The EZ6301QI is a triple output PowerSoC with one
buck and two low drop-out (LDO) regulators. It has
three separated inputs and outputs. The DC-DC buck
can support up to 1.5A of continuous output current
while the other two outputs are separated 300mA
LDOs.
• Integrated 1.5A Buck Module with 2x300mA LDO
The EZ6301QI employs Intel Enpirion’s lateral
MOSFET technology for monolithic integration and
very low switching loss. The DC-DC switches at
2.5MHz in fixed PWM operation to eliminate the low
frequency noise that is created by pulse frequency
modulation operating modes. The MOSFET ratios are
optimized to offer high conversion efficiency for
lower VOUT settings.
The Intel Enpirion power solution significantly helps
in system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
All Enpirion products are ROHS compliant and leadfree manufacturing environment compatible.
CA1
RB1
VFB
RB
POK
VINL2
AGND
VOUTL2
PGND
VFBL2
POKL2
AGND
PGND
VINL2
ENL2
o
LDO (0.9V to 3.3V)
• Pin Compatible with EZ6303QI
• RoHS Compliant, MSL Level 3, 260 °C Reflow
APPLICATIONS
• Intel FPGAs (MAX, ARRIA, CYCLONE, STRATIX)
• All SERDES and IO Supplies Requiring Low Noise
100
95
90
85
80
75
VOUT = 3.3V
70
VOUT = 2.5V
65
CONDITIONS
VIN = 5.0V
60
COUT2
CIN2
Buck (0.6V to 3.3V)
• Over-Current, Short Circuit, Under-Voltage,
Thermal and Pre-Bias Protections
CA
RC
SS
EN
o
• Programmable Soft-Start (buck)
RA
PGND
AGND
LDO (1.6V to 5.5V)
• Independent Output Enables and Power OK Flags
EFFICIENCY (%)
COUT
CSS
o
• Independent Input and Output Terminals
VOUT
EZ6301QI
Buck (2.7V to 6.6V)
Buck Efficiency vs. Output Current
AVIN
PGND
o
• Output Voltage Range
VOUT
10
CIN
• Input Voltage Range
VOUTL1
PGND
VFBL1
AGND
POKL1
PGND
VINL1
ENL1
PVIN
10nF
• Optimized Total Solution Size (120 mm2)
• Applications Needing High Reliability
VOUTL1
COUT1
VIN
• High Efficiency Buck (Up to 96 %)
• Low Power/Space Constrained Applications
RA1
CIN1
VINL1
• Tiny 7mm x 4mm x 1.85mm QFN Package
55
RB2
RA2
VOUT = 1.8V
VOUT = 1.2V
50
VOUTL2
0
CA2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
OUTPUT CURRENT (A)
Figure 1: Simplified Applications Circuit
Figure 2: Efficiency at VIN = 5 V
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
ORDERING INFORMATION
Part Number
Package Markings
TA Rating (°C)
Package Description
EZ6301QI
EZ6301QI
-40 to +85
40-pin (4mm x 7mm x 1.85mm) QFN
EVB-EZ6301QI
EZ6301QI
QFN Evaluation Board
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
NC(SW)
NC(SW)
NC(SW)
NC(SW)
EN
PGTE
BTMP
POK
ENL1
POKL1
POKL2
NC(SW) 1
NC(SW)
PIN FUNCTIONS
40
39
38
37
36
35
34
33
32
31
30
29
KEEP-OUT
NC(SW) 2
4
41 PGND
VOUT 6
13
14
15
16
17
18
19
20
PVIN
AVIN
AGND
VFB
SS
VOUT
12
PGND
11
PGND
10
VOUT
9
VOUT
7
VOUT 8
27
VFBL2
26
VOUTL2
25
VINL2
24
PGND
23
VINL1
22
VOUTL1
21
VFBL1
43 VOUT
VOUT
VOUT
42
PGND
5
VOUT
PGND
ENL2
KEEP-OUT
NC(SW) 3
PGND
28
Figure 3: Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: The dot on top left is pin 1 indicator on top of the device package.
NOTE C: Keep-Out are No Connect pads that should not to be electrically connected to each other or to any external
signal, ground or voltage. They do not need to be soldered to the PCB.
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
PIN DESCRIPTIONS
PIN
NAME
TYPE
FUNCTION
1, 2, 3,
36-40
NC(SW)
-
No Connect. These pins are internally connected to the common
switching node of the internal MOSFETs. They must be soldered to PCB
but not be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in device damage.
4, 5,
14, 15,
24
PGND
Ground
Power ground. Noisy ground for the power stages.
6-13
VOUT
Power
Regulated switching converter output. VOUT needs to be decoupled
towards PGND.
16
PVIN
Power
Input power supply. Connect to input power supply; needs to be
decoupled to PGND.
17
AVIN
Power
Analog Input voltage. This pin has to be connected to PVIN through a
10Ω resistor and decoupled towards AGND.
18
AGND
Power
Analog ground. The quiet ground for the control circuits.
Analog
Feedback input pin for switching converter. The compensation network
and resistor divide are connected to this pin. The output voltage
regulation is based on the VFB node voltage equal to 0.6V.
Analog
Soft start pin. A soft-start capacitor is connected between this pin and
AGND. The value of the capacitor controls the soft-start slew rate for the
DC-DC regulator.
19
20
VFB
SS
21
VFBL1
Analog
LDO1 feedback pin. The compensation/divider network from the LDO
output to ANGD, having the feedback node as mid point. The output
voltage regulation is based on the VFBL1 node voltage equal to 0.9V.
22
VOUTL1
Power
LDO1 regulated converter output. Connect to the load and place output
filter capacitor(s) between these pins and PGND pins.
23
VINL1
Power
LDO1 input power supply. The power supply connected to this pin needs
to be decoupled to PGND.
25
VINL2
Power
LDO2 input power supply. The power supply connected to this pin needs
to be decoupled to PGND.
26
VOUTL2
Power
LDO2 regulated converter output. Connect to the load and place output
filter capacitor(s) between these pins and PGND pins.
27
VFBL2
Analog
LDO2 feedback pin. The compensation/divider network from the LDO
output to ANGD, having the feedback node as mid point. The output
voltage regulation is based on the VFBL2 node voltage equal to 0.9V.
28
ENL2
Analog
LDO2 input enable. Applying logic high enables the output and initiates
soft-start. Applying logic low disables the output.
29
POKL2
Digital
LDO2 Power OK. POKL2 is open drain logic used for power system state
indication. POKL2 is logic high when VOUT is within ±10% of nominal.
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
PIN
NAME
TYPE
FUNCTION
30
POKL1
Digital
LDO1 Power OK. POKL1 is open drain logic used for power system state
indication. POKL1 is logic high when VOUT is within ±10% of nominal.
31
ENL1
Analog
LDO1 input enable. Applying logic high enables the output and initiates a
soft-start. Applying logic low disables the output.
32
POK
Digital
Switcher power OK. POK is open drain logic used for power system state
indication. POK is logic high when VOUT is within ±10% of nominal.
33
BTMP
-
Bottom Plate connection for internal PGTE. This pin has to be soldered to
the PCB but has to be left floating.
34
PGTE
-
PMOS Gate. This pin has to be soldered to the PCB but has to be left
floating.
35
EN
Analog
Switcher Enable. Applying logic high enables the output and initiates a
soft-start. Applying logic low disables the output.
Ground
Not perimeter pins. Device thermal pads to be connected to the system
GND plane for heat-sinking purposes. Covered in the Layout
Recommendation section.
41, 42
PGND
43
VOUT
Not perimeter pins. Device thermal pads to be connected to the system
VOUT plane for heat-sinking purposes. Covered in the Layout
Recommendation section.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
MIN
MAX
UNITS
PVIN, AVIN, VINL1, VINL2,
VOUTL1, VOUTL2
-0.3
7.0
V
EN, ENL1, ENL2, POK, POKL1,
POKL2
-0.3
VIN+0.3
V
VFB, SS
-0.3
2.7
V
PGTE
VIN – 2.7V
VIN
-
BTMP
0
2.7
V
7.0
V
10.5
V
NC(SW) Voltage DC
NC(SW) Voltage Peak < 5ns
SYMBOL
VSW
VSW_PEAK
-2.0
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
MIN
Maximum Operating Junction
Temperature
Storage Temperature Range
Reflow Peak Body
Temperature
-65
(10 Sec) MSL3 JEDEC J-STD-020A
MAX
UNITS
+150
°C
+150
°C
+260
°C
MAX
UNITS
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.7
6.6
V
LDO Input Voltage Range
VINL1,2
1.6
5.5
V
DC-DC Output Voltage Range
VOUT
0.6
VIN – VDO (1)
V
VOUTL1/2
0.9
3.3
V
Switcher Input Voltage Range
LDO Output Voltage Range
DC/DC Output Current Range
IOUT
1.5
A
LDO1/2 Output Current Range
IOUT_LDO
0.3
A
Operating Ambient Temperature Range
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
Thermal Shutdown
TSD
155
°C
Thermal Shutdown Hysteresis
TSDH
20
°C
Thermal Resistance: Junction to Ambient (0 LFM) (2)
JA
11.5
°C/W
Thermal Resistance: Junction to Case (0 LFM)
JC
1
°C/W
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
ELECTRICAL CHARACTERISTICS
NOTE: VIN = 5V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25 °C.
PARAMETER
Operating Input
Voltage (Switcher)
SYMBOL
VIN
TEST CONDITIONS
MIN
PVIN = AVIN
2.7
TYP
MAX
UNITS
6.6
V
Under Voltage LockOut – VIN Rising
VUVLOR
Voltage above which UVLO is
not asserted
2
2.3
2.6
V
Under Voltage LockOut – VIN Falling
VUVLOF
Voltage below which UVLO is
asserted
1.7
2.1
2.5
V
Under Voltage LockOut Hysteresis
250
Buck Shut-Down
Current
IS
EN = ENL1 = ENL2 = 0V
Operating Quiescent
Current
IQ
AVIN only
No Load Quiescent
Current
IVINQ
DC-DC Initial VFB Pin (3)
Voltage Accuracy
VFB
VFB
Feedback Pin Input
Leakage Current (4)
IFB
Soft Start Capacitance
Range (4)
PVIN and AVIN
TA = 25°C
900
A
14
mA
24
VOUT = 1.2V
No Load
680
mA
0.597
0.6
0.603
V
0.591
0.6
0.609
V
2.7V ≤ VIN ≤ 6.6V
DC-DC VFB Pin (3)
Voltage (Line, Load and
Temperature)
VOUT Rise Time Range (4)
500
mV
0A ≤ ILOAD ≤ 1.5A
-40°C ≤ TA ≤ 85°C
tRISE
VFB pin input leakage current
-10
10
nA
Capacitor programmable
0.65
6.5
ms
10
100
nF
CSS_RANGE
Soft-Start Charging
Current
ISS
Buck Dropout
Resistance (4)
RDO
Input to output resistance
170
255
m
Drop-Out Voltage(4)
VDO
VINMIN-VOUT at full load (1.5A)
255
383
mV
DC-DC Continuous
Output Current
IOUT
1.5
A
9
0
µA
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
PARAMETER
Buck Over Current Trip
Level
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IOCP
VIN = 5V, VOUT = 1.2V
1.8
2.45
3.1
A
Current Limit Retry
Time
TCL_TRY
Precision Disable
Threshold
VDISABLE
EN pin logic going low
0.97
1.03
1.07
V
Precision Enable
Threshold
VENABLE
EN pin logic going high
1.1
1.14
1.17
V
Enable Hysteresis
ENHYS
6.5
ms
110
mV
45
µA
EN Pin Input Current
IEN
EN pin has 159kΩ pull-down
Switching Frequency
(Free Running)
FSW
Free running frequency of
oscillator
POK High Range
POKRANGE
Typical percentage range
within VOUT nominal when
POK is asserted high
POK Low Voltage
VPOKL_B
With 4mA current sink into
POK
0.4
V
POK High Voltage
VPOKH_B
2.5V ≤ VIN ≤ 6.6V
VIN
V
POK Pin Leakage
Current (4)
IPOKH_B
POK is high
1
µA
Operating Input
Voltage (LDO)
VIN
PVIN = AVIN
5.5
V
LDO Shut-Down Supply
Current
ISL
EN = ENL1 = ENL2 = 0V
30
40
A
LDO Quiescent Current
(LDO1 or LDO2)
IQLDO
No resistor divider on the
output.
200
450
A
LDO Dropout
Resistance (4)
RDOL
Input to output resistance
250
m
LDO Drop-Out
Voltage(4)
VLDO_DO
VINMIN-VOUT at full load
(300mA)
75
mV
LDO Over Current Trip
Level
IOCPL
VIN = 5V, VOUT = 1.2V
LDO VFBL1,2 Pin
Voltage (Line, Load and
Temperature)
VFBL1,2
2.25
2.5
2.75
±10
MHz
%
Linear Regulators
1.6V ≤ VIN ≤ 5.5V
0A ≤ ILOAD ≤ 0.3A
1.6
400
600
800
mA
0.8865
0.9
0.9135
V
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LDO Precision Disable
Threshold
VDISABLEL
EN pin logic going low
0.97
1.03
1.07
V
LDO Precision Enable
Threshold
VENABLEL
EN pin logic going high
1.1
1.14
1.17
V
LDO Enable Hysteresis
ENHYSL
110
mV
LDO ENL1 or ENL2
Input Current
IENL1, IENL2
ENL1,2 pin has 159kΩ pulldown
45
µA
LDO POK High Range
POKLRANGE
Typical percentage range
within VOUT nominal when
POK is asserted high
±10
%
LDO POK Low Voltage
VPOKL_L
With 4mA current sink into
POK
0.4
V
LDO POK High Voltage
VPOKH_L
2.5V ≤ VIN ≤ 6.6V
VIN
V
LDO POK Pin Leakage
Current (4)
IPOKH_L
POK is high
1
µA
LDO PSRR(4)
PSRR
100Hz
48
dB
10kHz
34
dB
50kHz
20
dB
(3) The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
(4) Parameter not production tested but is guaranteed by design.
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
TYPICAL PERFORMANCE CURVES
Buck Power Loss VIN = 2.7V
Buck Efficiency VIN = 2.7V
0.45
90
0.4
85
0.35
Power Loss (W)
0.5
95
EFFICIENCY (%)
100
80
75
70
VOUT = 2.5V
65
VOUT = 1.8V
60
VOUT = 1.8V
VOUT = 1.2V
0.3
0.25
0.2
0.15
0.1
VOUT = 1.2V
55
VOUT = 2.5V
0.05
0
50
0
0.25
0.5
0.75
1
1.25
0
1.5
0.25
Buck Efficiency VIN = 3.3V
1
1.25
1.5
Buck Power Loss VIN = 3.3V
0.5
95
0.45
90
0.4
85
0.35
Power Loss (W)
100
80
75
70
VOUT = 2.5V
65
VOUT = 1.8V
60
VOUT = 1.2V
55
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
0.3
0.25
0.2
0.15
0.1
0.05
50
0
0
0.25
0.5
0.75
1
1.25
1.5
0
0.25
OUTPUT CURRENT (A)
0.5
0.75
1
1.25
1.5
OUTPUT CURRENT (A)
Buck Efficiency VIN = 5V
Buck Power Loss VIN = 5V
0.5
95
0.45
VOUT = 3.3V
90
0.4
VOUT = 2.5V
85
0.35
VOUT = 1.8V
0.3
VOUT = 1.2V
Power Loss (W)
100
EFFICIENCY (%)
0.75
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY (%)
0.5
80
75
0.25
70
VOUT = 3.3V
65
VOUT = 2.5V
60
VOUT = 1.8V
0.1
55
VOUT = 1.2V
0.05
50
0.2
0.15
0
0
0.25
0.5
0.75
1
1.25
1.5
OUTPUT CURRENT (A)
0
0.25
0.5
0.75
1
1.25
1.5
OUTPUT CURRENT (A)
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
Buck VOUT vs. Output Current
Buck VOUT vs. Output Current
0.606
CONDITIONS
VOUT = 0.6V
VIN as listed
0.602
0.6
0.598
0.596
3
5
0.594
0
CONDITIONS
VOUT = 1.2V
VIN as listed
1.208
BUCK VOLTAGE (V)
BUCK VOLTAGE (V)
0.604
3.5
5.5
4
6
0.5
4.5
6.5
1.203
1.198
1.193
3
5
1.188
1
0
1.5
0.5
4
6
4.5
6.5
1
1.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Buck VOUT vs. Output Current
Buck VOUT vs. Output Current
2.525
1.817
CONDITIONS
VOUT = 1.8V
VIN as listed
1.807
1.802
1.797
1.792
1.787
3
5
1.782
0
CONDITIONS
VOUT = 2.5V
VIN as listed
2.515
BUCK VOLTAGE (V)
1.812
BUCK VOLTAGE (V)
3.5
5.5
3.5
5.5
4
6
0.5
4.5
6.5
1
2.505
2.495
2.485
3
5
2.475
1.5
0
3.5
5.5
0.5
OUTPUT CURRENT (A)
4
6
4.5
6.5
1
1.5
OUTPUT CURRENT (A)
LDO VOUT vs. Output Current
Buck VOUT vs. Output Current
0.909
0.907
CONDITIONS
VOUT = 3.3V
VIN as listed
3.317
LDO VOLTAGE (V)
BUCK VOLTAGE (V)
3.327
3.307
3.297
3.287
3.277
4
4.5
5
5.5
6
CONDITIONS
VOUT = 0.9V
0.905
VIN as listed
0.903
0.901
0.899
0.897
0.895
0.893
6.5
2
4
0.891
3.267
0
0.5
1
1.5
0
2.5
4.5
0.05
0.1
3
5
0.15
0.2
3.5
5.5
0.25
0.3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
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Advance Datasheet | Intel Enpirion® Power Solutions: EZ6301QI
TYPICAL PERFORMANCE CURVES (CONTINUED)
LDO VOUT vs. Output Current
1.01
1.82
CONDITIONS
VOUT = 1.0V
1.008
1.006
VIN as listed
1.004
1.002
1
0.998
0.996
0.994
2
4
0.992
0.99
0
2.5
4.5
0.05
0.1
CONDITIONS
VOUT = 1.8V
1.815
LDO VOLTAGE (V)
LDO VOLTAGE (V)
LDO VOUT vs. Output Current
3
5
0.15
0.25
VIN as listed
1.805
1.8
1.795
1.79
1.785
3.5
5.5
0.2
1.81
2.5
4.5
1.78
0.3
0
0.05
OUTPUT CURRENT (A)
VIN as listed
2.51
2.505
2.5
2.495
2.49
2.485
2.48
3
3.5
4
4.5
5
0.25
0.3
VIN as listed
3.31
3.3
3.29
3.28
3.27
5.5
2.475
3.5
4
4.5
5
5.5
3.26
0
0.05
0.1
0.15
0.2
0.25
0.3
0
OUTPUT CURRENT (A)
0.15
0.2
0.25
0.3
PSRR
CONDITIONS
VIN = 5.5V
VOUT = 2.5V
LOAD = 0.3A
COUT = 10µF
50
PSRR (dB)
40
0.1
60
CONDITIONS
VIN = 5.5V
4V
VOUT = 1V
LOAD = 0.2A
0.1A
COUT = 10µF
50
0.05
OUTPUT CURRENT (A)
PSRR
60
PSRR (dB)
0.2
CONDITIONS
VOUT = 3.3V
3.32
LDO VOLTAGE (V)
LDO VOLTAGE (V)
2.515
0.15
4
2
LDO VOUT vs. Output Current
3.33
CONDITIONS
VOUT = 2.5V
2.52
0.1
3.5
5.5
OUTPUT CURRENT (A)
LDO VOUT vs. Output Current
2.525
3
5
30
20
40
30
20
10
10
0
0
100
1000
10000
100000
FREQUENCY (Hz)
1000000
100
1000
10000
100000
FREQUENCY (Hz)
1000000
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TYPICAL PERFORMANCE CURVES (CONTINUED)
MAXIMUM OUTPUT CURRENT (A)
CONDITIONS
VIN = 5.5V
VOUT = 3.3V
LOAD = 0.2A
COUT = 10µF
50
PSRR (dB)
No Thermal Derating
PSRR
60
40
30
20
10
0
100
1000
10000
100000
FREQUENCY (Hz)
1000000
1.5
1.3
1.0
0.8
CONDITIONS
TJMAX = 125°C
θJA = 10°C/W
No Air Flow
Buck loss: 0.5W
LDO loss: 2.7W
BUCK
LDO1+LDO2
0.5
0.3
0.0
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
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TYPICAL PERFORMANCE CHARACTERISTICS
Buck Output Voltage Ripple
Buck Output Voltage Ripple
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1.2V
COUT = 47µF
No Load
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1.8V
COUT = 47µF
No Load
Buck Startup and Shutdown
Buck Startup and Shutdown
EN
EN
CONDITIONS
VIN = 5V
VOUT = 2.5V
COUT = 47µF
CSS = 15nF
No Load
VOUT
CONDITIONS
VIN = 5V
VOUT = 2.5V
COUT = 47µF
CSS = 15nF
1.5A
VOUT
POK
POK
LOAD
LOAD
LDO Startup and Shutdown
LDO Startup and Shutdown
ENLx
ENLx
VOUTLx
POKLx
VOUTLx
CONDITIONS
VIN = 5V
VOUT = 1V
No Load
CONDITIONS
VIN = 5V
VOUT = 1V
300mA
POKLx
LOAD
LOAD
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Buck Load Transient 0 to 1.5A
Buck Load Transient 0 to 1.5A
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1.2V
CA = 33pF
COUT = 47µF/0805
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 3.3V
CA = 27pF
COUT = 47µF/0805
LOAD
LOAD
LDO Load Transient 0 to 300mA
Buck Short Circuit Recovery
VOUTLx
(AC Coupled)
POK
CONDITIONS
VIN = 5V
VOUT = 1V
COUT = 10µF
VOUT
CONDITIONS
VIN = 5V
VOUT = 1V
COUT = 47µF
SW
LOAD
LOAD
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FUNCTIONAL BLOCK DIAGRAM
PVIN
NC(SW)
POK
DCDC Control
and Protection
EN
Driver and
Shoot
Through
Protection
SS
VOUT
159k
PGND
Reference
VFB
AVIN
AGND
VINL1
POKL1
ENL1
159k
LDO 1
Control and
Protection
Reference
VOUTL1
VFBL1
VINL2
LDO 2
Control and
Protection
159k
ENL2
POKL2
VOUTL2
VFBL2
Figure 4: Functional Block Diagram
FUNCTIONAL DESCRIPTION
Synchronous Buck Converter
The EZ6301QI is a synchronous, programmable power supply with integrated power MOSFET switches,
integrated inductor and two LDOs. The nominal input voltage range for the buck converter is 2.7V to 6.6V and
1.6V to 5.5V for the LDOs. The output voltage for all three rails can be programmed using external resistor
divider networks. The buck converter uses a voltage-mode type III compensation network. Much of the
compensation circuitry is internal to the device; however, a phase lead capacitor is required along with the
output voltage feedback resistor divider to complete the type III compensation network. The device uses a
low-noise PWM topology. Up to 1.5A of continuous output current can be drawn from this converter. The
2.5MHz switching frequency allows the use of small size input and output capacitors and enables wide loop
bandwidth within a small foot print. The low thermal resistance of the package allows the LDOs continuous
maximum current in the full temperature range.
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The EZ6301QI architecture includes the following features.
Operational Features:
•
Precision enable circuit with tight threshold range
•
Soft-start circuit allowing controlled startup with adjustable soft-start capacitance for buck converter and
built-in soft-start for LDOs
•
Power good circuits on all rails indicating the output voltage is within ±10% of programmed value
Protection Features:
•
Over-current protection with hiccup and reverse current protection for the buck converter
•
Over-current protection with fold-back for the LDOs
•
Thermal shutdown with hysteresis
•
Under-voltage lockout circuit to disable switching until the input is adequate
Precision Enable Operation
The enable (EN, ENL1, ENL2) pins provide means to startup or to shutdown the device. When the enable pin
is asserted high, the device will undergo a normal soft-start where the output will rise monotonically into
regulation. Asserting a logic low on this pin will deactivate the device by turning off the internal power switches
and the POK flag will also be pulled low. Precision voltage reference and comparator circuits are kept powered
up even when the device is disabled. The precision enable circuit ensures the device will enable or disable
within a tight voltage range for both high or low logic. This precision allows accurate sequencing for multiple
power supplies. In order to ensure a known state, the enable pin should be pulled high or low while the device’s
input voltage is above UVLO. When input voltage decays slowly and the device is operating below the
minimum operating voltage, switching chatter may occur due to insufficient voltage. In order to avoid chatter
during power down, a resistor divider may be connected on the enable pin to power down the switching DCDC regulator.
VIN = 3.3V
10k
EN
6.65k
Figure 5: Sample Enable Resistor Divider Circuit
The resistor divider circuit in Figure 5 may be used to disable the regulator at around 2.6V, but be sure to have
sufficient voltage for startup when choosing divider values. See the Electrical Characteristics Table for
technical specifications for the enable pins for the switcher and LDOs.
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Soft-Start Operation
DC-DC Buck:
The soft-start circuitry will reduce inrush current during startup as the regulator charges the output voltage up
to nominal level gradually. The DC-DC buck output rise time is controlled by the soft-start capacitor, which is
placed between the SS pin and the AGND pin. When the part is enabled, the soft-start (SS) current generator
charges the SS capacitor in a linear manner. Once the voltage on the SS capacitor reaches 0.6V, the controller
selects the intenral bandgap voltage as the reference. The voltage across the SS capacitor will continue
ramping up until it reaches around 1.27V. The rise time is defined as the time needed by the output voltage to
go from zero to the programmed value. The rise time (tRISE) is given by the following equation:
tRISE [ms] = Css [nF] x 0.065
With a 10nF soft-start capacitance on the SS pin, the soft-start rise time will be set to 0.65ms. The
recommended range for the value of the SS capacitor is between 10nF and 100nF. Note that excessive bulk
capacitance on the output can cause an over current event on startup if the soft-start time is too low. Refer to
the Compensation and Transient Response section for details on proper bulk capacitance usage.
LDO:
The LDOs have fixed internal soft-start. When enabled, the output will rise into regulation in a controlled
manner.
POK Operation
The POK signals (POK, POKL1, POKL2) are open drain signals to indicate if the output voltage is within the
specified range. They each require an external pull-up (10k-100k) to VIN. POK is asserted high when the rising
output voltage exceeds 90% of the programmed output voltage. If the nominal output voltage falls outside
the set range (typically 90% to 110% of nominal) the POK signal will be asserted low by an internal 4mA pulldown transistor.
Over-Current Protection
DC-DC Buck:
The current limit function is achieved by sensing the current flowing through the High Side Switch. When the
sensed current exceeds the over current trip point, both power FETs are turned off for the remainder of the
switching cycle. If the over-current condition is removed, the over-current protection circuit will enable normal
PWM operation. In the event the OCP circuit trips for a given number of consecutive PWM cycles, the device
enters hiccup mode; the device is disabled for about 6.5ms and restarted with a normal soft-start. This cycle
can continue indefinitely as long as the over current condition persists.
LDO:
The LDOs have foldback current limit. When an over-current event is detected, the LDO will limit the amount
of output current that is allowed in order to reduce power dissipation. The foldback current is typically 50%
of the nominal current limit.
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Thermal Protection
The thermal shutdown circuit disables the device operation (transistors turn off) when the junction
temperature exceeds 155°C. When the junction temperature drops by approximately 25°C, the converters will
re-start with a normal soft-start. By preventing operation at excessive temperatures, the thermal shutdown
circuit will protect the device from overstress.
Pre-Bias Start-up
The DC-DC buck regulator supports startup into a pre-biased output. A proprietary circuit ensures the output
voltage rises from the pre-bias voltage level to the programmed output voltage on startup. During this softstart period, the voltage rise is monotonic for output voltage range from 0% to 90% of nominal. If the pre-bias
voltage is above 90% on startup, there might be a slight dip (~3%) in output voltage before it rises
monotonically. If the pre-bias voltage is above 100% of nominal during startup, the device will not switch until
the output voltage decays below the target voltage. Note that when the device begins switching and the prebias output voltage is higher than nominal, the bottomside NFET will discharge the output quickly (but limited
to 2-cycles to prevent excessive current) to bring the voltage back into regulation. The pre-bias protection
circuit is designed to prevent improper behavior on startup regardless of the pre-bias output voltage during
soft-start.
Input Under-Voltage Lock-Out
When the device input voltage falls below UVLO, switching is disabled to prevent operation at insufficient
voltage levels. During startup, the UVLO circuit ensures that the converter will not start switching until the
input voltage is above the specified minimum voltage. Hysteresis and input de-glitch circuits are incorporated
in order to ensure high noise immunity and prevent a false trigger in the UVLO voltage region.
APPLICATION INFORMATION
Each output rail on the EZ6301QI can be programmed using the feedback reference voltage and a simple
resistor divider network (RA and RB). The DC-DC buck regulator feedback reference voltage is 0.6V and the LDO
feedback reference voltage is 0.9V (VFB = 0.6V, VFBL1 = VFBL2 = 0.9V).
DC-DC Buck
LDO
VOUT
VOUT
PGND
VFB
VOUTL1, 2
VOUTL1, 2
COUT
(47µF – 150µF)
RA
169k
CA
(10pF – 33pF)
PGND
RC
6.65k
VFB = 0.6V
VFBL1, 2
RB =
COUT
(10µF– 47µF)
CA
(10pF – 47pF)
VFBL1,2 = 0.9V
0.6V x 169k
RB =
VOUT - 0.6V
AGND
RA
110k
0.9V x 110k
VOUT - 0.9V
AGND
Figure 6: Output Voltage Setting (Buck left, LDO right)
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The recommended RA resistor value is shown in Figure 6 and Table 1 for each regulator. Depending on the
output voltage (VOUT), the RB resistor value may be calculated as shown in Figure 6. Since the accuracy of the
output voltage setting is dependent upon the feedback voltage and the external ressitors, 1% or better
resistors are recommended. The recommended external compensation values are shown in Table 1.
Table 1: External Compensation Recommendations
Rail
DC-DC
VOUT
RB
CA
0.6V
OPEN
33pF
0.9V
340kΩ
33pF
1.0V
255kΩ
33pF
1.2V
169kΩ
33pF
1.5V
113kΩ
27pF
RA
RC
COUT
47µF
169kΩ 6.65kΩ
or
2 x 22µF
1.8V 84.5kΩ 27pF
2.5V 53.6kΩ 27pF
3.3V 37.4kΩ 27pF
LDO
1.0V
1.0MΩ
33pF
1.2V
332kΩ
33pF
1.5V
165kΩ
27pF
1.8V
110kΩ
27pF
47µF
110kΩ
0
or
2 x 22µF
2.5V 61.9kΩ 27pF
3.3V 41.2kΩ 27pF
Compensation
Most of the DC-DC regulator’s compensation is internal, which simplifies the design. In some applications,
improved transient performance may be desired with additional output capacitors (COUT). In such an instance,
the phase-lead capacitor (CA) can be adjusted depending on the total output capacitance. Using Table 1 as the
reference for CA, if COUT is increased, then the CA should also be increased. The relationship is linearly shown
below:
ΔCOUT ≈ +50µF ΔCA ≈ +5pF
As COUT increases and the CA value is adjusted, the device bandwidth will reach its optimization level (at around
1/10th of the switching frequency). The limitation for adjusting the compensation is based on diminished
return. Significant increases in COUT and CA may not yield better transient response or in some situations cause
lower gain and phase margin. Over compensating with excessive output capacitance may also cause the device
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to trigger current limit on startup due to the energy required to charge the output up to regulation level. Due
to such limitations, the recommended maximum output capacitance (COUT_MAX) is 150µF and the recommended
maximum phase-lead capacitance (CA_MAX) is 47pF.
Input Capacitor Selection
The input of synchronous buck regulators can be very noisy and should be decoupled properly in order to
ensure stable operation. In addition, input parasitic line inductance can attribute to higher input voltage ripple.
The EZ6301QI requires a minimum of 10µF input capacitor on each of the rails. As the distance of the input
power source to the input is increased, it is recommended to increase input capacitance in order to mitigate
the line inductance from the source. Low-ESR ceramic capacitors should be used. The dielectric must be X5R
or X7R rated and the size must be at least 0805 (EIA) due to derating. Y5V or equivalent dielectric formulations
must not be used as these lose too much capacitance with frequency, temperature and bias voltage. In some
applications, lower value capacitors are needed in parallel with the larger capacitors in order to provide high
frequency decoupling. Larger electrolytic or tantalum bulk capacitors may be used in conjunction to increase
total input capacitance but should not be used solely as a replacement for the ceramic capacitors.
Table 2: Recommended Input Capacitors
Description
MFG
10 µF, 10V, 10%
X7R, 1206
22 µF, 10V, 20%
X5R, 1206
P/N
Murata
GRM31CR71A106KA01L
Taiyo Yuden
LMK316B7106KL-T
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Output Capacitor Selection
The output ripple of a synchronous buck converter can be attributed to its inductance, switching frequency
and output decoupling. The EZ6301QI requires a minimum of 47µF output capacitance for the DC-DC buck
regulator and 10µF for each of the LDOs. Low ESR ceramic capacitors should be used. The dielectric must be
X5R or X7R rated and the size must be at least 0805 (EIA) due to derating. Y5V or equivalent dielectric
formulations must not be used as these lose too much capacitance with frequency, temperature and bias
voltage.
Table 3: Recommended Output Capacitors
Description
47µF, 6.3V, 20%
X5R, 1206
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK316BJ476ML-T
Taiyo Yuden
LMK316BJ226ML-T
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Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance (ESR) and effective series inductance (ESL):
Z = ESR + ESL
The resonant frequency of a ceramic capacitor is inversely proportional to the capacitance. Lower capacitance
corresponds to higher resonant frequency. When two capacitors are placed in parallel, the benefit of both are
combined. It is beneficial to decouple the output with capacitors of various capacitance and size. Placing them
all in parallel reduces the impedance and will hence result in lower output ripple.
1
Z Total
1
1
1
...
Z1 Z 2
Zn
THERMAL CONSIDERATIONS
Thermal considerations are important elements of power supply design. Whenever there are power losses in
a system, the heat that is generated by the power dissipation needs to be taken into account. The Intel Enpirion
PowerSoC technology helps alleviate some of those concerns.
The EZ6301QI DC-DC converter is packaged in a 4mm x 7mm x 1.85mm 40-pin QFN package. The QFN
package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad
on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to
act as a heat sink. The recommended maximum junction temperature for continuous operation is 125°C.
Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload
protection circuit designed to turn off the device at an approximate junction temperature value of 155°C.
The following example and calculations illustrate the thermal performance of the EZ6301QI with the following
parameters:
VIN = VINL1 = VINL2= 5V
VOUT = 3.3V, VOUTL1 = 2.5V, VOUTL2 = 1.8V
IOUT = 1.5A, IOUTL1 = 300mA, IOUTL2 = 300mA
First, calculate the total output power based on all rails.
POUT = VOUT x IOUT = 3.3V x 1.5A = 4.95W
POUTL1 = VOUTL1 x IOUTL1 = 2.5V x 300mA = 0.75W
POUTL2 = VOUT x IOUT = 1.8V x 300mA = 0.54W
Next, determine the input power. For the DC-DC buck regulator we can use the efficiency (η) shown in Figure
7 to determine the input power.
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Buck Efficiency vs. Output Current
100
95
EFFICIENCY (%)
90
85
80
75
VOUT = 3.3V
70
VOUT = 2.5V
65
CONDITIONS
VIN = 5.0V
60
55
VOUT = 1.8V
VOUT = 1.2V
50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
OUTPUT CURRENT (A)
Figure 7: Efficiency vs. Output Current
For the DC-DC buck regulator, VIN = 5V, VOUT = 3.3V at 3A, η ≈ 92%
η = POUT / PIN = 92% = 0.92
PIN = POUT / η
PIN ≈ 4.95W / 0.92 ≈ 5.38W
The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
= 5.38W – 4.95W ≈ 0.43W
For the LDOs, the input current is approximately equal to the output current (note that the quiescent current
of the LDO is assumed to be negligible).
PDL1 = PINL1 – POUTL1
PDL1 = 5V x 300mA – 2.5V x 300mA = 0.75W
PDL2 = 5V x 300mA – 1.8V x 300mA = 0.96W
The total power loss is the sum of all losses on all rails.
PDTOTAL = PD + PDL1 + PDL2
PDTOTAL = 0.43W + 0.75W + 0.96W
PDTOTAL = 2.14W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EZ6301QI has a θJA value of 11.5°C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PDTOTAL x θJA
ΔT ≈ 2.14W x 11.5°C/W ≈ 24.6°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 24.6°C ≈ 49.6°C
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The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PDTOTAL x θJA
≈ 125°C – 24.6°C ≈ 100.4°C
The maximum ambient temperature the device can reach is 100.4°C given the input and output conditions.
Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate.
APPLICATION SCHEMATIC
27pF
61.9k
110k
10µF
5V
PVIN
3.3V @ 1.5A
10
10µF
2.5V @ 300mA
VOUTL1
PGND
VFBL1
POKL1
AGND
5V
PGND
ENL1
VINL1
47µF
VOUT
AVIN
10nF
47µF
6.65k
PGND
EZ6301QI
PGND
27pF
169k
VFB
SS
POK
15nF
37.4k
AGND
5V
VOUTL2
PGND
VFBL2
POKL2
AGND
PGND
VINL2
EN
ENL2
AGND
47µF
10µF
110k
110k
1.8V @ 300mA
27pF
Figure 8: Application Schematic for VOUT = 3.3V, VOUTL1=2.5V, VOUTL2 = 1.8V
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LAYOUT RECOMMENDATIONS
Figure 9 shows critical components and layer 1 traces of a recommended minimum footprint EZ6301QI layout.
ENABLE and other small signal pins need to be connected and routed according to specific customer
application. Visit the Enpirion Power Solutions website at www.altera.com/powersoc for more information
regarding layout. Please refer to this Figure 9 while reading the layout recommendations in this section.
Figure 9: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EZ6301QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
Voltage and GND traces between the capacitors and the EZ6301QI should be as close to each other as possible
so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: The system ground plane should be on the 2nd layer (below the surface layer). This
ground plane should be continuous and un-interrupted.
Recommendation 3: The large thermal pad underneath the device must be connected to the system ground
plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must
have at least 1-oz. copper plating on the inside wall, making the finished hole size around 0.2mm to 0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figure 9.
Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. Put the vias under the capacitors along the edge of the GND copper closest to the Voltage copper.
Please see Figure 9. These vias connect the input/output filter capacitors to the GND plane, and help reduce
parasitic inductances in the input and output current loops. If the vias cannot be placed under C IN and COUT,
then put them just outside the capacitors along the GND slit separating the two components. Do not use
thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 9 this connection is made at the input capacitor
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furthest from the PVIN pin and on the input source side. Avoid connecting AVIN near the PVIN pin even though
it is the same node as the input ripple is higher there.
Recommendation 6: The VOUT sense point should be connected at the last output filter capacitor furthest from
the VOUT pins. Keep the sense trace as short as possible in order to avoid noise coupling into the control loop.
Recommendation 7: Keep RA, CA, RC and RB close to the VFB pin (see Figure 9). The VFB pin is a high-impedance,
sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R B directly to the
AGND pin instead of going through the GND plane. The AGND should connect to the PGND at a single point
from the AGND pin to the PGND plane on the 2nd layer.
Recommendation 8: The layer 1 metal under the device must not be more than shown in Figure 9. See the
following section regarding Exposed Metal on Bottom of Package. As with any switch-mode DC-DC
converter, try not to run sensitive signal or control lines underneath the converter package on other layers.
DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 10.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EZ6301QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pads. The “shaded-out” area in Figure 10 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package.
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Figure 10: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
Figure 11: Solder stencil drawing (Top View)
The solder stencil aperture for the non-perimeter pads is shown in Figure 11 and is based on Enpirion power
product manufacturing specifications.
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PACKAGE DIMENSIONS
Figure 12: EZ6301QI Package Dimensions
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
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REVISION HISTORY
Rev
A
B
Date
Change(s)
November, 2017
Initial Release
December, 2017
•
•
•
Added Pin Compatibility to EZ6303QI in Features section
Updated Performance Curve titles to illustrate Buck or LDO
Corrected RB resistance values for Buck in Table 1
WHERE TO GET MORE INFORMATION
For more information about Intel and Intel Enpirion PowerSoCs, visit https://www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
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