Section I. HardCopy Stratix
Device Family Data Sheet
This section provides designers with the data sheet specifications for
HardCopy® Stratix structured ASICs. The chapters contain feature
definitions of the internal architecture, JTAG boundary-scan testing
information, DC operating conditions, AC timing parameters, and a
reference to power consumption for HardCopy Stratix structured ASICs.
This section contains the following:
Revision History
Altera Corporation
■
Chapter 1, Introduction to HardCopy Stratix Devices
■
Chapter 2, Description, Architecture, and Features
■
Chapter 3, Boundary-Scan Support
■
Chapter 4, Operating Conditions
■
Chapter 5, Quartus II Support for HardCopy Stratix Devices
■
Chapter 6, Design Guidelines for HardCopy Stratix Performance
Improvement
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Section I–1
Preliminary
Revision History
Section I–2
Preliminary
HardCopy Series Handbook, Volume 1
Altera Corporation
1. Introduction to HardCopy
Stratix Devices
H51001-2.4
Introduction
HardCopy® Stratix ® structured ASICs, Altera’s second-generation
HardCopy structured ASICs, are low-cost, high-performance devices
with the same architecture as the high-density Stratix FPGAs. The
combination of Stratix FPGAs for prototyping and design verification,
HardCopy Stratix devices for high-volume production, and the
Quartus® II design software beginning with version 3.0, provide a
complete and powerful alternative to ASIC design and development.
HardCopy Stratix devices are architecturally equivalent and have the
same features as the corresponding Stratix FPGA. They offer pin-to-pin
compatibility using the same package as the corresponding Stratix FPGA
prototype. Designers can prototype their design to verify functionality
with Stratix FPGAs before seamlessly migrating the proven design to a
HardCopy Stratix structured ASIC.
The Quartus II software provides a complete set of inexpensive and
easy-to-use tools for designing HardCopy Stratix devices. Using the
successful and proven methodology from HardCopy APEX™ devices,
Stratix FPGA designs can be seamlessly and quickly migrated to a
low-cost ASIC alternative. Designers can use the Quartus II software to
design HardCopy Stratix devices to obtain an average of 50% higher
performance and up to 40% lower power consumption than can be
achieved in the corresponding Stratix FPGAs. The migration process is
fully automated, requires minimal customer involvement, and takes
approximately eight weeks to deliver fully tested HardCopy Stratix
prototypes.
The HardCopy Stratix devices use the same base arrays across multiple
designs for a given device density and are customized using the top two
metal layers. The HardCopy Stratix family consists of the HC1S25,
HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table 1–1 provides the
details of the HardCopy Stratix devices.
Altera Corporation
September 2008
1–1
Preliminary
HardCopy Series Handbook, Volume 1
Table 1–1. HardCopy Stratix Devices and Features
Device
LEs (1)
M512 Blocks
M4K Blocks
M-RAM
Blocks
DSP Blocks (2)
PLLs (3)
HC1S25
25,660
224
138
2
10
6
HC1S30
32,470
295
171
2 (4)
12
6
HC1S40
41,250
384
183
2 (4)
14
6
HC1S60
57,120
574
292
6
18
12
HC1S80
79,040
767
364
6 (4)
22
12
Notes to Table 1–1:
(1)
(2)
(3)
(4)
LE: logic elements.
DSP: digital signal processing.
PLLs: phase-locked loops.
In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All
other resources are identical to the Stratix counterpart.
Features
HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 μm
all-layer-copper metal fabrication process (up to eight layers of metal) as
the Stratix FPGAs.
■
■
■
■
■
■
■
■
■
■
■
■
1–2
Preliminary
Preserves the functionality of a configured Stratix device
Pin-compatible with the Stratix counterparts
On average, 50% faster than their Stratix equivalents
On average, 40% less power consumption than their Stratix
equivalents
25,660 to 79,040 LEs
Up to 5,658,408 RAM bits available
TriMatrix memory architecture consisting of three RAM block sizes
to implement true dual-port memory and first-in-first-out (FIFO)
buffers
Embedded high-speed DSP blocks provide dedicated
implementation of multipliers, multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
which provide identical features as the FPGA counterparts,
including spread spectrum, programmable bandwidth, clock
switchover, real-time PLL reconfiguration, advanced multiplication,
and phase shifting
Supports numerous single-ended and differential I/O standards
Supports high-speed networking and communications bus
standards including RapidIO™, UTOPIA IV, CSIX, HyperTransport
technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),
and SFI-4
Differential on-chip termination support for LVDS
Altera Corporation
September 2008
Features
■
■
■
■
■
1
Supports high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,
double data rate (DDR) SDRAM, DDR fast-cycle RAM (FCRAM),
and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) megafunctions from
Altera® MegaCore® functions, and Altera Megafunction Partners
Program (AMPP SM) megafunctions
Available in space-saving flip-chip FineLine BGA® and wire-bond
packages (Tables 1–2 and 1–3)
Optional emulation of original FPGA configuration sequence
Optional instant-on power-up
The actual performance and power consumption improvements
over the Stratix equivalents mentioned in this data sheet are
design-dependent.
Table 1–2. HardCopy Stratix Device Package Options and I/O Pin Counts
Note (1)
Device
672-Pin
FineLine BGA (2)
HC1S25
473
780-Pin
FineLine BGA (3)
HC1S30
597
HC1S40
613 (4)
1,020-Pin
FineLine BGA (3)
HC1S60
782
HC1S80
782
Notes to Table 1–2:
(1)
(2)
(3)
(4)
Altera Corporation
September 2008
Quartus II I/O pin counts include one additional pin, PLLENA, which is not a
general-purpose I/O pin. PLLENA can only be used to enable the PLLs.
This device uses a wire-bond package.
This device uses a flip-chip package.
In the Stratix EP1S40F780 FPGA, the I/O pins U12 and U18 are general-purpose
I/O pins. In the FPGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the HardCopy Stratix
HC1S40F780 device, U12 and U18 must be connected to ground. The
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE and HC1S40F780 pin-outs are
identical.
1–3
Preliminary
HardCopy Series Handbook, Volume 1
Table 1–3. HardCopy Stratix Device Package Sizes
Device
672-Pin
FineLine BGA
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
Pitch (mm)
1.00
1.00
1.00
Area
(mm2 )
Length × width
(mm × mm)
Document
Revision History
729
841
1,089
27 × 27
29 × 29
33 × 33
Table 1–4 shows the revision history for this chapter.
Table 1–4. Document Revision History
Date and Document
Version
Changes Made
Summary of Changes
September 2008
v2.4
Revised chapter number and metadata.
—
June 2007 v2.3
Updated Introduction section.
Updated Table 1–2.
—
December 2006
v2.2
Updated revision history.
—
March 2006
Formerly chapter 5; no content change.
—
October 2005 v2.1
Minor edits
—
January 2005 v2.0
Minor edits
—
June 2003 v1.0
Initial release of Chapter 5, Introduction to HardCopy Stratix
Devices, in the HardCopy Device Handbook.
1–4
Preliminary
Altera Corporation
September 2008
2. Description, Architecture,
and Features
H51002-3.4
Introduction
HardCopy® Stratix ® structured ASICs provide a comprehensive
alternative to ASICs. The HardCopy Stratix device family is fully
supported by the Quartus® II design software, and, combined with a vast
intellectual property (IP) portfolio, provides a complete path from
prototype to volume production. Designers can now procure devices,
tools, and Altera® IP for their high-volume applications.
As shown in Figure 2–1, HardCopy Stratix devices preserve their Stratix
FPGA counterpart’s architecture, but the programmability for logic,
memory, and interconnect is removed. HardCopy Stratix devices are also
manufactured in the same process technology and process voltage as
Stratix FPGAs. Removing all configuration and programmable routing
resources and replacing it with direct metal interconnect results in
considerable die size reduction and the ensuing cost savings.
Figure 2–1. HardCopy Stratix Device Architecture
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
M-RAM Block
LABs
LABs
DSP
Block
Altera Corporation
September 2008
2–1
HardCopy Stratix and Stratix FPGA Differences
The HardCopy Stratix family consists of base arrays that are common to
all designs for a particular device density. Design-specific customization
is done within the top two metal layers. The base arrays use an
area-efficient sea-of-logic-elements (SOLE) core and extend the flexibility
of high-density Stratix FPGAs to a cost-effective, high-volume production
solution. With a seamless migration process employed in numerous
successful designs, functionality-verified Stratix FPGA designs can be
migrated to fixed-function HardCopy Stratix devices with minimal risk
and guaranteed first-time success.
The SRAM configuration cells of the original Stratix devices are replaced
in HardCopy Stratix devices by metal connects, which define the function
of each logic element (LE), digital signal processing (DSP) block,
phase-locked loop (PLL), embedded memory, and I/O cell in the device.
These resources are interconnected using metallization layers. Once a
HardCopy Stratix device has been manufactured, the functionality of the
device is fixed and no re-programming is possible. However, as is the case
with Stratix FPGAs, the PLLs can be dynamically configured in
HardCopy Stratix devices.
HardCopy Stratix
and Stratix FPGA
Differences
To ensure HardCopy Stratix device functionality and performance,
designers should thoroughly test the original Stratix FPGA-based design
for satisfactory results before committing the design for migration to a
HardCopy Stratix device. Unlike Stratix FPGAs, HardCopy Stratix
devices are customized at the time of manufacturing and therefore do not
have programmability support.
Since HardCopy Stratix devices are customized within the top two metal
layers, no configuration circuitry is required. Refer to “Power-Up Modes
in HardCopy Stratix Devices” on page 2–7 for more information.
Depending on the design, HardCopy Stratix devices can provide, on
average, a 50% performance improvement over equivalent Stratix
FPGAs. The performance improvement is achieved by die size reduction,
metal interconnect optimization, and customized signal buffering.
HardCopy Stratix devices consume, on average, 40% less power than
their equivalent Stratix FPGAs.
1
2–2
Designers can use the Quartus II software to design HardCopy
Stratix devices, estimate performance and power consumption,
and maximize system throughput.
Altera Corporation
September 2008
Description, Architecture, and Features
Table 2–1 illustrates the differences between HardCopy Stratix and
Stratix devices.
Table 2–1. HardCopy Stratix and Stratix Device Comparison (Part 1 of 2)
HardCopy Stratix
Stratix
Customized device. All
reprogrammability support is removed
and no configuration is required.
Re-programmable with configuration is
required upon power-up.
Average of 50% performance
improvement over corresponding
FPGA (1).
High-performance FPGA.
Average of 40% less power
consumption compared to
corresponding FPGA (1).
Standard FPGA power consumption.
Contact Altera for information regarding IP support for all devices is available.
specific IP support.
Double data rate (DDR) SDRAM
maximum operating frequency is
pending characterization.
DDR SDRAM can operate at 200 MHz
for -5 speed grade devices.
All routing connections are direct and
all unused routing is removed.
MultiTrack™ routing stitches together
routing resources to provide a path.
HC1S30 and HC1S40 devices have
two M-RAM blocks. HC1S80 devices
have six M-RAM blocks.
EP1S30 and EP1S40 devices have four
M-RAM blocks. EP1S80 devices have
nine M-RAM blocks.
It is not possible to initialize M512 and
M4K RAM contents during power-up.
The contents of M512 and M4K RAM
blocks can be preloaded during
configuration with data specified in a
memory initialization file (.mif).
The contents of memory output
registers are unknown after power-on
reset (POR).
The contents of memory output
registers are initialized to '0' after POR.
HC1S30 and HC1S40 devices have six
PLLs.
HC1S30 devices have 10 PLLs.
HC1S40 devices have 12 PLLs.
PLL dynamic reconfiguration uses
ROM for information. This
reconfiguration is performed in the
back-end and does not affect the
migration flow.
PLL dynamic reconfiguration uses a
MIF to initialize a RAM resource with
information.
The I/O elements (IOEs) are equivalent The IOEs are optimized for the FPGA
but not identical to FPGA IOEs due to architecture.
slight design optimizations for
HardCopy devices.
Altera Corporation
September 2008
2–3
Logic Elements
Table 2–1. HardCopy Stratix and Stratix Device Comparison (Part 2 of 2)
HardCopy Stratix
Stratix
The I/O drive strength for single-ended
I/O pins are slightly different and is
modeled in the HardCopy Stratix IBIS
models.
The I/O drive strength for single-ended
I/O pins are found in Stratix IBIS
models.
In the HC1S40 780-pin FineLine BGA® In the HC1S40 780-pin FineLine BGA
device, the I/O pins U12 and U18 must device, the I/O pins U12 and U18 are
available as general-purpose I/O pins.
be connected to ground.
The BSDL file describes re-ordered
Joint Test Action Group (JTAG)
boundary-scan chains.
The JTAG boundary-scan chain is
defined in the BSDL file.
Note to Table 2–1:
(1)
Logic Elements
Performance and power consumption are design dependant.
Logic is implemented in HardCopy Stratix devices using the same
architectural units as the Stratix device family. The basic unit is the logic
element (LE) with logic array blocks (LAB) consisting of 10 LEs. The
implementation of LEs and LABs is identical to the Stratix device family.
In the HardCopy Stratix device family, all extraneous routing resources
not essential to the specific design are removed for performance and die
size efficiency. Therefore, the MultiTrack interconnect for routing
implementation between LABs and other device resources in the Stratix
device family is no longer necessary in the HardCopy Stratix device
family.
Table 2–2 illustrates the differences between HardCopy Stratix and
Stratix logic.
Table 2–2. HardCopy Stratix and Stratix Logic Comparison
HardCopy Stratix
All routing connections are direct and
all unused routing is removed.
Embedded
Memory
2–4
Stratix
MultiTrack routing stitches routing
resources together to provide a path.
TriMatrix™ memory blocks from Stratix devices, including M512, M4K,
and M-RAM memory blocks, are available in HardCopy Stratix devices.
Embedded memory is seamlessly implemented in the equivalent
resource.
Altera Corporation
September 2008
Description, Architecture, and Features
Although memory resource implementation is equivalent, the number of
specific M-RAM blocks are not necessarily the same between
corresponding Stratix and HardCopy Stratix devices. Table 2–3 shows the
number of M-RAM blocks available in each device.
Table 2–3. HardCopy Stratix and Stratix M-RAM Block Comparison
HardCopy Stratix
Device
Stratix
M-RAM Blocks
Device
M-RAM Blocks
HC1S25
2
EP1S25
2
HC1S30
2
EP1S30
4
HC1S40
2
EP1S40
4
HC1S60
6
EP1S60
6
HC1S830
6
EP1S830
9
In HardCopy Stratix devices, it is not possible to preload RAM contents
using a MIF after powering up; the output registers of memory blocks
will have unknown values. This occurs because there is no configuration
process that is executed.
1
Violating the setup or hold time requirements on address
registers could corrupt the memory contents. This requirement
applies to both read and write operations.
Table 2–4 illustrates the differences between HardCopy Stratix and
Stratix memory.
Table 2–4. HardCopy Stratix and Stratix Memory Comparison
HardCopy Stratix
Altera Corporation
September 2008
Stratix
HC1S30 and HC1S40 devices have
two M-RAM blocks. HC1S80 devices
have six M-RAM blocks.
EP1S30 and EP1S40 devices have four
M-RAM blocks. EP1S80 devices have
nine M-RAM blocks.
It is not possible to initialize M512 and
M4k RAM contents during power-up.
The contents of M512 and M4K RAM
blocks can be preloaded during
configuration with data specified in a
MIF.
The contents of memory output
registers are unknown after POR.
The contents of memory output
registers are initialized to ‘0’ after POR.
2–5
DSP Blocks
DSP Blocks
DSP blocks in HardCopy Stratix devices are architecturally identical to
those in Stratix devices. The number of DSP blocks available in
HardCopy Stratix devices matches the number of DSP blocks available in
the corresponding Stratix device.
PLLs and Clock
Networks
The PLLs in HardCopy Stratix devices are identical to those in Stratix
devices. The clock networks are also implemented exactly as they are in
Stratix devices. The number of PLLs can vary between corresponding
Stratix and HardCopy Stratix devices. Table 2–5 shows the number of
PLLs available in each device.
Table 2–5. HardCopy Stratix and Stratix PLL Comparison
HardCopy Stratix
Device
Stratix
PLLs
Device
PLLs
HC1S25
6
EP1S25
6
HC1S30
6
EP1S30
10
HC1S40
6
EP1S40
12
HC1S60
12
EP1S60
12
EP1S830
12
EP1S830
12
Table 2–6 illustrates the differences between HardCopy Stratix and
Stratix PLLs.
Table 2–6. HardCopy Stratix and Stratix PLL Differences
HardCopy Stratix
I/O Structure and
Features
2–6
Stratix
HC1S30 and HC1S40 devices have six
PLLs.
HC1S30 devices have 10 PLLs.
HC1S40 devices have12 PLLs.
PLL dynamic reconfiguration uses
ROM for information. This
reconfiguration is performed in the
back-end and does not affect the
migration flow.
PLL dynamic reconfiguration uses a
MIF to initialize a RAM resource with
information.
The HardCopy Stratix IOEs are equivalent, but not identical to, the Stratix
FPGA IOEs. This is due to the reduced die size, layout difference, and
metal customization of the HardCopy Stratix device. The differences are
minor but may be relevant to customers designing with tight DC and
switching characteristics. However, no signal integrity concerns are
introduced with HardCopy Stratix IOEs.
Altera Corporation
September 2008
Description, Architecture, and Features
When designing with very tight timing constraints (for example, DDR or
quad data rate [QDR]), or if using the programmable drive strength
option, Altera recommends verifying final drive strength using updated
IBIS models located on the Altera website at www.altera.com.
Differential I/O standards are unaffected.
I/O pin placement and VREF pin placement rules are identical between
HardCopy Stratix and Stratix devices. Unused pin settings will carry over
from Stratix device settings and are implemented as tri-stated outputs
driving ground or outputs driving VCC.
In Stratix EP1S40 780-pin FineLine BGA FPGAs, the I/O pins U12 and
U18 are available as general-purpose I/O pins. In the FPGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the Hardcopy
Stratix HC1S40 780-pin FineLine BGA device, the I/O pins U12 and U18
must be connected to ground. HC1S40 780-pin FineLine BGA and
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE pin-outs are identical.
Table 2–7 illustrates the differences between HardCopy Stratix and
Stratix I/O pins.
Table 2–7. HardCopy Stratix and Stratix I/O Pin Comparison
HardCopy Stratix
Stratix
The IOEs are equivalent, but not
identical to, the FPGA IOEs due to
slight design optimizations for
HardCopy devices.
IOEs are optimized for the FPGA
architecture.
The I/O drive strength for single-ended
I/O pins are slightly different and are
found in the HardCopy Stratix IBIS
models.
The I/O drive strength for single-ended
I/O pins are found in Stratix IBIS
models.
In the HC1S40 780-pin FineLine BGA In the EP1S40 780-pin FineLine BGA
device, the I/O pins U12 and U18 must device, the I/O pins U12 and U18 are
be connected to ground.
available as general-purpose I/O pins.
Power-Up
Modes in
HardCopy Stratix
Devices
Altera Corporation
September 2008
Designers do not need to configure HardCopy Stratix devices, unlike
their FPGA counterparts. However, to facilitate seamless migration,
configuration can be emulated in HardCopy Stratix devices.
The modes in which a HardCopy Stratix device can be made ready for
operation after power-up are: instant on, instant on after 50 ms, and
configuration emulation. These modes are briefly described below.
2–7
Hot Socketing
■
■
■
1
In instant on mode, the HardCopy Stratix device is available for use
shortly after the device receives power. The on-chip POR circuit
resets all registers. The CONF_DONE output is tri-stated once the POR
has elapsed. No configuration device or configuration data is
necessary.
In instant on after 50 ms mode, the HardCopy Stratix device
performs in a fashion similar to the instant on mode, except that there
is an additional delay of 50 ms, during which time the device is held
in reset stage. The CONF_DONE output is pulled low during this time,
and then tri-stated after the 50 ms have elapsed. No configuration
device or configuration data is necessary for this option.
In configuration emulation mode, the HardCopy series device
emulates the behavior of an APEX or Stratix FPGA during its
configuration phase. When this mode is used, the HardCopy device
uses a configuration emulation circuit to receive configuration bit
streams. When all the configuration data is received, the HardCopy
series device transitions into an initialization phase and releases the
CONF_DONE pin to be pulled high. Pulling the CONF_DONE pin high
signals that the HardCopy series device is ready for normal
operation. If the optional open-drain INIT_DONE output is used, the
normal operation is delayed until this signal is released by the
HardCopy series device.
HardCopy II and some HardCopy Stratix devices do not
support configuration emulation mode.
Instant on and instant on after 50 ms modes are the recommended
power-up modes because these modes are similar to an ASIC’s
functionality upon power-up. No changes to the existing board design or
the configuration software are required.
All three modes provide significant benefits to system designers. They
enable seamless migration of the design from the FPGA device to the
HardCopy device with no changes to the existing board design or the
configuration software. The pull-up resistors on nCONFIG, nSTATUS, and
CONF_DONE should be left on the printed circuit board.
f
Hot Socketing
2–8
For more information, refer to the HardCopy Series Configuration
Emulation chapter in the HardCopy Series Handbook.
HardCopy Stratix devices support hot socketing without any external
components. In a hot socketing situation, a device’s output buffers are
turned off during system power up or power down. To simplify board
design, HardCopy Stratix devices support any power-up or power-down
sequence (VCCIO and V CCINT). For mixed-voltage environments, you can
Altera Corporation
September 2008
Description, Architecture, and Features
drive signals into the device before or during power up or power down
without damaging the device. HardCopy Stratix devices do not drive out
until they have attained proper operating conditions.
You can power up or power down the V CCIO and VCCINT pins in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
■
■
1
HARDCOPY_
FPGA_
PROTOTYPE
Devices
The hot socketing DC specification is | I IOPIN | < 300 µA.
The hot socketing AC specification is | I IOPIN | < 8 mA for 10 ns or
less. This specification takes into account the pin capacitance only.
Additional capacitance for trace, connector, and loading needs to be
taken into consideration separately. I IOPIN is the current at any user
I/O pin on the device.
The DC specification applies when all V CC supplies to the device
are stable in the powered-up or powered-down conditions. For
the AC specification, the peak current duration due to power-up
transients is 10 ns or less.
HARDCOPY_FPGA_PROTOTYPE devices are Stratix FPGAs available
for designers to prototype their HardCopy Stratix designs and perform
in-system verification before migration to a HardCopy Stratix device. The
HARDCOPY_FPGA_PROTOTYPE devices have the same available
resources as in the final HardCopy Stratix devices.
The Quartus II software version 4.1 and later contains the latest timing
models. For designs with tight timing constraints, Altera strongly
recommends compiling the design with the Quartus II software
version 4.1 or later. To properly verify I/O features, it is important to
design with the HARDCOPY_FPGA_PROTOTYPE device option prior to
migrating to a HardCopy Stratix device.
Altera Corporation
September 2008
2–9
Document Revision History
1
Some HARDCOPY_FPGA_PROTOTYPE devices, as indicated
in Table 2–8, have fewer M-RAM blocks compared to the
equivalent Stratix FPGAs. The selective removal of these
resources provides a significant price benefit to designers using
HardCopy Stratix devices.
Table 2–8. M-RAM Block Comparison Between Various Devices
Number
of LEs
HARDCOPY_FPGA_PROTOTYPE
Devices
HardCopy Stratix Devices
Stratix Devices
Device
M-RAM Blocks
Device
M-RAM Blocks
Device
M-RAM Blocks
25,660
EP1S25
2
HC1S25
2
EP1S25
2
32,470
EP1S30
2
HC1S30
2
EP1S30
4
41,250
EP1S40
2
HC1S40
2
EP1S40
4
57,120
EP1S60
6
HC1S60
6
EP1S60
6
79,040
EP1S830
6
HC1S830
6
EP1S830
9
f
For more information about how the various features in the Quartus II
software can be used for designing HardCopy Stratix devices, refer to
the Quartus II Support for HardCopy Stratix Devices chapter of the
HardCopy Series Handbook.
HARDCOPY_FPGA_PROTOTYPE FPGA devices have the identical
speed grade as the equivalent Stratix FPGAs. However, HardCopy Stratix
devices are customized and do not have any speed grading. HardCopy
Stratix devices, on an average, can be 50% faster than their equivalent
HARDCOPY_FPGA_PROTOTYPE devices. The actual improvement is
design-dependent.
Document
Revision History
Table 2–9 shows the revision history for this chapter.
Table 2–9. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
September 2008
v3.4
Revised chapter number and metadata.
June 2007 v3.3
●
●
●
2–10
Updated Table 2–1.
Added note to the “Embedded Memory” section.
Updated the “Hot Socketing” section.
Summary of Changes
—
—
Altera Corporation
September 2008
Description, Architecture, and Features
Table 2–9. Document Revision History (Part 2 of 2)
Date and Document
Version
Changes Made
Summary of Changes
December 2006
v3.2
Updated revision history.
—
March 2006
Formerly chapter 6; no content change.
—
October 2005 v3.1
●
●
May 2005
v3.0
●
●
●
●
●
●
January 2005
v2.0
●
●
●
Minor edits
Updated graphics
Added Table 6-1
Added the Logic Elements section
Added the Embedded Memory section
Added the DSP Blocks section
Added the PLLs and Clock Networks section
Added the I/O Structure and Features section
Minor update.
Added summary of I/O and timing differences between
Stratix FPGAs and HardCopy Stratix devices
Removed section on Quartus II support of HardCopy
Stratix devices
Added “Hot Socketing” section
Minor update.
August 2003
v1.1
Edited section headings’ hierarchy.
June 2003
v1.0
Initial release of Chapter 6, Description, Architecture and
Features, in the HardCopy Device Handbook
Altera Corporation
September 2008
Minor edits.
Minor edits.
—
2–11
Document Revision History
2–12
Altera Corporation
September 2008
3. Boundary-Scan Support
H51004-3.4
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All HardCopy® Stratix ® structured ASICs provide JTAG boundry-scan
test (BST) circuitry that complies with the IEEE Std. 1149.1-1990
specification. The BST architecture offers the capability to efficiently test
components on printed circuit boards (PCBs) with tight lead spacing by
testing pin connections, without using physical test probes, and
capturing functional data while a device is in normal operation.
Boundary-scan cells in a device can force signals onto pins, or capture
data from pin or core logic signals. Forced test data is serially shifted into
the boundary-scan cells. Captured data is serially shifted out and
externally compared to expected results.
A device using the JTAG interface uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. HardCopy Stratix devices support
the JTAG instructions as shown in Table 3–1.
Table 3–1. HardCopy Stratix JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD 00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins.
EXTEST (1)
00 0000 0000
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
IDCODE
00 0000 0110
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Altera Corporation
September 2008
3–1
Preliminary
HardCopy Series Handbook, Volume 1
Table 3–1. HardCopy Stratix JTAG Instructions (Part 2 of 2)
JTAG Instruction
CLAMP (1)
Instruction Code
00 0000 1010
Description
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Note to Table 3–1:
(1)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
f
The boundary-scan description language (BSDL) files for HardCopy
Stratix devices are different from the corresponding Stratix FPGAs. The
BSDL files for HardCopy Stratix devices are available for download
from the Altera website at www.altera.com.
The HardCopy Stratix device instruction register length is 10 bits; the
USERCODE register length is 32 bits. The USERCODE registers are
mask-programmed, so they are not re-programmable. The designer can
choose an appropriate 32-bit sequence to program into the USERCODE
registers.
Tables 3–2 and 3–3 show the boundary-scan register length and device
IDCODE information for HardCopy Stratix devices.
Table 3–2. HardCopy Stratix Boundary-Scan Register Length
Device
Maximum Boundary-Scan Register Length
HC1S25 672-pin FineLine BGA
1,458
HC1S30 780-pin FineLine BGA
1,878
HC1S40 780-pin FineLine BGA
1,878
HC1S60 1,020-pin FineLine BGA
2,382
HC1S80 1,020-pin FineLine BGA
2,382
3–2
Preliminary
Altera Corporation
September 2008
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 3–3. 32-Bit HardCopy Stratix Device IDCODE
IDCODE (32 Bits) (1)
Device
Version
(4 Bits)
Part Number
(16 Bits)
Manufacturer Identity
(11 Bits)
LSB
(1 Bit) (2)
HC1S25
0000
0010 0000 0000 0011
000 0110 1110
1
HC1S30
0000
0010 0000 0000 0100
000 0110 1110
1
HC1S40
0000
0010 0000 0000 0101
000 0110 1110
1
HC1S60
0000
0010 0000 0000 0110
000 0110 1110
1
HC1S80
0000
0010 0000 0000 0111
000 0110 1110
1
Notes to Table 3–3:
(1)
(2)
The most significant bit (MSB) is on the left.
The IDCODE’s least significant bit (LSB) is always 1.
Figure 3–1 shows the timing requirements for the JTAG signals.
Figure 3–1. HardCopy Stratix JTAG Waveforms
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to Be
Captured
Signal
to Be
Driven
Altera Corporation
September 2008
tJSZX
tJSH
tJSCO
tJSXZ
3–3
Preliminary
HardCopy Series Handbook, Volume 1
Table 3–4 shows the JTAG timing parameters and values for HardCopy
Stratix devices.
Table 3–4. HardCopy Stratix JTAG Timing Parameters and Values
Symbol
f
Document
Revision History
Parameter
Min
Max
Unit
tJCP
TCK clock period
100
ns
tJCH
TCK clock high time
50
ns
tJCL
TCK clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
tJSH
Capture register hold time
45
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
ns
ns
For more information on JTAG, refer to AN 39: IEEE Std. 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices.
Table 3–5 shows the revision history for this chapter.
Table 3–5. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
Summary of Changes
September 2008
v3.4
Updated chapter number and metadata.
—
June 2007 v3.3
Updated Figure 3–1.
—
December 2006
v3.2
Updated revision history.
—
March 2006
Formerly chapter 7; no content change.
—
3–4
Preliminary
Altera Corporation
September 2008
Document Revision History
Table 3–5. Document Revision History (Part 2 of 2)
Date and Document
Version
October 2005 v3.1
Changes Made
●
●
Minor edits
Graphic updates
May 2005
v3.0
Updated “IEEE Std. 1149.1 (JTAG) Boundary-Scan
Support” section
January 2005
v2.0
Added information about USERCODE registers
June 2003
v1.0
Initial release of Chapter 7, Boundary-Scan Support, in the
HardCopy Device Handbook
Altera Corporation
September 2008
Summary of Changes
—
3–5
Preliminary
HardCopy Series Handbook, Volume 1
3–6
Preliminary
Altera Corporation
September 2008
4. Operating Conditions
H51005-3.4
Recommended
Operating
Conditions
Tables 4–1 through 4–3 provide information on absolute maximum
ratings, recommended operating conditions, DC operating conditions,
and capacitance for 1.5-V HardCopy ® Stratix® devices.
Table 4–1. HardCopy Stratix Device Absolute Maximum Ratings
Symbol
VCCINT
Parameter
Supply voltage
Notes (1), (2)
Conditions
With respect to ground
VCCIO
Minimum
Maximum
Unit
–0.5
2.4
V
–0.5
4.6
V
VI
DC input voltage (3)
–0.5
4.6
V
IOUT
DC output current, per pin
–25
40
mA
TSTG
Storage temperature
No bias
–65
150
°C
TJ
Junction temperature
BGA packages under bias
135
°C
Minimum
Maximum
Unit
1.425
1.575
V
3.00 (3.135)
3.60 (3.465)
V
Table 4–2. HardCopy Stratix Device Recommended Operating Conditions
Symbol
Parameter
Conditions
VCCINT
Supply voltage for internal logic (4)
and input buffers
VCCIO
Supply voltage for output
buffers, 3.3-V operation
(4), (5)
Supply voltage for output
buffers, 2.5-V operation
(4)
2.375
2.625
V
Supply voltage for output
buffers, 1.8-V operation
(4)
1.71
1.89
V
Supply voltage for output
buffers, 1.5-V operation
(4)
1.4
1.6
V
VI
Input voltage
(3), (6)
–0.5
4.1
V
VO
Output voltage
0
VCCIO
V
TJ
Operating junction temperature For commercial use
0
85
°C
–40
100
°C
For industrial use
Altera Corporation
September 2008
4–1
Recommended Operating Conditions
Table 4–3. HardCopy Stratix Device DC Operating Conditions
Symbol
Parameter
Conditions
Note (7)
Minimum
Typical
Maximum
Unit
II
Input pin leakage current VI = VCCIOmax to 0 V (8)
–10
10
μA
IOZ
Tri-stated I/O pin leakage VO = VCCIOmax to 0 V
current
(8)
–10
10
μA
ICC0
VCC supply current
(standby) (All memory
blocks in power-down
mode)
VI = ground, no load,
no toggling inputs
RCONF
Value of I/O pin pull-up
resistor before and
during configuration
Vi=0; VCCIO = 3.3 V (9)
15
25
50
kΩ
Vi=0; VCCIO = 2.5 V (9)
20
45
70
kΩ
Vi=0; VCCIO = 1.8 V (9)
30
65
100
kΩ
Vi=0; VCCIO = 1.5 V (9)
50
100
150
kΩ
1
2
kΩ
Recommended value of
I/O pin external
pull-down resistor before
and during configuration
mA
Notes to Tables 4–1 through 4–3:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
4–2
Refer to the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
Typical values are for TA = 25 °C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
This value is specified for normal device operation. The value may vary during power up. This applies for all VCCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO .
Altera Corporation
September 2008
Operating Conditions
Tables 4–4 through 4–31 list the DC operating specifications for the
supported I/O standards. These tables list minimal specifications only;
HardCopy Stratix devices may exceed these specifications. Table 4–32
provides information on capacitance for 1.5-V HardCopy Stratix
devices.
Table 4–4. LVTTL Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO
Output supply voltage
3.0
3.6
V
VI H
High-level input voltage
1.7
4.1
V
VIL
Low-level input voltage
–0.5
0.7
V
VOH
High-level output voltage
IOH = –4 to –24 mA (1)
VOL
Low-level output voltage
IOL = 4 to 24 mA (1)
2.4
V
0.45
V
Minimum
Maximum
Unit
Table 4–5. LVCMOS Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
3.0
3.6
V
VIH
High-level input voltage
1.7
4.1
V
VIL
Low-level input voltage
–0.5
0.7
V
VOH
High-level output voltage
VCCIO = 3.0,
IOH = –0.1 mA
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA
VCCIO – 0.2
V
0.2
V
Minimum
Maximum
Unit
2.375
2.625
V
Table 4–6. 2.5-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VIH
High-level input voltage
1.7
4.1
V
VIL
Low-level input voltage
–0.5
0.7
V
VOH
High-level output voltage
VOL
Low-level output voltage
Altera Corporation
September 2008
IOH = –0.1 mA
2.1
V
IOH = –1 mA
2.0
V
IOH = –2 to –16 mA (1)
1.7
V
IOL = 0.1 mA
0.2
V
IOL = 1 mA
0.4
V
IOL = 2 to 16 mA (1)
0.7
V
4–3
Recommended Operating Conditions
Table 4–7. 1.8-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VI H
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 to –8 mA (1)
VOL
Low-level output voltage
IOL = 2 to 8 mA (1)
Minimum
Maximum
Unit
1.65
1.95
V
0.65 × VCCIO
2.25
V
–0.3
0.35 × VCCIO
V
VCCIO – 0.45
V
0.45
V
Minimum
Maximum
Unit
1.4
1.6
V
0.65 × VCCIO
VCCIO + 0.3
V
–0.3
0.35 × VCCIO
V
Table 4–8. 1.5-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VI H
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (1)
VOL
Low-level output voltage
IOL = 2 mA (1)
0.75 × VCCIO
V
0.25 × VCCIO
V
Table 4–9. 3.3-V LVDS I/O Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
I/O supply voltage
VID
Input differential voltage
swing
4–4
Conditions
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
0.1 V < VCM < 1.1 V
J = 1 through 10
300
1,000
mV
1.1 V ≤ VCM ≤ 1.6 V
J=1
200
1,000
mV
1.1 V ≤ VCM ≤ 1.6 V
J = 2 through10
100
1,000
mV
1.6 V < VCM < 1.8 V
J = 1 through 10
300
1,000
mV
Altera Corporation
September 2008
Operating Conditions
Table 4–9. 3.3-V LVDS I/O Specifications (Part 2 of 2)
Symbol
VICM
Parameter
Input common mode
voltage
Conditions
Typical
Maximum
Unit
LVDS
0.3 V < VID < 1.0 V
J = 1 through 10
100
1,100
mV
LVDS
0.3 V < VID < 1.0 V
J = 1 through 10
1,600
1,800
mV
LVDS
0.2 V < VID < 1.0 V
J=1
1,100
1,600
mV
LVDS
0.1 V < VID < 1.0 V
J = 2 through 10
1,100
1,600
mV
550
mV
50
mV
1,375
mV
50
mV
110
Ω
VOD (2)
Output differential
voltage
RL = 100 Ω
Δ VOD
Change in VOD between
high and low
RL = 100 Ω
VOCM
Output common mode
voltage
RL = 100 Ω
Δ VOCM
Change in VOCM between RL = 100 Ω
high and low
RL
Receiver differential
input resistor
Altera Corporation
September 2008
Minimum
250
1,125
90
375
1,200
100
4–5
Recommended Operating Conditions
Table 4–10. 3.3-V PCML Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
VCCIO
I/O supply voltage
VID
Input differential voltage
swing
300
600
mV
VICM
Input common mode
voltage
1.5
3.465
V
VOD
Output differential
voltage
300
500
mV
Δ VOD
Change in VOD between
high and low
50
mV
VOCM
Output common mode
voltage
3.3
V
Δ VOCM
Change in VOCM between
high and low
50
mV
VT
Output termination
voltage
R1
Output external pull-up
resistors
45
50
55
Ω
R2
Output external pull-up
resistors
45
50
55
Ω
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
300
1,000
mV
1
2
V
2.5
370
2.85
VCCIO
V
Table 4–11. LVPECL Specifications
Symbol
Parameter
Conditions
VCCIO
I/O supply voltage
VID
Input differential voltage
swing
VICM
Input common mode
voltage
VOD
Output differential
voltage
RL = 100 Ω
525
700
970
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1.5
1.7
1.9
V
RL
Receiver differential
input resistor
90
100
110
Ω
4–6
Altera Corporation
September 2008
Operating Conditions
Table 4–12. HyperTransport Technology Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VCCIO
I/O supply voltage
VID
Input differential voltage
swing
300
900
mV
VICM
Input common mode
voltage
300
900
mV
VOD
Output differential
voltage
RL = 100 Ω
820
mV
Δ VOD
Change in VOD between
high and low
RL = 100 Ω
50
mV
VOCM
Output common mode
voltage
RL = 100 Ω
780
mV
Δ VOCM
Change in VOCM between RL = 100 Ω
high and low
50
mV
RL
Receiver differential
input resistor
380
440
485
650
90
100
110
Ω
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
Table 4–13. 3.3-V PCI Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VIH
High-level input voltage
0.5 × VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.5
0.3 × VCCIO
V
VOH
High-level output voltage IOUT = –500 μA
VOL
Low-level output voltage
0.9 × VCCIO
V
IOUT = 1,500 μA
0.1 × VCCIO
V
Maximum
Unit
3.6
V
Table 4–14. PCI-X 1.0 Specifications
Symbol
Parameter
Conditions
Minimum
VCCIO
Output supply voltage
VIH
High-level input voltage
0.5 × VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.5
0.35 × VCCIO
V
VIPU
Input pull-up voltage
VOH
High-level output voltage IOUT = –500 μA
VOL
Low-level output voltage
Altera Corporation
September 2008
3.0
Typical
0.7 × VCCIO
IOUT = 1,500 μA
V
0.9 × VCCIO
V
0.1 × VCCIO
V
4–7
Recommended Operating Conditions
Table 4–15. GTL+ I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VTT
Termination voltage
1.35
1.5
1.65
V
VREF
Reference voltage
0.88
1.0
1.12
V
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
VREF + 0.1
V
IOL = 34 mA (1)
VREF – 0.1
V
0.65
V
Table 4–16. GTL I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VTT
Termination voltage
1.14
1.2
1.26
V
VREF
Reference voltage
0.74
0.8
0.86
V
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
VREF + 0.05
V
IOL = 40 mA (1)
VREF – 0.05
V
0.4
V
Table 4–17. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.65
1.8
1.95
V
VCCIO
Output supply voltage
VREF
Reference voltage
0.8
0.9
1.0
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH(DC)
High-level DC input
voltage
VREF + 0.125
VIL(DC)
Low-level DC input
voltage
VIH(AC)
High-level AC input
voltage
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –6.7 mA (1)
VOL
Low-level output voltage
4–8
V
VREF – 0.125
VREF + 0.275
V
VREF – 0.275
IOL = 6.7 mA (1)
V
VTT + 0.475
V
V
VTT – 0.475
V
Altera Corporation
September 2008
Operating Conditions
Table 4–18. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.65
1.8
1.95
V
0.8
0.9
1.0
V
VREF
VREF + 0.04
V
VCCIO
Output supply voltage
VREF
Reference voltage
VTT
Termination voltage
VREF – 0.04
VIH(DC)
High-level DC input
voltage
VREF + 0.125
VIL(DC)
Low-level DC input
voltage
VIH(AC)
High-level AC input
voltage
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –13.4 mA (1)
VOL
Low-level output voltage
V
VREF – 0.125
VREF + 0.275
V
V
VREF – 0.275
VTT + 0.630
V
V
IOL = 13.4 mA (1)
VTT – 0.630
V
Table 4–19. SSTL-2 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.25
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
1.15
1.35
V
VIH(DC)
High-level DC input
voltage
VREF + 0.18
3.0
V
VIL(DC)
Low-level DC input
voltage
–0.3
VREF – 0.18
V
VIH(AC)
High-level AC input
voltage
VREF + 0.35
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –8.1 mA (1)
VOL
Low-level output voltage
V
VREF – 0.35
VTT + 0.57
V
V
IOL = 8.1 mA (1)
VTT – 0.57
V
Table 4–20. SSTL-2 Class II Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
Altera Corporation
September 2008
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
4–9
Recommended Operating Conditions
Table 4–20. SSTL-2 Class II Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.25
1.35
V
VREF
Reference voltage
1.15
VIH(DC)
High-level DC input
voltage
VREF + 0.18
VCCIO + 0.3
V
VIL(DC)
Low-level DC input
voltage
–0.3
VREF – 0.18
V
VIH(AC)
High-level AC input
voltage
VREF + 0.35
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –16.4 mA (1)
VOL
Low-level output voltage
V
VREF – 0.35
VTT + 0.76
V
V
IOL = 16.4 mA (1)
VTT – 0.76
V
Table 4–21. SSTL-3 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
VCCIO
Output supply voltage
VTT
Termination voltage
VREF – 0.05
VREF
VREF + 0.05
V
VREF
Reference voltage
1.3
1.5
1.7
V
VIH(DC)
High-level DC input
voltage
VREF + 0.2
VCCIO + 0.3
V
VIL(DC)
Low-level DC input
voltage
–0.3
VREF – 0.2
V
VIH(AC)
High-level AC input
voltage
VREF + 0.4
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –8 mA (1)
VOL
Low-level output voltage
V
VREF – 0.4
VTT + 0.6
V
V
IOL = 8 mA (1)
VTT – 0.6
V
Table 4–22. SSTL-3 Class II Specifications (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
VCCIO
Output supply voltage
VTT
Termination voltage
VREF – 0.05
VREF
VREF + 0.05
V
VREF
Reference voltage
1.3
1.5
1.7
V
4–10
Altera Corporation
September 2008
Operating Conditions
Table 4–22. SSTL-3 Class II Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VIH(DC)
High-level DC input
voltage
VREF + 0.2
VCCIO + 0.3
V
VIL(DC)
Low-level DC input
voltage
–0.3
VREF – 0.2
V
VIH(AC)
High-level AC input
voltage
VREF + 0.4
VIL(AC)
Low-level AC input
voltage
VOH
High-level output voltage IOH = –16 mA (1)
VOL
Low-level output voltage
V
VREF – 0.4
VT T + 0.8
V
V
IOL = 16 mA (1)
VTT – 0.8
V
Table 4–23. 3.3-V AGP 2× Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.15
3.3
3.45
V
VCCIO
Output supply voltage
VREF
Reference voltage
0.39 × VCCIO
0.41 × VCCIO
V
VIH
High-level input voltage
(4)
0.5 × VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
(4)
0.3 × VCCIO
V
VOH
High-level output voltage IOUT = –0.5 mA
VOL
Low-level output voltage
0.9 × VCCIO
IOUT = 1.5 mA
3.6
V
0.1 × VCCIO
V
Maximum
Unit
Table 4–24. 3.3-V AGP 1× Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VIH
High-level input voltage
(4)
VIL
Low-level input voltage
(4)
VOH
High-level output voltage IOUT = –0.5 mA
VOL
Low-level output voltage
Altera Corporation
September 2008
Minimum
Typical
3.15
3.3
0.5 × VCCIO
IOUT = 1.5 mA
0.9 × VCCIO
3.45
V
VCCIO + 0.5
V
0.3 × VCCIO
V
3.6
V
0.1 × VCCIO
V
4–11
Recommended Operating Conditions
Table 4–25. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.4
1.5
1.6
V
VREF
Input reference voltage
0.68
0.75
0.9
V
VTT
Termination voltage
0.7
0.75
0.8
V
VIH (DC)
DC high-level input
voltage
VREF + 0.1
VIL (DC)
DC low-level input
voltage
–0.3
VIH (AC)
AC high-level input
voltage
VREF + 0.2
VIL (AC)
AC low-level input
voltage
VOH
High-level output voltage IOH = 8 mA (1)
VOL
Low-level output voltage
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
IOH = –8 mA (1)
0.4
V
Table 4–26. 1.5-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.4
1.5
1.6
V
VREF
Input reference voltage
0.68
0.75
0.9
V
VTT
Termination voltage
0.7
0.75
0.8
V
VIH (DC)
DC high-level input
voltage
VREF + 0.1
VIL (DC)
DC low-level input
voltage
–0.3
VIH (AC)
AC high-level input
voltage
VREF + 0.2
VIL (AC)
AC low-level input
voltage
VOH
High-level output voltage IOH = 16 mA (1)
VOL
Low-level output voltage
4–12
V
VREF – 0.1
V
VREF – 0.2
IOH = –16 mA (1)
V
VCCIO – 0.4
V
V
0.4
V
Altera Corporation
September 2008
Operating Conditions
Table 4–27. 1.8-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.65
1.80
1.95
V
VREF
Input reference voltage
0.70
0.90
0.95
V
VCCIO × 0.5
VTT
Termination voltage
VIH (DC)
DC high-level input
voltage
VREF + 0.1
VIL (DC)
DC low-level input
voltage
–0.5
VIH (AC)
AC high-level input
voltage
VREF + 0.2
VIL (AC)
AC low-level input
voltage
VOH
High-level output voltage IOH = 8 mA (1)
VOL
Low-level output voltage
V
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
IOH = –8 mA (1)
0.4
V
Table 4–28. 1.8-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.65
1.80
1.95
V
VREF
Input reference voltage
0.70
0.90
0.95
V
VCCIO × 0.5
VTT
Termination voltage
VIH (DC)
DC high-level input
voltage
VREF + 0.1
VIL (DC)
DC low-level input
voltage
–0.5
VIH (AC)
AC high-level input
voltage
VREF + 0.2
VIL (AC)
AC low-level input
voltage
VOH
High-level output voltage IOH = 16 mA (1)
VOL
Low-level output voltage
Altera Corporation
September 2008
V
V
VREF – 0.1
V
VREF – 0.2
IOH = –16 mA (1)
V
VCCIO – 0.4
V
V
0.4
V
4–13
Recommended Operating Conditions
Table 4–29. 1.5-V Differential HSTL Specifications
Symbol
VCCIO
Parameter
Conditions
I/O supply voltage
VDIF (DC) DC input differential
voltage
Minimum
Typical
Maximum
Unit
1.4
1.5
1.6
V
0.2
VCM (DC) DC common mode input
voltage
V
0.68
VDIF (AC) AC differential input
voltage
0.9
V
0.4
V
Table 4–30. CTT I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
2.05
3.3
3.6
V
VTT/VREF
Termination and input
reference voltage
1.35
1.5
1.65
V
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
IO
Output leakage current
(when output is high Z)
GND ≤ VO U T ≤
VC CI O
VREF + 0.2
V
VREF – 0.2
VREF + 0.4
V
V
VREF – 0.4
V
10
μA
3.3 V
Unit
–10
Table 4–31. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
1.5 V
Min
Low sustaining current
VIN > VIL (maximum)
High sustaining current VIN < VIH (minimum)
Max
1.8 V
Min
Max
2.5 V
Min
Max
Min
Max
25
30
50
70
μA
–25
–30
–50
–70
μA
Low overdrive current
0 V < VIN < VCCIO
160
200
300
500
μA
High overdrive current
0 V < VIN < VCCIO
–160
–200
–300
–500
μA
2.0
V
Bus hold trip point
4–14
0.5
1.0
0.68
1.07
0.7
1.7
0.8
Altera Corporation
September 2008
Operating Conditions
Table 4–32. Stratix Device Capacitance
Symbol
Note (5)
Parameter
Minimum
Typical
Maximum
Unit
CIOTB
Input capacitance on I/O pins in I/O banks 3, 4, 7,
and 8.
11.5
pF
CIOLR
Input capacitance on I/O pins in I/O banks 1, 2, 5,
and 6, including high-speed differential receiver
and transmitter pins.
8.2
pF
CCLKTB
Input capacitance on top/bottom clock input pins:
CLK[4..7] and CLK[12..15] .
11.5
pF
CCLKLR
Input capacitance on left/right clock inputs: CLK1,
CLK3 , CLK8, CLK10.
7.8
pF
CCLKLR+
Input capacitance on left/right clock inputs: CLK0,
CLK2 , CLK9, and CLK11.
4.4
pF
Notes to Tables 4–4 through 4–32:
(1)
(2)
(3)
(4)
(5)
Drive strength is programmable according to values in the Stratix Architecture chapter of the Stratix Device
Handbook.
When the tx_outclock port of the altlvds_tx megafunction is 717 MHz, VO D ( m i n ) = 235 mV on the output
clock pin.
Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
VREF specifies the center point of the switching range.
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
Power
Consumption
Altera offers two ways to calculate power for a design, the Altera® web
power calculator and the power estimation feature in the Quartus® II
software.
The interactive power calculator on the Altera website is typically used
prior to designing the FPGA in order to get a magnitude estimate of the
device power. The Quartus II software power estimation feature allows
designers to apply test vectors against their design for more accurate
power consumption modeling.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
Timing Closure
Altera Corporation
September 2008
The timing numbers in Tables 4–34 to 4–43 are only provided as an
indication of allowable timing for HardCopy Stratix devices. The
Quartus II software provides preliminary timing information for
HardCopy Stratix designs, which can be used as an estimation of the
device performance.
4–15
Timing Closure
The final timing numbers and actual performance for each HardCopy
Stratix design is available when the design migration is complete and are
subject to verification and approval by Altera and the designer during the
HardCopy Design review process.
f
For more information, refer to the HardCopy Series Back-End Timing
Closure chapter in the HardCopy Series Handbook.
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–1 shows the pin-to-pin timing model for bidirectional
IOE pin timing. All registers are within the IOE.
Figure 4–1. External Timing in HardCopy Stratix Devices
OE Register
D
PRN
Q
Dedicated
Clock
CLRN
Output Register
D
PRN
Q
tINSU
tINH
tOUTCO
tXZ
tZX
Bidirectional
Pin
CLRN
Input Register
D
PRN
Q
CLRN
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
4-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in the Stratix Device Handbook.
4–16
Altera Corporation
September 2008
Operating Conditions
Table 4–33 shows the external I/O timing parameters when using global
clock networks.
Table 4–33. HardCopy Stratix Global Clock External I/O Timing Parameters
Notes (1), (2)
Symbol
Parameter
tINSU
Setup time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
tINH
Hold time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
tOUTCO
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by CLK pin
tINSUPLL
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
tINHPLL
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
tOUTCOPLL
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
tXZPLL
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
tZXPLL
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Notes to Table 4–33:
(1)
(2)
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. Designers should use
the Quartus II software to verify the external timing for any pin.
HardCopy Stratix External I/O Timing
These timing parameters are for both column IOE and row IOE pins. In
HC1S30 devices and above, designers can decrease the tSU time by using
FPLLCLK, but may get positive hold time in HC1S60 and HC1S80
devices. Designers should use the Quartus II software to verify the
external devices for any pin.
Altera Corporation
September 2008
4–17
Timing Closure
Tables 4–34 through 4–35 show the external timing parameters on column
and row pins for HC1S25 devices.
Table 4–34. HC1S25 External I/O Timing on Column Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Max
tINSU
1.371
ns
tINH
0.000
ns
tOUTCO
2.809
7.155
ns
tXZ
2.749
7.040
ns
tZX
2.749
7.040
ns
tINSUPLL
1.271
ns
tINHPLL
0.000
ns
tOUTCOPLL
1.124
2.602
ns
tXZPLL
1.064
2.487
ns
tZXPLL
1.064
2.487
ns
Table 4–35. HC1S25 External I/O Timing on Row Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
4–18
Max
tINSU
1.665
ns
tINH
0.000
ns
tOUTCO
2.834
7.194
ns
tXZ
2.861
7.276
ns
tZX
2.861
7.276
ns
tINSUPLL
1.538
tINHPLL
0.000
tOUTCOPLL
1.164
2.653
ns
tXZPLL
1.191
2.735
ns
tZXPLL
1.191
2.735
ns
ns
ns
Altera Corporation
September 2008
Operating Conditions
Tables 4–36 through 4–37 show the external timing parameters on column
and row pins for HC1S30 devices.
Table 4–36. HC1S30 External I/O Timing on Column Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Max
tINSU
1.935
ns
tINH
0.000
ns
tOUTCO
2.814
7.274
ns
tXZ
2.754
7.159
ns
tZX
2.754
7.159
ns
tINSUPLL
1.265
ns
tINHPLL
0.000
ns
tOUTCOPLL
1.068
2.423
ns
tXZPLL
1.008
2.308
ns
tZXPLL
1.008
2.308
ns
Table 4–37. HC1S30 External I/O Timing on Row Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Altera Corporation
September 2008
Max
tINSU
1.995
ns
tINH
0.000
ns
tOUTCO
2.917
7.548
ns
tXZ
2.944
7.630
ns
tZX
2.944
7.630
ns
tINSUPLL
1.337
tINHPLL
0.000
tOUTCOPLL
1.164
2.672
ns
tXZPLL
1.191
2.754
ns
tZXPLL
1.191
2.754
ns
ns
ns
4–19
Timing Closure
Tables 4–38 through 4–39 show the external timing parameters on column
and row pins for HC1S40 devices.
Table 4–38. HC1S40 External I/O Timing on Column Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Max
tINSU
2.126
ns
tINH
0.000
ns
tOUTCO
2.856
7.253
ns
tXZ
2.796
7.138
ns
tZX
2.796
7.138
ns
tINSUPLL
1.466
ns
tINHPLL
0.000
ns
tOUTCOPLL
1.092
2.473
ns
tXZPLL
1.032
2.358
ns
tZXPLL
1.032
2.358
ns
Table 4–39. HC1S40 External I/O Timing on Row Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
4–20
Max
tINSU
2.020
ns
tINH
0.000
ns
tOUTCO
2.912
7.480
ns
tXZ
2.939
7.562
ns
tZX
2.939
7.562
ns
tINSUPLL
1.370
tINHPLL
0.000
tOUTCOPLL
1.144
2.693
ns
tXZPLL
1.171
2.775
ns
tZXPLL
1.171
2.775
ns
ns
ns
Altera Corporation
September 2008
Operating Conditions
Tables 4–40 through 4–41 show the external timing parameters on column
and row pins for HC1S60 devices.
Table 4–40. HC1S60 External I/O Timing on Column Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Max
tINSU
2.000
ns
tINH
0.000
ns
tOUTCO
3.051
6.977
ns
tXZ
2.991
6.853
ns
tZX
2.991
6.853
ns
tINSUPLL
1.315
ns
tINHPLL
0.000
ns
tOUTCOPLL
1.029
2.323
ns
tXZPLL
0.969
2.199
ns
tZXPLL
0.969
2.199
ns
Table 4–41. HC1S60 External I/O Timing on Row Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Altera Corporation
September 2008
Max
tINSU
2.232
ns
tINH
0.000
ns
tOUTCO
3.182
7.286
ns
tXZ
3.209
7.354
ns
tZX
3.209
7.354
ns
tINSUPLL
1.651
tINHPLL
0.000
tOUTCOPLL
1.154
2.622
ns
tXZPLL
1.181
2.690
ns
tZXPLL
1.181
2.690
ns
ns
ns
4–21
Timing Closure
Tables 4–42 through 4–43 show the external timing parameters on column
and row pins for HC1S80 devices.
Table 4–42. HC1S80 External I/O Timing on Column Pins Using Global Clock
Networks
Performance
Parameter
Unit
Min
Max
tINSU
0.884
ns
tINH
0.000
ns
tOUTCO
3.267
7.415
ns
tXZ
3.207
7.291
ns
tZX
3.207
7.291
ns
tINSUPLL
0.506
ns
tINHPLL
0.000
ns
tOUTCOPLL
1.635
2.828
ns
tXZPLL
1.575
2.704
ns
tZXPLL
1.575
2.704
ns
Table 4–43. HC1S80 External I/O Timing on Rows Using Pin Global Clock
Networks
Performance
Symbol
Unit
Min
4–22
Max
tINSU
1.362
ns
tINH
0.000
ns
tOUTCO
3.457
7.859
ns
tXZ
3.484
7.927
ns
tZX
3.484
7.927
ns
tINSUPLL
0.994
tINHPLL
0.000
tOUTCOPLL
1.821
3.254
ns
tXZPLL
1.848
3.322
ns
tZXPLL
1.848
3.322
ns
ns
ns
Altera Corporation
September 2008
Operating Conditions
Maximum Input and Output Clock Rates
Tables 4–44 through 4–46 show the maximum input clock rate for column
and row pins in HardCopy Stratix devices.
Table 4–44. HardCopy Stratix Maximum Input Clock Rate for CLK[7..4] and
CLK[15..12] Pins
I/O Standard
Altera Corporation
September 2008
Performance
Unit
LVTTL
422
MHz
2.5 V
422
MHz
1.8 V
422
MHz
1.5 V
422
MHz
LVCMOS
422
MHz
GTL
300
MHz
GTL+
300
MHz
SSTL-3 class I
400
MHz
SSTL-3 class II
400
MHz
SSTL-2 class I
400
MHz
SSTL-2 class II
400
MHz
SSTL-18 class I
400
MHz
SSTL-18 class II
400
MHz
1.5-V HSTL class I
400
MHz
1.5-V HSTL class II
400
MHz
1.8-V HSTL class I
400
MHz
1.8-V HSTL class II
400
MHz
3.3-V PCI
422
MHz
3.3-V PCI-X 1.0
422
MHz
Compact PCI
422
MHz
AGP 1×
422
MHz
AGP 2×
422
MHz
CTT
300
MHz
Differential HSTL
400
MHz
LVPECL (1)
645
MHz
PCML (1)
300
MHz
LVDS (1)
645
MHz
HyperTransport
technology (1)
500
MHz
4–23
Timing Closure
Table 4–45. HardCopy Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11]
Pins and FPLL[10..7]CLK Pins
I/O Standard
4–24
Performance
Unit
LVTTL
422
MHz
2.5 V
422
MHz
1.8 V
422
MHz
1.5 V
422
MHz
LVCMOS
422
MHz
GTL
300
MHz
GTL+
300
MHz
SSTL-3 class I
400
MHz
SSTL-3 class II
400
MHz
SSTL-2 class I
400
MHz
SSTL-2 class II
400
MHz
SSTL-18 class I
400
MHz
SSTL-18 class II
400
MHz
1.5-V HSTL class I
400
MHz
1.5-V HSTL class II
400
MHz
1.8-V HSTL class I
400
MHz
1.8-V HSTL class II
400
MHz
3.3-V PCI
422
MHz
3.3-V PCI-X 1.0
422
MHz
Compact PCI
422
MHz
AGP 1×
422
MHz
AGP 2×
422
MHz
CTT
300
MHz
Differential HSTL
400
MHz
LVPECL (1)
717
MHz
PCML (1)
400
MHz
LVDS (1)
717
MHz
HyperTransport
technology (1)
717
MHz
Altera Corporation
September 2008
Operating Conditions
Table 4–46. HardCopy Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10]
Pins
I/O Standard
Performance
Unit
LVTTL
422
MHz
2.5 V
422
MHz
1.8 V
422
MHz
1.5 V
422
MHz
LVCMOS
422
MHz
GTL
300
MHz
GTL+
300
MHz
SSTL-3 class I
400
MHz
SSTL-3 class II
400
MHz
SSTL-2 class I
400
MHz
SSTL-2 class II
400
MHz
SSTL-18 class I
400
MHz
SSTL-18 class II
400
MHz
1.5-V HSTL class I
400
MHz
1.5-V HSTL class II
400
MHz
1.8-V HSTL class I
400
MHz
1.8-V HSTL class II
400
MHz
3.3-V PCI
422
MHz
3.3-V PCI-X 1.0
422
MHz
Compact PCI
422
MHz
AGP 1×
422
MHz
AGP 2×
422
MHz
CTT
300
MHz
Differential HSTL
400
MHz
LVPECL (1)
645
MHz
PCML (1)
300
MHz
LVDS (1)
645
MHz
HyperTransport
technology (1)
500
MHz
Note to Tables 4–44 through 4–46:
(1)
Altera Corporation
September 2008
These parameters are only available on row I/O pins.
4–25
Timing Closure
Tables 4–47 through 4–48 show the maximum output clock rate for
column and row pins in HardCopy Stratix devices.
Table 4–47. HardCopy Stratix Maximum Output Clock Rate for PLL[5, 6, 11,
12] Pins (Part 1 of 2)
I/O Standard
4–26
Performance
Unit
LVTTL
350
MHz
2.5 V
350
MHz
1.8 V
250
MHz
1.5 V
225
MHz
LVCMOS
350
MHz
GTL
200
MHz
GTL+
200
MHz
SSTL-3 class I
200
MHz
SSTL-3 class II
200
MHz
SSTL-2 class I (3)
200
MHz
SSTL-2 class I (4)
200
MHz
SSTL-2 class I (5)
150
MHz
SSTL-2 class II (3)
200
MHz
SSTL-2 class II (4)
200
MHz
SSTL-2 class II (5)
150
MHz
SSTL-18 class I
150
MHz
SSTL-18 class II
150
MHz
1.5-V HSTL class I
250
MHz
1.5-V HSTL class II
225
MHz
1.8-V HSTL class I
250
MHz
1.8-V HSTL class II
225
MHz
3.3-V PCI
350
MHz
3.3-V PCI-X 1.0
350
MHz
Compact PCI
350
MHz
AGP 1×
350
MHz
AGP 2×
350
MHz
CTT
200
MHz
Differential HSTL
225
MHz
Differential SSTL-2 (6)
200
MHz
LVPECL (2)
500
MHz
PCML (2)
350
MHz
Altera Corporation
September 2008
Operating Conditions
Table 4–47. HardCopy Stratix Maximum Output Clock Rate for PLL[5, 6, 11,
12] Pins (Part 2 of 2)
I/O Standard
Performance
Unit
LVDS (2)
500
MHz
HyperTransport
technology (2)
350
MHz
Table 4–48. HardCopy Stratix Maximum Output Clock Rate (Using I/O Pins)
for PLL[1, 2, 3, 4] Pins (Part 1 of 2)
I/O Standard
Altera Corporation
September 2008
Performance
Unit
LVTTL
400
MHz
2.5 V
400
MHz
1.8 V
400
MHz
1.5 V
350
MHz
LVCMOS
400
MHz
GTL
200
MHz
GTL+
200
MHz
SSTL-3 class I
167
MHz
SSTL-3 class II
167
MHz
SSTL-2 class I
150
MHz
SSTL-2 class II
150
MHz
SSTL-18 class I
150
MHz
SSTL-18 class II
150
MHz
1.5-V HSTL class I
250
MHz
1.5-V HSTL class II
225
MHz
1.8-V HSTL class I
250
MHz
1.8-V HSTL class II
225
MHz
3.3-V PCI
250
MHz
3.3-V PCI-X 1.0
225
MHz
Compact PCI
400
MHz
AGP 1×
400
MHz
AGP 2×
400
MHz
CTT
300
MHz
Differential HSTL
225
MHz
LVPECL (2)
717
MHz
PCML (2)
420
MHz
4–27
High-Speed I/O Specification
Table 4–48. HardCopy Stratix Maximum Output Clock Rate (Using I/O Pins)
for PLL[1, 2, 3, 4] Pins (Part 2 of 2)
I/O Standard
Performance
Unit
LVDS (2)
717
MHz
HyperTransport
technology (2)
420
MHz
Notes to Tables 4–47 through 4–48:
(1)
(2)
(3)
(4)
(5)
(6)
High-Speed I/O
Specification
Differential SSTL-2 outputs are only available on column clock pins.
These parameters are only available on row I/O pins.
SSTL-2 in maximum drive strength condition.
SSTL-2 in minimum drive strength with ≤10pF output load condition.
SSTL-2 in minimum drive strength with > 10pF output load condition.
Differential SSTL-2 outputs are only supported on column clock pins.
Table 4–49 provides high-speed timing specifications definitions.
Table 4–49. High-Speed Timing Specifications and Terminology
High-Speed Timing Specification
Terminology
tC
High-speed receiver/transmitter input and output clock period.
fHSCLK
High-speed receiver/transmitter input and output clock frequency.
tRISE
Low-to-high transmission time.
tFALL
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t C/w).
fHSDR
Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t SW (max) – tSW (min).
Input jitter (peak-to-peak)
Peak-to-peak input jitter on high-speed PLLs.
Output jitter (peak-to-peak)
Peak-to-peak output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tLOCK
Lock time for high-speed transmitter and receiver PLLs.
4–28
Altera Corporation
September 2008
Operating Conditions
Table 4–50 shows the high-speed I/O timing for HardCopy Stratix
devices.
Table 4–50. High-Speed I/O Specifications (Part 1 of 2) Notes (1), (2)
Performance
Symbol
Conditions
Unit
Min
fHSCLK (Clock frequency)
W=4
(LVDS, LVPECL, HyperTransport W = 2
technology)
W=2
fHSCLK = fHSDR / W
W=1
10
210
MHz
(Serdes bypass)
50
231
MHz
(Serdes used)
150
420
MHz
(Serdes bypass)
100
462
MHz
300
717
MHz
300
840
Mbps
300
840
Mbps
300
840
Mbps
J=4
300
840
Mbps
J=2
100
462
Mbps
J = 1 (LVDS and LVPECL
only)
100
462
Mbps
W = 4 to 30 (Serdes used)
10
100
MHz
W = 2 (Serdes bypass)
50
200
MHz
W = 2 (Serdes used)
150
200
MHz
W = 1 (Serdes bypass)
100
250
MHz
W = 1 (Serdes used)
300
400
MHz
J = 10
300
400
Mbps
J=8
300
400
Mbps
J=7
300
400
Mbps
J=4
300
400
Mbps
J=2
100
400
Mbps
J=1
100
250
Mbps
200
ps
W = 1 (Serdes used)
fHSDR Device operation (PCML)
Max
to 30 (Serdes used)
fHSDR Device operation
J = 10
(LVDS, LVPECL, HyperTransport J = 8
technology)
J=7
fHSCLK (Clock frequency)
(PCML)
fHSCLK = fHSDR / W
Typ
TCCS
All
SW
PCML (J = 4, 7, 8, 10)
750
ps
PCML (J = 2)
900
ps
PCML (J = 1)
Altera Corporation
September 2008
1,500
ps
LVDS and LVPECL (J = 1)
500
ps
LVDS, LVPECL,
HyperTransport technology
(J = 2 through 10)
440
ps
4–29
PLL Specifications
Table 4–50. High-Speed I/O Specifications (Part 2 of 2) Notes (1), (2)
Performance
Symbol
Conditions
Unit
Min
Input jitter tolerance
(peak-to-peak)
All
Output jitter (peak-to-peak)
All
Output t RISE
LVDS
HyperTransport technology
Output t FALL
250
ps
160
ps
80
110
120
ps
110
170
200
ps
90
130
150
ps
PCML
80
110
135
ps
LVDS
80
110
120
ps
110
170
200
ps
90
130
160
ps
PCML
105
140
175
ps
LVDS (J = 2 through 10)
47.5
50
52.5
%
45
50
55
%
100
μs
LVPECL
LVDS (J =1) and LVPECL,
PCML, HyperTransport
technology
tLOCK
Max
LVPECL
HyperTransport technology
tDUTY
Typ
All
Notes to Table 4–50:
(1)
(2)
When J = 4, 7, 8, and 10, the SERDES block is used.
When J = 2 or J = 1, the SERDES is bypassed.
PLL
Specifications
Table 4–51 describes the HardCopy Stratix device enhanced PLL
specifications.
Table 4–51. Enhanced PLL Specifications (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency
3 (1)
684
MHz
fINDUTY
Input clock duty cycle
40
60
%
fEINDUTY
External feedback clock input duty
cycle
40
60
%
tINJITTER
Input clock period jitter
±200 (2)
ps
tEINJITTER
External feedback clock period jitter
±200 (2)
ps
tFCOMP
External feedback clock compensation
time (3)
6
ns
4–30
Altera Corporation
September 2008
Operating Conditions
Table 4–51. Enhanced PLL Specifications (Part 2 of 3)
Symbol
Parameter
Min
fOUT
Output frequency for internal global or
regional clock
fOUT_EXT
Typ
Max
Unit
0.3
500
MHz
Output frequency for external clock (2)
0.3
526
MHz
tOUTDUTY
Duty cycle for external clock output
(when set to 50%)
45
55
%
tJITTER
Period jitter for external clock output (5)
±100 ps for >200 MHz outclk
±20 mUI for 200 MHz. Refer to the Stratix FPGA Errata Sheet for more information on the PLL.
(11) Applicable when the PLL input clock has been running continuously for at least 10 µs.
(12) Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 µs.
4–32
Altera Corporation
September 2008
Operating Conditions
Table 4–52 describes the HardCopy Stratix device fast PLL
specifications.
Table 4–52. Fast PLL Specifications
Symbol
fIN
Parameter
Min
Max
Unit
CLKIN frequency (for m = 1) (1), (2)
300
717
MHz
CLKIN frequency (for m = 2 to 19)
300/
m
1,000/m
MHz
CLKIN frequency (for m = 20 to 32)
10
1,000/m
MHz
fOUT
Output frequency for internal global or
regional clock (3)
9.4
420
MHz
fOUT_EXT
Output frequency for external clock (2)
9.375
717
MHz
fVCO
VCO operating frequency
300
1,000
MHz
tINDUTY
CLKIN duty cycle
40
tINJITTER
Period jitter for CLKIN pin
tDUTY
Duty cycle for DFFIO 1× CLKOUT pin (4)
tJITTER
Period jitter for DFFIO clock out (4)
45
Period jitter for internal global or
regional clock
60
%
±200
ps
55
%
±80
ps
±100 ps for >200-MHz outclk
±20 mUI for 95% LE utilization), and a large number of
LogicLock regions, the design may not fit in the device. Turning off
Reserve Unused Logic in less critical LogicLock regions can help Fitter
placement. The LEs allowed to float in placement and be packed into
unused LEs of LogicLock regions may not be placed optimally after
migration to the HardCopy Stratix device since they are merged with
other LogicLock regions.
After running the HardCopy Timing Optimization Wizard, the
LogicLock region properties are reset to their default conditions. This
allows a successful and immediate placement of your design in the
Quartus II software. You can further refine the LogicLock region
properties for additional benefits.
Altera recommends using the following properties for LogicLock regions
in the HardCopy design project:
■
■
■
■
Turn off Soft Region
Select either Auto or Fixed as the Size after you are satisfied with the
placement and timing result of a LogicLock region in a successful
HardCopy Stratix compilation
Select either Floating or Locked as the Location after you are
satisfied with the placement and timing results
Reserve Unused Logic is not applicable in the HardCopy Stratix
device placement because logic array block (LAB) contents can not
be changed after the HardCopy Timing Optimization Wizard is run
An example of a well partitioned design using LogicLock regions
effectively for some portions of the design is shown in Figure 6–1. Only
the most critical logic functions required are placed in LogicLock regions
in order to achieve the desired performance in the HardCopy Stratix
Altera Corporation
September 2008
6–5
Using Design Space Explorer for HardCopy Stratix Designs
device. The dark blue rectangles shown in Figure 6–1 are the
user-assigned LogicLock regions that have fixed locations. In this
example, the design needed to be constrained by LogicLock regions first
inside the HARDCOPY_FPGA_PROTOTYPE with Reserve Unused
Logic turned off in Properties in LogicLock regions. This selection allows
the Quartus II software to isolate and compact the logic of these blocks in
the HARDCOPY_FPGA_PROTOTYPE such that the placement is tightly
controlled in the HardCopy Stratix device.
Figure 6–1. A Well Partitioned Design
In the example shown in Figure 6–1, once suitable locations were
identified for LogicLock regions, the LogicLock region properties were
changed from floating to locked. The Quartus II software can then
reproduce their placement in subsequent compilations, while focusing
attention on fixing other portions of the design.
Using Design
Space Explorer
for HardCopy
Stratix Designs
6–6
The DSE feature in the Quartus II software allows you to evaluate various
compilation settings to achieve the best results for your FPGA designs.
DSE can also be used in the HardCopy Stratix project after running the
HardCopy Timing Optimization wizard.
Only some of the DSE settings affect HardCopy Stratix designs because
HDL synthesis and physical optimization have been completed on the
FPGA. No logic restructuring can occur after using the HardCopy Timing
Optimization wizard. When you compile your design, the placement of
LABs is optimized in the HardCopy Stratix device. To access the DSE GUI
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
in your open project in the Quartus II software, select Launch Design
Space Explorer (Tools menu). An example of the DSE GUI and DSE
Settings window for the HardCopy Stratix device is shown in Figure 6–2.
Figure 6–2. DSE Settings Window in the DSE GUI
Recommended DSE Settings for HardCopy Stratix Designs
The HardCopy Stratix design does not require all advanced settings or
effort-level settings in DSE. Altera recommends using the following
settings in DSE for HardCopy Stratix designs:
■
■
In the Settings tab (Figure 6–2), make the following selections:
●
Under Project Settings, enter several seed numbers in the Seeds
box. Each seed number requires one full compile of the
HardCopy Stratix project.
●
Under Project Settings, select Allow LogicLock Region
Restructuring.
●
Under Exploration Settings, select Search for Best
Performance, and select Low (Seed Sweep) from the Effort
Level menu.
Turn on Archive all Compilations (Options menu).
After running DSE with the seed sweep setting, view the results and
identify which seed settings produced the best compilation results. Use
the archive of the identified seed, or merge the compilation settings and
seed number from the DSE archived project into your primary HardCopy
Stratix project.
Altera Corporation
September 2008
6–7
Performance Improvement Example
Performance
Improvement
Example
With the design used for the performance improvement example in this
section, the designer was seeking performance improvement on an
HC1S30F780 design for an intellectual property (IP) core consisting of
approximately 5200 LEs, 75,000 bits of memory, and two digital signal
processing (DSP) multiplier accumulators (MACs). The final application
needed to fit in a reserved portion of the HC1S30 device floorplan, so the
entire block of IP was initially bounded in a single LogicLock region. The
IP block was evaluated as a stand-alone block.
Initial Design Example Settings
The default settings in the Quartus II software version 4.2 were used, with
the following initial constraints added:
■
The device was set to the target Stratix FPGA device which is the
prototype for the HC1S30F780 device:
set_global_assignment -name DEVICE
EP1S30F780C6_HARDCOPY_FPGA_PROTOTYPE
■
A LogicLock region was created for the block to bound it in the
reserved region.
■
The LogicLock region properties were set to Auto Size and Floating
Location, and Reserve Unused Logic was turned on:
set_global_assignment -name LL_STATE FLOATING
set_global_assignment -name LL_AUTO_SIZE ON
set_global_assignment -name LL_RESERVED OFF
set_global_assignment -name LL_SOFT OFF
■
Virtual I/O pins were used for the ports of the core since this core
does not interface to pins in the parent design, and the I/O pins were
placed outside the LogicLock region and are represented as registers
in LEs.
The initial compilation results yielded 65.30-MHz fMAX in the FPGA. The
block was constrained through virtual I/O pins and a LogicLock region
to keep the logic from spreading throughout the floorplan.
6–8
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
The initial compile-relevant statistics for this example are provided in
Table 6–1.
Table 6–1. Initial Compilation Statistics
Result Type
Results
fMAX
65.30 MHz
Total logic elements (LEs)
5,187/32,470 (15%)
Total LABs
564/3,247 (17%)
M512 blocks
20/295 (6%)
M4K blocks
16/171 (9%)
M-RAM blocks
0/2 (0%)
Total memory bits
74,752/2,137,536 (3%)
Total RAM block bits
85,248/2,137,536 (3%)
DSP block 9-bit elements
2/96 (2%)
The design project was migrated to the HardCopy device using the
HardCopy Timing Optimization wizard and was compiled. The default
settings of the LogicLock region in a HardCopy Stratix project in the
Quartus II software have the Soft Region option turned on. With this
setting, the HardCopy Stratix compilation yields an f MAX of 66.48 MHz,
mainly due to the Fitter placement being scattered in an open design
(Figure 6–3). Because the Soft Region is set to on, the LogicLock region is
not bounded. This is not an optimal placement in the HardCopy Stratix
design and is not the best possible performance.
Altera Corporation
September 2008
6–9
Performance Improvement Example
Figure 6–3. HardCopy Stratix Device Floorplan with Soft Region On
To keep the LogicLock region contents bounded in the final placement in
the HardCopy Stratix device floorplan, turn off the Soft Region option.
After turning off the Soft Region option and compiling the HardCopy
Stratix design, the result is an fMAX of 88.14 MHz—a gain of 33% over the
Stratix FPGA device performance. The bounded placement in the
LogicLock region helps to achieve performance improvement in
well-partitioned design blocks by taking advantage of the smaller die size
and custom metal routing interconnect of the HardCopy Stratix device.
The floorplan of the bounded LogicLock region is visible in Figure 6–4. In
this figure, you can see the difference in disabling the Soft Region setting
in the HardCopy Stratix design.
6–10
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
Figure 6–4. HardCopy Stratix Device Floorplan with Soft Region Off
Using Analysis and Synthesis Settings for Performance
Improvement
After establishing the baseline for improvement for this design of
65.30 MHz FPGA/88.14 MHz HardCopy, you can gain additional
performance improvement in the Stratix FPGA and HardCopy Stratix
devices using the available features in the Quartus II software.
Changing the Analysis & Synthesis Effort from Balanced to Speed
yields additional benefit in performance, but at the cost of additional LE
resources. The Tcl command for this assignment is as follows:
set_global_assignment -name
STRATIX_OPTIMIZATION_TECHNIQUE SPEED
Altera Corporation
September 2008
6–11
Performance Improvement Example
The relevant compilation results of the FPGA are provided in Table 6–2.
Table 6–2. Relevant Compile Results
Result Type
Results
f MAX
68.88 MHz
Total logic elements
5,508/32,470 (16%)
Total LABs
598/3,247 (18%)
M512 blocks
20/295 (6%)
M4K blocks
16/171 (9%)
M-RAM blocks
0/2 (0%)
Total memory bits
74,752/2,137,536 (3%)
Total RAM block bits
85,248/2,137,536 (3%)
DSP block 9-bit elements
2/96 (2%)
Increasing the LE resources by 6% only yielded an additional 3 MHz in
performance in the FPGA, without using additional settings. However,
after migrating this design to the HardCopy Stratix design and compiling
it, the performance did not improve over the previous HardCopy Stratix
design compile, and was slightly worse in performance at 87.34 MHz.
This shows that the Quartus II software synthesis was very effective with
the Synthesis Effort Level set to Balanced, and there was only marginal
improvement in the FPGA when this option was set to Speed.
The next settings activated in this example were the Synthesis Netlist
Optimizations shown below in Tcl format for WYSIWYG synthesis
remapping and gate-level retiming after synthesis mapping:
set_global_assignment -name
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name
ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
6–12
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
Making these settings in the FPGA while leaving Analysis & Synthesis
Effort set to Speed yielded some additional improvement in the FPGA as
shown in Table 6–3.
Table 6–3. Results of Analysis & Synthesis Effort Set to Speed
Result Type
Results
f MAX
70.28 MHz
Total logic elements
5,515/32,470 (16%)
Total LABs
597/3,247 (18%)
The WYSIWYG resynthesis added a minimal increase in LEs over the
speed setting, and the design performance improved by 2 MHz in the
FPGA. Using the HardCopy Timing Optimization wizard to migrate the
design to HardCopy and subsequently compiling the HardCopy Stratix
design, we find that performance is not improved beyond previous
compiles, with an fMAX of 86.58 MHz.
The Quartus II software automatically optimizes state machines and
restructures multiplexers when these settings are set to Auto in the
Analysis & Synthesis settings. Changing these options from Auto
usually does not yield performance improvement.
For example, changing the multiplexer restructuring and state machine
processing settings from both set to Auto, to On and One-Hot,
respectively, actually hurt performance, not allowing the Quartus II
software to determine the optimization on a case-by-case basis. With
these settings, the FPGA compiled to an fMAX of 65.99 MHz, and the
HardCopy Stratix design only performed at 83.77 MHz. For this design
example, it is better to leave these settings to Auto as seen in the Tcl
assignments in the “Using Fitter Assignments and Physical Synthesis
Optimizations for Performance Improvement” section, and allow the
Quartus II software to determine when to use these features.
Using Fitter Assignments and Physical Synthesis Optimizations
for Performance Improvement
After exploring the Analysis & Synthesis optimization settings in the
Quartus II software, you can use the Fitter Settings and Physical
Synthesis Optimization features to gain further performance
improvement in your Stratix FPGA and HardCopy Stratix devices. In this
design example, multiplexer and state machine restructuring settings
have been set to Auto, and the Synthesis Optimization Technique is set
Altera Corporation
September 2008
6–13
Performance Improvement Example
for Speed. The Fitter effort is set to Standard Fit (highest effort). The
next features enabled are the Physical Synthesis Optimizations as seen
in the Tcl assignments below and in Figure 6–5:
set_global_assignment -name
PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name
PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT
EXTRA
Figure 6–5. Physical Synthesis Optimization Settings
The compiled design shows a performance increase in the FPGA, running
at an fMAX of 74.34 MHz, requiring additional LE resources as a result of
the physical synthesis and logic duplication. In this example, you can see
how performance can be increased in the Stratix FPGA device at the
expense of additional LE resources, as this design’s LE resources grew
almost 12% over the beginning compilation. The compiled FPGA
design’s statistics are provided in Table 6–4.
Table 6–4. Compiled FPGA Design Statistics
6–14
Result Type
Results
f MAX
74.34 MHz
Total logic elements
5,781/32,470 (17%)
Total LABs
610/3,247 (18%)
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
Running the HardCopy Timing Optimization wizard on this design and
compiling the HardCopy Stratix project yields an fMAX of 92.01 MHz,
a 24% improvement over the FPGA timing.
Design Space Explorer
The available Fitter Settings produce an additional performance
improvement. The DSE feature is used on the Stratix FPGA device to run
through the various seeds in the design and select the best seed point to
use for future compiles. This can often yield additional performance
benefits as the Quartus II software further refines placement of the LEs
and performs clustering of associated logic together.
For this design example, DSE was run with high effort (physical
synthesis) and multiple placement seeds. Table 6–5 shows the DSE
results. The base compile matches the fifth compile in the DSE variations,
showing that the work already done on the design before DSE was
optimal. The FPGA project was optimized before running DSE.
Table 6–5. DSE Results
Altera Corporation
September 2008
Compile Point
Clock Period: CLK
Logic Cells
Base (Best)
13.451 ns (74.34 MHz)
5,781
1
13.954 ns
5,703
2
13.712 ns
6,447
3
14.615 ns
5,777
4
13.911 ns
5,742
5
13.451 ns
5,781
6
14.838 ns
5,407
7
14.177 ns
5,751
8
14.479 ns
5,827
9
14.863 ns
5,596
10
14.662 ns
5,605
11
14.250 ns
5,710
12
14.016 ns
5,708
13
13.840 ns
5,802
14
13.681 ns
5,788
15
14.829 ns
5,644
6–15
Performance Improvement Example
Additional correlation is seen inside the .dse.rpt file, showing
the summary of assignments used for each compile inside the Quartus II
software. The base compile settings and the fifth compile settings show
good correlation, as shown in Table 6–6. The MUX_RESTRUCTURE setting
did not have any effect on the design performance. This may be due to an
already efficient HDL coding for multiplexer structures, requiring no
optimization.
Table 6–6. Base Compile and Fifth Compile Correlation
Setting
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
SEED
New Value
Base Value
ON
ON
1
1
STATE_MACHINE_PROCESSING
AUTO
AUTO
MUX_RESTRUCTURE
OFF
AUTO
PHYSICAL_SYNTHESIS_COMBO_LOGIC
ON
ON
STANDARD FIT
STANDARD FIT
NORMAL
NORMAL
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
ON
ON
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
ON
ON
STRATIX_OPTIMIZATION_TECHNIQUE
SPEED
SPEED
PHYSICAL_SYNTHESIS_EFFORT
EXTRA
EXTRA
FITTER_EFFORT
AUTO_PACKED_REGISTERS_STRATIX
The information presented in Table 6–6 confirms that the FPGA Prototype
device has been optimized as much as possible without manual floorplan
adjustments.
Design Space Explorer for HardCopy Stratix Devices
Migrating this compiled design to the HardCopy Stratix project and
compiling the HardCopy Stratix design optimization, results in a design
performance of 92.01 MHz. The next task is to run DSE on the HardCopy
Stratix project using Low Effort (Seed Sweep) in the Exploration
Settings, and entering a range of seed numbers with which to compile the
project.
6–16
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
The results of the DSE run with the Seed Sweep option are summarized
in Table 6–7.
Table 6–7. DSE Results Run with Seed Sweep
Compile Point
Clock Period: CLK
Base (Best)
10.868 ns
1
11.710 ns
2
11.040 ns
3
10.790 ns
4
10.945 ns
5
11.154 ns
6
11.707 ns
7
11.648 ns
8
11.476 ns
9
11.423 ns
10
11.449 ns
The results in Table 6–7 illustrate how the Seed Sweep option in DSE
provides additional improvement in the HardCopy Stratix design, even
after DSE has been run on the Stratix FPGA project. In this example,
compile point 3 using seed value = 4 turns out to be slightly beneficial
over other seeds in the Fitter Placement. The HardCopy Stratix device has
an fMAX of 92.71 MHz.
Back-Annotation and Location Assignment Adjustments
Another technique available for improving performance in the
HardCopy Stratix design is manually adjusting placement and
back-annotating location assignments from the placement results. These
techniques should be one of the last steps taken for design optimization
of HardCopy Stratix devices.
Observing the floorplan of the 92.71 MHz compile (Figure 6–6), the
placement of the LogicLock region is stretched vertically, and additional
improvement is possible if the aspect ratio of the LogicLock region is
defined, and placement in it is refined.
Altera Corporation
September 2008
6–17
Performance Improvement Example
Figure 6–6. Vertically Stretched LogicLock Region
This floorplan would be better optimized if the LogicLock region had a
more square shape, helping the paths that go from memory-to-memory,
by containing the M4K and M512 memory blocks in a smaller space, and
allowing LAB placement to be adjusted by the Fitter. In the HardCopy
Stratix device, signals are routed between LABs, DSP blocks, and
memory blocks using the customized metal layers. The reconfigurable
routing tracks in the Stratix FPGA device limit the routing paths and
delays between elements in the HardCopy Stratix device. This flexibility
allows for aspect ratio changes in LogicLock regions, so the raw distance
between points becomes the critical factor, and not the usage of available
routing resources in the FPGA.
For the final placement optimization in this example, the LogicLock
region was fixed in a square region that encompassed two columns of
M4K blocks, four columns of M512 blocks, two columns of DSP blocks,
and enough LABs to fit the remaining resources required. After
compiling the design with these new LogicLock assignments, the
performance increased to 93.46 MHz in the HardCopy Stratix device. The
critical path and LogicLock region location can be seen in the zoomed-in
area of the floorplan (Figure 6–7).
You can see in Figure 6–7 that the critical path shown is from an M4K
block to an M512 block through several levels of logic. The placement of
the memory blocks can be optimized manually, since the LogicLock
region contains more memory blocks than necessary.
6–18
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
Figure 6–7. Critical Path and LogicLock Region
Fly Lines in Zoomed-In
Portion of Floorplan
Using the critical path “fly lines” as a guide for placement optimization,
manual location assignments were made for some of the M512 and M4K
instances used in the design. The resulting compile improved the fMAX to
94.67 MHz. The new critical path (Figure 6–8) shows how placement of
all path elements are confined to a much smaller area. As a result, the
routing distances and delays are smaller through the path.
Altera Corporation
September 2008
6–19
Performance Improvement Example
Figure 6–8. New Critical Path
Examining this new critical path placement, you can see that there is
room for further performance improvement through additional location
assignments. The current slowest path is 9.775 ns of delay. Manually
moving the LABs in this critical path and placing them between the M4K
and M512 endpoints, and subsequently recompiling, shows improved
results not only for this path, but for several other paths, as this path
contained a major timing bottleneck. The critical path between this start
and endpoint was reduced to 8.797 ns (Figure 6–9). However, the entire
design only improved to 100.30 MHz because other paths are now the
slowest paths in the design. This illustrates that fixing one major
bottleneck path can raise the entire design performance since one high
fanout node can affect multiple timing paths, as was the case in this
example.
6–20
Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
Figure 6–9. Improved Results
In summary, this design example started with 65.30 MHz in the Stratix
FPGA device, and was improved to 74.34 MHz. It was then taken from
the Stratix FPGA device compile and improved to 100.30 MHz in the
HardCopy Stratix design, for a performance improvement of 35%.
Conclusion
Using performance-optimization techniques specifically for HardCopy
Stratix devices can achieve significant performance improvement over
the Stratix FPGA prototype device. Many of these changes must be
incorporated up-front in the HARDCOPY_FPGA_PROTOTYPE so that
your design is properly prepared for performance improvement after
running the HardCopy Timing Optimization wizard.
The example discussed in this chapter demonstrates the process for
performance improvement and various features in the Quartus II
software available for use when optimizing your Stratix FPGA prototype
and HardCopy Stratix device. It also demonstrates the importance of
planning ahead for the HardCopy Stratix design implementation while
continuing to work in the HARDCOPY_FPGA_PROTOTYPE design if
you are going to seek performance improvement in the HardCopy Stratix
device.
Altera Corporation
September 2008
6–21
Document Revision History
Document
Revision History
Table 6–8 shows the revision history for this chapter.
Table 6–8. Document Revision History
Date and Document
Version
Changes Made
September 2008
v1.4
Updated chapter number and metadata.
June 2007 v1.3
●
●
Updated the “Background Information” section.
Completed minor typographical updates.
Summary of Changes
—
—
December 2006
v1.2
Updated revision history.
—
March 2006
Formerly chapter 21; no content change.
—
October 2005 v1.1
●
●
July 2005
v1.0
6–22
Updated graphics
Minor edits
Initial release of Chapter 21, Design Guidelines
for HardCopy Stratix Performance Improvement.
—
—
Altera Corporation
September 2008
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