25G Ethernet Intel Stratix 10 FPGA
IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 18.1
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Contents
Contents
1. About the 25G Ethernet Intel FPGA IP Core.................................................................... 4
1.1. 25G Ethernet Intel FPGA IP Core Supported Features................................................ 7
1.2. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support.....................9
1.2.1. 25G Ethernet Intel FPGA IP Core Device Family Support..................................9
1.2.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support....................... 10
1.3. IP Core Verification.............................................................................................. 10
1.3.1. Simulation Environment............................................................................11
1.3.2. Compilation Checking............................................................................... 11
1.3.3. Hardware Testing..................................................................................... 11
1.4. Performance and Resource Utilization..................................................................... 11
1.5. Release Information............................................................................................. 14
2. Getting Started............................................................................................................. 15
2.1. Installing and Licensing Intel FPGA IP Cores............................................................ 15
2.1.1. Intel FPGA IP Evaluation Mode................................................................... 16
2.2. Specifying the Intel Stratix 10 IP Core Parameters and Options.................................. 18
2.3. Simulating the IP Core..........................................................................................18
2.4. Generated File Structure....................................................................................... 19
2.5. Integrating Your IP Core in Your Design.................................................................. 22
2.5.1. Pin Assignments...................................................................................... 22
2.5.2. Adding the Transceiver PLL .......................................................................22
2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP
Feature...................................................................................................24
2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core.......................... 26
2.6. Compiling the Full Design and Programming the FPGA.............................................. 27
3. 25G Ethernet Intel FPGA IP Core Parameters............................................................... 28
4. Functional Description.................................................................................................. 31
4.1. 25G Ethernet Intel FPGA IP Core Functional Description............................................ 31
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath.......................................32
4.1.2. 25 GbE TX PCS........................................................................................ 34
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath...................................... 34
4.1.4. Link Fault Signaling Interface.....................................................................38
4.1.5. 25 GbE RX PCS........................................................................................40
4.1.6. Flow Control............................................................................................40
4.1.7. 1588 Precision Time Protocol Interfaces...................................................... 43
4.2. User Interface to Ethernet Transmission.................................................................. 52
4.2.1. Order of Transmission...............................................................................52
4.2.2. Bit Order For TX and RX Datapaths.............................................................53
5. Reset............................................................................................................................ 54
6. Interfaces and Signal Descriptions............................................................................... 55
6.1.
6.2.
6.3.
6.4.
6.5.
TX MAC Interface to User Logic..............................................................................56
RX MAC Interface to User Logic..............................................................................58
Transceivers........................................................................................................59
Transceiver Reconfiguration Signals........................................................................ 60
Avalon-MM Management Interface..........................................................................62
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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Contents
6.6.
6.7.
6.8.
6.9.
PHY Interface Signals........................................................................................... 62
1588 PTP Interface Signals....................................................................................64
Miscellaneous Status and Debug Signals................................................................. 69
Reset Signals...................................................................................................... 69
7. Control, Status, and Statistics Register Descriptions.....................................................70
7.1.
7.2.
7.3.
7.4.
7.5.
PHY Registers......................................................................................................71
TX MAC Registers.................................................................................................73
RX MAC Registers................................................................................................ 74
Pause/PFC Flow Control Registers...........................................................................75
Statistics Registers...............................................................................................79
7.5.1. TX Statistics Registers.............................................................................. 80
7.5.2. RX Statistics Registers.............................................................................. 83
7.6. 1588 PTP Registers.............................................................................................. 86
7.7. TX Reed-Solomon FEC Registers............................................................................ 89
7.8. RX Reed-Solomon FEC Registers............................................................................ 89
8. Debugging the Link....................................................................................................... 91
8.1. Error Insertion Test and Debugging........................................................................ 92
9. 25G Ethernet Intel Stratix 10 FPGA IP User Guide Archives.......................................... 93
10. Document Revision History for the 25G Ethernet Intel Stratix 10 FPGA IP User
Guide....................................................................................................................... 94
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1. About the 25G Ethernet Intel FPGA IP Core
The Intel® Stratix® 10 25G Ethernet Intel FPGA IP core implements the 25G & 50G
Ethernet Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and the
IEEE 802.3by 25Gb Ethernet specification. The IP core includes an option to support
unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet
Standard. The MAC client side interface for the 25G Ethernet Intel FPGA IP core is a
64-bit Avalon® Streaming (Avalon-ST) interface. It maps to one 25.78125 Gbps
transceiver. The IP core optionally includes Reed-Solomon forward error correction
(FEC) for support of direct attach copper (DAC) cable. IEEE 802.3 Clause 74 KR-FEC is
not supported.
The IP core provides standard media access control (MAC) and physical coding
sublayer (PCS), Reed-Solomon FEC, and PMA functions shown in the following block
diagram. The PHY comprises the PCS, optional Reed-Solomon FEC, and elective PMA.
Figure 1.
25G Ethernet MAC, PCS, and PMA IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
ATX PLL
clk_ref
390.625 MHz
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
TX
RS-FEC
(optional)
tx_serial_clk
12.890625 GHz
Hard PMA
25.78125 Gbps
TX Serial Interface
Reconfiguration Interface
System Resets
Avalon-ST
RX Client Interface
clk_rxmac
RX
Adapter
390.625 MHz
RX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps
RX Serial Interface
clk_ref
644.53125 MHz/322.265625 MHz
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
1. About the 25G Ethernet Intel FPGA IP Core
UG-20109 | 2018.10.05
Figure 2.
10G/25G Ethernet MAC, PCS, and PMA IP Clock Diagram
ATX PLL
(25G)
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
alt_e25_top
Avalon-MM Management
Interface
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
tx_serial_clk
12.890625 GHz
clk_ref
390.625 MHz (25G) / 156.25 MHz (10G)
TX
Adapter
Avalon-ST
TX Client Interface
ATX PLL
(10G)
tx_serial_clk
5.15625 GHz
TX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps/10.3125 GHz
TX Serial Interface
Reconfiguration Interface
System Resets
RX
Adapter
Avalon-ST
RX Client Interface
clk_rxmac
Figure 3.
RX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps/10.3125 GHz
RX Serial Interface
clk_ref
644.53125 MHz/322.265625 MHz
390.625 MHz (25G) / 156.25 MHz (10G)
25G Ethernet MAC and PCS IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
ATX PLL
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
tx_serial_clk
12.890625 GHz
390.625 MHz
To external PHY
tx_clkout
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
TX
RS-FEC
(optional)
tx_parallel_data[63:0]
RX
RS-FEC
(optional)
rx_parallel_data[63:0]
tx_control_phy[1:0]
System Resets
Avalon-ST
RX Client Interface
clk_rxmac
Send Feedback
RX
Adapter
390.625 MHz
rx_control_phy[1:0]
rx_clkout
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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1. About the 25G Ethernet Intel FPGA IP Core
UG-20109 | 2018.10.05
Figure 4.
10G/25G Ethernet MAC and PCS IP Clock Diagram
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
ATX PLL tx_serial_clk
(25G) 12.890625 GHz
Towards external PHY
ATX PLL tx_serial_clk
(10G) 5.15625 GHz
Towards external PHY
390.625 MHz (25G) / 156.25 MHz (10G)
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
tx_clkout
TX
RS-FEC
(optional)
tx_parallel_data[63:0]
RX
RS-FEC
(optional)
rx_parallel_data[63:0]
tx_control_phy[1:0]
System Resets
Avalon-ST
RX Client Interface
RX
Adapter
clk_rxmac
Note:
1.
390.625 MHz (25G) / 156.25 MHz (10G)
rx_control_phy[1:0]
rx_clkout
To configure the IP between 10G and 25G, follow the reconfiguration sequence as
defined in the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide and Intel
Stratix 10 E-Tile Transceiver PHY User Guide. For simplification, refer to the
reconfiguration sequencer module from the design example, which is not part the
IP.
2. For MAC + PCS core variant, follow the reset sequence guideline as defined in
Recommended Reset Sequence of the Intel Stratix 10 L- and H-Tile Transceiver
PHY User Guide to ensure the 25G Ethernet Intel FPGA IP is having a proper reset
sequence.
The following block diagram shows an example of a network application with 25G
Ethernet Intel FPGA IP MAC and PHY.
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Figure 5.
Example Network Application
FPGA Network Interface and Packet Processor, Frame Multiplexer, and Cross Connect
Ethernet Switch
CPU Farm
NPU Farm
OTN Cross Connect
(Optional)
HiGig
PCIe
Interlaken
OTN
Custom Aggregation
Packet Processing
Monitoring
Frame Multiplexing
HiGig
PCIe
Interlaken
OTN
25GbE
MAC + PHY
25 Gbps
xN
25GbE
MAC + PHY
Security
Processor
QSFP28
CFP4
QSFP28
CFP4
25 Gbps
Memory
Related Information
•
25 Gigabit Ethernet Consortium
•
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
•
Intel Stratix 10 E-Tile Transceiver PHY User Guide
1.1. 25G Ethernet Intel FPGA IP Core Supported Features
The 25G Ethernet Intel FPGA IP core is designed to the 25G & 50G Ethernet
Specification, Draft 1.6 from the 25 Gigabit Ethernet Consortium and designed to the
IEEE 802.3by 25Gb Ethernet specification, as well as the IEEE 802.3ba-2012 High
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1. About the 25G Ethernet Intel FPGA IP Core
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Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC
provides RX cut-through frame processing to optimize latency. The IP core supports
the following features:
•
•
•
•
PHY features:
—
Soft PCS logic that interfaces seamlessly to Intel Stratix 10 FPGA
25.78125 gigabits per second (Gbps) or 10.3125 Gbps serial transceivers.
—
Support for dynamic reconfiguration between the Ethernet data rates of
25.78125 Gbps and 10.3125 Gbps.
—
Optional Reed-Solomon forward error correction (FEC).
—
Elective physical medium attachment (PMA).
Frame structure control features:
—
Support for jumbo packets, defined as packets greater than 1500 bytes.
—
Receive (RX) CRC removal and pass-through control.
—
Transmit (TX) CRC generation and insertion.
—
RX and TX preamble pass-through option for applications that require
proprietary user management information transfer.
—
TX automatic frame padding to meet the 64-byte minimum Ethernet frame
length.
Frame monitoring and statistics:
—
RX CRC checking and error reporting.
—
RX malformed packet checking per IEEE specification.
—
Optional statistics counters.
—
Optional fault signaling detects and reports local fault and generates remote
fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
—
Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012
Ethernet Standard.
Flow control:
—
Standard IEEE 802.3 Clause 31 and Priority-Based IEEE 802.1Qbb flow
control.
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•
Precision Time Protocol support:
—
•
•
Optional support for the IEEE Standard 1588-2008 Precision Clock
Synchronization Protocol (1588 PTP). This feature supports PHY operating
speed with a constant timestamp accuracy of ± 4 ns and a dynamic timestamp
accuracy of ± 1 ns.
Debug and testability features:
—
Programmable serial PMA local loopback (TX to RX) at the serial transceiver
for self-diagnostic testing.
—
TX error insertion capability.
—
Optional access to Altera Debug Master Endpoint (ADME) for serial link
debugging or monitoring PHY signal integrity.
User system interfaces:
—
Avalon Memory-Mapped (Avalon-MM) management interface to access the IP
core control and status registers.
—
Avalon Streaming (Avalon-ST) data path interface connects to client logic.
—
Configurable ready latency of 0 or 3 clock cycles for Avalon-ST TX interface.
—
Hardware and software reset control.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet
Standard.
Related Information
IEEE website
The IEEE 802.3 Ethernet Standard is available on the IEEE website.
1.2. 25G Ethernet Intel FPGA IP Core Device Family and Speed
Grade Support
1.2.1. 25G Ethernet Intel FPGA IP Core Device Family Support
Table 1.
Intel FPGA IP Core Device Support Levels
Device Support
Level
Definition
Advance
The IP core is available for simulation and compilation for this device family. Timing models include
initial engineering estimates of delays based on early post-layout information. The timing models are
subject to change as silicon testing improves the correlation between the actual silicon and the timing
models. You can use this IP core for system architecture and resource utilization studies, simulation,
pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer
strategy (datapath width, burst depth, I/O standards tradeoffs).
Preliminary
The IP core is verified with preliminary timing models for this device family. The IP core meets all
functional requirements, but might still be undergoing timing analysis for the device family. It can be
used in production designs with caution.
Final
The IP core is verified with final timing models for this device family. The IP core meets all functional
and timing requirements for the device family and can be used in production designs.
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Table 2.
25G Ethernet Intel FPGA IP Core Device Family Support
Shows the level of support offered by the 25G Ethernet Intel FPGA IP core for each Intel FPGA device family.
Device Family
Support
Intel Stratix 10
Advance
Other device families
No support
Related Information
Timing and Power Models
Reports the default device support levels in the current version of the Quartus
Prime Pro Edition software.
1.2.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
Table 3.
Supported Device Speed Grades
IP Core
25G Ethernet Intel FPGA IP
Device Family
Intel Stratix 10 L-, H-, and E-Tile
Supported Speed Grades
(1)
•
•
Transceiver speed grade: -1 or -2
Core speed grade: -1 and -2
Related Information
Stratix 10 GX/SX Device Overview
Provides more information on the sample ordering code and available options for
Intel Stratix 10 devices.
1.3. IP Core Verification
To ensure functional correctness of the 25G Ethernet Intel FPGA IP core, Intel
performs extensive validation through both simulation and hardware testing. Before
releasing a version of the 25G Ethernet Intel FPGA IP core, Intel runs comprehensive
regression tests in the current version of the Intel Quartus® Prime Pro Edition
software.
Intel verifies that the current version of the Intel Quartus Prime Pro Edition software
compiles the previous version of each IP core. Any exceptions to this verification are
reported in the Intel FPGA IP Release Notes. Intel does not verify compilation with IP
core versions older than the previous release.
Related Information
(1)
•
Knowledge Base Issues for IP core
Exceptions to functional correctness are documented in the 25G Ethernet Intel
FPGA IP core errata.
•
25G Ethernet Intel FPGA IP Release Notes
•
Intel Quartus Prime Design Suite Update Release Notes
Includes changes in minor releases (updates).
Only Intel Stratix 10 devices ending with "VG", VGS3", and "LG" suffixes in the part number
are supported.
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1.3.1. Simulation Environment
Intel performs the following tests on the 25G Ethernet Intel FPGA IP core in the
simulation environment using internal and third-party standard bus functional models
(BFM):
•
Constrained random tests that cover randomized frame size and contents.
•
Assertion based tests to confirm proper behavior of the IP core with respect to the
specification.
•
Extensive coverage of our runtime configuration space and proper behavior in all
possible modes of operation.
1.3.2. Compilation Checking
Intel performs compilation testing on an extensive set of 25G Ethernet Intel FPGA IP
core variations and designs to ensure the Intel Quartus Prime Pro Edition software
places and routes the IP core ports correctly.
1.3.3. Hardware Testing
Intel performs hardware testing of the key functions of the 25G Ethernet Intel FPGA IP
core using internal loopback and also with other 25G switches. The hardware tests
also ensure reliable solution coverage for hardware related areas such as
performance, link synchronization, and reset recovery.
1.4. Performance and Resource Utilization
The following table shows the typical device resource utilization for selected
configurations using the current version of the Intel Quartus Prime software. With the
exception of M20K memory blocks, the numbers of ALMs and logic registers are
rounded up to the nearest 100. The timing margin for this IP core is a minimum of
15%.
Table 4.
IP Core Variation Encoding for Resource Utilization Table for MAC+PCS+PMA
Core Variant
"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not
available.
A
B
C
D
Ready Latency
0
0
3
3
Enable RS-FEC
—
On
—
—
IP Core Variation
Parameter
Core Variant
MAC+PCS+PMA
Enable flow control
—
Standard flow
control, 1 queue
Standard flow
control, 1 queue
Standard flow
control, 1 queue
Enable link fault generation
—
—
On
On
Enable preamble passthrough
—
—
On
On
Enable TX CRC passthrough
On
—
—
—
Enable MAC statistics counters
—
On
On
On
continued...
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IP Core Variation
A
B
C
D
Enable IEEE 1588
—
—
On
—
Enable 10G/25G Dynamic Rate
Switching
—
—
—
On
Enable Altera Debug Master
Endpoint (ADME)
—
—
—
On
Parameter
Table 5.
IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with
MAC+PCS+PMA Core Variant for Intel Stratix 10 Devices
Lists the resources and expected performance for selected variations of the 25G Ethernet Intel FPGA IP core.
These results were obtained using the Intel Quartus Prime software v18.1.
•
The transceiver PLL reference clock frequency is 644.531250 MHz.
•
The numbers of ALMs and logic registers are rounded up to the nearest 100.
•
The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel Quartus
PrimeFitter Report.
IP Core Variation
Table 6.
ALMs
Dedicated Logic
Registers
Block Memory Bits
A
3850
9300
0
B
17440
55790
114880
C
14270
41080
11912
D
8595
16003
0
IP Core Variation Encoding for Resource Utilization Table for MAC+PCS Core
Variant
"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not
available.
A
B
C
D
Ready Latency
0
0
3
3
Enable RS-FEC
—
On
—
—
IP Core Variation
Parameter
Core Variant
Enable flow control
—
Standard flow
control, 1 queue
Standard flow
control, 1 queue
Standard flow
control, 1 queue
Enable link fault generation
—
—
On
On
Enable preamble passthrough
—
—
On
On
Enable TX CRC passthrough
On
—
—
—
Enable MAC statistics counters
—
On
On
On
Enable IEEE 1588
—
—
On
—
Enable 10G/25G Dynamic Rate
Switching
—
—
—
On
Enable Altera Debug Master
Endpoint (ADME)
—
—
—
On
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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MAC+PCS
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Table 7.
IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with
MAC+PCS Core Variant for Intel Stratix 10 Devices
Lists the resources and expected performance for selected variations of the 25G Ethernet Intel FPGA IP core.
These results were obtained using the Intel Quartus Prime software v18.1.
•
The transceiver PLL reference clock frequency is 644.531250 MHz.
•
The numbers of ALMs and logic registers are rounded up to the nearest 100.
•
The numbers of ALMs, before rounding, are the ALMs needed numbers from the Intel Quartus
PrimeFitter Report.
IP Core Variation
ALMs
Dedicated Logic
Registers
Block Memory Bits
A
3850
7826
0
B
17342
41141
114880
C
14136
35321
11912
D
8100
1500
0
Related Information
•
25G Ethernet Intel FPGA IP Core Parameters on page 28
Information about the parameters and values in the IP core variations.
•
Fitter Resources Reports in the Quartus Prime Pro Edition Help
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1.5. Release Information
Table 8.
25G Ethernet Intel FPGA IP Core Current Release Information
Item
Version
18.1
Release Date
2018.09.24
Ordering Codes
Variations without 1588 PTP option and without FEC option:
IP-25GEUMACPHY (IPR-25GEUMACPHY for renewal)
Variations with 1588 PTP option and without FEC option:
IP-25GEUMACPHYF (IPR-25GEUMACPHYF for renewal)
Variations without 1588 PTP option and with FEC option:
IP-25GEUMACPHYFC (IPR-25GEUMACPHYFC for renewal)
Variations with 1588 PTP option and with FEC option:
IP-25GEUMACPHYFFC (IPR-25GEUMACPHYFFC for renewal)
25G Ethernet Intel Stratix 10 FPGA IP User Guide
14
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2. Getting Started
Related Information
•
Introduction to Intel FPGA IP Cores
Provides general information about all Intel FPGA IP cores, including
parameterizing, generating, upgrading, and simulating IP cores.
•
Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP
version upgrades.
•
Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
2.1. Installing and Licensing Intel FPGA IP Cores
The Intel Quartus Prime Pro Edition software installation includes the Intel FPGA IP
library. This library provides many useful IP cores for your production use without the
need for an additional license. Some Intel FPGA IP cores require purchase of a
separate license for production use. The Intel FPGA IP Evaluation Mode allows you to
evaluate these licensed Intel FPGA IP cores in simulation and hardware, before
deciding to purchase a full production IP core license. You only need to purchase a full
production license for licensed Intel IP cores after you complete hardware testing and
are ready to use the IP in production.
The Intel Quartus Prime software installs IP cores in the following locations by default:
Figure 6.
IP Core Installation Path
intelFPGA(_pro)
quartus - Contains the Intel Quartus Prime software
ip - Contains the Intel FPGA IP library and third-party IP cores
altera - Contains the Intel FPGA IP library source code
- Contains the Intel FPGA IP source files
Table 9.
IP Core Installation Locations
Location
Software
Platform
:\intelFPGA_pro\quartus\ip\altera
Intel Quartus Prime Pro Edition
Windows*
:/intelFPGA_pro/quartus/ip/altera
Intel Quartus Prime Pro Edition
Linux*
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
2. Getting Started
UG-20109 | 2018.10.05
2.1.1. Intel FPGA IP Evaluation Mode
The free Intel FPGA IP Evaluation Mode allows you to evaluate licensed Intel FPGA IP
cores in simulation and hardware before purchase. Intel FPGA IP Evaluation Mode
supports the following evaluations without additional license:
•
Simulate the behavior of a licensed Intel FPGA IP core in your system.
•
Verify the functionality, size, and speed of the IP core quickly and easily.
•
Generate time-limited device programming files for designs that include IP cores.
•
Program a device with your IP core and verify your design in hardware.
Intel FPGA IP Evaluation Mode supports the following operation modes:
•
Tethered—Allows running the design containing the licensed Intel FPGA IP
indefinitely with a connection between your board and the host computer.
Tethered mode requires a serial joint test action group (JTAG) cable connected
between the JTAG port on your board and the host computer, which is running the
Intel Quartus Prime Programmer for the duration of the hardware evaluation
period. The Programmer only requires a minimum installation of the Intel Quartus
Prime software, and requires no Intel Quartus Prime license. The host computer
controls the evaluation time by sending a periodic signal to the device via the
JTAG port. If all licensed IP cores in the design support tethered mode, the
evaluation time runs until any IP core evaluation expires. If all of the IP cores
support unlimited evaluation time, the device does not time-out.
•
Untethered—Allows running the design containing the licensed IP for a limited
time. The IP core reverts to untethered mode if the device disconnects from the
host computer running the Intel Quartus Prime software. The IP core also reverts
to untethered mode if any other licensed IP core in the design does not support
tethered mode.
When the evaluation time expires for any licensed Intel FPGA IP in the design, the
design stops functioning. All IP cores that use the Intel FPGA IP Evaluation Mode time
out simultaneously when any IP core in the design times out. When the evaluation
time expires, you must reprogram the FPGA device before continuing hardware
verification. To extend use of the IP core for production, purchase a full production
license for the IP core.
You must purchase the license and generate a full production license key before you
can generate an unrestricted device programming file. During Intel FPGA IP Evaluation
Mode, the Compiler only generates a time-limited device programming file (_time_limited.sof) that expires at the time limit.
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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Figure 7.
Intel FPGA IP Evaluation Mode Flow
Install the Intel Quartus Prime
Software with Intel FPGA IP Library
Parameterize and Instantiate a
Licensed Intel FPGA IP Core
Verify the IP in a
Supported Simulator
Compile the Design in the
Intel Quartus Prime Software
Generate a Time-Limited Device
Programming File
Program the Intel FPGA Device
and Verify Operation on the Board
No
IP Ready for
Production Use?
Yes
Purchase a Full Production
IP License
Include Licensed IP
in Commercial Products
Note:
Refer to each IP core's user guide for parameterization steps and implementation
details.
Intel licenses IP cores on a per-seat, perpetual basis. The license fee includes firstyear maintenance and support. You must renew the maintenance contract to receive
updates, bug fixes, and technical support beyond the first year. You must purchase a
full production license for Intel FPGA IP cores that require a production license, before
generating programming files that you may use for an unlimited time. During Intel
FPGA IP Evaluation Mode, the Compiler only generates a time-limited device
programming file (_time_limited.sof) that expires at the time
limit. To obtain your production license keys, visit the Self-Service Licensing Center or
contact your local Intel FPGA representative.
The Intel FPGA Software License Agreements govern the installation and use of
licensed IP cores, the Intel Quartus Prime design software, and all unlicensed IP cores.
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Related Information
•
Intel Quartus Prime Licensing Site
•
Intel FPGA Software Installation and Licensing
2.2. Specifying the Intel Stratix 10 IP Core Parameters and Options
The 25G Ethernet Intel FPGA IP parameter editor allows you to quickly configure your
custom IP variation. Use the following steps to specify IP core options and parameters
in the Intel Quartus Prime Pro Edition software.
1. In the Intel Quartus Prime Pro Edition, click File ➤ New Project Wizard to create
a new Quartus Prime project, or File ➤ Open Project to open an existing Quartus
Prime project. The wizard prompts you to specify a device.
2.
In the IP Catalog (Tools ➤ IP Catalog), locate and double-click the name of the
IP core to customize. The New IP Variation window appears.
3. In the New IP Variation dialog box, specify a top-level name for your custom IP
variation. The parameter editor saves the IP variation settings in a file named
.ip.
4.
Click Create. The parameter editor appears.
5. On the IP tab, specify the parameters for your IP core variation. Refer to 25G
Ethernet Intel FPGA IP Core Parameters on page 28 for information about specific
IP core parameters.
6.
Optionally, to generate a simulation testbench or compilation and hardware design
example, follow the instructions in the 25G Ethernet Intel Stratix 10 FPGA IP
Design Example User Guide.
7.
Click Generate HDL. The Generation dialog box appears.
8. Specify output file generation options, and then click Generate. The IP variation
files generate according to your specifications.
9. Click Finish. The parameter editor adds the top-level .ip file to the current
project automatically. If you are prompted to manually add the .ip file to the
project, click Project ➤ Add/Remove Files in Project to add the file.
10. After generating and instantiating your IP variation, make appropriate pin
assignments to connect ports.
Related Information
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Information about the Example Design tab in the 25G Ethernet Intel FPGA IP
parameter editor for Intel Stratix 10 devices.
2.3. Simulating the IP Core
You can simulate your 25G Ethernet Intel FPGA IP core variation with the functional
simulation model and the testbench generated with the IP core. The functional
simulation model is a cycle-accurate model that allows for fast functional simulation of
your IP core instance using industry-standard Verilog HDL simulators. You can
simulate the Intel-provided testbench or create your own testbench to exercise the IP
core functional simulation model.
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The functional simulation model and testbench files are generated in project
subdirectories. These directories also include scripts to compile and run the design
example.
Note:
Use the simulation models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
In the top-level wrapper file for your simulation project, you can set the the following
RTL parameters to enable simulation optimization. These optimizations significantly
decrease the time to reach link initialization.
•
SIM_SHORT_RST: Shortens the reset times to speed up simulation.
•
SIM_SHORT_AM: Shortens the interval between alignment markers to accelerate
alignment marker lock. Alignment markers are used when Reed-Solomon FEC is
enabled.
•
SIM_SIMPLE_RATE: Sets the PLL reference clock (clk_ref) to 625 MHz instead of
644.53125 MHz to optimize PLL simulation model behavior
In general, parameters are set through the IP core parameter editor and you should
not change them manually. The only exceptions are these simulation optimization
parameters.
To set these parameters on the PHY blocks, add the following lines to the top-level
wrapper file:
defparam .SIM_SHORT_RST = 1'b1;
defparam .SIM_SHORT_AM = 1'b1;
defparam .SIM_SIMPLE_RATE = 1'b1;
Note:
You can use the example testbench as a guide for setting the simulation parameters in
your own simulation environment. These lines are already present in the Intelprovided testbench for the IP core.
Related Information
•
Simulating Intel FPGA Designs
Intel Quartus Prime Pro Edition Handbook Volume 3: Verification chapter that
provides information about simulating Intel FPGA IP cores.
•
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Information about generating and simulating the Intel-provided 25G Ethernet
Intel FPGA IP testbench. This testbench demonstrates a basic test of the IP
core. It is not intended to be a substitute for a full verification environment.
2.4. Generated File Structure
The Intel Quartus Prime Pro Edition software generates the following IP core output
file structure.
For information about the file structure of the design example, refer to the 25G
Ethernet Intel Stratix 10 FPGA IP Design Example User Guide.
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Figure 8.
IP Core Generated Files
.ip - System or IP integration file
IP variation files
alt_e25s10_0_example_design
_
IP variation files
Example location for your IP core
design example files. The default location is
alt_e25s10_0_example_design, but
you are prompted to specify a different path
.cmp - VHDL component declaration file
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
.ppf - XML I/O pin information file
.qgsimc - Lists simulation parameters to support incremental regeneration
.qgsynthc - Lists synthesis parameters to support incremental regeneration
.qip - Lists IP synthesis files
.sip - Lists files for simulation
_generation.rpt- IP generation report
.html - Connection and memory map data
.bsf - Block symbol schematic
.spd - Combines individual simulation scripts
sim
synth
Simulation files
IP synthesis files
.v or .vhd
Top-level simulation file
.v or .vhd
Top-level IP synthesis file
synth
Subcore
synthesis files
Simulator scripts
Table 10.
Subcore libraries
sim
Subcore
Simulation files
IP Core Generated Files
File Name
Description
.ip
The Platform Designer system or top-level IP variation file. is the
name that you give your IP variation.
.sopcinfo
Describes the connections and IP component parameterizations in your
Platform Designer system. You can parse its contents to get requirements
when you develop software drivers for IP components.
Downstream tools such as the Nios® II Gen 2 tool chain use this file.
The .sopcinfo file and the system.h file generated for the Nios II Gen 2 tool
chain include address map information for each slave relative to each master
that accesses the slave. Different masters may have a different address map to
access a particular slave component.
.cmp
The VHDL Component Declaration (.cmp) file is a text file that contains local
generic and port definitions that you can use in VHDL design files.
This IP core does not support VHDL. However, the Intel Quartus Prime software
generates this file.
continued...
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File Name
Description
.html
A report that contains connection information, a memory map showing the
address of each slave with respect to each master to which it is connected, and
parameter assignments.
_generation.rpt
IP or Platform Designer generation log file. A summary of the messages during
IP generation.
.qgsimc
Lists simulation parameters to support incremental regeneration.
.qgsynthc
Lists synthesis parameters to support incremental regeneration.
.qip
Contains all the required information about the IP component to integrate and
compile the IP component in the Intel Quartus Prime Pro Edition software.
.csv
Contains information about the upgrade status of the IP component.
.bsf
A Block Symbol File (.bsf) representation of the IP variation for use in Intel
Quartus Prime Pro Edition Block Diagram Files (.bdf).
.spd
Required input file for ip-make-simscript to generate simulation scripts for
supported simulators. The .spd file contains a list of files generated for
simulation, along with information about memories that you can initialize.
.ppf
The Pin Planner File (.ppf) stores the port and node assignments for IP
components created for use with the Pin Planner.
_bb.v
You can use the Verilog black-box (_bb.v) file as an empty module declaration
for use as a black box.
_inst.v and _inst.vhd
HDL example instantiation template. You can copy and paste the contents of
this file into your HDL file to instantiate the IP variation.
This IP core does not support VHDL. However, the Intel Quartus Prime Pro
Edition software generates the _inst.vhd file.
.regmap
If IP contains register information, .regmap file generates. The .regmap file
describes the register map information of master and slave interfaces. This file
complements the .sopcinfo file by providing more detailed register
information about the system. This enables register display views and user
customizable statistics in the System Console.
.svd
Allows hard processor system (HPS) System Debug tools to view the register
maps of peripherals connected to HPS within a Platform Designer system.
During synthesis, the .svd files for slave interfaces visible to System Console
masters are stored in the .sof file in the debug section. System Console reads
this section, which Platform Designer can query for register map information.
For system slaves, Platform Designer can access the registers by name.
synth/.v or .vhd
Top-level IP synthesis HDL files that instantiate each submodule or child IP core
for synthesis.
This IP core does not support VHDL. However, the Intel Quartus Prime software
generates this file.
sim/.v or .vhd
Top-level simulation files that instantiate each submodule or child IP core for
simulation.
This IP core does not support VHDL. However, the Intel Quartus Prime Pro
Edition software generates this file.
sim/mentor/
Contains a ModelSim script msim_setup.tcl to set up and run a simulation.
sim/aldec/
Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a
simulation.
sim/synopsys/vcs/
Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.
sim/synopsys/vcsmx/
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to
set up and run a VCS MX® simulation.
continued...
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File Name
Description
sim/cadence/
Contains a shell script ncsim_setup.sh and other setup files to set up and
run an NCSIM simulation.
sim/xcelium/
Contains a shell script xcelium_setup.sh and other setup files to set up and
run an xcelium simulation.
/
For each generated child IP core directory, Platform Designer generates
synth/ and sim/ sub-directories.
Related Information
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Information about the 25G Ethernet Intel FPGA IP core design example file
structure.
2.5. Integrating Your IP Core in Your Design
2.5.1. Pin Assignments
When you integrate your 25G Ethernet Intel FPGA IP core instance in your design, you
must make appropriate pin assignments. While compiling the IP core alone, you can
create virtual pins to avoid making specific pin assignments for top-level signals.
When you are ready to map the design to hardware, you can change to the correct pin
assignments.
Related Information
Intel Quartus Prime Help
For information about the Intel Quartus Prime software, including virtual pins.
2.5.2. Adding the Transceiver PLL
The 25G Ethernet Intel FPGA IP core targets Intel Stratix 10 devices. Intel Stratix 10
devices require an external PLL to drive the TX transceiver serial clock, in order to
compile and to function correctly in hardware. In many cases, the same PLL can be
shared with an additional transceiver in your design.
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Figure 9.
PLL Configuration Example for 25G Configuration
The TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be
instantiated outside the 25G Ethernet Intel FPGA IP core.
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
ATX PLL
clk_ref
390.625 MHz
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
TX
RS-FEC
(optional)
tx_serial_clk
12.890625 GHz
Hard PMA
25.78125 Gbps
TX Serial Interface
Reconfiguration Interface
System Resets
Avalon-ST
RX Client Interface
RX
Adapter
clk_rxmac
Figure 10.
RX
RS-FEC
(optional)
Hard PMA
25.78125 Gbps
RX Serial Interface
clk_ref
644.53125 MHz/322.265625 MHz
390.625 MHz
PLL Configuration Example for 10G/25G Configuration
The TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be
instantiated outside the 25G Ethernet Intel FPGA IP core.
ATX PLL
(25G)
pll_ref_clk
644.53125 MHz/322.265625 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
tx_serial_clk
12.890625 GHz
clk_ref
390.625 MHz (25G) / 156.25 MHz (10G)
TX
MAC
ATX PLL
(10G)
TX
RS-FEC
(optional)
tx_serial_clk
5.15625 GHz
Hard PMA
25.78125 Gbps/10.3125 GHz
TX Serial Interface
Reconfiguration Interface
System Resets
Avalon-ST
RX Client Interface
clk_rxmac
Send Feedback
RX
Adapter
RX
RS-FEC
(optional)
390.625 MHz (25G) / 156.25 MHz (10G)
Hard PMA
25.78125 Gbps/10.3125 GHz
RX Serial Interface
clk_ref
644.53125 MHz/322.265625 MHz
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You can use the IP Catalog to create a transceiver PLL.
•
Select Intel Stratix 10 L-Tile/H-Tile Transceiver ATX PLL.
•
In the parameter editor, set the following parameter values:
—
For 25G configuration:
•
—
For 10G configuration:
•
—
PLL output frequency to 12890.625 MHz. The transceiver performs
dual edge clocking, using both the rising and falling edges of the input
clock from the PLL. Therefore, this PLL output frequency setting supports a
25.78125 Gbps data rate through the transceiver.
PLL output frequency to 5156.25 MHz. The transceiver performs dual
edge clocking, using both the rising and failing edges of the input clock
from the PLL. Therefore, this PLL output frequency setting supports a
10.3125 Gbps data rate through the transceiver.
PLL reference clock frequency to 644.53125 or 322.265625 MHz.
You must connect the ATX PLL to the 25G Ethernet Intel FPGA IP core as follows:
•
Connect the clock output port of the ATX PLL to the tx_serial_clk input port of
the 25G Ethernet Intel FPGA IP core.
•
Connect the pll_locked output port of the ATX PLL to the tx_pll_locked
input port of the 25G Ethernet Intel FPGA IP core.
•
Drive the ATX PLL reference clock port and the 25G Ethernet Intel FPGA IP core
clk_ref input port with the same clock. The clock frequency must be the
frequency you specify for the ATX PLL IP core PLL reference clock frequency
parameter.
Related Information
•
Transceivers on page 59
•
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
Information about the correspondence between PLLs and transceiver channels,
and information about how to configure an external transceiver PLL for your
own design. You specify the clock network to which the PLL output connects by
setting the clock network in the PLL parameter editor.
2.5.3. Adding the External Time-of-Day Module for Variations with 1588
PTP Feature
25G Ethernet Intel FPGA IP cores that include the 1588 PTP module require an
external time-of-day (TOD) module to provide a continuous flow of current time-ofday information. The TOD module must update the time-of-day output value on every
clock cycle, and must provide the TOD value in the V2 format (96 bits) or the 64-bit
TOD format, or both.
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Intel provides the following components that you can combine to create the TOD
module the 25G Ethernet Intel FPGA IP core requires:
•
A simple TOD clock module, available from the IP Catalog (Interface Protocols
> Ethernet > Reference Design Components > Ethernet IEEE 1588 Time of
Day Clock Intel FPGA IP). You can instantiate two of these clock modules and
connect one to the TX MAC and the other to the RX MAC.
•
A single-format TOD synchronizer, available from the IP Catalog (Interface
Protocols > Ethernet > Reference Design Components > Ethernet IEEE
1588 TOD Synchronizer Intel FPGA IP). This component can handle only a
single TOD format. Therefore, if you set the Time of day format parameter to
the value of Enable both formats, you must instantiate and connect two TOD
synchronizer modules. If your IP core supports only a single TOD format, your
design requires only a single TOD synchronizer module.
Each TOD synchronizer connects a master TOD clock and a slave TOD clock.
•
If you create your TOD module with a single TOD synchronizer, the master TOD
clock connects to the TX MAC of the 25G Ethernet Intel FPGA IP core and the slave
TOD clock connects to the RX MAC of the 25G Ethernet Intel FPGA IP core.
•
Alternatively, you can drive both the TX and RX TOD clocks from a single master
TOD clock. In that case, your design must include two TOD synchronizers, one to
connect the master TOD clock and the slave TX TOD clock and one to connect the
master TOD clock and the slave RX TOD clock.
If your IP core supports both TOD formats, double the number of TOD synchronizers
in your TOD module. The configuration you implement depends on your system design
requirements for 1588 PTP functionality.
Figure 11.
TOD Synchronizer and TOD Clocks in 96-Bit TOD Format Design
Shows the required connections between two TOD clock components and a TOD synchronizer component in a
single TOD format design. In a simple TOD module, the master TOD clock connects to the TX MAC of the IP
core, and the slave TOD clock connects to the RX MAC of the IP core. If your 25G Ethernet Intel FPGA IP core
supports both TOD formats, a second TOD synchronizer connects to the corresponding 64-bit time-of-day
signals of the same master and slave TOD clocks.
Master ToD Clock
period_rst_n
period_clk
ToD Synchronizer
1’b1
start_tod_synch
Slave ToD Clock
tod_slave_valid
tod_slave_data
reset_slave
clk_slave
time_of_day_96b
time_master_data
reset_master
clk_master
PLL
clk_sampling
time_of_day_96b_load_valid
time_of_day_96b_load_data
period_rst_n
period_clk
For information about the Ethernet IEEE 1588 Time of Day Clock and Ethernet IEEE
1588 TOD Synchronizer components, and the requirements for the PLL that connects
to the TOD synchronizer, refer to the Ethernet Design Example Components User
Guide.
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Table 11.
TOD Module Required Connections to 25G Ethernet Intel FPGA IP Core
Lists the required connections between the TOD module and the 25G Ethernet Intel FPGA IP core, using signal
names for TOD modules that provide both a 96-bit TOD and a 64-bit TOD. If you create your own TOD module
it must have the output signals required by the 25G Ethernet Intel FPGA IP core. However, its signal names
could be different than the TOD module signal names in the table. The signals that the IP core includes depend
on the value you set for Time of day format in the parameter editor. For example, an RX TOD module might
require only a 96-bit TOD out signal. This table does not list required connections between the TOD module and
additional parts of your design.
TOD Module Signal
25GbE IP Core Signal
rst_n (input to TX and RX TOD clocks)
Drive this signal from the same source as the csr_rst_n
input signal to the 25G Ethernet Intel FPGA IP core.
period_rst_n (input to RX TOD clock)
reset_slave (input to Synchronizer)
Drive these signals from the same source as the rx_rst_n
input signal to the 25G Ethernet Intel FPGA IP core.
period_rst_n (input to TX TOD clock)
reset_master (input to Synchronizer)
Drive these signals from the same source as the tx_rst_n
input signal to the 25G Ethernet Intel FPGA IP core.
time_of_day_96b[95:0] (output from TX TOD clock)
tx_time_of_day_96b_data[95:0] (input)
time_of_day_64b[63:0] (output from TX TOD clock)
tx_time_of_day_64b_data[63:0] (input)
time_of_day_96b[95:0] (output from RX TOD clock)
rx_time_of_day_96b_data[95:0] (input)
time_of_day_64b[63:0] (output from RX TOD clock)
rx_time_of_day_64b_data[63:0] (input)
period_clk (input to TX TOD clock)
clk_master (input to Synchronizer)
clk_txmac (output)
period_clk (input to RX TOD clock)
clk_slave (input to Synchronizer)
clk_rxmac (output)
Related Information
•
External Time-of-Day Module for 1588 PTP Variations on page 50
•
Ethernet Design Example Components User Guide
Describes the Ethernet IEEE 1588 Time of Day Clock component and the
Ethernet IEEE 1588 TOD Synchronizer component available in the Intel Quartus
Prime software from the IP Catalog.
2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
The Quartus Prime software provides the options to specify design partitions and Logic
Lock (Standard) or Logic Lock regions for incremental compilation, to control
placement on the device. To achieve timing closure for your design, you might need to
provide floorplan guidelines using one or both of these features.
The appropriate floorplan is always design-specific, and depends on your full design.
Related Information
Intel Quartus Prime Pro Edition Handbook Volume 2: Design Implementation and
Optimization
Describes incremental compilation, design partitions, and Logic Lock regions.
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2.6. Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the Intel
Quartus Prime software to compile your design. After successfully compiling your
design, program the targeted Intel FPGA with the Programmer and verify the design in
hardware.
Note:
The 25G Ethernet Intel FPGA IP core design example synthesis directories include
Synopsys Constraint (.sdc) files that you can copy and modify for your own design.
Related Information
•
Incremental Compilation for Hierarchical and Team-Based Design
•
Programming Intel Devices
•
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Information about generating the design example and the design example
directory structure.
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25G Ethernet Intel Stratix 10 FPGA IP User Guide
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3. 25G Ethernet Intel FPGA IP Core Parameters
The 25G Ethernet Intel FPGA IP parameter editor provides the parameters you can set
to configure the 25G Ethernet Intel FPGA IP core and design example.
The 25G Ethernet Intel FPGA IP parameter editor includes an Example Design tab.
For information about that tab, refer to the 25G Ethernet Intel Stratix 10 FPGA IP
Design Example User Guide.
Table 12.
IP Core Parameters
Parameter
Range
Default Setting
Description
General Options
Device Family
Stratix 10
Stratix 10
Ready Latency
0, 3
0
MAC+PCS
+PMA, MAC
+PCS
MAC+PCS
+PMA
Core Variant
Selects the device family.
Selects the readyLatency value on the TX client
interface. readyLatency is an Avalon-ST interface
property that defines the number of clock cycles of
delay from when the IP core asserts the l1_tx_ready
signal to the clock cycle in which the IP core can accept
data on the TX client interface. Refer to the Avalon
Interface Specifications.
Selecting a latency of 3 eases timing closure at the
expense of increased latency for the datapath.
If you set the readyLatency to 3 and turn on standard
flow control, data might be delayed in the IP core while
the IP core is backpressured.
Selects the primary blocks to include in the IP core
variation.
• MAC+PCS+PMA—When enabled, the IP core
generates with capability of MAC, PCS, and PMA
protocol layers.
• MAC+PCS—When enabled the IP core generates
with the capability of MAC and PCS only.
PCS/PMA Options
Enable RS-FEC
Enabled,
Disabled
Disabled
When enabled, the IP core implements Reed-Solomon
forward error correction (FEC).
Flow Control Options
Enable flow control
Enabled,
Disabled
Disabled
When enabled, the IP core implements flow control.
When either link partner experiences congestion, the
respective transmit control sends pause frames.
Register settings control flow control behavior, including
whether the IP core implements standard flow control
or priority-based flow control.
If you turn on standard flow control and set the
readyLatency to 3, data might be delayed in the IP core
while the IP core is backpressured.
Number of queues
1-8
8
Specifies the number of queues used in managing flow
control.
continued...
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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Registered
3. 25G Ethernet Intel FPGA IP Core Parameters
UG-20109 | 2018.10.05
Parameter
Range
Default Setting
Description
MAC Options
Enable link fault
generation
Enabled,
Disabled
Disabled
When enabled, the IP core implements link fault
signaling as defined in the IEEE 802.3-2012 IEEE
Standard for Ethernet. The MAC includes a
Reconciliation Sublayer (RS) to manage local and
remote faults. When enabled, the local RS TX logic can
transmit remote fault sequences in case of a local fault
and can transmit IDLE control words in case of a
remote fault.
Enable preamble
passthrough
Enabled,
Disabled
Disabled
When enabled, the IP core is in RX and TX preamble
pass-through mode. In RX preamble pass-through
mode, the IP core passes the preamble and Start
Frame Delimiter (SFD) to the client instead of stripping
them out of the Ethernet packet. In TX preamble passthrough mode, the client specifies the preamble and
provides the SFD to be sent in the Ethernet frame.
Enable TX CRC
passthrough
Enabled,
Disabled
Disabled
When enabled, TX MAC does not insert the CRC-32
checksum in the out-going frame. In pass-through
mode, the client must provide frames with at least 64
bytes, including the Frame Check Sequence (FCS).
When disabled, the TX MAC computes and inserts a 32bit FCS in the TX MAC frame.
This parameter is not available if you turn on Enable
IEEE 1588.
Enable MAC statistics
counters
Enabled,
Disabled
Enabled
When enabled, the IP core includes statistics counters
that characterize TX and RX traffic.
IEEE 1588 Options
Enable IEEE 1588
Time of day format
Fingerprint width
Enabled,
Disabled
Disabled
If enabled, the IP core supports the IEEE Standard
1588-2008 Precision Clock Synchronization Protocol, by
providing the hooks to implement the Precise Timing
Protocol (PTP).
This parameter is not available if you turn on Enable
TX CRC passthrough.
Enable 96-bit
timestamp
format, Enable
64-bit
timestamp
format, Enable
both formats
Enable both
formats
Specifies the interface to the Time of Day module. If
you select Enable both formats, the IP core includes
both the 64-bit interface and the 96-bit interface.
This parameter is available only in variations with
Enable IEEE 1588 turned on. The IP core provides the
Time of Day interface; the IP core does not include
Time of Day and synchronizer modules to connect to
this interface.
1–32
4
Specifies the number of bits in the fingerprint that the
IP core handles.
This parameter is available only in variations with
Enable IEEE 1588 turned on.
10G/25G Rate Switching
Enable 10G/25G
dynamic rate switching
Enabled,
Disabled
Disabled
If enabled, the IP core supports dynamic
reconfiguration between the 10 Gbps and the 25 Gbps
data rates.
Configuration, Debug and Extension Options
Enable Altera Debug
Master Endpoint
(ADME)
Enabled,
Disabled
Disabled
If enabled, the IP core turns on the following features
in the Intel Stratix 10 PHY IP core that is included in
the 25G Ethernet Intel FPGA IP core:
• Enable Altera Debug Master Endpoint (ADME)
• Enable capability registers
continued...
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25G Ethernet Intel Stratix 10 FPGA IP User Guide
29
3. 25G Ethernet Intel FPGA IP Core Parameters
UG-20109 | 2018.10.05
Parameter
Range
Default Setting
Description
If turned off, the IP core is configured without these
features.
For information about these Intel Stratix 10 features,
refer to the Intel Stratix 10 L- and H-Tile Transceiver
PHY User Guide.
Reference clock
frequency
644.531250,
322.265625
644.531250
Specifies the frequency of the transceiver CDR
reference clock input in MHz.
Related Information
•
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Information about the Example Design tab in the 25GbE parameter editor.
•
Avalon Interface Specifications
Detailed information about Avalon-ST interfaces and the Avalon-ST
readLatency parameter.
•
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
Information about Intel Stratix 10 Native PHY IP core features, including ADME.
25G Ethernet Intel Stratix 10 FPGA IP User Guide
30
Send Feedback
UG-20109 | 2018.10.05
Send Feedback
4. Functional Description
4.1. 25G Ethernet Intel FPGA IP Core Functional Description
The 25G Ethernet Intel FPGA IP core implements an Ethernet MAC in accordance with
the 25G & 50G Ethernet Specification. The IP core implements an Ethernet PCS and
PMA (PHY) that handles the frame encapsulation and flow of data between a client
logic and Ethernet network.
Figure 12.
25G Ethernet Intel FPGA IP Core with MAC, PCS, and PMA Clock Diagram
pll_ref_clk
644.53125 MHz
clk_txmac
Avalon-ST
TX Client Interface
alt_e25_top
TX
Adapter
Avalon-MM Management
Interface
ATX PLL
clk_ref
390.625 MHz
TX
MAC
TX
PCS
CSR
Reset
RX
MAC
RX
PCS
TX
RS-FEC
(optional)
tx_serial_clk
12.890625 GHz
66:64 Basic
Hard PCS/PMA
25.78125 Gbps
TX Serial Interface
Reconfiguration Interface
System Resets
Avalon-ST
RX Client Interface
RX
Adapter
clk_rxmac
390.625 MHz
RX
RS-FEC
(optional)
66:64 Basic
Hard PCS/PMA
25.78125 Gbps
RX Serial Interface
clk_ref
644.53125 MHz
Note:
1. 66:64 encode/decode function is implemented as part of the soft PCS.
In the TX direction, the MAC assembles packets and sends them to the PHY. It
completes the following tasks:
•
Accepts client frames.
•
Inserts the inter-packet gap (IPG), preamble, start of frame delimiter (SFD), and
padding. The source of the preamble and SFD depends on whether the IP core is
in preamble-passthrough mode.
•
Adds the CRC bits if enabled.
•
Updates statistics counters if enabled.
The PCS encodes MAC frames. The PHY, if selected, will perform reliable transmission
over the media to the remote end.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
4. Functional Description
UG-20109 | 2018.10.05
In the RX direction, the PMA, if selected, passes frames to the PCS that sends them to
the MAC. The MAC completes the following tasks:
•
Performs CRC and malformed packet checks.
•
Updates statistics counters if enabled.
•
Strips out the CRC, preamble, and SFD.
•
Passes the remainder of the frame to the client.
In preamble pass-through mode, the MAC passes on the preamble and SFD to the
client instead of stripping them out. In RX CRC pass-through mode, the MAC passes
on the CRC bytes to the client and asserts the end-of-packet signal in the same clock
cycle as the final CRC byte.
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath
The TX MAC module receives the client payload data with the destination and source
addresses. It then adds, appends, or updates various header fields in accordance with
the configuration specified. The MAC does not modify the destination address, the
source address, or the payload received from the client. However, the TX MAC module
adds a preamble, if the IP core is not configured to receive the preamble from user
logic. It pads the payload of frames greater than eight bytes to satisfy the minimum
Ethernet frame payload of 46 bytes. By default, the MAC inserts the CRC bytes. The
TX MAC module inserts IDLE bytes to maintain an average IPG of 12.
Figure 13.
Typical Client Frame at the Transmit Interface
Illustrates the changes that the TX MAC makes to the client frame. This figure uses the following notational
conventions:
•
= payload size, which is arbitrarily large
•
= number of padding bytes (0–46)
•
= number of IPG bytes
MAC Frame
Provided by client in l1_tx_data in preamble pass-through mode
Added by MAC for TX packets otherwise
Start
Figure 14.
Preamble
[47:0]
SFD[7:0]
Destination
Addr[47:0]
Source
Addr[47:0]
Payload Data from Client
Type/
Length[15:0]
Added by MAC for TX packets
Payload
[-1:0]
PAD []
CRC32
[31:0]
EFD[7:0]
IPG
[-1:0]
TX MAC Functions
TX MAC Functions
User logic
Pad
Preamble
insertion
IPG
insertion
CRC
generation
Link fault
generation
To PCS
MAC Frame
Status Check
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
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4.1.1.1. Frame Padding
When the length of the client frame is less than 64 bytes, the TX MAC module inserts
pad bytes (0x00) after the payload to create a frame length equal to the minimum
size of 64 bytes (including CRC).
The IP core filters out all client frames with lengths less than 9 bytes. The IP core
drops these frames silently.
4.1.1.2. Preamble Insertion
In the TX datapath the MAC prepends an eight-byte preamble to the client frame. If
you turn on Enable link fault generation, this MAC module also incorporates the
functions of the reconciliation sublayer (RS).
The source of the 7-byte preamble (including a Start byte) and 1-byte SFD depends
on whether you turn on Enable preamble passthrough in the parameter editor.
If the preamble pass-through feature is enabled, the client provides the eight-byte
preamble (including the 0xFB Start byte and final 1-byte SFD) on l1_tx_data. The
client is responsible for providing the correct Start byte (0xFB) and an appropriate
SFD byte. If the preamble pass-through feature is disabled, the MAC inserts the
standard Ethernet preamble in the transmitted Ethernet frame.
Note that a single parameter in the 25G Ethernet Intel FPGA IP parameter editor turns
on both RX and TX preamble passthrough.
4.1.1.3. Inter-Packet Gap Generation and Insertion
The TX MAC maintains the minimum inter-packet gap (IPG) between transmitted
frames required by the IEEE 802.3 Ethernet standard. The deficit idle counter (DIC)
maintains the average IPG of 12 bytes.
4.1.1.4. Frame Check Sequence (CRC32) Insertion
The component GUI includes the Enable TX CRC passthrough parameter to control
CRC generation. When enabled, TX MAC does not insert the CRC32 checksum in the
out-going frame. In pass-through mode, the client must provide frames with at least
64 bytes, so that the IP core does not pad them. When disabled, the TX MAC
computes and inserts a 32-bit Frame Check Sequence (FCS) in the TX MAC frame. The
MAC computes the CRC32 over the frame bytes that include the source address,
destination address, length, data, and pad (if applicable). The CRC checksum
computation excludes the preamble, SFD, and FCS.
In pass-through mode, the l1_tx_endofpacket, l1_rx_endofpacket,
l1_tx_empty[2:0], and l1_rx_empty are asserted in the same clock cycle with
the final FCS byte. When pass-through mode is disabled, the l1_tx_endofpacket,
l1_rx_endofpacket, l1_tx_empty[2:0], and l1_rx_empty are asserted in the
same clock cycle with the byte before the first FCS bytes.
The encoding is defined by the following generating polynomial:
FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X +1
CRC bits are transmitted with MSB first.
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25G Ethernet Intel Stratix 10 FPGA IP User Guide
33
4. Functional Description
UG-20109 | 2018.10.05
Note that you control whether the IP core implements TX CRC insertion or
passthrough with a parameter in the 25G Ethernet Intel FPGA IP parameter editor. You
control RX CRC forwarding dynamically with the MAC_CRC_CONFIG register.
Related Information
Order of Transmission on page 52
4.1.2. 25 GbE TX PCS
The soft TX PCS implements MII encoding and scrambling. The 66-bit output stream is
input to the hard PCS and PMA block.
Figure 15.
High Level Block Diagram of the TX PCS with Optional RS-FEC
Soft TX PCS
MII Data
MII Control
Hard TX PCS
MII Encoder
Scrambler
64:66 Bit
MII Encoding
Data
Scrambling
RS-FEC
(optional)
Hard PMA
25.7815 Gbps
64:66 Bit to
256:257 Bit
Transcoding
The Hard PCS and PMA blocks are configured in 66:64 bit basic generic 10G PCS mode
whose status can be read through Control and Status registers. These blocks use
FIFOs in elastic-buffer mode. The PMA operates at 25.78125 Gbps.
Related Information
Ethernet section of the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
Provides more information about the PMA and PCS for Ethernet protocols.
4.1.2.1. TX RSFEC
If you turn on Enable RS-FEC in the 25G Ethernet Intel FPGA IP parameter editor, the
IP core includes Reed-Solomon forward error correction (FEC) in both the receive and
transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 108 of the IEEE Standard
802.3by. The Reed-Solomon FEC algorithm includes the following modules:
•
64B/66B to 256B/257B Transcoding
•
257:80 gearbox
•
High-Speed Reed-Solomon Encoder
•
80:66 gearbox
4.1.3. 25G Ethernet Intel FPGA IP Core RX MAC Datapath
The RX MAC receives Ethernet frames and forwards the payload with relevant header
bytes to the client after performing some MAC functions on header bytes. The RX MAC
processes all incoming valid frames.
25G Ethernet Intel Stratix 10 FPGA IP User Guide
34
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4. Functional Description
UG-20109 | 2018.10.05
Figure 16.
Flow of Client Frame With Preamble Pass-Through Turned On
This figure uses the following notational conventions:
•
= payload size, which is arbitrarily large.
•
= number of padding bytes (0–46).
Client Frame
Start[7:0]
If CRC forwarding is turned on
Preamble
[47:0]
SFD[7:0]
Destination
Addr[47:0]
Source
Addr[47:0]
Type/
Length[15:0]
Payload
[-1:0]
PAD [-1:0]
CRC32
[31:0]
Source
Addr[47:0]
Type/
Length[15:0]
Payload
[-1:0]
PAD [-1:0]
CRC32
[31:0]
Client - MAC Rx Interface
Start[7:0]
Figure 17.
Preamble
[47:0]
Destination
Addr[47:0]
Ethernet MAC Frame
SFD[7:0]
EFD[7:0]
Flow of Client Frame With Preamble Pass-Through Turned Off
This figure uses the following notational conventions:
•
= payload size, which is arbitrarily large.
•
= number of padding bytes (0–46).
Client Frame on l_rx_data
Destination
Source
Type/
Addr[47:0]
Addr[47:0] Length[15:0]
If CRC forwarding is turned on
Payload
[-1:0]
PAD [-1:0]
CRC32
[31:0]
Payload
[-1:0]
PAD [-1:0]
CRC32
[31:0]
Client - MAC Rx Interface
Start[7:0]
Preamble
[47:0]
SFD[7:0]
Destination
Addr[47:0]
Source
Addr[47:0]
Type/
Length[15:0]
EFD[7:0]
Ethernet MAC Frame
Figure 18.
RX MAC Datapath
RX MAC
Frame Data
Data/Annotations Annotation
and Data
Delay
Reconverge
Frame Annotations
CRC Result
CRC
Check
Preamble
Processing
Status Error
Send Feedback
Embedded
CRC
CRC
Extract
Calculated
Data
Data
CRC
CRC
CRC
Network
Overwrite
Annotations
Annotations
MII
Reader
MII Data
MII Control
Frame
Status
Checking
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
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4.1.3.1. IP Core Preamble Processing
If you turn on Enable preamble passthrough in the parameter editor, the RX MAC
forwards preamble bytes. The TX MAC requires the preamble bytes to be included in
the frames at the Avalon-ST interface.
If you turn off Enable preamble passthrough, the IP core removes the preamble
bytes. l1_rx_startofpacket is aligned to the MSB of the destination address.
Note that a single parameter in the 25G Ethernet Intel FPGA IP parameter editor turns
on both RX and TX preamble passthrough.
4.1.3.2. IP Core Malformed Packet Handling
While receiving an incoming packet from the Ethernet link, the 25G Ethernet Intel
FPGA IP core expects to detect a terminate character at the end of the packet. When it
detects an expected terminate character, the IP core generates an EOP on the client
interface. However, sometimes the IP core detects an unexpected control character
when it expects a terminate character.
If the 25G Ethernet Intel FPGA IP core detects an Error character, a Start character, an
IDLE character, or any other non-terminate control character, when it expects a
terminate character, it performs the following actions:
•
Generates an EOP.
•
Asserts a malformed packet error (l1_rx_error[0]).
•
Asserts an FCS error (l1_rx_error[1]).
If the IP core subsequently detects a terminate character, it does not generate another
EOP indication.
When the IP core receives a packet that contains an error deliberately introduced on
the Ethernet link using the 25G Ethernet Intel FPGA IP TX error insertion feature, the
IP core identifies it as a malformed packet.
At this time, the 25G Ethernet Intel FPGA IP core does not recognize non-zero 4-bit
ordered set types as an error.
4.1.3.3. Length/Type Field Processing
This two-byte header represents either the length of the payload or the type of MAC
frame.
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
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•
Length/type < 0x600—The field represents the payload length of a basic Ethernet
frame. The MAC RX continues to check the frame and payload lengths.
•
Length/type >= 0x600—The field represents the frame type. The following frame
types are possible:
—
Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC RX
continues to check the frame and payload lengths.
—
Length/type = 0x8808—Control frames. The next two bytes are the Opcode
field that indicates the type of control frame. For pause frames (Opcode =
0x0001) and PFC frames (Opcode = 0x0101), the MAC RX proceeds with
pause frame processing. In addition to processing any pause request, the IP
core passes these frames to the RX client interface and updates the
appropriate l2_rxstatus_data bits.
—
For other field values, the MAC RX forwards the receive frame to the client.
4.1.3.3.1. Length Checking
The MAC function checks the frame and payload lengths of basic, VLAN tagged, and
stacked VLAN tagged frames.
The IP core checks that the frame length is valid—is neither undersized nor oversized.
A valid frame length is at least 64 (0x40) bytes and does not exceed the following
maximum value for the different frame types:
•
Basic frames—The number of bytes specified in the MAX_RX_SIZE_CONFIG
register.
•
VLAN tagged frames—The value specified in the MAX_RX_SIZE_CONFIG register
plus four bytes.
•
Stacked VLAN tagged frames—The value specified in the MAX_RX_SIZE_CONFIG
register plus eight bytes.
If the length/type field in a basic MAC frame or the client length/type field in a VLAN
tagged frame has a value less than 0x600, the IP core also checks the payload length.
The IP core keeps track of the payload length as it receives a frame, and checks the
length against the relevant frame field. The payload length is valid if it satisfies the
following conditions:
•
The actual payload length matches the value in the length/type or client length/
type field.
•
Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes,
excluding 1536.
•
VLAN tagged frames—the payload length is between 42 (0x2A)and 1536
(0x0600), excluding 1536.
•
Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536
(0x0600), excluding 1536.
The RX MAC does not drop frames with invalid length or invalid payload length. If the
frame or payload length is not valid, the MAC function asserts output error bits.
•
l2_rx_error[2]—Undersized frame.
•
l2_rx_error[3]—Oversized frame.
•
l2_rx_error[4]—Payload length error.
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25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
UG-20109 | 2018.10.05
If the length field value is greater than the actual payload length, the IP core asserts
l1_rx_error[4]. If the length field value is less than the actual payload length, the
MAC RX considers the frame to have excessive padding and does not assert
l1_rx_error[4].
4.1.3.4. RX CRC Checking and Dynamic Forwarding
The RX MAC checks the incoming CRC32 for errors. It asserts l1_rx_error[1] in
the same cycle as l1_rx_endofpacket when it detects an error. CRC checking takes
several cycles. The packet frame is delayed to align the CRC output with the end of
the frame.
By default, the RX MAC strips off the CRC bytes before forwarding the packet to the
MAC client. You can configure the core to retain the RX CRC and forward it to the
client by updating the MAC_CRC_CONFIG register.
4.1.4. Link Fault Signaling Interface
Link fault signaling reflects the health of the link. It operates between the remote
Ethernet device Reconciliation Sublayer (RS) and the local Ethernet device RS. The
link fault modules communicate status during the interframe period.
You enable link fault signaling by turning on Enable link fault generation in the
parameter editor. For bidirectional fault signaling, the IP core implements the
functionality defined in the IEEE 802.3ba 10G Ethernet Standard and Clause 46 based
on the LINK_FAULT configuration register settings.
For unidirectional fault signaling, the core implements Clause 66 of the IEEE
802.3-2012 Ethernet Standard.
Figure 19.
Link Fault Block Diagram
TX MAC
TX Link Fault
25G MII
Interface
RX MAC
Link
Fault
RX Link Fault
TX PHY
25G MII
Interface
RX PHY
Local Fault (LF)
If an Ethernet PHY sublayer detects a fault that makes the link unreliable, it notifies
the RS of the local fault condition. If unidirectional is not enabled, the core follows
Clause 46. The RS stops sending MAC data, and continuously generates a remote fault
status on the TX datapath. After a local fault is detected, the RX PCS modifies the MII
data and control to send local fault sequence ordered sets. Refer to Link Fault
Signaling Based On Configuration and Status below.
The RX PCS cannot recognize the link fault under the following conditions:
•
The RX PCS is not fully aligned.
•
The bit error rate (BER) is high.
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
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Remote Fault (RF)
If unidirectional is not enabled, the core follows Clause 46. If the RS receives a remote
fault status, the TX datapath stops sending MAC data and continuously generates idle
control characters. If the RS stops receiving fault status messages, it returns to
normal operation, sending MAC client data. Refer to Link Fault Signaling Based On
Configuration and Status below.
Link Status Signals
The MAC RX generates two link fault signals: local_fault_status and
remote_fault_status.
Note:
These signals are real time status signals that reflect the status of the link regardless
of the settings in the link fault configuration register.
This register is generated only if you turn on Enable link fault generation. The MAC
TX interface uses the link fault status signals for additional link fault signaling.
Table 13.
Link Fault Signaling Based On Configuration and Status
For more information about the LINK_FAULT register, refer to TX MAC Registers.
LINK_FAULT Register (0x405)
Bit [0]
Bit [3]
Bit [1]
Bit [2]
Real Time Link Status
LF
Received
RF
Received
Configured TX
Behavior
TX Data
Comment
TX RF
1'b0
Don't
care
Don't
care
Don't
care
Don’t care
Don’t care
On
Off
Disable Link fault signaling on
TX.
RX still reports link status.
TX side Link fault signaling
disabled on the link.
TX data and idle.
1'b1
1'b1
Don't
care
Don't
care
Don't care
Don't care
Off
On
Force RF.
TX: Stop data. Transmit RF only
1'b1
1'b0
1'b1
1'b1
Don't care
Don't care
On
Off
Unidir: Backwards compatible.
TX: Transmit data and idle. No
RF.
1'b1
1'b0
1'b1
1'b0
1'b1
1'b0
On
On
Unidir: LF received.
TX: Transmit data 1 column
IDLE after end of packet and RF
1'b1
1'b0
1'b1
1'b0
1'b0
1'b1
On
Off
Unidir: RF receives
TX: Transmit data and idle. No
RF.
1'b1
1'b0
1'b1
1'b0
1'b0
1'b0
On
Off
Unidir: No link fault
TX: Transmit data and idle. No
RF.
1'b1
1'b0
1'b0
Don't
care
1'b1
1'b0
Off
On
Bidir: LF received
TX: Stop data. Transmit RF
only.
1'b1
1'b0
1'b0
Don't
care
1'b0
1'b1
Off
Off
Bidir: RF received
TX: Stop data. Idle only. No RF.
1'b1
1'b0
1'b0
Don’t
care
1'b0
1'b0
On
Off
Bidir: No link fault
TX: Transmit data and idle. No
RF.
Send Feedback
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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4. Functional Description
UG-20109 | 2018.10.05
At this time, the 25G Ethernet Intel FPGA IP core does not recognize received nonzero 4-bit ordered set types as an error.
Related Information
•
TX MAC Registers on page 73
Information about the LINK_FAULT register.
•
IEEE website
The Ethernet specifications are available on the IEEE website.
4.1.5. 25 GbE RX PCS
The soft RX PCS interfaces to the hard PCS and PMA blocks configured in 66:64 10G
PCS Basic Generic Mode with bitslip enabled. The hard PCS drives a 66-bit output
stream to the soft RX PCS. The soft RX PCS implements word lock, descrambling, and
MII decoding. It drives output data to the MAC. You can read the status of FIFOs at
the interface of Hard RX PCS using the Control and Status registers.
Figure 20.
High Level Block Diagram of the RX PCS with Optional RS-FEC Datapath
Soft RX PCS
Hard RX PCS
alt_epscs_a10e25rxg
66:64 Basic
Hard PCS/PMA
25.7815 Gbps
Frame
Watch
Slip
Data
Lock Monitor
and
Control Logic
Descrambler
MII Decoder
Data Scrambling
64:66 Bit
MII Decoding
MII Data and
Control
RS-FEC
(optional)
Word Lock
256:257 Bit
to 64:66 Bit
Transcoding
4.1.5.1. RX RSFEC
If you turn on Enable RS-FEC in the 25G Ethernet Intel FPGA IP parameter editor, the
IP core includes Reed-Solomon forward error correction (FEC) in both the receive and
transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 108 of the IEEE Standard
802.3by. The Reed-Solomon FEC algorithm includes the following modules:
•
Alignment marker lock
•
66:80 gearbox
•
High-speed Reed-Solomon decoder
•
80:257 gearbox
•
256B/257B to 64B/66B Transcoding
4.1.6. Flow Control
Flow control reduces congestion at the local or remote link partner. When either link
partner experiences congestion, the respective transmit control sends pause frames.
XOFF Pause frames stop the remote transmitter. XON Pause frames let the remote
transmitter resume data transmission. Flow control supports both Pause and Priority
Flow Control (PFC) control frames.
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Figure 21.
Flow Control Module Conceptual Overview
The flow control module acts as a buffer between client logic and the TX and RX MAC.
TX Pause/PFC
Frame Control
Frame
Arbiter
MAC
(Core)
TX User Interface
Pause Duration
Pause/PFC Beat
Conversion
RX User Interface
RX Pause/PFC
Frame Control
PHY
CSR
Flow Control
TX Clock
RX Clock
TX Reset
RX Reset
Flow Control includes the following features:
•
Caution:
Pause or PFC frame generation and transmission:
—
Configurable selection of pause flow control (Standard) or priority-based flow
control
—
Programmable 1-bit or 2-bit XON/XOFF request mode
—
In 2-bit request mode, programmable selection of register or signal-based
control
—
Programmable per-queue XOFF frame separation
—
Programmable destination and source addresses in outgoing pause and PFC
frames
—
Programmable pause and PFC quanta
•
PFC frame transmission follows a priority-based arbitration scheme, where the
Frame Type indication is provided for the usage of external downstream logic.
•
Stopping the next client frame transmission on the reception of a valid Pause
frame
•
Stopping the per queue client frame transmission on the reception of a valid PFC
frame from the client. Includes per-queue PFC Pause quanta duration indicator
•
Pause or PFC frame reception and decode:
—
Programmable destination address for filtering incoming pause and PFC frames
—
Configurable Pause or PFC per-queue enable, directing the IP core to ignore
incoming pause frames on disabled queues
—
Per-queue client frame transmission pause duration indicator
The 25G Ethernet Intel FPGA IP core supports the flow control feature for either value
of the Ready Latency parameter. However, in standard flow control you might
experience data delay if you select the value of 3 for this parameter. The IP core might
still hold user data packet in its internal buffer if transmission of the IP core stops due
to flow control. This issue does not occur in priority-based flow control.
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Related Information
Pause/PFC Flow Control Registers on page 75
Describes the registers that the IP core uses to implement the flow control
functionality.
4.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request
An XON/XOFF request triggers the IP core to transmit a Pause or PFC flow control
frame on the Ethernet link. You can control XON/XOFF requests using the TX flow
control registers or the pause_insert_tx0 and pause_insert_tx1 input signals.
You can specify whether the IP core accepts XON/XOFF requests in 1-bit or 2-bit
format by updating the TX Flow Control Request Mode register field. By default
the IP core assumes 1-bit requests.
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4.1.6.2. XON/XOFF Pause Frames
You can trigger the 25G Ethernet Intel FPGA IP core to transmit PFC XOFF frame with
a pause duration that specified in TX Flow Control Quanta register by updating the
pause_insert_tx0 and pause_insert_tx1 input signals or TX flow control
registers. If an enabled priority queue is in the XOFF condition, a new PFC frame is
transmitted after the minimum time gap. You specify the minimum time gap in the per
priority queue TX Flow Control Signal XOFF Request Hold Quanta register.
The minimum time gap between two consecutive PFC frames is 1 pause quanta or
512-bit times. PFC frame transmission ends when none of the PFC interfaces of all
enabled priority queues is requesting PFC frames.
A transition from XOFF to XON in any enabled priority queue triggers the IP core to
transmit a PFC frame with pause quanta of 0 for the associated priority queue. The IP
core sends a single XON flow control frame. In the rare case that the XON frame is
lost or corrupted, the remote partner should still be able to resume transmission. The
remote partner resumes transmission after the duration specified in the previous XOFF
flow control frame expires.
In the case of standard flow control, the IP core transmits Pause frames instead of PFC
frames. The transmission behavior is identical.
When the IP core is in standard flow control mode and receives a Pause frame, the IP
core stops processing TX client data, either immediately or at the next frame
boundary. Client data transmission resumes when all of the following conditions are
true:
•
The time specified by the pause quanta has elapsed and there is no new quanta
value
•
A valid pause frame with 0 pause duration has been received
A Pause frame has no effect if the associated TX Flow Control Enable register bit
is set to disable XON and XOFF flow control.
4.1.7. 1588 Precision Time Protocol Interfaces
If you turn on Enable IEEE 1588, the 25G Ethernet Intel FPGA IP core processes and
provides 1588 Precision Time Protocol (PTP) timestamp information as defined in the
IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement
and Control Systems Standard. This feature supports PHY operating speed with a
constant timestamp accuracy of ± 4 ns and a dynamic timestamp accuracy of ± 1 ns.
1588 PTP packets carry timestamp information. The 25G Ethernet Intel FPGA IP core
updates the incoming timestamp information in a 1588 PTP packet to transmit a
correct updated timestamp with the data it transmits on the Ethernet link, using a
one-step or two-step clock.
A fingerprint can accompany a 1588 PTP packet. You can use this information for
client identification and other client uses. If provided fingerprint information, the IP
core passes it through unchanged.
The IP core connects to a time-of-day (TOD) module that continuously provides the
current time of day based on the input clock frequency. Because the module is outside
the 25G Ethernet Intel FPGA IP core, you can use the same module to provide the
current time of day for multiple modules in your system.
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Related Information
•
1588 PTP Registers on page 86
•
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems Standard is available on the IEEE website.
4.1.7.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA
IP Core
The 1588 specification in IEEE 1588-2008 Precision Clock Synchronization Protocol for
Networked Measurement and Control Systems Standard describes various systems
you can implement in hardware and software to synchronize clocks in a distributed
system by communicating offset and frequency correction information between master
and slave clocks in arbitrarily complex systems. A 1588 system that includes the 25G
Ethernet Intel FPGA IP core with 1588 PTP functionality uses the incoming and
outgoing timestamp information from the IP core and the other modules in the system
to synchronize clocks across the system.
The 25G Ethernet Intel FPGA IP core with 1588 PTP functionality provides the
timestamp manipulation and basic update capabilities required to integrate your IP
core in a 1588 system. You can specify that packets are PTP packets, and how the IP
core should update incoming timestamps from the client interface before transmitting
them on the Ethernet link. The IP core does not implement the event messaging
layers of the protocol, but rather provides the basic hardware capabilities that support
a system in implementing the full 1588 protocol.
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Figure 22.
Example Ethernet System with Ordinary Clock Master and Ordinary Clock
Slave
You can implement both master and slave clocks using the 25G Ethernet Intel FPGA IP core with 1588 PTP
functionality. Refer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature for
implementation of the TOD module.
ToD
Packet
Packet
CPU
Packet Packet
User Logic
Parser
Packet
Packet Packet
Parser
Packet
rx_tod
User Logic
T1
MAC TX
1588
Cable
PHY
MAC RX
1588
T4
25GbE IP Core
FPGA-OC Master
ToD
PHY
T3
MAC TX
1588
Packet
Packet
Packet Packet
User
Logic
Parser
MAC RX
1588
Packet
rx_tod
Packet
Packet Packet
User
Logic
CPU
Parser
25GbE IP Core
T2
FPGA-OC Slave
Figure 23.
Hardware Configuration Example Using 25G Ethernet Intel FPGA IP core in a
1588 System in Transparent Clock Mode
Refer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature for implementation of
the TOD module.
FPGA-TC
ToD
Cable
PHY
Te2
MAC TX
1588
MAC RX
1588
Ti1
25GbE IP Core
Send Feedback
ToD
Ti2
Ti1
Packet
Packet Packet + Ti2
User Logic
Parser
User Logic
Packet + Ti1 Packet
Parser
Packet
Te1
MAC TX
1588
Packet
rx_tod
Packet Packet + Ti1
User Logic
Parser
Packet + Ti2 Packet
User Logic
Parser
Packet
rx_tod
MAC RX
1588
Ti2
PHY
Cable
25GbE IP Core
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Figure 24.
Software Flow Using Transparent Clock Mode System
This figure from the 1588 standard is augmented with the timestamp labels shown in the transparent clock
system figure. A precise description of the software requirements is beyond the scope of this document. Refer
to the 1588 standard.
Figure 25.
Example Boundary Clock with One Slave Port and Two Master Ports
You can implement a 1588 system in boundary clock mode using the 25G Ethernet Intel FPGA IP core with
1588 PTP functionality. Refer to Adding the External Time-of-Day Module for Variations with 1588 PTP Feature
for implementation of the TOD module.
ToD
Cable
PHY
T3
MAC TX
1588
MAC RX
1588
Packet
Packet
Packet Packet
User Logic
Parser
Packet
rx_tod
Packet
Packet Packet
User Logic
Parser
Packet
Packet
CPU
User Logic
Packet Packet
Parser
Packet
User Logic
Packet Packet
Parser
Packet
rx_tod
T1
MAC TX
1588
MAC RX
1588
PHY
Cable
T4
25GbE IP Core
T2
25GbE IP Core
BC Master 0
BC Slave
Packet
Packet Packet
Parser
Packet
Packet Packet
User Logic
Parser
Packet
rx_tod
User Logic
Packet
T1
MAC TX
1588
MAC RX
1588
PHY
Cable
T4
25GbE IP Core
FPGA BC
BC Master 1
Related Information
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems Standard is available on the IEEE website.
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4.1.7.2. PTP Transmit Functionality
When you send a 1588 PTP packet to a 25G Ethernet Intel FPGA IP core with Enable
IEEE 1588 turned on in the parameter editor, you must assert one and only one of
the following input signals with the TX SOP signal to tell the IP core the incoming
packet is a 1588 PTP packet:
•
tx_egress_timestamp_request_valid: assert this signal to tell the IP core to
process the current packet in two-step processing mode.
•
tx_etstamp_ins_ctrl_timestamp_insert: assert this signal to tell the IP
core to process the current packet in one-step processing mode and to insert the
exit timestamp for the packet in the packet (insertion mode).
•
tx_etstamp_ins_ctrl_residence_time_update: assert this signal to tell the
IP core to process the current packet in one-step processing mode and to update
the timestamp in the packet by adding the latency through the IP core (the
residence time in the IP core) to the cumulative delay field maintained in the
packet (correction mode). This mode supports transparent clock systems.
The IP core transmits the 1588 PTP packet in an Ethernet frame after PTP processing.
Figure 26.
PTP Transmit Block Diagram
TOD Module
tx_time_of_day_96b_data
tx_time_of_day_64b_data
tx_data
PTP data
clk_txmac
TX MAC
TX
Adapter
TX PTP
TX
PCS
TX
PMA
tx_egress_timestamp_96b_valid
tx_egress_timestamp_96b_data
tx_egress_timestamp_64b_valid
tx_egress_timestamp_64b_data
In one-step mode, the IP core either overwrites the timestamp information provided
at the user-specified offset with the packet exit timestamp (insertion mode), or adds
the residence time in this system to the value at the specified offset (correction
mode). You tell the IP core how to process the timestamp by asserting the appropriate
signal with the TX SOP signal. You must specify the offset of the timestamp in the
packet (tx_etstamp_ins_ctrl_offset_timestamp) in insertion mode, or the
offset of the correction field in the packet
(tx_etstamp_ins_ctrl_offset_correction_field) in correction mode. In
addition, the IP core zeroes out or updates the UDP checksum, or leaves the UDP
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checksum as is, depending on the mutually exclusive
tx_etstamp_ins_ctrl_checksum_zero and
tx_etstamp_ins_ctrl_checksum_correct signals.
Two-step PTP processing ignores the values on the one-step processing signals. In
two-step processing mode, the IP core does not modify the current timestamp in the
packet. Instead, the IP core transmits a two-step derived timestamp on the separate
tx_egress_timestamp_96b_data[95:0] or
tx_egress_timestamp_64b_data[63:0] bus, when it begins transmitting the
Ethernet frame. The value on the tx_egress_timestamp_{96b,64b}_data bus is
the packet exit timestamp. The tx_egress_timestamp_{96b,64b}_data bus
holds a valid value when the corresponding tx_egress_timestamp_{96b,
64b}_valid signal is asserted.
In addition, to help the client to identify the packet, you can specify a fingerprint to be
passed by the IP core in the same clock cycle with the timestamp. To specify the
number of distinct fingerprint values the IP core can handle, set the Fingerprint
width parameter to the desired number of bits W. You provide the fingerprint value to
the IP core in the tx_egress_timestamp_request_fingerprint[(W–1):0]
signal. The IP core then drives the fingerprint on the appropriate
tx_egress_timestamp_{96b,64b}_fingerprint[(W–1):0] port with the
corresponding output timestamp, when it asserts the tx_egress_timestamp_{96b,
64b}_valid signal.
The IP core calculates the packet exit timestamp.
exit TOD = entry TOD + IP core maintained expected latency + user-configured PMA
latency
•
entry TOD is the value in tx_time_of_day_96b_data or
tx_time_of_day_64b_data when the packet enters the IP core.
•
The expected latency through the IP core is a static value. The IP core maintains
this value internally.
•
The IP core reads the user-configured PMA latency from the
TX_PTP_PMA_LATENCY register. This option is provided for user flexibility.
The IP core provides the exit TOD differently in different processing modes.
•
In two-step mode, the IP core drives the exit TOD on
tx_egress_timestamp_96b_data and on tx_egress_timestamp_64b_data,
as available.
•
In one-step processing insertion mode, the IP core inserts the exit TOD in the
timestamp field of the packet at the offset you specify in
tx_etstamp_ins_ctrl_offset_timestamp.
•
In one-step processing correction mode, the IP core calculates the exit TOD and
uses it only to calculate the residence time.
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In one-step processing correction mode, the IP core calculates the updated correction
field value:
exit correction field value = entry correction field value + residence time + asymmetry
extra latency
•
•
residence time = exit TOD – entry (ingress) timestamp.
entry (ingress) timestamp is the value on
tx_etstamp_ins_ctrl_ingress_timestamp_{95,64}b in the SOP cycle
when the IP core received the packet on the TX client interface. The application is
responsible to drive this signal with the correct value for the cumulative
calculation. The correct value depends on system configuration.
•
The IP core reads the asymmetry extra latency from the TX_PTP_ASYM_DELAY
register if the tx_egress_asymmetry_update signal is asserted. This option is
provided for additional user-defined precision. You can set the value of this
register and set the tx_egress_asymmetry_update signal to indicate the
register value should be included in the latency calculation.
Related Information
•
1588 PTP Registers on page 86
•
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems Standard is available on the IEEE website.
4.1.7.3. PTP Receive Functionality
If you turn on Enable IEEE 1588 in the 25G Ethernet Intel FPGA IP parameter editor,
the IP core provides a 96-bit (V2 format) or 64-bit timestamp with every packet on
the RX client interface, whether it is a 1588 PTP packet or not. The value on the
timestamp bus (rx_ingress_timestamp_96b_data[95:0] or
rx_ingress_timestamp_64b_data[63:0] or both, if present) is valid in the same
clock cycle as the RX SOP signal. The value on the timestamp bus is not the current
timestamp; instead, it is the timestamp from the time when the IP core received the
packet on the Ethernet link. The IP core captures the time-of-day from the TOD
module on rx_time_of_data_96b_data or rx_time_of_day_64b_data at the
time it receives the packet on the Ethernet link, and sends that timestamp to the
client on the RX SOP cycle on the timestamp bus
rx_ingress_timestamp_96b_data[95:0] or
rx_ingress_timestamp_64b_data[63:0] or both, if present. User logic can use
this timestamp or ignore it.
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Figure 27.
PTP Receive Block Diagram
rx_data
SOP
SOP
RX
Adapter
RX MAC
RX
PCS
rx_ingress_timestamp_64b_data
rx_ingress_timestamp_96b_data
clk_rxmac
PTP_RX
rx_time_of_day_96b_data
RX PMA
rx_time_of_day_64b_data
TOD Module
Related Information
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems Standard is available on the IEEE website.
4.1.7.4. External Time-of-Day Module for 1588 PTP Variations
25G Ethernet Intel FPGA IP cores that include the 1588 PTP module require an
external time-of-day (TOD) module to provide the current time-of-day in each clock
cycle, based on the incoming clock. The TOD module must update the time-of-day
output value on every clock cycle, and must provide the TOD value in the V2 format
(96 bits) or the 64-bit TOD format, or both.
Related Information
Adding the External Time-of-Day Module for Variations with 1588 PTP Feature on page
24
4.1.7.5. PTP Timestamp and TOD Formats
The 25G Ethernet Intel FPGA IP core supports a 96-bit timestamp (V2 format) or a 64bit timestamp (correction-field format) in PTP packets. The 64-bit timestamp and TOD
signals of the IP core are in an Intel-defined 64-bit format that is distinct from the V1
format, for improved efficiency in one-step processing correction mode. Therefore, if
your system need not handle any packets in one-step processing correction mode, you
should set the Time of day format parameter to the value of Enable 96-bit
timestamp format.
You control the format or formats the IP core supports with the Time of day format
parameter. If you set the value of this parameter to Enable 96-bit timestamp
format or Enable both formats, your IP core can support two-step processing
mode, one-step processing insertion mode, and one-step processing correction mode,
and can support both V1 and V2 formats. You can set the parameter value to Enable
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64-bit timestamp format to support one-step processing correction mode more
efficiently. However, if you do so, your IP core variation cannot support two-step
processing mode and cannot support one-step processing insertion mode. If you turn
on both of these parameters, the value you drive on the
tx_estamp_ins_ctrl_timestamp_format or
tx_etstamp_ins_ctrl_residence_time_calc_format signal determines the
format the IP core supports for the current packet.
The IP core completes all internal processing in the V2 format. However, if you specify
V1 format for a particular PTP packet in one-step insertion mode, the IP core inserts
the appropriate V1-format timestamp in the outgoing packet on the Ethernet link.
V2 Format
The IP core maintains the time-of-day (TOD) in V2 format according to the IEEE
specification::
•
Bits [95:48]: Seconds (48 bits).
•
Bits [47:16]: Nanoseconds (32 bits). This field overflows at 1 billion.
•
Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it
overflows at 0xFFFF.
The IP core can receive time-of-day information from the TOD module in V2 format or
in 64-bit TOD format, or both, depending on your setting for the Time of day format
parameter.
V1 Format
V1 timestamp format is specified in the IEEE specification:
•
Bits [63:32]: Seconds (32 bits).
•
Bits [31:0]: Nanoseconds (32 bits). This field overflows at 1 billion.
Intel 64-Bit TOD Format
The Intel 64-bit TOD format is distinct from the V1 format and supports a longer time
delay. It is intended for use in transparent clock systems, in which each node adds its
own residence time to a running total latency through the system. This format
matches the format of the correction field in the packet, as used in transparent clock
mode.
•
Bits [63:16]: Nanoseconds (48 bits). This field can specify a value greater than 4
seconds.
•
Bits [15:0]: Fractions of nanosecond (16 bits). This field is a true fraction; it
overflows at 0xFFFF.
The TOD module provides 64-bit TOD information to the IP core in this 64-bit TOD
format. The expected format of all 64-bit input timestamp and TOD signals to the IP
core is the Intel 64-bit TOD format. The format of all 64-bit output timestamp and
TOD signals from the IP core is the Intel 64-bit TOD format. If you build your own TOD
module that provides 64-bit TOD information to the IP core, you must ensure it
provides TOD information in the Intel 64-bit TOD format.
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Related Information
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems Standard is available on the IEEE website.
4.1.7.6. Design Considerations in PTP
•
When the PTP option is enabled together with RS-FEC option, there is no accuracy
loss by neglecting bit shift due to transcode effect with the assumption transcode
effect will be totally reversed at the receiver side.
•
When the PTP option is enabled together with 10/25G switching option,
tx_period, rx_period, tx_pma_delay, and rx_pma_delay need to be
reconfigured according to the running speed. Refer to the 1588 PTP Registers
section for the correct value.
4.2. User Interface to Ethernet Transmission
The IP core reverses the bit stream for transmission per Ethernet requirements. The
transmitter handles the insertion of the inter-packet gap, frame delimiters, and
padding with zeros as necessary. The transmitter also handles FCS computation and
insertion.
The IP core transmits complete packets. After transmission begins, it must complete
with no IDLE insertions. Between the end of one packet and the beginning of the next
packet, the data input is not considered and the transmitter sends IDLE characters. An
unbounded number of IDLE characters can be sent between packets.
4.2.1. Order of Transmission
The IP core transmits bytes on the Ethernet link starting with the preamble and ending
with the FCS in accordance with the IEEE 802.3 standard. On the transmit client
interface, the IP core expects the client to send the the most significant bytes of the
frame first, and to send each byte in big-endian format. Similarly, on the receive client
interface, the IP core sends the client the most significant bytes of the frame first, and
orders each byte in big-endian format.
Figure 28.
Byte Order on the Client Interface Lanes
Describes the byte order on the Avalon-ST interface. Destination Address[40] is the broadcast/multicast bit (a
type bit), and Destination Address[41] is a locally administered address bit.
[23:16]
0
1
0
00
...
...
NN
LSB[ 7:0]
[31:24]
1
MSB[7 :0]
2
Data (D)
[7:0]
3
[15:8]
4
[7:0]
5
[15:8]
0
[39:32]
[23:16]
1
[47:40]
2
Type/
Length (TL)
Source Address (SA)
[7:0]
3
[15:8]
4
[31:24]
Bit
5
[39:32]
Octet
[47:40]
D estination Address (DA)
For example, the destination MAC address includes the following six octets ACDE-48-00-00-80. The first octet transmitted (octet 0 of the MAC address described in
the 802.3 standard) is AC and the last octet transmitted (octet 5 of the MAC address)
is 80. The first bit transmitted is the low-order bit of AC, a zero. The last bit
transmitted is the high order bit of 80, a one.
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The preceding table and the following figure show that in this example, 0xAC is driven
on DA5 (DA[47:40]) and 0x80 is driven on DA0 (DA[7:0]).
Figure 29.
Octet Transmission on the 25GbE Avalon-ST Signals
In the following diagram Preamble pass through and CRC pass through mode are disabled.
clk_txmac
l1_tx_data[63:56]
DA5
SA3
D2
D58
DA5
D82
DA5
SA3
l1_tx_data[55:48]
DA4
SA2
D3
D59
DA4
D83
DA4
SA2
l1_tx_data[47:40]
DA3
SA1
D4
D60
DA3
D84
DA3
SA1
l1_tx_data[39:32]
DA2
SA0
D5
D61
DA2
D85
DA2
SA0
l1_tx_data[31:24]
DA1
TL1
D6
D62
DA1
D86
DA1
TL1
l1_tx_data[23:16]
DA0
TL0
D7
D63
DA0
D87
DA0
TL0
l1_tx_data[15:8]
SA5
D0
D8
SA5
D88
SA5
D0
l1_tx_data[7:0]
SA4
D1
D9
SA4
D89
SA4
D1
l1_tx_startofpacket
l1_tx_endofpacket
l1_tx_empty[2:0]
2
0
4.2.2. Bit Order For TX and RX Datapaths
The TX bit order matches the placement shown in the PCS lanes as illustrated in IEEE
Standard for Ethernet, Section 4, Figure 49-5. The RX bit order matches the
placement shown in IEEE Standard for Ethernet, Section 4, Figure 49-6.
Related Information
IEEE website
The IEEE Standard for Ethernet, Section 4 is available on the IEEE website.
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5. Reset
Control and Status registers control three parallel soft resets. These soft resets are not
self-clearing. Software clears them by writing to the appropriate register. Asserting the
external hard reset csr_rst_n returns Control and Status registers to their original
values.
Figure 30.
Conceptual Overview of Reset Logic
The three hard resets are top-level ports. The soft resets are internal signals which are outputs of the
PHY_CONFIG register. Software writes the appropriate bit of the PHY_CONFIG to assert a soft reset.
soft_txp_rst
tx_pcs_sclr
tx_rst_n
TX
PCS
csr_rst_n
Control
and Status
Registers
(CSR)
eio_sys_rst
tx_mac_sclr
TX
MAC
TX
Adapter
Transceivers
CSR Reset
soft_rxp_rst
rx_pcs_sclr
rx_rst_n
RX
PCS
pcs_ready
rx_mac_sclr
RX
MAC
RX
Adapter
The internal soft reset signals reset the following functions:
•
soft_txp_rst: Resets the IP core in TX direction. Resets the TX PCS, MAC, and
adapter.This soft reset leads to deassertion of tx_lanes_stable output signal.
•
soft_rxp_rst: Resets the IP core in RX direction. Resets the RX PCS, MAC, and
adapter. This soft reset leads to the deassertion of rx_pcs_ready output signal.
•
eio_sys_rst: Resets the IP core. Resets the TX and RX MACs, PCS, adapters,
and transceivers. Does not reset the Control and Status registers. This soft reset
leads to the deassertion of tx_lanes_stable and rx_pcs_ready output signal.
Related Information
•
Reset Signals on page 69
•
PHY Registers on page 71
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
UG-20109 | 2018.10.05
Send Feedback
6. Interfaces and Signal Descriptions
Figure 31.
25G Ethernet Intel FPGA IP Signals and Interfaces
25G Ethernet
Avalon-ST
TX Datapath
Avalon-ST
RX Datapath
Avalon-MM
Interface
to IP Core CSRs
Reset
Signals
Miscellaneous
Status and Debug
Signals
clk_txmac
l1_tx_data[63:0]
l1_tx_valid
l1_tx_startofpacket
l1_tx_endofpacket
l1_tx_empty[2:0]
l1_tx_error
l1_tx_ready
l1_txstatus_valid
l1_txstatus_data[39:0]
l1_txstatus_error[6:0]
pause_insert_tx0[FCQN-1:0]
pause_insert_tx1[FCQN-1:0]
clk_rxmac
l1_rx_data[63:0]
l1_rx_valid
l1_rx_startofpacket
l1_rx_endofpacket
l1_rx_empty[2:0]
l1_rx_error[5:0]
l1_rxstatus_valid
l1_rxstatus_data[39:0]
pause_receive_rx[FCQN-1:0]
clk_status
reset_status
status_addr[15:0]
status_read
status_write
status_readdata[31:0]
status_readdata_valid
status_writedata[31:0]
status_waitrequest
tx_rst_n
rx_rst_n
csr_rst_n
tx_lanes_stable
rx_block_lock
rx_am_lock
rx_pcs_ready
local_fault_status
remote_fault_status
unidirectional_en
link_fault_gen_en
tx_serial
rx_serial
clk_ref
tx_serial_clk (1)
tx_pll_locked
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_address[10:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
tx_clkout
tx_clkout2
rx_clkout
rx_clkout2
rvalid
tvalid_phy
tx_parallel_data_phy[63:0]
tx_control_phy[1:0]
rx_parallel_data_phy[63:0]
rx_control_phy[1:0]
tx_fifo_latency_pulse
tx_pcs_fifo_latency_pulse
rx_fifo_latency_pulse
rx_pcs_fifo_latency_pulse
rx_bitslip
rx_digitalreset
tx_digitalreset
rx_is_lockedtodata
rx_set_lockedtoref
rx_set_lockedtodata
rx_seriallpbken
tx_ready
rx_ready
phy_reset
tx_empty_phy
tx_pempty_phy
tx_full_phy
tx_pfull_phy
rx_empty_phy
rx_pempty_phy
rx_full_phy
rx_pfull_phy
tx_time_of_day_96b_data[95:0]
tx_time_of_day_64b_data[63:0]
rx_time_of_day_96b_data[95:0]
rx_time_of_day_64b_data[63:0]
tx_etstamp_ins_ctrl_timestamp_insert
tx_etstamp_ins_ctrl_residence_time_update
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0]
tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0]
tx_etstamp_ins_ctrl_timestamp_format
tx_etstamp_ins_ctrl_residence_time_calc_format
tx_etstamp_ins_ctrl_offset_timestamp[15:0]
tx_etstamp_ins_ctrl_offset_correction_field[15:0]
tx_etstamp_ins_ctrl_checksum_zero
tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
tx_etstamp_ins_ctrl_checksum_correct
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
tx_egress_asymmetry_update
tx_egress_timestamp_request_valid
tx_egress_timestamp_96b_data[95:0]
tx_egress_timestamp_96b_valid
tx_egress_timestamp_64b_data[63:0]
tx_egress_timestamp_64b_valid
tx_egress_timestamp_request_fingerprint[-1:0]
tx_egress_timestamp_96b_fingerprint[-1:0]
tx_egress_timestamp_64b_fingerprint[-1:0]
rx_ingress_timestamp_96b_data[95:0]
rx_ingress_timestamp_96b_valid
rx_ingress_timestamp_64b_data[63:0]
rx_ingress_timestamp_64b_valid
latency_sclk
Serial Data Signals(2)
Reconfiguration Signals (2)
PHY Interface Signals (3)
1588 Precise Timing
Protocol Interface
Notes:
1. When 10/25G dynamic rate switching is enabled, the tx_serial_clk signal is changed to tx_serial_clk0
and tx_serial_clk1 signals.
2. These signals are applicable only for MAC+PCS+PMA core variant.
3. These signals are applicable only for MAC+PCS core variant.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
6. Interfaces and Signal Descriptions
UG-20109 | 2018.10.05
6.1. TX MAC Interface to User Logic
The TX MAC provides an Avalon-ST interface to the FPGA fabric. The minimum packet
size is nine bytes.
Table 14.
Avalon-ST TX Datapath
All interface signals are clocked by the clk_txmac clock. The value you specify for Ready Latency in the 25G
Ethernet Intel FPGA IP parameter editor is the Avalon-ST readyLatency value on this interface.
Direction
Description
Output
Clock for the TX logic. Derived from pll_refclk, and is an output from
the 25G Ethernet Intel FPGA IP core. clk_txmac is guaranteed to be
stable when tx_lanes_stable is asserted. The frequency of this clock
is 390.625 MHz. All TX MAC interface signals are synchronous to
clk_txmac.
l1_tx_data[63:0]
Input
Data input to MAC. Bit 63 is the MSB and bit 0 is the LSB. Bytes are read
in the usual left to right order.
The 25G Ethernet Intel FPGA IP core does not process incoming frames
of less than nine bytes correctly. You must ensure such frames do not
reach the TX client interface.
You must send each TX data packet without intermediate idle cycles.
Therefore, you must ensure your application can provide the data for a
single packet in consecutive clock cycles. If data might not be available
otherwise, you must buffer the data in your design and wait to assert
l1_tx_startofpacket when you are assured the packet data to send
on l1_tx_data[63:0] is available or will be available on time.
l1_tx_valid
Input
When asserted, indicates valid data is available on l1_tx_data[63:0].
You must assert this signal continuously between the assertions of
l1_tx_startofpacket and l1_tx_endofpacket for the same
packet.
l1_tx_startofpacket
Input
When asserted, indicates the first byte of a frame. When
l1_tx_startofpacket is asserted, the MSB of l1_tx_data drives
the start of packet.
Signal
clk_txmac
Packets that drive l1_tx_startofpacket and l1_tx_endofpacket
in the same cycle are ignored.
l1_tx_endofpacket
Input
When asserted, indicates the end of a packet.
Packets that drive l1_tx_startofpacket and l1_tx_endofpacket
in the same cycle are ignored.
l1_tx_empty[2:0]
Input
Specifies the number of empty bytes on l1_tx_data when
l1_tx_endofpacket is asserted.
l1_tx_error
Input
l1_tx_ready
Output
When asserted, indicates that the MAC can accept the data. The IP core
asserts the l1_tx_ready signal on clock cycle to indicate that
clock cycle is a ready cycle. The client may only
assert l1_tx_valid and transfer data during ready cycles.
l1_txstatus_valid
Output
When asserted, indicates that l1_txstatus_data[39:0] is driving
valid data.
When asserted in the same cycle as l1_tx_endofpacket, indicates the
current packet should be treated as an error packet. Assertion at any
other position in the packet is ignored.
The TX statistics counters do not reflect errors the IP core creates in
response to this signal.
continued...
25G Ethernet Intel Stratix 10 FPGA IP User Guide
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Signal
Direction
Description
l1_txstatus_data[39:0]
Output
Specifies information about the transmit frame. The following fields are
defined:
• Bit[39]: When asserted, indicates a PFC frame
• Bit[38]: When asserted, indicates a unicast frame
• Bit[37]: When asserted, indicates a multicast frame
• Bit[36]: When asserted, indicates a broadcast frame
• Bit[35]: When asserted, indicates a pause frame
• Bit[34]: When asserted, indicates a control frame
• Bit[33]: When asserted, indicates a VLAN frame
• Bit[32]: When asserted, indicates a stacked VLAN frame
• Bits[31:16]: Specifies the frame length from the first byte of the
destination address to the last bye of the FCS
• Bits[15:0]: Specifies the payload length
l1_txstatus_error[6:0]
Output
Specifies the error type in the transmit frame. The following fields are
defined:
• Bits[6:3]: Reserved
• Bit[2]: Payload length error
• Bit[1]: Oversized frame
• Bit[0]: Reserved
Input
pause_insert_tx0[FCQN-1:0
]
pause_insert_tx1[FCQN-1:0
]
Available if you specify Pause or PFC. Indicates to the MAC if an XON,
XOFF, Pause or PFC frame should be sent. FCQN equals 1 for Pause and
1-8 for PFC.
In 1-bit programming mode, the IP core ignores
pause_insert_tx1[FCQN-1:0]. In 2-bit programming mode, the
higher-order bit is in pause_insert_tx1[FCQN-1:0] and the lowerorder bit is in pause_insert_tx0[FCQN-1:0].
The following encodings are defined for 1-bit programming mode:
• 0 = No request
• 0 to 1 = Generate XOFF request
• 1 = Continue to generate XOFF request
• 1 to 0 = Generate XON request
The following encodings are defined for the 2-bit programming model:
• 2'b00: No further XON/XOFF request. If there is a XON/XOFF flow
control frame in progress, it is sent
• 2'b01: Generate XON flow control frame
• 2'b10: Generate XOFF request
• 2'b11: Invalid
Figure 32.
Client to 25G Ethernet Intel FPGA IP MAC Avalon-ST Interface
The IP core expects data order in l1_tx_data is highest byte to lowest byte. The first byte of the destination
address is on l1_tx_data[63:56], 0xabe4 . . . in this timing diagram. The ready latency is 0 in this
example.
clk_txmac
tx_lanes_stable
l1_tx_valid
l1_tx_ready
l1_tx_data
0... abe4...
0101...
0202...
0303...
0404...
0505...
0606...
0707...
0808...
0...
4
0
l1_tx_startofpacket
l1_tx_endofpacket
l1_tx_empty
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25G Ethernet Intel Stratix 10 FPGA IP User Guide
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6. Interfaces and Signal Descriptions
UG-20109 | 2018.10.05
Related Information
Avalon Interface Specifications
Detailed information about Avalon-ST interfaces and the Avalon-ST readyLatency
parameter.
6.2. RX MAC Interface to User Logic
The RX MAC provides an Avalon-ST interface to the FPGA fabric. The datapath consists
of a single 64-bit word.
Table 15.
Avalon-ST RX Datapath
All interface signals are clocked by the clk_rxmac clock.
Signal
Direction
Description
clk_rxmac
Output
Clock for the RX MAC. Recovered from the incoming data. This clock is
guaranteed stable when rx_pcs_ready is asserted. The frequency of
this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G
data rate.. All RX MAC interface signals are synchronous to
clk_rxmac.
l1_rx_data[63:0]
Output
Data output from the MAC. Bit[63] is the MSB and bit[0] is the LSB.
Bytes are read in the usual left to right order. The IP core reverses the
byte order to meet the requirements of the Ethernet standard.
l1_rx_valid
Output
When asserted, indicates that l1_rx_data[63:0] is driving valid data.
If you turn off Enable RS-FEC, the IP core asserts this signal
continuously between the assertions of l1_tx_startofpacket and
l1_tx_endofpacket for the same packet. However, if you turn on
Enable RS-FEC, the IP core drives IDLE cycles during alignment marker
cycles.
l1_rx_startofpacket
Output
When asserted, indicates the first byte of a frame.
l1_rx_endofpacket
Output
When asserted, indicates the last data byte of a frame, before the frame
check sequence (FCS). In CRC pass-through mode, it is the last byte of
the FCS. The packet can end at any byte position.
l1_rx_empty[2:0]
Output
Specifies the number of empty bytes when l1_rx_endofpacket is
asserted.
The packet can end at any byte position. The empty bytes are the loworder bytes.
l1_rx_error[5:0]
Output
When asserted in the same cycle as l1_rx_endofpacket, indicates the
current packet should be treated as an error packet. The 6 bits of
l1_rx_error specify the following errors:
•
•
l1_rx_error[5]: Unused.
l1_rx_error[4]: Payload length error. If the length field is
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