8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
J
J
J
J
J
J
J
J
Real Time and Programmed Wait State
Bus Operation
Binary-code Compatible with MCS® 51
Pin Compatible with 44-lead PLCC and
40-lead PDIP MCS 51 Sockets
®
Register-based MCS 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes, Words,
and Double Words
Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
Linear Addressing
ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
16-bit Internal Code Fetch
J
64-Kbyte Extended Stack Space
J
J
J
32 Programmable I/O Lines
Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
Three Flexible 16-bit Timer/counters
J
Hardware Watchdog Timer
J
J
Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
J
High-performance CHMOS Technology
J
Static Standby to 16-MHz Operation
J
On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
8-bit, “Min” 2-clock External Code Fetch
in
Page Mode
User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
J
256-Kbyte Expanded External Code/Data
Memory Space
J
J
J
J
J
Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
Package Options (PDIP, PLCC, and
Ceramic DIP)
Fast MCS 251 Instruction Pipeline
This document contains information on products with “[M] [C] '94 '95 C” as the last line of the top marking
diagram. A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binarycode compatible with MCS 51 microcontrollers and pin compatible with 40-lead PDIP and 44-lead PLCC
MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing,
and efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without
ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of
any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
July 2004
Order Number: 272783-004
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P2.7:0
Port 0
Drivers
Port 2
Drivers
Code
OTPROM/ROM
8 Kbytes
or
16 Kbytes
Data RAM
512 Bytes
or
1024 Bytes
P1.7:0
P3.7:0
Port 1
Drivers
Port 3
Drivers
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Peripheral
Interface
Bus Interface
Interrupt
Handler
Data Bus (8)
SRC2 (8)
Data Address (24)
Instruction Sequencer
SRC1 (8)
IB Bus (8)
Code Address (24)
Code Bus (16)
Timer/
Counters
PCA
Serial I/O
ALU
Register
File
Data
Memory
Interface
Clock
&
Reset
Peripherals
DST (16)
MCS® 251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
A4214-01
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
2
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TEMPERATURE RANGE
With the commercial (standard) temperature option,
the device operates over the temperature range
0°C to +70°C. The express temperature option
provides -40°C to +85°C device operation.
PROLIFERATION OPTIONS
Quality and Reliability Handbook (order number
210997).
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
change depending on operating conditions and
application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology.
Table 2. Thermal Characteristics
Table 1 lists the proliferation options. See Figure 2
for the 8XC251SA/SB/SP/SQ family nomenclature.
Table 1. Proliferation Options
θJA
θJC
46°C/W
16°C/W
45°C/W
16°C/W
30.5°C/W
10°C/W
Package Type
44-lead PLCC
40-lead PDIP
8XC251SA/SB/SP/SQ
(0 – 16 MHz; 5 V ±10%)
40-lead Ceramic DIP
80C251SB16
CPU-only
80C251SQ16
CPU-only
83C251SA16
ROM
83C251SB16
ROM
83C251SP16
ROM
83C251SQ16
ROM
Pkg.
87C251SA16
OTPROM/EPROM
X
44 ld. PLCC
0°C to +70°C
87C251SB16
OTPROM/EPROM
87C251SP16
OTPROM/EPROM
X
40 ld. Plastic DIP
0°C to +70°C
87C251SQ16
OTPROM/EPROM
X
40 ld. Ceramic DIP
0°C to +70°C
X
44 ld. PLCC
-40°C to +85°C
X
40 ld. Plastic DIP
-40°C to +85°C
PROCESS INFORMATION
This device is manufactured on a complimentary
high-performance
metal-oxide
semiconductor
(CHMOS) process. Additional process and reliability
information is available in Intel’s Components
PACKAGE OPTIONS
Table 3 lists the 8XC251SA/SB/SP/SQ packages.
Table 3. Package Information
NOTE:
Definition
Temperature
To address the fact that many of the package prefix variables have changed, all
package prefix variables in this document
are now indicated with an "x".
3
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
X
XX
8
X
X
XXXXX
XX
a
ck
gin
s
tio
on
Op
pti
-in
rn
gO
Bu
nd
ea
tur
ra
ed
pe
eS
vic
De
ily
am
tF
uc
od
on
Pr
ati
ns
rm
tio
nfo
Op
sI
ry
es
mo
oc
Pr
me
mra
og
Pr
Pa
e
mp
Te
ns
A2815-01
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature
Table 4. Description of Product Nomenclature
Parameter
Temperature and Burn-in
Options
Packaging Options
Program Memory Options
Process Information
Options
Description
no mark
Commercial operating temperature range (0°C to 70°C) with
Intel standard burn-in.
X
Express operating temperature range (-40°C to 85°C) with
Intel standard burn-in.
X
44-lead Plastic Leaded Chip Carrier (PLCC)
X
40-lead Plastic Dual In-line Package (PDIP)
X
40-lead Ceramic Dual In-line Package (Ceramic DIP)
0
Without ROM/OTPROM/EPROM
3
ROM
7
User programmable OTPROM/EPROM
C
CHMOS
Product Family
251
8-bit control architecture
Device Memory Options
SA
1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM
SB
1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
Device Speed
SP
512-byte RAM/8-Kbyte ROM/OTPROM/EPROM
SQ
512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
16
External clock frequency
NOTES:
1. To address the fact that many of the package prefix variables have changed, all package prefix variables in the document are now indicated with an "x".
4
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251SA/SB/SP/SQ Memory Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory (FF:FFF8H–FF:FFFFH are internally decoded for Configuration
Byte data in all ROM/OTPROM/EPROM devices with EA# = 1. For all devices
with EA# = 0, the last 8 bytes of the external address range FF:XFF8H–
FF:XFFFH contain Configuration Byte information).
1, 3, 10
FF:3FFFH
FF:0000H
External memory or for internal ROM/OTPROM/EPROM devices: 16-Kbytes of
internal addresses as determined by the EA# pin (Table 8). Note: 8-Kbyte internal
ROM/OTPROM/EPROM array addresses end at FF:1FFFH.
3, 4, 5
FE:FFFFH
FE:0000H
External Memory
3
FD:FFFFH
FD:0000H
Reserved
6
FC:FFFFH
FC:0000H
Reserved
6
FB:FFFFH
04:0000H
Reserved
6
03:FFFFH
03:0000H
Reserved
6
02:FFFFH
02:0000H
Reserved
6
01:FFFFH
01:0000H
External Memory
3
00:FFFFH
00:E000H
External memory or with EMAP# bit = 0 this address range for 16-Kbyte devices
is redirected to internal ROM/OTPROM/EPROM array region.
5, 7
00:DFFFH
00:0420H
External Memory
7
00:041FH
00:0080H
On-chip RAM (512 byte RAM devices end at 00:021FH
7
00:007FH
00:0020H
On-chip RAM
8
00:001FH
00:0000H
Storage for R0–R7 of Register File
2, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate internal address spaces.
3. Data in this area is accessible by indirect addressing only.
4. Devices can reset into different internal or external starting locations depending on the state of EA#
and configuration register information (see EA#. See also UCONFIG1:0 bit definitions).
5. The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map
into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal
ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte
ROM/OTPROM/EPROM devices.
6. This reserved area returns unspecified values and writes no data.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
10. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
5
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6
5
4
3
2
1
44
43
42
41
40
P1.4 / CEX1
P1.3 / CEX0
P1.2 / ECI
P1.1 / T2EX
P1.0 / T2
VSS1
VCC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
8XC251SA/SB/SP/SQ 44-lead PLCC Package
7
8
9
10
11
12
13
14
15
16
17
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
View of component as
mounted on PC board
39
38
37
36
35
34
33
32
31
30
29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA# / VPP
VSS2
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
VSS
VSS2
A8 / P2.0
A9 / P2.1
A10 / P2.2
A11 / P2.3
A12 / P2.4
18
19
20
21
22
23
24
25
26
27
28
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
VCC2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
A4205-02
Figure 3. 8XC251SA/SB/SP/SQ 44-lead PLCC Package
6
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
P1.0 / T2
1
40
VCC
P1.1 / T2EX
2
39
AD0 / P0.0
P1.2 / ECI
3
38
AD1 / P0.1
P1.3 / CEX0
4
37
AD2 / P0.2
P1.4 / CEX1
5
36
AD3 / P0.3
P1.5 / CEX2
6
35
AD4 / P0.4
P1.6 / CEX3 / WAIT#
7
34
AD5 / P0.5
P1.7 / CEX4 / A17 / WCLK
8
33
AD6 / P0.6
RST
9
32
P3.0 / RXD
10
31
AD7 / P0.7
EA# / VPP
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
P3.1 / TXD
11
30
ALE / PROG#
P3.2 / INT0#
12
29
PSEN#
P3.3 / INT1#
13
28
A15 / P2.7
P3.4 / T0
14
27
A14 / P2.6
P3.5 / T1
15
26
A13 / P2.5
P3.6 / WR#
16
25
A12 / P2.4
P3.7 / RD# / A16
17
24
A11 / P2.3
XTAL2
18
23
A10 / P2.2
XTAL1
VSS
19
22
A9 / P2.1
20
21
A8 / P2.0
View of
component
as mounted
on PC board
A4206-03
Figure 4. 8XC251SA/SB/SP/SQ 40-lead PDIP and Ceramic DIP Packages
7
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. PLCC/DIP Lead Assignments Listed by Functional Category
Address & Data
Name
Input/Output
PLCC
DIP
PLCC
DIP
AD0/P0.0
43
39
P1.0/T2
2
1
AD1/P0.1
42
38
P1.1/T2EX
3
2
AD2/P0.2
41
37
P1.2/ECI
4
3
AD3/P0.3
40
36
P1.3/CEX0
5
4
AD4/P0.4
39
35
P1.4/CEX1
6
5
AD5/P0.5
38
34
P1.5/CEX2
7
6
AD6/P0.6
37
33
P1.6/CEX3/WAIT#
8
7
AD7/P0.7
36
32
P1.7/CEX4/A17/WCLK
9
8
A8/P2.0
24
21
P3.0/RXD
11
10
A9/P2.1
25
22
P3.1/TXD
13
11
A10/P2.2
26
23
P3.4/T0
16
14
A11/P2.3
27
24
P3.5/T1
17
15
A12/P2.4
28
25
A13/P2.5
29
26
A14/P2.6
30
27
A15/P2.7
31
28
P3.7/RD#/A16
19
17
P1.7/CEX4/A17/WCLK
9
8
Processor Control
Name
8
Name
Power & Ground
Name
PLCC
DIP
VCC
44
40
VCC2
12
VSS
22
VSS1
1
VSS2
23, 34
EA#/VPP
35
20
31
PLCC
DIP
P3.2/INT0#
14
12
P3.3/INT1#
15
13
EA#/VPP
35
31
P3.6/WR#
18
16
RST
10
9
P3.7/RD#/A16
19
17
XTAL1
21
18
ALE/PROG#
33
30
XTAL2
20
19
PSEN#
32
29
Bus Control & Status
Name
PLCC
DIP
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 7. Lead Assignments Arranged by Lead Number
PLCC
DIP
1
Name
PLCC
VSS1
23
DIP
Name
VSS2
2
1
P1.0/T2
24
21
A8/P2.0
3
2
P1.1/T2EX
25
22
A9/P2.1
4
3
P1.2/ECI
26
23
A10/P2.2
5
4
P1.3/CEX0
27
24
A11/P2.3
6
5
P1.4/CEX1
28
25
A12/P2.4
7
6
P1.5/CEX2
29
26
A13/P2.5
8
7
P1.6/CEX3/WAIT#
30
27
A14/P2.6
9
8
P1.7/CEX4/A17/WCLK
31
28
A15/P2.7
10
9
RST
32
29
PSEN#
11
10
P3.0/RXD
33
30
ALE/PROG#
12
VCC2
34
13
11
P3.1/TXD
35
31
VSS2
EA#/VPP
14
12
P3.2/INT0#
36
32
AD7/P0.7
15
13
P3.3/INT1#
37
33
AD6/P0.6
16
14
P3.4/T0
38
34
AD5/P0.5
17
15
P3.5/T1
39
35
AD4/P0.4
18
16
P3.6/WR#
40
36
AD3/P0.3
19
17
P3.7/RD#/A16
41
37
AD2/P0.2
20
18
XTAL2
42
38
AD1/P0.1
21
19
XTAL1
43
39
AD0/P0.0
22
20
VSS
44
40
VCC
9
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SIGNAL DESCRIPTIONS
Table 8. Signal Descriptions
Signal
Name
Alternate
Function
Type
Description
A17
O
18th Address Bit (A17). Output to memory as 18th external address
bit (A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Table 9). See also
RD# and PSEN#.
P1.7/CEX4/
WCLK
A16
O
Address Line 16. See RD#.
RD#
A15:8†
O
Address Lines. Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
P0.7:0
ALE
O
Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
PROG#
CEX4:0
I/O
Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
P1.6:3
P1.7/A17/
WAIT#
†
EA#
I
External Access. Directs program memory accesses to on-chip or off- VPP
chip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EPROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
ECI
I
PCA External Clock Input. External clock input to the 16-bit PCA
timer.
P1.2
INT1:0#
I
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
P3.3:2
PROG#
I
Programming Pulse. The programming pulse is applied to this pin for
programming the on-chip OTPROM.
ALE
P0.7:0
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
P1.1
P1.2
P1.7:3
I/O
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
T2EX
ECI
CEX3:0
CEX4/A17/
/WAIT#/
WCLK
P2.7:0
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
†
10
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate
Function
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PSEN#
O
Program Store Enable. Read signal output. This output is asserted
for a memory address range that depends on bits RD0 and RD1 in
configuration byte UCONFIG0 (see RD# and Table 9):
—
RD#
O
Read or 17th Address Bit (A16). Read signal output to external data
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
):
P3.7/A16
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins
are driven to their reset conditions when a voltage greater than VIH1 is
applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
—
RXD
I/O
Receive Serial Data. RXD sends and receives data in serial I/O mode
0 and receives data in serial I/O modes 1, 2, and 3.
P3.0
T1:0
I
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
P1.0
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determines count direction: 1=up, 0=down.
P1.1
TXD
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3.
P3.1
VCC
PWR
Supply Voltage. Connect this pin to the +5V supply voltage.
—
VCC2
PWR
Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP)
—
VPP
I
Programming Supply Voltage. The programming supply voltage is
applied to this pin for programming the on-chip OTPROM/EPROM.
EA#
VSS
GND
Circuit Ground. Connect this pin to ground.
—
T2
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
11
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
Signal
Name
Alternate
Function
Type
Description
VSS1
GND
Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SA/SB/SP/SQ as
a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected
without loss of compatibility. (Not available on DIP)
—
VSS2
GND
Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this pin to
ground is recommended. However, when using the 8XC251SB as a
pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected
without loss of compatibility. (Not available on DIP)
—
WAIT#
I
Real Time Wait State Input. The real time WAIT# input is enabled by
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real time WCLK output is driven at port 1.7
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with
a period of one-half the ocillator frequency.
P1.7/CEX4/
A17
WR#
O
Write. Write signal output to external memory.
P3.6
XTAL1
I
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
—
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
—
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for pagemode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
Table 9. Memory Signal Selections (RD1:0)
RD1:0
12
P1.7/CEX/
A17
RD#
PSEN#
WR#
Features
0 0
A17
RD# = A16
Asserted for
all addresses
Asserted for writes to all
memory locations
256-Kbyte external
memory
0 1
P1.7/CEX4
RD# = A16
Asserted for
all addresses
Asserted for writes to all
memory locations
128-Kbyte external
memory
1 0
P1.7/CEX4
P3.7 only
Asserted for
all addresses
Asserted for writes to all
memory locations
One additional port
pin
1 1
P1.7/CEX4
Asserted for
≤ 7F:FFFFH
Asserted for
≥ 80:0000H
Asserted for all compatible MCS 51 memory
locations
Compatible with
MCS 51 microcontrollers
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS†
Ambient Temperature under Bias:
Commercial ..........................................0°C to +70°C
Express .............................................-40°C to +85°C
Storage Temperature ..............................-65°C to +150°C
Voltage on EA#/VPP Pin to VSS.................. 0 V to +13.0 V
Voltage on Any other Pin to VSS .............. -0.5 V to +6.5 V
IOL per I/O Pin ..........................................................15 mA
Power Dissipation ................................................... 1.5 W
NOTE:
Maximum power dissipation is based on
package heat-transfer limitations, not
device power consumption.
OPERATING CONDITIONS†
NOTICE: This document contains information on products in the design phase of
development. Do not finalize a design with
this information. Revised information will be
published when the product is available.
Verify with your local Intel Sales Office that
you have the latest datasheet before finalizing a design.
†WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the
“Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
TA (Ambient Temperature Under Bias):
Commercial ..........................................0°C to +70°C
Express .............................................-40°C to +85°C
VCC (Digital Supply Voltage) ...................... 4.5 V to 5.5 V
VSS .............................................................................. 0 V
13
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Table 10. DC Characteristics at VCC = 4.5 – 5.5 V
Max
Units
VIL
Symbol
Input Low Voltage
(except EA#)
Parameter
Min
-0.5
0.2VCC – 0.1
V
VIL1
Input Low Voltage
(EA#)
0
0.2VCC – 0.3
V
VIH
Input High Voltage
(except XTAL1, RST)
0.2VCC + 0.9
VCC + 0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7VCC
VCC + 0.5
V
VOL
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
V
IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
(Note 1, Note 2)
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
(Note 1, Note 2)
VOH
Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)
V
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
(Note 3)
VCC – 0.3
VCC – 0.7
VCC – 1.5
Typical
Test Conditions
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to
sink current greater than the listed test conditions.
2.
3.
4.
14
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 10. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VOH1
Output High Voltage
(Port 0 in External
Address)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
Voh2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
IIL
Logical 0 Input Current (Port 1, 2, 3)
-50
µA
VIN = 0.45 V
ILI
Input Leakage Current (Port 0)
+/-10
µA
0.45 < VIN < VCC
ITL
Logical 1-to-0 Transition Current (Port 1,
2, 3)
-650
µA
VIN = 2.0 V
Rrst
RST Pulldown Resistor
225
kΩ
Cio
Pin Capacitance
10
(Note 4)
Ipd
Powerdown Current
10
(Note 4)
< 20
µA
Idl
Idle Mode Current
5
(Note 4)
7
mA
FOSC = 16 MHz
ICC
Operating Current
20
(Note 4)
45
mA
FOSC = 16 MHz
40
pF
FOSC = 16 MHz
TA = 25 °C
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to
sink current greater than the listed test conditions.
2.
3.
4.
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
15
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VCC
VCC
IPD
VCC
P0
EA#
RST
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
(NC)
XTAL2
XTAL1
VSS
All other 8XC251SA/SB/SP/SQ pins are unconnected.
A4208-01
Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V
16
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
A.C. Characteristics
Table 11 lists AC timing parameters for the
8XC251SA/SB/SP/SQ with no wait states. External
wait states can be added by extending
PSEN#/RD#/WR# and/or by extending ALE. In the
table, Notes 3 and 5 mark parameters affected by an
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Figures 6–11 show the bus cycles with the timing
parameters.
Table 11. AC Characteristics (Capacitive Loading = 50 pF)
Symbol
Parameter
@ Max Fosc (1)
Min
Max
FOSC
XTAL1 Frequency
N/A
N/A
Tosc
1/FOSC
N/A
N/A
Tlhll
ALE Pulse Width
@ 12 MHz
@ 16 MHz
73.3
52.5
Address Valid to ALE Low
@ 12 MHz
@ 16 MHz
63.3
42.5
Address Hold after ALE Low
@ 12 MHz
@ 16 MHz
10
10
RD# or PSEN# Pulse Width
@ 12 MHz
@ 16 MHz
156.6
115
WR# Pulse Width
@ 12 MHz
@ 16 MHz
156.6
115
ALE Low to RD# or PSEN# Low
@ 12 MHz
@ 16 MHz
63.3
42.5
ALE High to Address Hold
@ 12 MHz
@ 16 MHz
83.3
62.5
Tavll
Tllax
TRLRH (2)
Twlwh
Tllrl (2)
Tlhax
@ 12 MHz
@ 16 MHz
Fosc Variable
Min
Max
0
16
83.3
62.5
(1+2M)
TOSC – 10
(1+2M)
TOSC – 20
Units
MHz
ns
ns
(3)
ns
(3)
ns
10
2(1+N)
TOSC – 10
2(1+N)
TOSC – 10
ns
(4)
ns
(4)
ns
TOSC – 20
(1+2M)
TOSC
ns
(3)
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
17
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
Symbol
Parameter
@ Max Fosc (1)
Min
TRLDV (2) RD#/PSEN# Low to valid Data/Instruction In
@ 12 MHz
@ 16 MHz
Max
0
RD#/PSEN# Low to Address Float
Trhdz1
Instruction Float after RD#/PSEN# High
@ 12 MHz
@ 16 MHz
10
10
Data Float after RD#/PSEN# High
@ 12 MHz
@ 16 MHz
176.6
135
TRHLH2
TWHLH
Tavdv1
Tavdv2
TAVDV3
Typ.=0 2
(5)
RD#/PSEN# High to ALE High (Instruction)
@ 12 MHz
@ 16 MHz
10
10
RD#/PSEN# High to ALE High (Data)
@ 12 MHz
@ 16 MHz
176.6
135
WR# High to ALE High
@ 12 MHz
@ 16 MHz
176.6
135
Typ. = 0
(5)
Units
ns
(4)
ns
2
ns
ns
10
ns
2Tosc
+10
ns
10
ns
2Tosc + 10
ns
2Tosc + 10
Address (P0) Valid to Valid Data/Instruction In
@ 12 MHz
@ 16 MHz
263.2
180
Address (P2) Valid to Valid Data/Instruction In
@ 12 MHz
@ 16 MHz
278.2
195
Address (P0) Valid to Valid Instruction In
@ 12 MHz
@ 16 MHz
116.6
75
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
18
Max
2(1+N)
Tosc – 50
0
TRLAZ (2)
Trhlh1
Min
116.6
75
TRHDX (2) Data/Instruction Hold Time. Occurs after
RD#/PSEN# are exerted to VOH
Trhdz2
Fosc Variable
4(1+M/2)
TOSC – 70
4(1+M/2)
TOSC – 55
ns
(3)
ns
(3)
ns
2TOSC
– 50
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
Symbol
Tavrl (2)
Tavwl1
TAVWL2
TWHQX
TQVWH
TWHAX
Parameter
@ Max Fosc (1)
Min
Address Valid to RD#/PSEN# Low
@ 12 MHz
@ 16 MHz
146.6
105
Address (P0) Valid to WR# Low
@ 12 MHz
@ 16 MHz
156.6
115
Address (P2) Valid to WR# Low
@ 12 MHz
@ 16 MHz
166.6
125
Data Hold after WR# High
@ 12 MHz
@ 16 MHz
63.3
42.5
Data Valid to WR# High
@ 12 MHz
@ 16 MHz
143.6
102
WR# High to Address Hold
@ 12 MHz
@ 16 MHz
146.6
105
Max
Fosc Variable
Min
2(1+M)
TOSC – 20
2(1+M)
TOSC – 10
2(1+M)
TOSC
Max
Units
ns
(3)
ns
(3)
ns
(3)
ns
TOSC – 20
2(1+N)
TOSC – 23
ns
(4)
ns
2TOSC – 20
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
19
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SYSTEM BUS TIMINGS
TOSC
XTAL1
ALE
TLHLL†
TRLRH†
TLLRL†
TRHLH2
RD#/PSEN#
TRLDV†
TRLAZ
TLHAX†
TRHDZ2
TAVLL†
P0
TLLAX
A7:0
TRHDX
D7:0
TAVRL†
Data In
TAVDV1†
TAVDV2†
P2/A16/A17
A15:8/A16/A17
† The value of this parameter depends on wait states. See the table of AC characteristics.
A4210-01
Figure 6. External Read Data Bus Cycle in Nonpage Mode
20
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC
XTAL1
ALE
TLHLL†
TRLRH†
TRHLH1
TLLRL†
RD#/PSEN#
TRLDV†
TRLAZ
TLHAX
TAVLL
P0
†
†
TLLAX
A7:0
TAVRL†
TRHDZ1
TRHDX
D7:0
Instruction In
TAVDV1†
TAVDV2†
P2/A16/A17
A15:8/A16/A17
† The value of this parameter depends on wait states. See the table of AC characteristics.
A4211-01
Figure 7. External Instruction Bus Cycle in Nonpage Mode
21
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC
XTAL1
ALE
TLHLL†
TWLWH†
WR#
TLHAX†
TAVLL†
TLLAX
P0
TQVWH
TWHQX
A7:0
D7:0
Data Out
TAVWL1†
TAVWL2†
P2/A16/A17
TWHLH
TWHAX
A15:8/A16/A17
† The value of this parameter depends on wait states. See the table of AC characteristics.
A4179-01
Figure 8. External Write Data Bus Cycle in Nonpage Mode
22
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC
XTAL1
ALE
TLHLL†
TRLRH†
TLLRL†
TRHLH2
RD#/PSEN#
TRLDV†
TRLAZ
TLHAX†
TRHDZ2
TAVLL†
P2
TLLAX
TRHDX
A15:8
D7:0
†
Data In
TAVRL
TAVDV1†
TAVDV2†
P0/A16/A17
A7:0/A16/A17
† The value of this parameter depends on wait states. See the table of AC characteristics.
A4212-01
Figure 9. External Read Data Bus Cycle in Page Mode
23
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC
XTAL1
ALE
TLHLL†
TWLWH†
WR#
TLHAX†
TAVLL†
TLLAX
P2
TQVWH
TWHQX
A15:8
D7:0
Data Out
TAVWL1†
TAVWL2†
P0/A16/A17
TWHLH
TWHAX
A7:0/A16/A17
† The value of this parameter depends on wait states. See the table of AC characteristics.
A4182-01
Figure 10. External Write Data Bus Cycle in Page Mode
24
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC
XTAL1
ALE
TLHLL†
TLLRL†
†††
RD#/PSEN#
TRLDV†
TRLAZ
TRHDZ1
TLHAX†
TAVLL†
P2
TRHDX
TLLAX
A15:8
TAVRL†
D7:0
TAVDV1†
TAVDV2†
P0/A16/A17
D7:0
Instruction In
A7:0/A16/A17
Page Miss††
Instruction In
TAVDV3
A7:0/A16/A17
Page Hit††
† The value of this parameter depends on wait states. See the table of AC characteristics.
†† A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2TOSC); a page miss requires two states (4TOSC).
††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
A4213-02
Figure 11. External Instruction Bus Cycle in Page Mode
25
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
AC Characteristics — Serial Port, Shift Register Mode
Table 12. Serial Port Timing — Shift Register Mode
Symbol
Parameter
Min
Max
Units
TXLXL
Serial Port Clock Cycle Time
12TOSC
ns
TQVSH
Output Data Setup to Clock Rising Edge
10TOSC – 133
ns
TXHQX
Output Data hold after Clock Rising Edge
2TOSC – 117
ns
TXHDX
Input Data Hold after Clock Rising Edge
0
ns
TXHDV
Clock Rising Edge to Input Data Valid
10TOSC – 133
ns
TXLXL
TXD
TXHQX
Set TI†
TQVXH
RXD
(Out)
0
1
2
Valid
7
6
5
TAV†
TXHDV
RXD
(In)
4
3
Set RI†
TXHDX
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 12. Serial Port Waveform — Shift Register Mode
26
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
External Clock Drive
Table 13. External Clock Drive
Symbol
Parameter
1/TCLCL
Oscillator Frequency (FOSC)
Min
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
10
ns
TCHCL
Fall Time
10
ns
TCLCH
VCC – 0.5
Max
Units
16
MHz
TCHCX
0.7 VCC
TCLCX
0.45 V
0.2 VCC – 0.1
TCHCL
TCLCL
A4119-01
Figure 13. External Clock Drive Waveforms
Outputs
Inputs
VCC – 0.5
0.2 VCC + 0.9
VIH MIN
0.45 V
0.2 VCC – 0.1
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 14. AC Testing Input, Output Waveforms
27
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VLOAD + 0.1 V
VOH – 0.1 V
Timing Reference
Points
VLOAD
VOL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 15. Float Waveforms
VCC
A0 - A7
P3
A8 - A15
P1
Address
(16 Bits)
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
VCC
RST
P2
EA#/Vpp
XTAL1
4 MHz
to
6 MHz
ALE/PROG#
Data
(8 Bits)
Programming
Signals
PSEN#
XTAL2
VSS
P0
Program/Verify Mode
(8 Bits)
A4209-01
Figure 16. Setup for Programming and Verifying Nonvolatile Memory
28
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
The 87C251SA/SB/SP/SQ has several areas of
nonvolatile memory that can be programmed
and/or verified: on-chip code memory (16
Kbytes), lock bits (3 bits), encryption array (128
bytes), and signature bytes (3 bytes). The
8XC251SA/SB/SP/SQ User’s Manual (Order
Number: 272795) provides procedures for
programming and verifying the nonvolatile
memory.
Information in Figures 17 and 18 define the
configuration bits. Figure 19 shows the
waveforms for the programming and verification
cycles, and Table 15 lists the timing specifications.
The
signature
bytes
of
the
83C251SA/SB/SP/SQ ROM versions and the
87C251SA/SB/SP/SQ OTP versions are factory
programmed. Table 16 lists the addresses and
the contents of the signature bytes.
Figure 16 shows the setup for programming
and/or verifying the nonvolatile memory. Table 14
lists the programming and verification operations
and indicates which operations apply to the
different versions of the 87C251SA/SB/SP/SQ. It
also specifies the signals on the programming
input
(PROG#)
and
the
ports.
The
ROM/OTPROM/EPROM mode (port 0) specifies
the operation (program or verify) and the base
address of the memory area. The addresses
(ports 1 and 3) are relative to the base address.
(On-chip
memory
for
an
8-Kbyte
ROM/OTPROM/EPROM device is located at
address range FF:0000H–FF:1FFFH. On-chip
memory for a 16-Kbyte ROM/OTPROM/EPROM
device is located at address range FF:0000H–
FF:3FFFH.
The
other
areas
of
the
ROM/OTPROM/EPROM are outside the memory
address space and are accessible only during
programming and verification.)
Factory-programmed ROM and OTPROM
versions of 8XC251SA/SB/SP/SQ use configuration byte information supplied in a separate
hexadecimal disk file. 8XC251SA/SB/SP/SQ
devices without internal ROM/OTPROM/EPROM
arrays fetch configuration byte information from
external application memory based on an internal
address range of FF:FFF9:8H.
NOTE:
The VPP source in Figure 16 must be well
regulated and free of glitches. The voltage
on the VPP pin must not exceed the
specified maximum, even under transient
conditions.
29
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 14. Programming and Verification Modes
Mode
8XC251SA/S
B/SP/SQ
X=7
Program on-chip code
memory
Y
Verify on-chip code
memory
Y
P0
P2
5 Pulses
68H
Data
0000H–3FFFH (16K)
000H-1FFFH (8K)
High
28H
Data
0000H–3FFFH (16K)
0000H-1FFFH (8K)
X=3
Y
Addresses
P1 (high), P3 (low)
PROG#
Notes
1
Program configuration
bytes
2
Verify configuration
bytes
2
Program lock bits
Y
Verify lock bits
Y
Program encrypt ion
array
Y
Verify signature bytes
Y
25 Pulses
Y
Y
6BH
XX
0001H–0003H
1, 3
High
2BH
Data
0000H
4
25 Pulses
6CH
Data
0000H–007FH
1
High
29H
Data
0030H, 0031H, 0060H
NOTES:
1. The PROG# pulse waveform is shown in Figure 19.
2. Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use configuration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ
devices without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from
external application memory based on an internal address range of FF:FFF9:8H.
3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with
the address as follows: LB3 - 0003H, LB2 - 0002H, LB1 - 0001H
4. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High = programmed.
30
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Address FF:FFF8H
UCONFIG0
7
0
UCON
WSA1#
WSA0#
XALE#
RD1
RD0
PAGE#
SRC
Bit
Number
Bit
Mnemonic
7
UCON
Configuration byte location selector:
Clearing this bit causes the device to fetch configuration information
from on-chip memory. Setting this bit causes the device to locate
configuration information based upon the state of EA# during reset
(EA# = VCC = on-chip; EA# = VSS = off-chip).
6:5
WSA1#,
WSA0#
(see Note)
Wait State Select (for all pages except 01H). WSA0# is identical to
the WSA bit defined in the 8XC251SB A-step:
Function
WSA1#WSA0# Description
1
1
0
0
4
XALE#
3:2
RD1, RD0
1
0
1
0
No wait states (01: page controlled by CONFIG1)
Insert 1 wait state for all pages except the 01: page
Insert 2 wait states for all pages except the 01: page
Insert 3 wait states for all pages except the 01: page
Extend Ale:
If this bit is set, the time of the ALE pulse is TOSC. Clearing this bit
extends the time of the ALE pulse from TOSC to 3TOSC, which adds
one external wait state.
RD# and PSEN# function select:
RD1RD0RD# RangeP1.7/CEX4/A17 PSEN# Range
0
0
1
1
0
1
0
1
RD# = A16A17onlyAll Addresses
RD# = A16P1.7/CEX4All Addresses
P3.7 onlyP1.7/CEX4All Addresses
≤ 7F:FFFFHP1.7/CEX4≥ 80:0000H
1
PAGE#
Page Mode Select:
Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0).
Set this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0
(compatible with MCS 51 microcontrollers)).
0
SRC
Source Mode/Binary Mode Select:
Set this bit for source mode. Clear this bit for binary mode (binarycode compatible with MCS 51 microcontrollers).
Figure 17. Configuration Byte 0
NOTE:
Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use configuration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices
without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external
application memory based on an internal address range of FF:FFF9:8H.
31
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
.
Address FF:FFF9H
UCONFIG1
7
0
—
Bit
—
—
INTR
WSB
WSB1#
WSB0#
EMAP#
Number
Bit
Mnemonic
7:5
—
4
INTR
Interrupt Mode:
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the
PC register and the PSW1 register). If this byte is clear, interrupts push 2
bytes onto the stack (the 2 lower bytes of the PC register).
3
WSB
Wait State B. Only use this bit for A-step compatibility:
Clear this bit to generate one external wait state for memory region 01:.
Set this bit for no wait states for region 01:.
2:1
WSB1#,
WSB0#
Function
Reserved; set these bits when writing to UCONFIG1.
Wait States (01:XXXXH page only)
WSB1# WSB0# Description
11
10
01
00
0
EMAP#
No wait states
Insert 1 wait state for the 01: page
Insert 2 wait states for the 01: page
Insert 3 wait states for the 01: page
EPROM MAP:
Clearing this bit maps the upper 8 Kbytes of on-chip code memory
(FF:2000H–FF:3FFFH) to 00:E000H–00:FFFFH. If this bit is set, the
upper 8 Kbytes of on-chip code memory are mapped only to FF:2000H–
FF:3FFFH. If this bit is set mapping does not occur.
Figure 18. Configuration Byte 1
NOTE:
Factory-programmed ROM and OTPROM versions of 8XC251SA/SB/SP/SQ use configuration byte
information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices without
internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application
memory based on an internal address range of FF:FFF9:8H.
32
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Programming Cycle
Verification Cycle
Address (16 Bits)
Address
P1, P3
TAVQV
P2
Data In (8 Bits)
TDVGL
Data Out
TGHDX
TAVGL
TGHAX
TGHGL
PROG#
TGLGH
1
2
3
4
5
TGHSL
TSHGL
EA#/VPP
12.75V
5V
TELQV
TEHQZ
TEHSH
P0
Mode (8 Bits)
Mode
A4128-01
Figure 19. Timing for Programming and Verification of Nonvolatile Memory
33
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 15. Nonvolatile Memory Programming and Verification Characteristics at
TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V
Symbol
Definition
Min
Max
Units
12.5
13.5
D.C. Volts
75
mA
6.0
MHz
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
Fosc
Oscillator Frequency
TAVGL
Address Setup to PROG# Low
48TOSC
TGHAX
Address Hold after PROG#
48TOSC
TDVGL
Data Setup to PROG# Low
48TOSC
TGHDX
Data Hold after PROG#
48TOSC
TEHSH
ENABLE High to VPP
48TOSC
TSHGL
VPP Setup to PROG# Low
10
µs
TGHSL
VPP Hold after PROG#
10
µs
TGLGH
PROG# Width
90
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
PROG# High to PROG# Low
10
TGHGL
NOTE:
4.0
µs
110
48TOSC
48TOSC
48TOSC
µs
Notation for timing parameters:
A = Address
D = Data
E = Enable
G = PROG#
H = High
Q = Data out
S = Supply (VPP)
V = Valid
X = No Longer Valid
Z = Floating
Table 16. Contents of the Signature Bytes
34
ADDRESS
CONTENTS
30H
89H
Indicates Intel Devices
DEVICE TYPE
31H
40H
Indicates MCS251 core product
60H
7AH
Indicates 83C251SA device
60H
7BH
Indicates 83C251SB device
60H
4AH
Indicates 83C251SP device
60H
4BH
Indicates 83C251SQ device
60H
FAH
Indicates 87C251SA device
60H
FBH
Indicates 87C251SB device
60H
CAH
Indicates 87C251SP device
60H
CBH
Indicates 87C251SQ device
61H
55H
Indicates 8XC251SA/SB/SP/SQ B-step products
L = Low
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Revision History
The following changes appear in the -004 datasheet:
1.
To address the fact that many of the package prefix variables have changed, all package prefix variables
in the document are now indicated with an "x".
The (-003) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94
'95 C” as the last line of the topside marking. This datasheet replaces earlier product information. The
following changes appear in the -003 datasheet:
1.
2.
3.
UCONFIG0.7 (UCON) is now defined.
Real time wait state operation is described in the datasheet.
Memory map reserved locations are newly defined.
The (-002) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94
'95 B” as the last line of the topside marking. This datasheet replaces earlier product information. The
following changes appear in the -002 datasheet:
1.
2.
3.
A corrected PDIP diagram appears on page 7.
A corrected formula to calculate TLHLL is described on page 17.
The RD#/PSEN# waveform is changed in Figure 11 on page 25.
35
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