PBL38621/2QNA

June 1999 PBL 386 21/2 Subscriber Line Interface Circuit Description Key Features The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in DAML, FITL and other telecommunications equipment. The PBL 386 21/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 21/2 has constant current feed, programmable to max. 30 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 21/2 is compatible with loop start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable the two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC. • 24-pin SSOP package • High and low battery with automatic switching • 60 mW on-hook power dissipation in active state • On-hook transmission • Long loop battery feed tracks Vbat for maximum line voltage • Only +5 V feed in addition to battery • Selectable transmit gain (1x or 0.5x) • No power-up sequence • 44V open loop voltage @ -48V battery feed • Full longitudinal current capability during on-hook state • Analog over temperature protection permits transmission while the protection circuit is active • Polarity reversal • Integrated Ring Relay driver • Ground key detector • Programmable signal headroom Ring Relay Driver DT TIPX Ground Key Detector RINGX • -40 °C to +85 °C ambient temperature range C1 Ring Trip Comparator DR RRLY Input Decoder and Control C2 C3 DET HP PSG LP Off-hook Detector PLD REF 21/2 386 PBL VTX AGND BGND 38 PB 6 L 21 /2 P B VBAT2 VBAT 21 / 2 PLC 38 6 Two-wire Interface POV L VCC Line Feed Controller and Longitudinal Signal Suppression VF Signal Transmission PTG RSN 24-pin SOIC, 24-pin SSOP, 28-pin PLCC Figure 1. Block diagram. 1 PBL 386 21/2 Maximum Ratings Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 TStg TAmb TJ -55 -40 -40 +150 +110 +140 °C °C °C Power supply, -40 °C ≤ TAmb ≤ +85 °C VCC with respect to A/BGND VBat2 with respect to A/BGND VBat with respect to A/BGND, continuous VBat with respect to A/BGND, 10 ms VCC VBat2 VBat VBat -0.4 VBat -75 -80 6.5 0.4 0.4 0.4 V V V V Power dissipation Continuous power dissipation at TAmb ≤ +85 °C PD 1.5 W 0,3 V Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage VG -0,3 BGND+14 V Ring trip comparator Input voltage Input current VDT, VDR IDT, IDR VBat -5 AGND 5 V mA Digital inputs, outputs (C1, C2, C3, DET) Input voltage VID -0.4 VCC V Output voltage VOD -0.4 VCC V TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V Maximum supplied TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 ITIPX, IRINGX -100 VTA, VRA -80 +100 2 mA V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 VTA, VRA VBat -10 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 VTA, VRA VTA, VRA VBat -25 VBat -35 10 15 V V Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VBat with respect to AGND AGND with respect to BGND TAmb VCC VBat VG -40 4.75 -58 -100 +85 5.25 -8 100 °C V V mV Recommended Operating Condition Notes 2 1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. 2. With the diodes DVB and DVB2 included, see figure 12. 3. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2. PBL 386 21/2 Electrical Characteristics -40 °C ≤ TAmb ≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, VBat = -58V to -40V, VBat2 = -17V, RLC=38.3 kΩ, IL = 22 mA. RL = 600 Ω, RF1= RF2= RP1= RP2=0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ ROV = ∞ unless otherwise specified. Current definition: current is positive if flowing into a pin. Parameter Ref fig Two-wire port Overload level, VTRO 2 Conditions Min On-Hook, ILdc < 5mA Active state 1% THD Note 1, ROV = ∞ 1.0 1.0 Input impedance, ZTR Longitudinal impedance, ZLOT, ZLOR Longitudinal current limit, ILOT, ILOR Note 2 0 < f < 100 Hz active state Longitudinal to metallic balance, BLM IEEE standard 455-1985, ZTRX=736Ω 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 Longitudinal to metallic balance, BLME VPeak VPeak ZT/200 20 35 10 Ω/wire mArms /wire dB dB dB 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 75 70 68 dB dB dB 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 Reverse polarity 0.2 kHz < f < 3.4 kHz 53 75 70 68 dB dB dB 4 0.2 kHz < f < 3.4 kHz 50 dB C Figure 2. Overload level, VTRO, two-wire port Unit 3 BLFE = 20 • Log ELo VTX Metallic to longitudinal balance, BMLE V BMLE = 20 • Log TR ; ERX = 0 VLo Max 3 BLME =20 • Log ELo VTR Longitudinal to four-wire balance, BLFE Typ RL VTRO 40 TIPX ILDC 1