Intel® Wireless Flash Memory (W18
SCSP)
32-Mbit W18 + 8-Mbit SRAM (38F1020W0YTQ0, 38F1020W0YBQ0)
Datasheet
Product Features
■
Flash Architecture
— Flexible, Multi-Partition, Dual-Operation:
Read-While-Write / Read-While-Erase
— 8 Partitions, 4 Mbits each
— 7 Main Partitions, 8 Main Blocks each
— 1 Parameter Partition, 8 Parameter + 7 Main
Blocks
— 32-KWord Main Blocks, 4-KWord
Parameter Blocks
— Top and Bottom Parameter Configuration
■
■
■
Flash Software
— Intel® Flash Data Integrator (Intel® FDI)
Optimized
— Common Flash Interface (CFI)
■
SCSP Architecture
— 32-Mbit Flash die + 8-Mbit SRAM die
— Reduces Board Space Requirement
— Simplifies PCB Design Complexity
— Easy Migration to Future SCSP Devices
■
SCSP Voltage
— 1.7 V to 1.95 V VCC/VCCQ and S-VCC
■
SCSP Packaging
— 0.8 mm Ball-Pitch Intel® SCSP
— Area: 8x10 mm, Height: 1.2 mm max
— 88-Ball (8 x 10 Matrix): 80 Active Balls with
2 Support Balls at Each Corner
■
SRAM Architecture and Performance
— 70 ns Access Time
— Low-Voltage Data Retention Mode
Flash Data Protection
— Absolute Protection with VPP and WP#
— Individual Dynamic Zero-Latency Block
Locking
— Individual Block Lock-Down
— Erase/Program Lockout during Power
Transitions
Flash Automation Suspend Operations
— Erase Suspend to Program or Read
— Program Suspend to Read
— 5 µs (typ) Program/Erase Suspend Latency
Flash Performance
— 65 ns Initial Access Speed
— 25 ns Page-Mode Read Speed; 4-Word Page
— 14 ns Burst-Mode Read Speed
— 4-, 8-, 16- or Continuous-Word Burst Modes
— Burst- and Page-Mode Reads in Parameter
and Main Partitions
— Burst Suspend
— Burst-Mode Reads can Traverse Partition
Boundaries
— Programmable WAIT Polarity
— Enhanced Factory Programming: 3.1 µs/
Word (typ)
■
■
■
Flash Quality and Reliability
— Extended Temperature: –25 °C to +85 °C
— Minimum 100,000 Block Erase Cycles
— Intel® 0.13 µm ETOXTM VIII Process
Technology
Flash Protection Register
— 64 Unique Device Identifier Bits
— 64 User-Programmable OTP Bits
By stacking the Intel® Wireless Flash Memory (W18) device in combination with a low-power
8-Mbit SRAM device, a versatile and compact Stacked Chip Scale Package (SCSP) provides a
solution for high-performance, low-power, board-constrained memory applications. This
datasheet describes the key features of this 32-Mbit W18 + 8-Mbit SRAM combination device.
Refer to the latest revision of the Intel® Wireless Flash Memory (W18) Datasheet (order number
290701) for flash device details not provided in this document.
Notice: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have
the latest datasheet before finalizing a design.
252635-002
May 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 38F1020W0YTQ0 device may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2004.
*Other names and brands may be claimed as the property of others.
2
Datasheet
38F1020W0YTQ0, 38F1020W0YBW0
Contents
1.0
Introduction ......................................................................................................................5
1.1
1.2
2.0
Functional Overview ........................................................................................................6
2.1
3.0
Absolute Maximum Ratings.................................................................................12
Operating Conditions...........................................................................................13
Capacitance ........................................................................................................13
Electrical Specifications ................................................................................................14
6.1
7.0
Signal Descriptions..............................................................................................10
Maximum Ratings and Operating Conditions .............................................................12
5.1
5.2
5.3
6.0
88-Ball Mechanical Specification...........................................................................7
Ballout and Signal Description .......................................................................................9
4.1
5.0
Block Diagram .......................................................................................................6
Package Information ........................................................................................................7
3.1
4.0
Nomenclature ........................................................................................................5
Conventions ..........................................................................................................5
DC Characteristics ..............................................................................................14
AC Characteristics .........................................................................................................15
7.1
7.2
Flash AC Characteristics.....................................................................................15
SRAM AC Characteristics ...................................................................................15
8.0
Power and Reset Specifications ...................................................................................18
9.0
Device Operation............................................................................................................19
10.0
Flash Read Operations ..................................................................................................20
11.0
Flash Program Operations ............................................................................................20
12.0
Flash Program and Erase Operations ..........................................................................20
13.0
Flash Security Modes ....................................................................................................20
14.0
Flash Set Configuration Register .................................................................................20
Appendix A
Appendix B
Appendix C
Appendix D
Write State Machine...........................................................................................21
Common Flash Interface....................................................................................21
Additional Information ......................................................................................21
Ordering Information ........................................................................................22
Datasheet
3
38F1020W0YTQ0, 38F1020W0YBW0
Revision History
4
Date of
Revision
Version
2/12/03
-001
Original SCSP release.
9/03
-002
Added number column to flash and RAM AC tables and updated title.
5/04
-002
Reformated the datasheet according to the new layout.
Description
Datasheet
38F1020W0YTQ0, 38F1020W0YBQ0
1.0
Introduction
This document contains information pertaining to the Intel® Wireless Flash Memory (W18 SCSP);
32-Mbit W18 + 8-Mbit SRAM SCSP device (38F1020W0YTQ0 and 38F1020W0YBQ0). The
intent of this datasheet is to provide information about this SCSP device where it may differ from
the discrete Intel® Wireless Flash memory (W18) device. Refer to the Intel® Wireless Flash
Memory (W18) Datasheet (order number 290701) for information not provided by this document.
1.1
Nomenclature
0x
k
M
Byte
Word
Kword
Mbits
SCSP
1.2
Hexadecimal prefix
1000
1,000,000
8 bits
16 bits
1024 words
1,048,576 bits
Stacked Chip Scale Package
Conventions
Device: Term used interchangeably throughout this document to denote either a particular die or
both die in the package.
VCC or VPP vs. VCC or VPP: When the reference is to signal or package connection name, the
notation will be VCC or VPP. When the reference is to timing or level, the notation will be
subscripted (e.g., VCC or VPP).
R-OE#, R-LB#, R-UB#, R-WE#: Used to identify OE#, LB#, UB#, WE#, RAM signals.
Datasheet
5
38F1020W0YTQ0, 38F1020W0YBQ0
2.0
Functional Overview
This section provides an overview of the features of the 38F1020W0YTQ0 and 38F1020W0YBQ0
devices.
The 38F1020W0YTQ0 and 38F1020W0YBQ0 devices combine one flash and one SRAM die into
a single package. Please refer to the discrete W18 datasheet for a complete overview of the flash
product features.
2.1
Block Diagram
Figure 1 contains the block diagram of the 38F1020W0YTQ0 and 38F1020W0YBQ0 devices.
Refer to Table 1, “Signal Descriptions” on page 10 for a description of each signal shown.
Figure 1. Block Diagram
VCC
OE#1
VCCQ
CE#1
WE#
CLK
ADV#
28F320W18
Flash
WP#
RST#
A[18:0]
S-CS1
6
WAIT
VSS
A[20:19]
S-VCC
VPP
D[15:0]
8-Mbit
SRAM
R-WE#
S-CS2
R-UB#
R-OE#
R-LB#
Datasheet
38F1020W0YTQ0, 38F1020W0YBQ0
3.0
Package Information
3.1
88-Ball Mechanical Specification
Datasheet
7
38F1020W0YTQ0, 38F1020W0YBQ0
Figure 2. 88-Ball Mechanical Specification
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
A
B
B
C
C
D
D
E
E
F
D
F
G
G
H
H
J
J
K
K
L
L
M
M
e
b
E
Top View - Ball
Down
Bottom View - Ball Up
A2
A1
A
Y
Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
8
Symbol
A
A1
A2
b
D
E
e
N
Y
S1
S2
Min
Millimeters
Nom
Max
1.200
0.200
0.325
9.900
7.900
1.100
0.500
Notes
Min
Inches
Nom
Max
0.0472
0.0079
0.860
0.375
10.000
8.000
0.800
88
1.200
0.600
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.100
1.300
0.700
0.0433
0.0197
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.0472
0.0236
0.0167
0.3976
0.3189
0.0039
0.0512
0.0276
Datasheet
38F1020W0YTQ0, 38F1020W0YBQ0
4.0
Ballout and Signal Description
The 38F1020W0YTQ0 and 38F1020W0YBQ0 devices are available in an 88-ball SCSP with ball
pitch of 0.8 mm. Figure 3 contains the ballout.
Figure 3. 88-Ball SCSP Package Diagram
A
1
2
3
4
5
DU
DU
A4
A18
A19
VSS
VCC1
A5
R-LB#
A23
VSS
A3
A17
A24
A2
A7
A1
6
7
8
8
7
6
5
4
DU
DU
DU
DU
VCC2
A21
A11
A11
A21
VCC2
VCC1
VSS
S-CS2
CLK
A22
A12
A12
A22
CLK
S-CS2
VPP
R-WE#
P-CS#
A9
A13
A13
A9
P-CS#
A25
WP#
ADV#
A20
A10
A15
A15
A10
A6
R-UB#
RST#
WE#
A8
A14
A16
A16
A0
D8
D2
D10
D5
D13
WAIT
CE#2
R-OE#
D0
D1
D3
D12
D14
D7
S-CS1#
OE#1
D9
D11
D4
D6
D15
CE#1
RFU
RFU
S-VCC
P-VCC
VCC2
VCCQ
VSS
VSS
VCCQ
VCC1
VSS
VSS
VSS
VSS
DU
DU
DU
DU
3
2
1
DU
DU
A19
A18
A4
VSS
A23
R-LB#
A5
R-WE#
VPP
A24
A17
A3
A20
ADV#
WP#
A25
A7
A2
A14
A8
WE#
RST#
R-UB#
A6
A1
CE#2
WAIT
D13
D5
D10
D2
D8
A0
OE#2
OE#2
D7
D14
D12
D3
D1
D0
R-OE#
VCCQ
VCCQ
D15
D6
D4
D11
D9
OE#1
S-CS1#
VCCQ
VCC2
P-VCC
S-VCC
RFU
RFU
CE#1
VSS
VSS
VSS
VSS
VCC1
VCCQ
VSS
VSS
DU
DU
DU
DU
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
P-Mode
P-Mode
L
M
A
L
Top View - Ball Side Down
M
Bottom View - Ball Side Up
NOTE: Solid balls are shown as ballout differences between various stacked combinations
across the Stacked-CSP Family. See Signal Descriptions for details on the electrical
connections applicable to the 38F1020W0YTQ0 or 38F1020W0YBQ0 device.
.
Datasheet
9
38F1020W0YTQ0, 38F1020W0YBQ0
4.1
Signal Descriptions
Table 1 describes the active signals used on the 38F1020W0YTQ0 and 38F1020W0YBQ0 devices.
Table 1.
Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Decodes a specific location for reads or writes, or targets a
Flash block for erase. Flash addresses are latched during writes, and for reads when
ADV# (or CLK with ADV# low) is issued.
A[25:0]
Input
A[20:0] decodes a specific location within the 28F320W18 die.
A[18:0] decodes a specific location within the 8-Mbit SRAM.
A[25:21] is not used in this device and may be treated as RFU.
D[15:0]
CE#1,
CE#2
Input/
Output
Input
DATA INPUTS/OUTPUTS: Inputs data for SRAM writes or Flash programming.
Flash commands issued during CUI writes are input on D[7:0] only.
D[15:0] outputs device memory contents or Flash ID codes. Flash SRD is read on
D[7:0] only. D[15:0] are floated when the device is deselected or the outputs are
disabled. Flash I/Os D[15:8, 6:0] are floated when the Flash WSM is busy.
FLASH CHIP ENABLE: CE#1-low selects the Flash component. When asserted,
the Flash internal control logic, input buffers, decoders, and sense amplifiers are
activated. When deasserted, the Flash die is deselected, power levels reduce to
standby, and data and WAIT outputs are placed in high-Z state.
CE#2 is not used in this device and may be treated as RFU.
Input
SRAM CHIP SELECTS: Activates the SRAM internal control logic, input buffers,
decoders, and sense amplifiers. When either are deasserted (S-CS1# = VIH or SCS2 = VIL), the SRAM is deselected and its power reduces to standby levels.
RST#
Input
FLASH RESET: RST#-low resets Flash internal circuitry and inhibits write
operations. This function may be employed to provide data protection during power
transitions. After exiting the reset state (RST# returned to logic-high), the selected
Flash die resumes operation in asynchronous read-array mode.
OE#1,
OE#2
Input
S-CS1#,
S-CS2
FLASH OUTPUT ENABLE: OE#1-low activates device output through the Flash
data buffers during a Flash read cycle. When deasserted, the Flash outputs tri-state
to high-Z.
OE#2 is not used in this device and may be treated as RFU.
R-OE#
Input
SRAM OUTPUT ENABLE: R-OE#-low activates device output through the SRAM
data buffers during a SRAM read cycle. When deasserted, the SRAM outputs tristate to high-Z.
WE#
Input
FLASH WRITE ENABLE: WE# controls writes to the selected Flash die. WE#-low
allows input to the Flash CUI, array, PR/PLR, RCR, or block lock bits. Addresses and
data are latched on this signal’s rising edge.
R-WE#
Input
SRAM WRITE ENABLE: R-WE#-low allows writes to the SRAM array.
Input
SRAM UPPER / LOWER BYTE ENABLES: R-UB#-low enables the SRAM highorder bytes (D[15:8]). R-LB#-low enables the SRAM low-order bytes (D[7:0]).
Input
FLASH ADDRESS VALID: During synchronous reads, Flash addresses are latched
on the ADV# rising edge or on a CLK transition with ADV# low. For asynchronous
reads, ADV# can be driven high to latch an address or it can be held low throughout
the read cycle.
CLK
Input
FLASH CLOCK: CLK synchronizes the Flash device to the system bus frequency.
Used only for burst reads, CLK increments the internal address generator within the
Flash device. Externally-applied addresses are latched by the Flash device via a
CLK transition if ADV# is asserted low.
WAIT
Output
FLASH WAIT: Indicates that Flash DOUT is not yet valid. Used only for synchronous
reads. WAIT is high-Z whenever CE#1 is deasserted, but is not gated by OE#1.
R-UB#,
R-LB#
ADV#
10
Datasheet
38F1020W0YTQ0, 38F1020W0YBQ0
Table 1.
Signal Descriptions (Sheet 2 of 2)
Symbol
WP#
Type
Input
Name and Function
FLASH WRITE PROTECT: Enables/disables the Flash lock-down mechanism.
WP#-low secures locked-down blocks from software unlock attempts. WP#-high
overrides the lock-down function, thus allowing system software to unlock lockeddown blocks.
FLASH PROGRAM/ERASE SUPPLY: Hardware program and erase protection. A
valid voltage level allows program or erase; memory contents cannot be altered
when VPP is at or below the VPP lockout voltage (VPPLK).
VPP
Power
Program or erase at invalid VPP voltages should not be attempted. Set VPP = VCC for
in-system read, program and erase operations. VPP must remain above VPP1MIN for
in-system program or erase operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter
blocks for 2500 cycles. VPP can be VPP2 for cumulative total, not to exceed 80 hours
maximum. Extended use of VPP at VPP2 may reduce block cycling capability.
Datasheet
VCC
Power
FLASH POWER SUPPLY: Supplies power to the Flash core.
S-VCC
Power
SRAM POWER SUPPLY: Supplies power for SRAM operations.
VSS
Power
GROUND: Do not float any VSS connection.
RFU
—
RESERVED for FUTURE USE: RFU locations are NC (no connect) on this product.
Contact Intel regarding their future use.
DU
—
DO NOT USE: Do not drive, leave disconnected.
11
38F1020W0YTQ0, 38F1020W0YBQ0
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Absolute maximum ratings for the 38F1020W0YTQ0 and 38F1020W0YBQ0 devices are shown in
Table 2.
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
NOTICE: This document contains information available at the time of its release. The specifications are
subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet
before finalizing a design.
Table 2.
Absolute Maximum Ratings
Maximum Ratings
Parameter
Unit
Min
Notes
Max
Temperature under Bias Expanded
–25
+85
°C
Storage Temperature
–65
+125
°C
Voltage On Any Signal (except VCC, VCCQ, VPP and S-VCC)
–0.5
+2.45
V
1
VCC Voltage
–0.2
+2.45
V
1
VCCQ and S-VCC Voltage
–0.2
+2.45
V
1
VPP Voltage
–0.2
+14
V
1,2
–
100
mA
Output Short Circuit Current
3
NOTES:
1. Specified voltages are with respect to VSS. Minimum DC voltage is –0.5 V on inputs and I/Os, and
–0.2 V on VCC, VCCQ, VPP and S-VCC supplies. During transitions, this level may undershoot to –
2.0 V for periods < 20 ns. During transitions, the maximum DC voltage level may overshoot to VCC
+ 2.0 V for periods < 20 ns.
2. VPP program voltage is normally VPP1. Maximum DC voltage on VPP may overshoot to +14 V for
periods < 20 ns. VPP can be VPP2 for 1000 erase cycles on main blocks, 2500 cycles on parameter
blocks.
3. Output shorted for no more than one second. No more than one output shorted at a time.
12
Datasheet
38F1020W0YTQ0, 38F1020W0YBQ0
5.2
Table 3.
5.3
Table 4.
Operating Conditions
Temperature and Voltage Operating Conditions
Symbol
Parameter
Min
Max
Unit
TA
Operating Temperature
–25
+85
°C
VCC
Flash Supply Voltage
1.7
1.95
V
VCCQ
Flash I/O Voltage
1.7
1.95
V
VPP1
Flash Program Logic Level
0.9
1.95
V
VPP2
Flash Factory Program Voltage
11.4
12.6
V
S-VCC
SRAM Supply Voltage
1.7
1.95
V
Test Condition
Ambient Temperature
Capacitance
Capacitance
Symbol
Parameter
Typ
Max
Unit
Condition
6
8
pF
VIN = 0.0 V
10
10
pF
VIN = 0.0 V
16
18
pF
VIN = 0.0 V
18
22
pF
VOUT = 0.0 V
8
12
pF
VOUT = 0.0 V
Input Capacitance, Flash
CIN
(CE#1, OE#1, WE#, RST#, WP#, ADV#, CLK,
A[20:19])
Input Capacitance, SRAM
CIN
CIN
COUT
COUT
(S-CS#1, S-CS2, R-OE#, R-WE#, R-UB#, RLB#)
Input Capacitance, Flash and SRAM
(A[18:0])
Output Capacitance, Flash and SRAM
(D[15:0])
Output Capacitance, Flash
(WAIT)
NOTE: Sampled, not 100% tested. TA = +25 °C, f = 1 MHz.
Datasheet
13
38F1020W0YTQ0, 38F1020W0YBQ0
6.0
Electrical Specifications
6.1
DC Characteristics
Refer to the discrete W18 Datasheet for flash DC current parameters and DC voltage information.
Table 5.
SRAM DC Characteristics
1.8 V SRAM
Parameter
Description
Test Conditions
Unit
Min
Max
VCC
Voltage Range
1.7
1.95
V
VDR
VCC for Data Retention
1.0
–
V
ICC
Operating Current at
min cycle time
IIO= 0 mA
–
35
mA
ICC2
Operating Current at
max cycle time (1us)
IIO= 0 mA
–
6
mA
–
20
µA
–
10
µA
S-VCC 0.15
–
V
-0.1
0.2
V
S-CS1#>=
S-VCC-0.2V
ISB
Standby Current
or S-CS2
