EM422M1684RTA-7FE

eorex Features • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • Single 2.5V ±0.2V Power Supply • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • 2,2.5,3 Clock read latency • Bi-directional,intermittent data strobe(DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Sequential & Interleaved Burst type available • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms EM42BM1684RTA 512Mb (8M×4Bank×16) Double DATA RATE SDRAM Description The EM42BM1684RTA is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Meg words x 4 banks by 16 bits. The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins. Available packages:TSOPII 66P 400mil. Ordering Information Part No EM42BM1684RTA-75F EM42BM1684RTA-6F EM42BM1684RTA-5F Organization 32M X 16 32M X 16 32M X 16 Max. Freq 133MHz @CL25 166MHz @CL25 200MHz @CL3 Package 66pin TSOP(ll) 66pin TSOP(ll) 66pin TSOP(ll) Grade Commercial Commercial Commercial Pb Free Free Free * EOREX reserves the right to change products or specification without notice. Jul. 2006 1/19 www.eorex.com eorex Pin Assignment EM42BM1684RTA 66pin TSOP-II / (400mil × 875mil) / (0.65mm Pin pitch) Jul. 2006 2/19 www.eorex.com eorex Pin Description (Simplified) Pin Name 45,46 CLK,/CLK EM42BM1684RTA Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when ”L” and disable the command decoder when “H”.The new command are overLooked when the command decoder is disabled but previous operation will still continue. (Clock Enable) Activates the CLK when “H” and deactivates when “L”. When deactivate the clock,CKE low signifies the power down or self refresh mode. (Address) Row address (A0 to A12) and Calumn address (CA0 to CA8) are multiplexed on the same pin. CA10 defines auto precharge at Calumn address. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output) Data Inputs and Outputs are synchronized with both edge of DQS. (Data Input/Output Mask) DM controls data inputs.LDM corresponds to the data on DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15. (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device. (Input) SSTL-2 Reference voltage for input buffer. 24 /CS 44 CKE 28~32,35~42 A0~A12 26, 27 23 BA0, BA1 /RAS 22 /CAS 21 16/51 20/47 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 1,18,33/ 34,48,66 3, 9, 15, 55.61/ 6, 12, 52, 58,64 14,17,19,25,43, 50,53 49 /WE LDQS/UDQS LDM/UDM DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC/RFU VREF Jul. 2006 3/19 www.eorex.com eorex Absolute Maximum Rating Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Short Circuit Current EM42BM1684RTA Rating -0.3 ~ +3.6 -0.3 ~ +3.6 Commercial 0 ~ +70 Extended N/A -55 ~ +150 1 50 Units V V ° C ° C W mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=2.5V, f=1MHz, TA=25° C) Symbol CCLK CI CO Parameter Clock Capacitance(CLK,/CLK) Input Capacitance for CKE, Address, /CS, /RAS, /CAS, /WE DM,Data&DQS Input/Output Capacitance Min. 2 2 4 Typ. Max. 3 3 5 Units pF pF pF Recommended DC Operating Conditions (TA=-0° ~+70°C) C Symbol VDD VDDQ VREF VTT VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) I/O Logic high Voltage I/O Termination Voltage Input Logic High Voltage Input Logic Low Voltage Min. 2.3 2.3 1.15 VREF-0.04 VREF+0.18 -0.3 Typ. 2.5 2.5 1.25 Max. 2.7 2.7 1.35 VREF+0.04 VDDQ+0.3 VREF-0.18 Units V V V V V V Jul. 2006 4/19 www.eorex.com eorex Recommended DC Operating Conditions (VDD=2.5V±0.2V, TA=0°C ~ 70° C) Symbol IDD1 IDD2P Parameter Operating Current (Note 1) EM42BM1684RTA Test Conditions Burst length=2, tRC≥tRC(min.), IOL=0mA, One bank active CKE≤VIL(max.), tCK=min CKE≥VIL(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks CKE≤VIL(max.), tCK=min CKE≥VIH(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks READ tCK ≥ tCK(min.), IOL=0mA, All banks active WRITE tRC≥ tRFC (min.), All banks active CKE≤0.2V Max. -5 110 -6 100 6 -75 100 Units mA mA Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non-power Down Mode Operating Current (Burst (Note 2) Mode) Refresh Current (Note 3) IDD2N 30 mA IDD3P 15 mA IDD3N 50 130 140 200 5 mA IDD4 IDD5 IDD6 mA mA mA Self Refresh Current *All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics. Recommended DC Operating Conditions (Continued) Symbol IIL IOL VOH VOL Parameter Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage Test Conditions 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled IO=-16.8mA IO=+16.8mA Min. -5 -5 VDDQ-0.373 0.373 Max. +5 +5 Units uA uA V V Jul. 2006 5/19 www.eorex.com eorex Block Diagram Auto/ Self Refresh Counter EM42BM1684RTA A0 A1 A2 Row Add. Buffer A3 A4 Address Register A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 Col. Add. Buffer Row Decoder DM Memory Array Write DQM Control Data In S/ A & I/ O Gating Col. Decoder Data Out DOi Mode Register Set Col Add. Counter Burst Counter Timing Register /CLK CLK CKE /CS / RAS / CAS / WE DM DQS Jul. 2006 6/19 www.eorex.com eorex AC Operating Test Conditions (VDD=2.5V±0.2V, TA=0°C ~70° C) Item Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level EM42BM1684RTA Conditions 1.25V/1.25V See diagram as below VREF+0.31V/ VREF-0.31V 1ns VDDQ/2 AC Operating Test Characteristics (VDD=2.5V±0.2V, TA=0°C ~70° C) Symbol tDQCK tDQSCK tCL,tCH tCK tDH,tDS tDIPW tHZ,tLZ tDQSQ tDQSS tDSL,tDS H Parameter DQ output access from CLK,/CLK DQS output access from CLK,/CLK CL low/high level width CL=2 Clock Cycle Time CL=2.5 CL=3 DQ and DM hold/setup time DQ and DM input pulse width for each input Data out high/low impedance time from CLK,/CLK DQS-DQ skew for associated DQ signal Write command to first latching DQS transition DQS input valid window Mode Register Set command cycle time Write Preamble setup time Write Preamble Address/control input hold/setup time Read Preamble -5 Min. -0.65 -0.55 0.45 6 5 0.4 1.75 -0.7 0.4 0.7 1.25 0.35 2 0 0.4 0.7 0.9 1.1 0.9 0.6 0.4 0.7 Max. 0.65 0.55 0.55 12 12 Min. -0.7 -0.6 0.45 7.5 6 0.45 1.75 -0.7 -6 Max. 0.7 0.6 0.55 12 12 Min. -7.5 Max. 0.75 0.75 0.55 12 12 - Units ns ns tCK ns ns ns ns ns -0.75 -0.75 0.45 10 7.5 0.5 1.75 0.7 -0.75 0.5 0.75 0.75 ns ns 0.45 0.75 1.25 1.25 tCK tCK tCK ns 0.35 2 0 0.6 0.8 1.1 0.9 0.4 0.35 2 0 0.6 1.0 1.1 tMRD tWPRES tWPST tIH,tIS tRPRE tCK ns tCK Jul. 2006 7/19 www.eorex.com eorex (VDD=2.5V±0.2V, TA=0°C ~70° C) Symbol tRPST tRAS tRC tRFC tRCD tRP tRRD tCCD tCDLR tCDLW tDPL tXSNR tXSRD tREFI Parameter Read Postamble Active to Precharge command period Active to Active command period Auto Refresh Row Cycle Time Active to Read or Write delay Precharge command period Active bank A to B command period Column address to column address delay Last data in to Read command Last data in to Write command Last data in to Precharge command Exit self Refresh to non-read command Exit self Refresh to read command Average periodic refresh interval 0 2 75 200 15.6 -5 Min. 0.4 40 55 70 15 15 10 1 2.5 tCK- tDQSS Max. 0.6 70k EM42BM1684RTA AC Operating Test Characteristics (Continued) -6 Min. 0.4 42 60 72 18 18 12 1 2.5 tCK- tDQSS 0 2 75 200 15.6 Max. 0.6 70k Min. 0.4 45 65 75 20 20 15 1 2.5 tCK- tDQSS 0 2 75 200 15.6 -75 Max. 0.6 70k Units tCK ns ns ns ns ns ns tCK tCK tCK tCK ns ns us Jul. 2006 8/19 www.eorex.com eorex Simplified State Diagram EM42BM1684RTA Jul. 2006 9/19 www.eorex.com eorex 1. Command Truth Table Command Ignore Command No Operation Burst Stop Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks Mode Register Set Symbol DESL NOP BSTH READ READA WRIT W RITA ACT PRE PALL MRS CKE n-1 n H H H H H H H H H H H X X X X X X X X X X X /CS H L L L L L L L L L L X H H H H H L L L L L EM42BM1684RTA BA0, BA1 X X X V V V V V V X L /RAS /CAS X H H L L L H H H H L /WE X H L H H L H H L L L A10 X X X L H L H V L H L A12~A0 X X X V V V V V X X V H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Item Idle Idle Self Refresh Idle Power Down Command CBR Refresh Command Self Refresh Entry Self Refresh Exit Power Down Entry Power Down Exit Symbol REF SELF CKE n-1 n HH H L L H L L H H L H /CS L L L H X X /RAS L L H X X X /CAS L L H X X X /WE H H H X X X Addr. X X X X X X Remark H = High level, L = Low level, X = High or Low level (Don't care) Jul. 2006 10/19 www.eorex.com eorex 3. Operative Command Table Current State /CS H L L L Idle L L L L H L L Row Active L L L L L H L L L Read L L L L H L L L L L L L X H H H H H L L X H H L H L H L X H L H BA/RA BA, A10 X Op-Code, Mode-Add X X X BA/CA/A10 ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA EM42BM1684RTA /R X H H H L L L L X H H H L L L L X H H H /C X H H L H H L L X H H L H H L L X H H L /W X H L X H L H L X H L L H L H L X H L H Addr. X X X BA/CA/A10 BA/RA BA, A10 X Op-Code, Mode-Add X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 Command DESL NOP TERM READ/WRIT/BW ACT PRE/PREA REFA MRS DESL NOP READ/READA W RIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA Action NOP NOP NOP ILLEGAL (Note 1) Bank active,Latch RA NOP (Note 4) Auto refresh Mode register NOP NOP Begin read,Latch CA, Determine auto-precharge Begin write,Latch CA, Determine auto-precharge ILLEGAL ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge (Note 1) ILLEGAL Terminate burst, PrecharE ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM=”H”,Latch CA,Begin read,Determine (Note 2) auto-precharge Terminate burst,Latch CA,Begin new write, Determine (Note 2) auto-precharge ILLEGAL (Note 1) (Note 1) (Note 3) Precharge/Precharge all Write L L L L L H L L L L L H H L L L H L H L BA/CA/A10 BA/RA BA, A10 X Op-Code, W RIT/WRITA ACT PRE/PREA REFA MRS Terminate burst with DM=”H”, Precharge ILLEGAL ILLEGAL www.eorex.com Jul. 2006 11/19 eorex Current State /CS H L L L Read with AP L L L L H L L L Write with AP L L L L H L L L Pre-charging L L L L H L L L Row Activating L L L L EM42BM1684RTA 3. Operative Command Table (Continued) /R X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L /C X H H L H H L L X H H L H H L L X H H L H H L L X H H L H H L L /W X H L X H L H L X H L X H L H L X H L X H L H L X H L X H L H L Addr. X X BA/CA/A10 BA/RA BA/A10 X X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add Command DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS Action NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP (Note 1) ILLEGAL ILLEGAL (Note 3) NOP(idle after tRP) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jul. 2006 12/19 www.eorex.com eorex Current State /CS H L L L Write Recovering L L L L L H L L L L L L L EM42BM1684RTA 3. Operative Command Table (Continued) /R X H H H H L L L L X H H H L L L L /C X H H L L H H L L X H H L H H L L /W X H L H L H L H L X H L X H L H L Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add Command DESL NOP TERM READ W RIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS Action NOP NOP NOP (Note 1) ILLEGAL New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL (Note 1) (Note 1) Refreshing Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle. Jul. 2006 13/19 www.eorex.com eorex 4. Command Truth Table for CKE Current State CKE n-1 n H X L H L H L H L H L H L L H X L H L H L H L H L H L L H H H L H L H L H L H L L H L H L H L Any State Other than Listed above H X H EM42BM1684RTA /CS X H L L L L X X H L L L L X X H L L L L L L L X X /R X X H H H L X X X H H H L X X X H H H L L L L X X /C X X H H L X X X X H H L X X X X H H L H L L L X X /W X X H L X X X X X H L X X X X X H L X H H L L X X Addr. X X X X X X X X X X X X X X X X X X X RA X Op-Code Op-Code X X Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access Refer to current state Refer to command truth table Self Refresh Both bank precharge power down All Banks Idle Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE’s low to high transition to issue a new command. Notes 2:CKE low to high transition is asynchronous as if restarts internal clock. Notes 3:Power down and self refresh can be entered only from the idle state of all banks. Jul. 2006 14/19 www.eorex.com eorex Mode Register Definition Mode Register Set EM42BM1684RTA The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. Jul. 2006 15/19 www.eorex.com eorex Address input for Mode Register Set ( MRS ) BA1 BA0 A12/11 EM42BM1684RTA A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Operation Mode CAS Latency Burst Length Burst Length Sequential 2 4 8 Reserved Reserved Reserved Full Page Interleave 2 4 8 Reserved Reserved Reserved Reserved A2 0 0 0 1 1 1 1 A1 0 1 1 0 0 1 1 A0 1 0 1 0 1 0 1 DLL Reset NO Yes A8 0 1 A7 0 1 Operation Mode Normal Test Burst Type Interleave Sequential A3 1 0 CAS Latency Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 BA0 0 1 An ~A0 MRS Cycle EMRS Cycle Jul. 2006 16/19 www.eorex.com eorex Burst Type (A3) Burst Length 2 A2 X X X 4 X X X 0 0 0 8 0 1 1 1 A1 X X 0 0 1 1 0 0 1 1 0 0 1 A0 0 0 0 1 0 1 0 1 0 1 0 1 0 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 EM42BM1684RTA Sequential Addressing Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 1 1 1 70123456 *Page length is a function of I/O organization and column addressing DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Jul. 2006 17/19 www.eorex.com eorex Extended Mode Register Set ( EMRS ) EM42BM1684RTA The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 0 BA0 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 /QFC A1 D.I.C A0 DLL RFU :Must be set as 0 QFC control Disable Enable A2 0 1 DLL Rest A0 0 1 0 Enable Disable Output Driver Impedance Control A1 0 1 Normal Weak BA0 0 1 MRS Mode MRS EMRS Jul. 2006 18/19 www.eorex.com eorex Package Description EM42BM1684RTA Jul. 2006 19/19 www.eorex.com