EM488M1644VTC_EV

____________________________________________ EM488M1644VTC 128Mb (2Mx4Bankx16) Synchronous DRAM Feature • Fully synchronous to positive clock edge • Single 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length (B/ L) - 1,2,4, 8 or full page • Programmable CAS Latency (C/ L) - 2 or 3 • Data Mask (DQM) for Read / Write masking • Programmable wrap sequence – Sequential (B/ L = 1/2/4/8/full page ) – Interleave (B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms (15.625us) Description The EM488M1644VTC is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks x 16 bits.All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Packages: TSOPII 54P 400mil Ordering Information Part No EM488M1644VTC –75F EM488M1644VTC –7F Organization Max. Freq 8M X16 133MHz @CL3 8M X16 143MHz @CL3 Package 54pin TSOP (II) 54pin TSOP (II) Power Commercial Commercial Pb Free Free * EOREX reserves the right to change products or specification without notice. 1 ____________________________________________ EM488M1644VTC Absolute Maximum Ratings Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current Rating -0.3 ~ 4.6 -0.3 ~ 4.6 0 ~ 70 -55 ~ 150 1 50 Units V V °C °C W mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70 °C ) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input logic high voltage Input logic low voltage Min. 3.0 3.0 2.0 -0.3 Typical 3.3 3.3 Typical 3.6 3.6 VDD+0.3 0.8 Units V V V V Note : 1. All voltage referred to VSS. 2. VIH (max) = 5.6V for pulse width ≤3ns 3. VIL (min) = -2.0V for pulse width ≤ 3ns Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25°C ) Symbol CCLK CI CO Parameter Clock capacitance Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output capacitance Min. 2.5 2.5 4.0 Max. 3.5 3.8 6.5 Units pF pF pF 2 ____________________________________________ EM488M1644VTC Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C ) Parameter Operating current Symbol ICC1 Test condition Burst length = 1, 85 tRC ≥ tRC (min), IOL = 0 mA, One bank active Precharge standby current in power down mode Precharge standby current in non-power down mode ICC2NS ICC2N CKE ≥ VIL (min.), tCK=15ns, /CS ≥ VIH (min.) Input signals are changed one time during 30ns CKE ≥ VIL (min.), tCK = ∞ Input signals are stable Active standby current in power down mode Active standby current in non-power down mode ICC3NS ICC3P ICC3PS ICC3N CKE ≤ VIL (max), tCK = 15ns CKE ≤ VIL (max), tCK = ∞ CKE ≥ VIL (min), tCK = 15ns, /CS ≥ VIH (min) Input signals are changed one time during 30ns CKE ≥ VIL (min), tCK = ∞ Input signals are stable operating current (Burst mode) Refresh current Self Refresh current ICC5 ICC6 tRC ≥ tRC(min.) CKE ≤ 0.2V ICC4 tCCD ≥ 2CLKs , IOL = 0 mA 110 170 3 mA mA 3 4 mA 2 35 mA 10 10 45 mA mA mA 10 mA 35 mA ICC2P ICC2PS CKE ≤ VIL (max.), tCK= 15 ns CKE ≤ VIL (max.), tCK= ∞ 2.5 2.5 mA mA MAX Units Notes mA mA 1 ＊ All voltages referenced to Vss. Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min) 3. Input signals are changed only one time during tCK (min) 4. Standard power version. 3 ____________________________________________ EM488M1644VTC Recommended DC Operating Conditions (Continued) Parameter Input leakage current Symbol Test condition IIL 0 ≤ VI ≤ VDDQ, VDDQ=VDD All other pins not under test=0 V 0 ≤ VO ≤ VDDQ, DOUT is disabled Io = -4mA Io = +4mA Min. -0.5 Max. +0.5 Unit uA Output leakage current High level output voltage Low level output voltage IOL VOH VOL -0.5 2.4 +0.5 0.4 uA V V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70°C ) Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level 1.4V / 1.4V See diagram as below 2.4V / 0.4V 2ns 1.4V 4 ____________________________________________ EM488M1644VTC Operating AC Characteristics ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C) Parameter Symbol -7 -7.5 Units Notes Min. Max. Min. Max. Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time Data-out high impedance time Data-out low impedance time Input hold time Input setup time ACTIVE to ACTIVE command period ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from PRECHARGE command Refresh time(4,096 cycle) CL = 3 CL = 2 tEF CL = 3 CL = 2 CL = 3 CL = 2 tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD 0 1 1.5 62 42 3 3 2 1 100k 0 1 1.5 67 45 3 3 2 1 100k CL = 3 CL = 2 CL = 3 CL = 2 tCH tCL tOH tHZ 2.5 2.5 3 3 7 tCK tAC 7 7.5 5.4 5.4 2.5 2.5 3 3 7 7.5 10 5.4 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK 2 2 2 2 2 tDPL tBDL tROH 2 1 3 2 64 2 1 3 2 64 CLK CLK CLK CLK ms ＊ All voltages referenced to Vss. Note : 1. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) 5 ____________________________________________ EM488M1644VTC Block Diagram 6 DOi ____________________________________________ EM488M1644VTC Pin Assignment : TSOP 54P x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 54pin TSOP-II (400mil x 875mil) 7 ____________________________________________ EM488M1644VTC Pin Descriptions (Simplified) Pin CLK /CS CKE Name System Clock Chip select Clock Enable Pin Function Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the precharge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. BA0, BA1 /RAS /CAS /WE Bank Address Row address strobe Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. UDQM / LDQM Data input/output Mask DQM controls I/O buffers. DQ0 ~ 15 Data input/output DQ pins have the same function as I/O pins on a conventional DRAM. VDD / VSS VDDQ / VSSQ NC Power supply / Ground VDD and VSS are power supply pins for internal circuits. Power supply / Ground VDDQ and VSSQ are power supply pins for the output buffers. No connection This pin is recommended to be left No Connection on the device. 8 ____________________________________________ EM488M1644VTC Simplified State Diagram 9 ____________________________________________ EM488M1644VTC Address Input for Mode Register Set BA1 BA0 A11 A10 A9 A8 A7 A6 A5 Cas Latency A4 A3 BT A2 A1 A0 Operation Mode Burst Length Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Interleave Sequential CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 A3 1 0 BA1 0 0 BA0 0 0 A11 0 0 A10 0 0 A9 0 1 A8 0 0 A7 0 0 Operation Mode Normal Burst read with Single-bit Write 10 ____________________________________________ EM488M1644VTC Burst Type ( A3 ) Burst Length 2 4 A2 X X X X X X 0 0 0 0 1 1 1 1 n A1 A0 X 0 X 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 n n Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 …... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - 8 Full Page * * Page length is a function of I/O organization and column addressing X16 (CA0 ~ CA8) : Full page = 512bits 11 ____________________________________________ EM488M1644VTC Truth Table 1.Command Truth Table Command Symbol CKE n-1 Ignore Command No operation Burst stop Read Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set DESL NOP BSTH READ WRIT WRITA ACT PRE PALL MRS H H H H H H H H H H H n X X X X X X X X X X X H L L L L L L L L L L X H H H H H L L L L L X H H L L L H H H H L X H L H H L H H L L L /CS /RAS /CAS /WE BA0, BA1 X X X V V V V V V X L X X X L H L H V L H L A10 A11, A9~A0 X X X V V V V V X X V Read with auto pre-charge READA 2. DQM Truth Table Command Symbol n-1 Data write / output enable Data mask / output disable Upper byte write enable / output enable Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL MRS H H H H H H H H H H H H CKE n x x x x x x x x x x x H L L L L L L L L L L /CS 3. CKE Truth Table Command Activating Any Idle Idle Self refresh Idle Power down Command Clock suspend mode entry Clock suspend mode CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit REF SELF Symbol CKE n-1 H L L H H L L H L n L L H H L H H L H X X X L L L H X X X X X L L H X X X X X X L L H X X X X X X H H H X X X X X X X X X X X X /CS /RAS /CAS /WE Addr. Clock suspend Clock suspend mode exit Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 12 ____________________________________________ EM488M1644VTC 4. Operative Command Table Current /CS /R state Idle /C /W Addr. Command Action Notes H L L L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X X X DESL Nop or power down 2 2 3 3 NOP or BST Nop or power down READ/READA ILLEGAL H BA/CA/A10 L BA/CA/A10 WRIT/WRITA ILLEGAL ACT H BA/RA Row activating L H L X X BA, A10 X Op-Code X X PRE/PALL REF/SELF MRS DESL Nop Refresh or self refresh Mode register accessing Nop 4 Row active H L L L L L L L NOP or BST Nop 5 5 3 6 4 H BA/CA/A10 READ/READA Begin read : Determine AP L BA/CA/A10 WRIT/WRITA Begin write : Determine AP H L H L X H L BA/RA BA, A10 X Op-Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP BST ILLEGAL Pre-charge ILLEGAL ILLEGAL Continue burst to end→ Row active Continue burst to end→ Row active Burst stop→ Row active Read H L L L L L L L L H BA/CA/A10 READ/READA Terminate burst, new read : Determine AP L BA/CA/A10 WRIT/WRITA Terminate burst, start write : Determine AP H L H L X H L BA/RA BA/A10 X Op-Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP BST ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end→ Write recovering Continue burst to end→ Write recovering Burst stop→ Row active 7 7.8 3 4 Write H L L L L L L L L H BA/CA/A10 READ/READA Terminate burst, start read: Determine AP 7, 8 L BA/CA/A10 WRIT/WRITA Terminate burst, new write: Determine AP 7 ILLEGAL H BA/RA ACT L H L BA/A10 X Op-Code PRE/PALL REF/SELF MRS Terminate burst, pre-charging ILLEGAL ILLEGAL 7.8 7 3 9 Remark H = High level, L = Low level, X = High or Low level (Don't care) 13 ____________________________________________ Current state /CS /R X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /C X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /W X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Addr. X X X Command DESL NOP BST EM488M1644VTC Notes Action Continue burst to end→ Pre-charging Continue burst to end→ Pre-charging ILLEGAL Read with AP H L L L L L L L L Write with AP H L L L L L L L L Pre-charging H L L L L L L L L Row activating H L L L L L L L L BA/CA/A10 READ/READA ILLEGAL BA/CA/A10 WRIT/WRITA ILLEGAL BA/RA BA, A10 X Op-Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP BST ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end→ Write recovering with auto pre-charge Continue burst to end→ Write recovering with auto pre-charge ILLEGAL 3 3 3 3 BA/CA/A10 READ/READA ILLEGAL BA/CA/A10 WRIT/WRITA ILLEGAL BA/RA BA, A10 X Op-Code X X X ACT PRE/PALL REF/SELF MRS DESL NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop→ Enter idle after tRP Nop→ Enter idle after tRP 3 3 3 3 BST ILLEGAL READ/READA ILLEGAL BA/CA/A10 BA/CA/A10 WRIT/WRITA ILLEGAL BA/RA BA, A10 X Op-Code X X ACT PRE/PALL REF/SELF MRS DESL NOP ILLEGAL Nop→ Enter idle after tRP ILLEGAL ILLEGAL Nop→ Enter idle after tRCD Nop→ Enter idle after tRCD ILLEGAL 3 3 3 X BST BA/CA/A10 READ/READA ILLEGAL BA/CA/A10 WRIT/WRITA ILLEGAL BA/RA BA, A10 X Op-Code ACT PRE/PALL REF/SELF MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3.1 3 Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge 14 ____________________________________________ Current state Write H recovering L L L L L L L L Write H recovering L with AP L L L L L L L Refreshing H L L L L Mode Register Accessing H L L L L X H H H H L L L L X H H H H L L L L H H L L X H H H L X H H L L H H L L X H H L L H H L L H L H L X H H L X X H L H L H L H L X H L H L H L H L X X X X X X H L X X X X X BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X DESL NOP BST /CS /R /C /W Addr. Command Action EM488M1644VTC Notes Nop→ Enter row active after tDPL Nop→ Enter row active after tDPL Nop→ Enter row active after tDPL Start read, Determine AP 8 3 3 ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop→ Enter pre-charge after tDPL Nop→ Enter pre-charge after tDPL Nop→ Enter pre-charge after tDPL 3.8 3 3 BA/CA/A10 READ/READA ACT PRE/PALL REF/SELF MRS DESL NOP BST WRIT/WRITA New write, Determine AP BA/CA/A10 READ/READA ILLEGAL WRIT/WRITA ILLEGAL ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop→ Enter idle after tRC Nop→ Enter idle after tRC ILLEGAL XX ACT/PRE/PALL ILLEGAL REF/SELF/MRS ILLEGAL DESL NOP BST READ/WRIT Nop Nop ILLEGAL ILLEGAL ACT/PRE/PALL/ ILLEGAL REF/SELF/MRS Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states;Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. 15 ____________________________________________ EM488M1644VTC 5. Command Truth Table for CKE Current state CKE /CS /R X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X /C X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X /W X X X X X X X X X X X X X X X X X X X X H X X X H X X X X X X X X X X X X X X X Addr. X X X X X X X X X X X X X X X X X Action INVALID, CLK (n – 1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down→ Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Power down Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend 2 1 1 1 Notes n-1 n Self refresh H X L L L L L Self refresh recovery H H H H H H H H Power down Both banks H L L H H idle H H H H H H H H L Row active Any state other than H L H H L listed above L H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L L Op-Code Refer to operations in Operative Command Table L Op-Code Refer to operations in Operative Command Table Remark : H = High level, L = Low level, X = High or Low level (Don't care) Notes: 1. Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Tabl 16 ____________________________________________ EM488M1644VTC Recommended Power On and Initialization : The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs.(Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. 17 ____________________________________________ EM488M1644VTC Package Drawing : TSOPII 54P 18