ESSDC256

64MB/128MB/256MB/512MB Secure Digital Card Description ESSDC64 / ESSDC128 / ESSDC256 / ESSDC512 are different memory capacities from 64MB to 512MB of the Secure Digital Card. They are non-volatile, which means no external power required to retain the information stored on these. Besides, They are also the solid-state device that without moving parts to skip or break down. ESMSDC64 / ESMSDC128 / ESMSDC256 / ESMSDC512 can offer an incredible combination of fast data transfer, great flexibility, excellent security and incredibly small size. Features Operating Voltage: 2.7V ~ 3.6V Operating Temperature: -25℃ ~ 85℃ Data Transfer Rate: Average 2MB/s Durability: 10,000 insertion/removal cycles Mechanical Write Protection Switch SD Host allows MultiMediaCard upward compatibility Form Factor: 24mm x 32mm x 2.1mm Pin Definition Pin No. 1 2 3 4 5 6 7 8 9 Name CD/DA CMD VSS1 VDD CLK VSS2 DAT0 DAT1 DAT2 Type I/O/PP PP S S I S I/O/PP I/O/PP I/O/PP Description Card Detect/Data Line[Bit3] Command/Response Supply voltage ground Supply voltage Clock Supply voltage ground Data Line [Bit0] Data Line [Bit1] Data Line [Bit2] Eorex Corporation www.eorex.com 1/6 64MB/128MB/256MB/512MB Secure Digital Card Architecture Eorex Corporation www.eorex.com 2/6 64MB/128MB/256MB/512MB Secure Digital Card Bus Operating Conditions 1. General Parameter Peak voltage on all lines All Inputs Input Leakage Current All Outputs Output Leakage Current -10 10 µA -10 10 µA Symbol Min. -0.3 Max. VDD+0.3 Unit V Remark 2. Power Supply Voltage Parameter Supply voltage Symbol VDD Min 2.0 Max 3.6 Unit V Remark CMD0, 12, 55, ACMD41 commands Supply voltage specified in OCR register Except CMD0, 15, 55, ACMD41 commands Supply voltage differentials (VSS1, VSS2) Power up time -0.3 0.3 250 V ms From 0V to VDD Min. Note: The current consumption of any card during the power-up procedure must not exceed 10mA. The total capacitance CL of each line of the MultiMediaCard bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line: CL = CHOST + CBUS + N* CCARD Where N is the number of connected cards. Requiring the sum of the host and bus capacitance’s not to exceed 30pF for up to 10 cards, and 40pF up to 30 cards, the following values must not be exceeded: Parameter Bus signal line capacitance Signal card capacitance Maximum signal line inductance Pull-up resistance inside card (pin1) RDAT3 10 Symbol CL CCARD Min Max 100 10 16 90 Unit pF pF nH KΩ fpp≦20MHz May be used for card detection Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only since they are connected separately to the SD Memory Card host. Parameter Pull-up resistance Bus signal line capacitance Eorex Corporation www.eorex.com 3/6 3. Bus Signal Line Load Remark fpp≦20MHz, 7 cards Symbol RCMD, RDAT CL Min 10 Max 100 250 Unit KΩ pF Remark To prevent bus floating fpp≦5MHz, 21 cards 64MB/128MB/256MB/512MB Secure Digital Card 4. Bus Signal Levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range: Parameter Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Symbol VOH VOL VIH VIL 0.625* VDD Min 0.75* VDD 0.125* VDD VDD+0.3 0.25* VDD Max Unit V V V V Remark IOH=-100µA @VDD min IOL=-100µA @VDD min VSS-0.3 Eorex Corporation www.eorex.com 4/6 64MB/128MB/256MB/512MB Secure Digital Card 5. Bus Timing Parameter Symbol Min Max Unit Remark Clock CLK (All values are referred to min (VIH) and max (VIL) Clock frequency Data Transfer Mode Clock frequency Identification Mode (The low freq. is required for MultiMediaCard compatibility.) Clock low time tWL 10 50 Clock high time tWH 10 50 Clock rise time tTLH 10 50 Clock fall time tTHL 10 50 Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK) Output Delay time Eorex Corporation www.eorex.com 5/6 fpp fOD 0 0 20 400 MHz KHz CL